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Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_190 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_190( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_70 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_70( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLEFromBeat_serial_tl_0_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}, flip beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<8>, head : UInt<1>, tail : UInt<1>}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}
connect io.protocol, protocol
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<8>, clock
node const = mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
node _io_beat_ready_T = eq(io.beat.bits.tail, UInt<1>(0h0))
node _io_beat_ready_T_1 = and(is_const, _io_beat_ready_T)
node _io_beat_ready_T_2 = or(_io_beat_ready_T_1, protocol.ready)
connect io.beat.ready, _io_beat_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.beat.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.beat.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_sink_WIRE : UInt<8>
connect _protocol_bits_sink_WIRE, const
connect protocol.bits.sink, _protocol_bits_sink_WIRE
node _T = shr(const, 8)
node _T_1 = and(io.beat.ready, io.beat.valid)
node _T_2 = and(_T_1, io.beat.bits.head)
when _T_2 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.beat.bits.payload
node _T_3 = and(io.beat.ready, io.beat.valid)
node _T_4 = and(_T_3, io.beat.bits.tail)
when _T_4 :
connect is_const, UInt<1>(0h1) | module TLEFromBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:140:7]
input clock, // @[TLChannelCompactor.scala:140:7]
input reset, // @[TLChannelCompactor.scala:140:7]
output io_beat_ready, // @[TLChannelCompactor.scala:75:14]
input io_beat_valid, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14]
);
reg is_const; // @[TLChannelCompactor.scala:88:25]
wire io_beat_ready_0 = is_const & ~io_beat_bits_tail; // @[TLChannelCompactor.scala:88:25, :91:{30,33}]
wire _GEN = io_beat_ready_0 & io_beat_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:140:7]
if (reset) // @[TLChannelCompactor.scala:140:7]
is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25, :140:7]
else // @[TLChannelCompactor.scala:140:7]
is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_173 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_173( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_15 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
node _source_ok_T_31 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[2])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[3])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[4])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[5])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[6])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[7])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[8])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_39, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = and(_T_11, _T_24)
node _T_113 = and(_T_112, _T_37)
node _T_114 = and(_T_113, _T_50)
node _T_115 = and(_T_114, _T_63)
node _T_116 = and(_T_115, _T_71)
node _T_117 = and(_T_116, _T_79)
node _T_118 = and(_T_117, _T_87)
node _T_119 = and(_T_118, _T_95)
node _T_120 = and(_T_119, _T_103)
node _T_121 = and(_T_120, _T_111)
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_121, UInt<1>(0h1), "") : assert_1
node _T_125 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_125 :
node _T_126 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_127 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<1>(0h0))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_136 = shr(io.in.a.bits.source, 2)
node _T_137 = eq(_T_136, UInt<1>(0h1))
node _T_138 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_139 = and(_T_137, _T_138)
node _T_140 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_141 = and(_T_139, _T_140)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_142 = shr(io.in.a.bits.source, 2)
node _T_143 = eq(_T_142, UInt<2>(0h2))
node _T_144 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_145 = and(_T_143, _T_144)
node _T_146 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_147 = and(_T_145, _T_146)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_148 = shr(io.in.a.bits.source, 2)
node _T_149 = eq(_T_148, UInt<2>(0h3))
node _T_150 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_151 = and(_T_149, _T_150)
node _T_152 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_153 = and(_T_151, _T_152)
node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_155 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_156 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_157 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_158 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_159 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_160 = or(_T_129, _T_135)
node _T_161 = or(_T_160, _T_141)
node _T_162 = or(_T_161, _T_147)
node _T_163 = or(_T_162, _T_153)
node _T_164 = or(_T_163, _T_154)
node _T_165 = or(_T_164, _T_155)
node _T_166 = or(_T_165, _T_156)
node _T_167 = or(_T_166, _T_157)
node _T_168 = or(_T_167, _T_158)
node _T_169 = or(_T_168, _T_159)
node _T_170 = and(_T_128, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<14>(0h2000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<13>(0h1000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<17>(0h10000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<18>(0h2f000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<17>(0h10000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = or(_T_177, _T_182)
node _T_214 = or(_T_213, _T_187)
node _T_215 = or(_T_214, _T_192)
node _T_216 = or(_T_215, _T_197)
node _T_217 = or(_T_216, _T_202)
node _T_218 = or(_T_217, _T_207)
node _T_219 = or(_T_218, _T_212)
node _T_220 = and(_T_172, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_171, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_222, UInt<1>(0h1), "") : assert_2
node _T_226 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_227 = shr(io.in.a.bits.source, 2)
node _T_228 = eq(_T_227, UInt<1>(0h0))
node _T_229 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_230 = and(_T_228, _T_229)
node _T_231 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_233 = shr(io.in.a.bits.source, 2)
node _T_234 = eq(_T_233, UInt<1>(0h1))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_239 = shr(io.in.a.bits.source, 2)
node _T_240 = eq(_T_239, UInt<2>(0h2))
node _T_241 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_242 = and(_T_240, _T_241)
node _T_243 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_244 = and(_T_242, _T_243)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_245 = shr(io.in.a.bits.source, 2)
node _T_246 = eq(_T_245, UInt<2>(0h3))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_252 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_226
connect _WIRE[1], _T_232
connect _WIRE[2], _T_238
connect _WIRE[3], _T_244
connect _WIRE[4], _T_250
connect _WIRE[5], _T_251
connect _WIRE[6], _T_252
connect _WIRE[7], _T_253
connect _WIRE[8], _T_254
connect _WIRE[9], _T_255
connect _WIRE[10], _T_256
node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_260 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_261 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_264 = mux(_WIRE[5], _T_257, UInt<1>(0h0))
node _T_265 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_266 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_267 = mux(_WIRE[8], _T_258, UInt<1>(0h0))
node _T_268 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_269 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = or(_T_259, _T_260)
node _T_271 = or(_T_270, _T_261)
node _T_272 = or(_T_271, _T_262)
node _T_273 = or(_T_272, _T_263)
node _T_274 = or(_T_273, _T_264)
node _T_275 = or(_T_274, _T_265)
node _T_276 = or(_T_275, _T_266)
node _T_277 = or(_T_276, _T_267)
node _T_278 = or(_T_277, _T_268)
node _T_279 = or(_T_278, _T_269)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_279
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<14>(0h2000)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<13>(0h1000)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_295 = cvt(_T_294)
node _T_296 = and(_T_295, asSInt(UInt<17>(0h10000)))
node _T_297 = asSInt(_T_296)
node _T_298 = eq(_T_297, asSInt(UInt<1>(0h0)))
node _T_299 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_300 = cvt(_T_299)
node _T_301 = and(_T_300, asSInt(UInt<18>(0h2f000)))
node _T_302 = asSInt(_T_301)
node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0)))
node _T_304 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_305 = cvt(_T_304)
node _T_306 = and(_T_305, asSInt(UInt<17>(0h10000)))
node _T_307 = asSInt(_T_306)
node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0)))
node _T_309 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_310 = cvt(_T_309)
node _T_311 = and(_T_310, asSInt(UInt<13>(0h1000)))
node _T_312 = asSInt(_T_311)
node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0)))
node _T_314 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<27>(0h4000000)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = or(_T_288, _T_293)
node _T_325 = or(_T_324, _T_298)
node _T_326 = or(_T_325, _T_303)
node _T_327 = or(_T_326, _T_308)
node _T_328 = or(_T_327, _T_313)
node _T_329 = or(_T_328, _T_318)
node _T_330 = or(_T_329, _T_323)
node _T_331 = and(_T_283, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = and(_WIRE_1, _T_332)
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_333, UInt<1>(0h1), "") : assert_3
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(source_ok, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_340 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_340, UInt<1>(0h1), "") : assert_5
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_347 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_347, UInt<1>(0h1), "") : assert_7
node _T_351 = not(io.in.a.bits.mask)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_352, UInt<1>(0h1), "") : assert_8
node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_356, UInt<1>(0h1), "") : assert_9
node _T_360 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_360 :
node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_365 = shr(io.in.a.bits.source, 2)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_368 = and(_T_366, _T_367)
node _T_369 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_370 = and(_T_368, _T_369)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_371 = shr(io.in.a.bits.source, 2)
node _T_372 = eq(_T_371, UInt<1>(0h1))
node _T_373 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_374 = and(_T_372, _T_373)
node _T_375 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_377 = shr(io.in.a.bits.source, 2)
node _T_378 = eq(_T_377, UInt<2>(0h2))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_382 = and(_T_380, _T_381)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_383 = shr(io.in.a.bits.source, 2)
node _T_384 = eq(_T_383, UInt<2>(0h3))
node _T_385 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_386 = and(_T_384, _T_385)
node _T_387 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_388 = and(_T_386, _T_387)
node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_391 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_392 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_393 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_394 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_395 = or(_T_364, _T_370)
node _T_396 = or(_T_395, _T_376)
node _T_397 = or(_T_396, _T_382)
node _T_398 = or(_T_397, _T_388)
node _T_399 = or(_T_398, _T_389)
node _T_400 = or(_T_399, _T_390)
node _T_401 = or(_T_400, _T_391)
node _T_402 = or(_T_401, _T_392)
node _T_403 = or(_T_402, _T_393)
node _T_404 = or(_T_403, _T_394)
node _T_405 = and(_T_363, _T_404)
node _T_406 = or(UInt<1>(0h0), _T_405)
node _T_407 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_408 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<14>(0h2000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<13>(0h1000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<18>(0h2f000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<13>(0h1000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<27>(0h4000000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<13>(0h1000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = or(_T_412, _T_417)
node _T_449 = or(_T_448, _T_422)
node _T_450 = or(_T_449, _T_427)
node _T_451 = or(_T_450, _T_432)
node _T_452 = or(_T_451, _T_437)
node _T_453 = or(_T_452, _T_442)
node _T_454 = or(_T_453, _T_447)
node _T_455 = and(_T_407, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = and(_T_406, _T_456)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_457, UInt<1>(0h1), "") : assert_10
node _T_461 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_462 = shr(io.in.a.bits.source, 2)
node _T_463 = eq(_T_462, UInt<1>(0h0))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_467 = and(_T_465, _T_466)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_468 = shr(io.in.a.bits.source, 2)
node _T_469 = eq(_T_468, UInt<1>(0h1))
node _T_470 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_471 = and(_T_469, _T_470)
node _T_472 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_473 = and(_T_471, _T_472)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<2>(0h2))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<2>(0h3))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_487 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_488 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_489 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_490 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_491 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_461
connect _WIRE_2[1], _T_467
connect _WIRE_2[2], _T_473
connect _WIRE_2[3], _T_479
connect _WIRE_2[4], _T_485
connect _WIRE_2[5], _T_486
connect _WIRE_2[6], _T_487
connect _WIRE_2[7], _T_488
connect _WIRE_2[8], _T_489
connect _WIRE_2[9], _T_490
connect _WIRE_2[10], _T_491
node _T_492 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_493 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_494 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_495 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_496 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_497 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_498 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_499 = mux(_WIRE_2[5], _T_492, UInt<1>(0h0))
node _T_500 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_501 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_502 = mux(_WIRE_2[8], _T_493, UInt<1>(0h0))
node _T_503 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_504 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_505 = or(_T_494, _T_495)
node _T_506 = or(_T_505, _T_496)
node _T_507 = or(_T_506, _T_497)
node _T_508 = or(_T_507, _T_498)
node _T_509 = or(_T_508, _T_499)
node _T_510 = or(_T_509, _T_500)
node _T_511 = or(_T_510, _T_501)
node _T_512 = or(_T_511, _T_502)
node _T_513 = or(_T_512, _T_503)
node _T_514 = or(_T_513, _T_504)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_514
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = or(_T_523, _T_528)
node _T_560 = or(_T_559, _T_533)
node _T_561 = or(_T_560, _T_538)
node _T_562 = or(_T_561, _T_543)
node _T_563 = or(_T_562, _T_548)
node _T_564 = or(_T_563, _T_553)
node _T_565 = or(_T_564, _T_558)
node _T_566 = and(_T_518, _T_565)
node _T_567 = or(UInt<1>(0h0), _T_566)
node _T_568 = and(_WIRE_3, _T_567)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_568, UInt<1>(0h1), "") : assert_11
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(source_ok, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_575 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(_T_575, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_575, UInt<1>(0h1), "") : assert_13
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(is_aligned, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_582 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_582, UInt<1>(0h1), "") : assert_15
node _T_586 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_586, UInt<1>(0h1), "") : assert_16
node _T_590 = not(io.in.a.bits.mask)
node _T_591 = eq(_T_590, UInt<1>(0h0))
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(_T_591, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_591, UInt<1>(0h1), "") : assert_17
node _T_595 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_595, UInt<1>(0h1), "") : assert_18
node _T_599 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_599 :
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_602 = and(_T_600, _T_601)
node _T_603 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_604 = shr(io.in.a.bits.source, 2)
node _T_605 = eq(_T_604, UInt<1>(0h0))
node _T_606 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_607 = and(_T_605, _T_606)
node _T_608 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_609 = and(_T_607, _T_608)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_610 = shr(io.in.a.bits.source, 2)
node _T_611 = eq(_T_610, UInt<1>(0h1))
node _T_612 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_613 = and(_T_611, _T_612)
node _T_614 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_615 = and(_T_613, _T_614)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_616 = shr(io.in.a.bits.source, 2)
node _T_617 = eq(_T_616, UInt<2>(0h2))
node _T_618 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_619 = and(_T_617, _T_618)
node _T_620 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_621 = and(_T_619, _T_620)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_622 = shr(io.in.a.bits.source, 2)
node _T_623 = eq(_T_622, UInt<2>(0h3))
node _T_624 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_625 = and(_T_623, _T_624)
node _T_626 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_627 = and(_T_625, _T_626)
node _T_628 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_631 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_632 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_633 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_634 = or(_T_603, _T_609)
node _T_635 = or(_T_634, _T_615)
node _T_636 = or(_T_635, _T_621)
node _T_637 = or(_T_636, _T_627)
node _T_638 = or(_T_637, _T_628)
node _T_639 = or(_T_638, _T_629)
node _T_640 = or(_T_639, _T_630)
node _T_641 = or(_T_640, _T_631)
node _T_642 = or(_T_641, _T_632)
node _T_643 = or(_T_642, _T_633)
node _T_644 = and(_T_602, _T_643)
node _T_645 = or(UInt<1>(0h0), _T_644)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_645, UInt<1>(0h1), "") : assert_19
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<13>(0h1000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = or(_T_667, _T_672)
node _T_699 = or(_T_698, _T_677)
node _T_700 = or(_T_699, _T_682)
node _T_701 = or(_T_700, _T_687)
node _T_702 = or(_T_701, _T_692)
node _T_703 = or(_T_702, _T_697)
node _T_704 = and(_T_662, _T_703)
node _T_705 = or(UInt<1>(0h0), _T_658)
node _T_706 = or(_T_705, _T_704)
node _T_707 = asUInt(reset)
node _T_708 = eq(_T_707, UInt<1>(0h0))
when _T_708 :
node _T_709 = eq(_T_706, UInt<1>(0h0))
when _T_709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_706, UInt<1>(0h1), "") : assert_20
node _T_710 = asUInt(reset)
node _T_711 = eq(_T_710, UInt<1>(0h0))
when _T_711 :
node _T_712 = eq(source_ok, UInt<1>(0h0))
when _T_712 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(is_aligned, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_716 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_717 = asUInt(reset)
node _T_718 = eq(_T_717, UInt<1>(0h0))
when _T_718 :
node _T_719 = eq(_T_716, UInt<1>(0h0))
when _T_719 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_716, UInt<1>(0h1), "") : assert_23
node _T_720 = eq(io.in.a.bits.mask, mask)
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(_T_720, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_720, UInt<1>(0h1), "") : assert_24
node _T_724 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_724, UInt<1>(0h1), "") : assert_25
node _T_728 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_728 :
node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_731 = and(_T_729, _T_730)
node _T_732 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_733 = shr(io.in.a.bits.source, 2)
node _T_734 = eq(_T_733, UInt<1>(0h0))
node _T_735 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_736 = and(_T_734, _T_735)
node _T_737 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_738 = and(_T_736, _T_737)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_739 = shr(io.in.a.bits.source, 2)
node _T_740 = eq(_T_739, UInt<1>(0h1))
node _T_741 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_742 = and(_T_740, _T_741)
node _T_743 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_744 = and(_T_742, _T_743)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_745 = shr(io.in.a.bits.source, 2)
node _T_746 = eq(_T_745, UInt<2>(0h2))
node _T_747 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_748 = and(_T_746, _T_747)
node _T_749 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_750 = and(_T_748, _T_749)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_751 = shr(io.in.a.bits.source, 2)
node _T_752 = eq(_T_751, UInt<2>(0h3))
node _T_753 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_754 = and(_T_752, _T_753)
node _T_755 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_758 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_759 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_760 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_763 = or(_T_732, _T_738)
node _T_764 = or(_T_763, _T_744)
node _T_765 = or(_T_764, _T_750)
node _T_766 = or(_T_765, _T_756)
node _T_767 = or(_T_766, _T_757)
node _T_768 = or(_T_767, _T_758)
node _T_769 = or(_T_768, _T_759)
node _T_770 = or(_T_769, _T_760)
node _T_771 = or(_T_770, _T_761)
node _T_772 = or(_T_771, _T_762)
node _T_773 = and(_T_731, _T_772)
node _T_774 = or(UInt<1>(0h0), _T_773)
node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_776 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_777 = and(_T_775, _T_776)
node _T_778 = or(UInt<1>(0h0), _T_777)
node _T_779 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = and(_T_778, _T_783)
node _T_785 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_786 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_787 = and(_T_785, _T_786)
node _T_788 = or(UInt<1>(0h0), _T_787)
node _T_789 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_790 = cvt(_T_789)
node _T_791 = and(_T_790, asSInt(UInt<14>(0h2000)))
node _T_792 = asSInt(_T_791)
node _T_793 = eq(_T_792, asSInt(UInt<1>(0h0)))
node _T_794 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_795 = cvt(_T_794)
node _T_796 = and(_T_795, asSInt(UInt<18>(0h2f000)))
node _T_797 = asSInt(_T_796)
node _T_798 = eq(_T_797, asSInt(UInt<1>(0h0)))
node _T_799 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_800 = cvt(_T_799)
node _T_801 = and(_T_800, asSInt(UInt<17>(0h10000)))
node _T_802 = asSInt(_T_801)
node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0)))
node _T_804 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_805 = cvt(_T_804)
node _T_806 = and(_T_805, asSInt(UInt<13>(0h1000)))
node _T_807 = asSInt(_T_806)
node _T_808 = eq(_T_807, asSInt(UInt<1>(0h0)))
node _T_809 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_810 = cvt(_T_809)
node _T_811 = and(_T_810, asSInt(UInt<27>(0h4000000)))
node _T_812 = asSInt(_T_811)
node _T_813 = eq(_T_812, asSInt(UInt<1>(0h0)))
node _T_814 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_815 = cvt(_T_814)
node _T_816 = and(_T_815, asSInt(UInt<13>(0h1000)))
node _T_817 = asSInt(_T_816)
node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0)))
node _T_819 = or(_T_793, _T_798)
node _T_820 = or(_T_819, _T_803)
node _T_821 = or(_T_820, _T_808)
node _T_822 = or(_T_821, _T_813)
node _T_823 = or(_T_822, _T_818)
node _T_824 = and(_T_788, _T_823)
node _T_825 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_826 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_827 = cvt(_T_826)
node _T_828 = and(_T_827, asSInt(UInt<17>(0h10000)))
node _T_829 = asSInt(_T_828)
node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0)))
node _T_831 = and(_T_825, _T_830)
node _T_832 = or(UInt<1>(0h0), _T_784)
node _T_833 = or(_T_832, _T_824)
node _T_834 = or(_T_833, _T_831)
node _T_835 = and(_T_774, _T_834)
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_835, UInt<1>(0h1), "") : assert_26
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(source_ok, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(is_aligned, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_845 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_845, UInt<1>(0h1), "") : assert_29
node _T_849 = eq(io.in.a.bits.mask, mask)
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_849, UInt<1>(0h1), "") : assert_30
node _T_853 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_853 :
node _T_854 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_855 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_858 = shr(io.in.a.bits.source, 2)
node _T_859 = eq(_T_858, UInt<1>(0h0))
node _T_860 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_861 = and(_T_859, _T_860)
node _T_862 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_863 = and(_T_861, _T_862)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_864 = shr(io.in.a.bits.source, 2)
node _T_865 = eq(_T_864, UInt<1>(0h1))
node _T_866 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_867 = and(_T_865, _T_866)
node _T_868 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_869 = and(_T_867, _T_868)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_870 = shr(io.in.a.bits.source, 2)
node _T_871 = eq(_T_870, UInt<2>(0h2))
node _T_872 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_873 = and(_T_871, _T_872)
node _T_874 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_875 = and(_T_873, _T_874)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_876 = shr(io.in.a.bits.source, 2)
node _T_877 = eq(_T_876, UInt<2>(0h3))
node _T_878 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_879 = and(_T_877, _T_878)
node _T_880 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_888 = or(_T_857, _T_863)
node _T_889 = or(_T_888, _T_869)
node _T_890 = or(_T_889, _T_875)
node _T_891 = or(_T_890, _T_881)
node _T_892 = or(_T_891, _T_882)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_884)
node _T_895 = or(_T_894, _T_885)
node _T_896 = or(_T_895, _T_886)
node _T_897 = or(_T_896, _T_887)
node _T_898 = and(_T_856, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_901 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_902 = and(_T_900, _T_901)
node _T_903 = or(UInt<1>(0h0), _T_902)
node _T_904 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = and(_T_903, _T_908)
node _T_910 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_911 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_912 = and(_T_910, _T_911)
node _T_913 = or(UInt<1>(0h0), _T_912)
node _T_914 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<14>(0h2000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<18>(0h2f000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<27>(0h4000000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = or(_T_918, _T_923)
node _T_945 = or(_T_944, _T_928)
node _T_946 = or(_T_945, _T_933)
node _T_947 = or(_T_946, _T_938)
node _T_948 = or(_T_947, _T_943)
node _T_949 = and(_T_913, _T_948)
node _T_950 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_951 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<17>(0h10000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = and(_T_950, _T_955)
node _T_957 = or(UInt<1>(0h0), _T_909)
node _T_958 = or(_T_957, _T_949)
node _T_959 = or(_T_958, _T_956)
node _T_960 = and(_T_899, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_960, UInt<1>(0h1), "") : assert_31
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(source_ok, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(is_aligned, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_970 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_970, UInt<1>(0h1), "") : assert_34
node _T_974 = not(mask)
node _T_975 = and(io.in.a.bits.mask, _T_974)
node _T_976 = eq(_T_975, UInt<1>(0h0))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_976, UInt<1>(0h1), "") : assert_35
node _T_980 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_980 :
node _T_981 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_982 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_983 = and(_T_981, _T_982)
node _T_984 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_985 = shr(io.in.a.bits.source, 2)
node _T_986 = eq(_T_985, UInt<1>(0h0))
node _T_987 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_988 = and(_T_986, _T_987)
node _T_989 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_990 = and(_T_988, _T_989)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_991 = shr(io.in.a.bits.source, 2)
node _T_992 = eq(_T_991, UInt<1>(0h1))
node _T_993 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_994 = and(_T_992, _T_993)
node _T_995 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_996 = and(_T_994, _T_995)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_997 = shr(io.in.a.bits.source, 2)
node _T_998 = eq(_T_997, UInt<2>(0h2))
node _T_999 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1002 = and(_T_1000, _T_1001)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1003 = shr(io.in.a.bits.source, 2)
node _T_1004 = eq(_T_1003, UInt<2>(0h3))
node _T_1005 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1006 = and(_T_1004, _T_1005)
node _T_1007 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1015 = or(_T_984, _T_990)
node _T_1016 = or(_T_1015, _T_996)
node _T_1017 = or(_T_1016, _T_1002)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1009)
node _T_1020 = or(_T_1019, _T_1010)
node _T_1021 = or(_T_1020, _T_1011)
node _T_1022 = or(_T_1021, _T_1012)
node _T_1023 = or(_T_1022, _T_1013)
node _T_1024 = or(_T_1023, _T_1014)
node _T_1025 = and(_T_983, _T_1024)
node _T_1026 = or(UInt<1>(0h0), _T_1025)
node _T_1027 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1028 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1029 = and(_T_1027, _T_1028)
node _T_1030 = or(UInt<1>(0h0), _T_1029)
node _T_1031 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1032 = cvt(_T_1031)
node _T_1033 = and(_T_1032, asSInt(UInt<14>(0h2000)))
node _T_1034 = asSInt(_T_1033)
node _T_1035 = eq(_T_1034, asSInt(UInt<1>(0h0)))
node _T_1036 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1037 = cvt(_T_1036)
node _T_1038 = and(_T_1037, asSInt(UInt<13>(0h1000)))
node _T_1039 = asSInt(_T_1038)
node _T_1040 = eq(_T_1039, asSInt(UInt<1>(0h0)))
node _T_1041 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1042 = cvt(_T_1041)
node _T_1043 = and(_T_1042, asSInt(UInt<18>(0h2f000)))
node _T_1044 = asSInt(_T_1043)
node _T_1045 = eq(_T_1044, asSInt(UInt<1>(0h0)))
node _T_1046 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1047 = cvt(_T_1046)
node _T_1048 = and(_T_1047, asSInt(UInt<17>(0h10000)))
node _T_1049 = asSInt(_T_1048)
node _T_1050 = eq(_T_1049, asSInt(UInt<1>(0h0)))
node _T_1051 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<13>(0h1000)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<27>(0h4000000)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1062 = cvt(_T_1061)
node _T_1063 = and(_T_1062, asSInt(UInt<13>(0h1000)))
node _T_1064 = asSInt(_T_1063)
node _T_1065 = eq(_T_1064, asSInt(UInt<1>(0h0)))
node _T_1066 = or(_T_1035, _T_1040)
node _T_1067 = or(_T_1066, _T_1045)
node _T_1068 = or(_T_1067, _T_1050)
node _T_1069 = or(_T_1068, _T_1055)
node _T_1070 = or(_T_1069, _T_1060)
node _T_1071 = or(_T_1070, _T_1065)
node _T_1072 = and(_T_1030, _T_1071)
node _T_1073 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1074 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1075 = cvt(_T_1074)
node _T_1076 = and(_T_1075, asSInt(UInt<17>(0h10000)))
node _T_1077 = asSInt(_T_1076)
node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0)))
node _T_1079 = and(_T_1073, _T_1078)
node _T_1080 = or(UInt<1>(0h0), _T_1072)
node _T_1081 = or(_T_1080, _T_1079)
node _T_1082 = and(_T_1026, _T_1081)
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_36
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(source_ok, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(is_aligned, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1092 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_39
node _T_1096 = eq(io.in.a.bits.mask, mask)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_40
node _T_1100 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1100 :
node _T_1101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1103 = and(_T_1101, _T_1102)
node _T_1104 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1105 = shr(io.in.a.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1111 = shr(io.in.a.bits.source, 2)
node _T_1112 = eq(_T_1111, UInt<1>(0h1))
node _T_1113 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1114 = and(_T_1112, _T_1113)
node _T_1115 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1116 = and(_T_1114, _T_1115)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1117 = shr(io.in.a.bits.source, 2)
node _T_1118 = eq(_T_1117, UInt<2>(0h2))
node _T_1119 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1120 = and(_T_1118, _T_1119)
node _T_1121 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1122 = and(_T_1120, _T_1121)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1123 = shr(io.in.a.bits.source, 2)
node _T_1124 = eq(_T_1123, UInt<2>(0h3))
node _T_1125 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1126 = and(_T_1124, _T_1125)
node _T_1127 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1128 = and(_T_1126, _T_1127)
node _T_1129 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1130 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1131 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1132 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1133 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1134 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1135 = or(_T_1104, _T_1110)
node _T_1136 = or(_T_1135, _T_1116)
node _T_1137 = or(_T_1136, _T_1122)
node _T_1138 = or(_T_1137, _T_1128)
node _T_1139 = or(_T_1138, _T_1129)
node _T_1140 = or(_T_1139, _T_1130)
node _T_1141 = or(_T_1140, _T_1131)
node _T_1142 = or(_T_1141, _T_1132)
node _T_1143 = or(_T_1142, _T_1133)
node _T_1144 = or(_T_1143, _T_1134)
node _T_1145 = and(_T_1103, _T_1144)
node _T_1146 = or(UInt<1>(0h0), _T_1145)
node _T_1147 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1148 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1149 = and(_T_1147, _T_1148)
node _T_1150 = or(UInt<1>(0h0), _T_1149)
node _T_1151 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1152 = cvt(_T_1151)
node _T_1153 = and(_T_1152, asSInt(UInt<14>(0h2000)))
node _T_1154 = asSInt(_T_1153)
node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0)))
node _T_1156 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1157 = cvt(_T_1156)
node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000)))
node _T_1159 = asSInt(_T_1158)
node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0)))
node _T_1161 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1162 = cvt(_T_1161)
node _T_1163 = and(_T_1162, asSInt(UInt<18>(0h2f000)))
node _T_1164 = asSInt(_T_1163)
node _T_1165 = eq(_T_1164, asSInt(UInt<1>(0h0)))
node _T_1166 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1167 = cvt(_T_1166)
node _T_1168 = and(_T_1167, asSInt(UInt<17>(0h10000)))
node _T_1169 = asSInt(_T_1168)
node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0)))
node _T_1171 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1172 = cvt(_T_1171)
node _T_1173 = and(_T_1172, asSInt(UInt<13>(0h1000)))
node _T_1174 = asSInt(_T_1173)
node _T_1175 = eq(_T_1174, asSInt(UInt<1>(0h0)))
node _T_1176 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1177 = cvt(_T_1176)
node _T_1178 = and(_T_1177, asSInt(UInt<27>(0h4000000)))
node _T_1179 = asSInt(_T_1178)
node _T_1180 = eq(_T_1179, asSInt(UInt<1>(0h0)))
node _T_1181 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1182 = cvt(_T_1181)
node _T_1183 = and(_T_1182, asSInt(UInt<13>(0h1000)))
node _T_1184 = asSInt(_T_1183)
node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0)))
node _T_1186 = or(_T_1155, _T_1160)
node _T_1187 = or(_T_1186, _T_1165)
node _T_1188 = or(_T_1187, _T_1170)
node _T_1189 = or(_T_1188, _T_1175)
node _T_1190 = or(_T_1189, _T_1180)
node _T_1191 = or(_T_1190, _T_1185)
node _T_1192 = and(_T_1150, _T_1191)
node _T_1193 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1194 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1195 = cvt(_T_1194)
node _T_1196 = and(_T_1195, asSInt(UInt<17>(0h10000)))
node _T_1197 = asSInt(_T_1196)
node _T_1198 = eq(_T_1197, asSInt(UInt<1>(0h0)))
node _T_1199 = and(_T_1193, _T_1198)
node _T_1200 = or(UInt<1>(0h0), _T_1192)
node _T_1201 = or(_T_1200, _T_1199)
node _T_1202 = and(_T_1146, _T_1201)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_41
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(source_ok, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(is_aligned, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1212 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_44
node _T_1216 = eq(io.in.a.bits.mask, mask)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_45
node _T_1220 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1220 :
node _T_1221 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1222 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1225 = shr(io.in.a.bits.source, 2)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
node _T_1227 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1230 = and(_T_1228, _T_1229)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1231 = shr(io.in.a.bits.source, 2)
node _T_1232 = eq(_T_1231, UInt<1>(0h1))
node _T_1233 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1236 = and(_T_1234, _T_1235)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1237 = shr(io.in.a.bits.source, 2)
node _T_1238 = eq(_T_1237, UInt<2>(0h2))
node _T_1239 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1240 = and(_T_1238, _T_1239)
node _T_1241 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1242 = and(_T_1240, _T_1241)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1243 = shr(io.in.a.bits.source, 2)
node _T_1244 = eq(_T_1243, UInt<2>(0h3))
node _T_1245 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1246 = and(_T_1244, _T_1245)
node _T_1247 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1248 = and(_T_1246, _T_1247)
node _T_1249 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1250 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1251 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1252 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1253 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1254 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1255 = or(_T_1224, _T_1230)
node _T_1256 = or(_T_1255, _T_1236)
node _T_1257 = or(_T_1256, _T_1242)
node _T_1258 = or(_T_1257, _T_1248)
node _T_1259 = or(_T_1258, _T_1249)
node _T_1260 = or(_T_1259, _T_1250)
node _T_1261 = or(_T_1260, _T_1251)
node _T_1262 = or(_T_1261, _T_1252)
node _T_1263 = or(_T_1262, _T_1253)
node _T_1264 = or(_T_1263, _T_1254)
node _T_1265 = and(_T_1223, _T_1264)
node _T_1266 = or(UInt<1>(0h0), _T_1265)
node _T_1267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = or(UInt<1>(0h0), _T_1269)
node _T_1271 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1272 = cvt(_T_1271)
node _T_1273 = and(_T_1272, asSInt(UInt<13>(0h1000)))
node _T_1274 = asSInt(_T_1273)
node _T_1275 = eq(_T_1274, asSInt(UInt<1>(0h0)))
node _T_1276 = and(_T_1270, _T_1275)
node _T_1277 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1279 = cvt(_T_1278)
node _T_1280 = and(_T_1279, asSInt(UInt<14>(0h2000)))
node _T_1281 = asSInt(_T_1280)
node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1284 = cvt(_T_1283)
node _T_1285 = and(_T_1284, asSInt(UInt<17>(0h10000)))
node _T_1286 = asSInt(_T_1285)
node _T_1287 = eq(_T_1286, asSInt(UInt<1>(0h0)))
node _T_1288 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1289 = cvt(_T_1288)
node _T_1290 = and(_T_1289, asSInt(UInt<18>(0h2f000)))
node _T_1291 = asSInt(_T_1290)
node _T_1292 = eq(_T_1291, asSInt(UInt<1>(0h0)))
node _T_1293 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1294 = cvt(_T_1293)
node _T_1295 = and(_T_1294, asSInt(UInt<17>(0h10000)))
node _T_1296 = asSInt(_T_1295)
node _T_1297 = eq(_T_1296, asSInt(UInt<1>(0h0)))
node _T_1298 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1299 = cvt(_T_1298)
node _T_1300 = and(_T_1299, asSInt(UInt<13>(0h1000)))
node _T_1301 = asSInt(_T_1300)
node _T_1302 = eq(_T_1301, asSInt(UInt<1>(0h0)))
node _T_1303 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1304 = cvt(_T_1303)
node _T_1305 = and(_T_1304, asSInt(UInt<27>(0h4000000)))
node _T_1306 = asSInt(_T_1305)
node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0)))
node _T_1308 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1309 = cvt(_T_1308)
node _T_1310 = and(_T_1309, asSInt(UInt<13>(0h1000)))
node _T_1311 = asSInt(_T_1310)
node _T_1312 = eq(_T_1311, asSInt(UInt<1>(0h0)))
node _T_1313 = or(_T_1282, _T_1287)
node _T_1314 = or(_T_1313, _T_1292)
node _T_1315 = or(_T_1314, _T_1297)
node _T_1316 = or(_T_1315, _T_1302)
node _T_1317 = or(_T_1316, _T_1307)
node _T_1318 = or(_T_1317, _T_1312)
node _T_1319 = and(_T_1277, _T_1318)
node _T_1320 = or(UInt<1>(0h0), _T_1276)
node _T_1321 = or(_T_1320, _T_1319)
node _T_1322 = and(_T_1266, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_46
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(source_ok, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(is_aligned, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1332 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_49
node _T_1336 = eq(io.in.a.bits.mask, mask)
node _T_1337 = asUInt(reset)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
when _T_1338 :
node _T_1339 = eq(_T_1336, UInt<1>(0h0))
when _T_1339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1336, UInt<1>(0h1), "") : assert_50
node _T_1340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1344 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(_T_1344, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1344, UInt<1>(0h1), "") : assert_52
node _source_ok_T_40 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_41 = shr(io.in.d.bits.source, 2)
node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h0))
node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<1>(0h1))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h2))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<2>(0h3))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_40
connect _source_ok_WIRE_1[1], _source_ok_T_46
connect _source_ok_WIRE_1[2], _source_ok_T_52
connect _source_ok_WIRE_1[3], _source_ok_T_58
connect _source_ok_WIRE_1[4], _source_ok_T_64
connect _source_ok_WIRE_1[5], _source_ok_T_65
connect _source_ok_WIRE_1[6], _source_ok_T_66
connect _source_ok_WIRE_1[7], _source_ok_T_67
connect _source_ok_WIRE_1[8], _source_ok_T_68
connect _source_ok_WIRE_1[9], _source_ok_T_69
connect _source_ok_WIRE_1[10], _source_ok_T_70
node _source_ok_T_71 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[2])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[3])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[4])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[5])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[6])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[7])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[8])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_79, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1348 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1348 :
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(source_ok_1, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1352 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_54
node _T_1356 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1357 = asUInt(reset)
node _T_1358 = eq(_T_1357, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = eq(_T_1356, UInt<1>(0h0))
when _T_1359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1356, UInt<1>(0h1), "") : assert_55
node _T_1360 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_56
node _T_1364 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_57
node _T_1368 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1368 :
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(source_ok_1, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(sink_ok, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1375 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_60
node _T_1379 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_61
node _T_1383 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_62
node _T_1387 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(_T_1387, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1387, UInt<1>(0h1), "") : assert_63
node _T_1391 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1392 = or(UInt<1>(0h1), _T_1391)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_64
node _T_1396 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1396 :
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(source_ok_1, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(sink_ok, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1403 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1404 = asUInt(reset)
node _T_1405 = eq(_T_1404, UInt<1>(0h0))
when _T_1405 :
node _T_1406 = eq(_T_1403, UInt<1>(0h0))
when _T_1406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1403, UInt<1>(0h1), "") : assert_67
node _T_1407 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_68
node _T_1411 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1412 = asUInt(reset)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
when _T_1413 :
node _T_1414 = eq(_T_1411, UInt<1>(0h0))
when _T_1414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1411, UInt<1>(0h1), "") : assert_69
node _T_1415 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1416 = or(_T_1415, io.in.d.bits.corrupt)
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_70
node _T_1420 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1421 = or(UInt<1>(0h1), _T_1420)
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_71
node _T_1425 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(source_ok_1, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1429 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_73
node _T_1433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(_T_1433, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1433, UInt<1>(0h1), "") : assert_74
node _T_1437 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1438 = or(UInt<1>(0h1), _T_1437)
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(_T_1438, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1438, UInt<1>(0h1), "") : assert_75
node _T_1442 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1442 :
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(source_ok_1, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1446 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(_T_1446, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1446, UInt<1>(0h1), "") : assert_77
node _T_1450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1451 = or(_T_1450, io.in.d.bits.corrupt)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_78
node _T_1455 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1456 = or(UInt<1>(0h1), _T_1455)
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(_T_1456, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1456, UInt<1>(0h1), "") : assert_79
node _T_1460 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1460 :
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(source_ok_1, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_81
node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_82
node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1473 = or(UInt<1>(0h1), _T_1472)
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(_T_1473, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1473, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<6>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1477 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1478 = asUInt(reset)
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(_T_1477, UInt<1>(0h0))
when _T_1480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1477, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1481 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1485 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1489 = eq(a_first, UInt<1>(0h0))
node _T_1490 = and(io.in.a.valid, _T_1489)
when _T_1490 :
node _T_1491 = eq(io.in.a.bits.opcode, opcode)
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_87
node _T_1495 = eq(io.in.a.bits.param, param)
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_88
node _T_1499 = eq(io.in.a.bits.size, size)
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_89
node _T_1503 = eq(io.in.a.bits.source, source)
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_90
node _T_1507 = eq(io.in.a.bits.address, address)
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_91
node _T_1511 = and(io.in.a.ready, io.in.a.valid)
node _T_1512 = and(_T_1511, a_first)
when _T_1512 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1513 = eq(d_first, UInt<1>(0h0))
node _T_1514 = and(io.in.d.valid, _T_1513)
when _T_1514 :
node _T_1515 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_92
node _T_1519 = eq(io.in.d.bits.param, param_1)
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_93
node _T_1523 = eq(io.in.d.bits.size, size_1)
node _T_1524 = asUInt(reset)
node _T_1525 = eq(_T_1524, UInt<1>(0h0))
when _T_1525 :
node _T_1526 = eq(_T_1523, UInt<1>(0h0))
when _T_1526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1523, UInt<1>(0h1), "") : assert_94
node _T_1527 = eq(io.in.d.bits.source, source_1)
node _T_1528 = asUInt(reset)
node _T_1529 = eq(_T_1528, UInt<1>(0h0))
when _T_1529 :
node _T_1530 = eq(_T_1527, UInt<1>(0h0))
when _T_1530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1527, UInt<1>(0h1), "") : assert_95
node _T_1531 = eq(io.in.d.bits.sink, sink)
node _T_1532 = asUInt(reset)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = eq(_T_1531, UInt<1>(0h0))
when _T_1534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1531, UInt<1>(0h1), "") : assert_96
node _T_1535 = eq(io.in.d.bits.denied, denied)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_97
node _T_1539 = and(io.in.d.ready, io.in.d.valid)
node _T_1540 = and(_T_1539, d_first)
when _T_1540 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<39>, clock, reset, UInt<39>(0h0)
regreset inflight_opcodes : UInt<156>, clock, reset, UInt<156>(0h0)
regreset inflight_sizes : UInt<312>, clock, reset, UInt<312>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<39>
connect a_set, UInt<39>(0h0)
wire a_set_wo_ready : UInt<39>
connect a_set_wo_ready, UInt<39>(0h0)
wire a_opcodes_set : UInt<156>
connect a_opcodes_set, UInt<156>(0h0)
wire a_sizes_set : UInt<312>
connect a_sizes_set, UInt<312>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1541 = and(io.in.a.valid, a_first_1)
node _T_1542 = and(_T_1541, UInt<1>(0h1))
when _T_1542 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1543 = and(io.in.a.ready, io.in.a.valid)
node _T_1544 = and(_T_1543, a_first_1)
node _T_1545 = and(_T_1544, UInt<1>(0h1))
when _T_1545 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1546 = dshr(inflight, io.in.a.bits.source)
node _T_1547 = bits(_T_1546, 0, 0)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
node _T_1549 = asUInt(reset)
node _T_1550 = eq(_T_1549, UInt<1>(0h0))
when _T_1550 :
node _T_1551 = eq(_T_1548, UInt<1>(0h0))
when _T_1551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1548, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<39>
connect d_clr, UInt<39>(0h0)
wire d_clr_wo_ready : UInt<39>
connect d_clr_wo_ready, UInt<39>(0h0)
wire d_opcodes_clr : UInt<156>
connect d_opcodes_clr, UInt<156>(0h0)
wire d_sizes_clr : UInt<312>
connect d_sizes_clr, UInt<312>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1552 = and(io.in.d.valid, d_first_1)
node _T_1553 = and(_T_1552, UInt<1>(0h1))
node _T_1554 = eq(d_release_ack, UInt<1>(0h0))
node _T_1555 = and(_T_1553, _T_1554)
when _T_1555 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1556 = and(io.in.d.ready, io.in.d.valid)
node _T_1557 = and(_T_1556, d_first_1)
node _T_1558 = and(_T_1557, UInt<1>(0h1))
node _T_1559 = eq(d_release_ack, UInt<1>(0h0))
node _T_1560 = and(_T_1558, _T_1559)
when _T_1560 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1561 = and(io.in.d.valid, d_first_1)
node _T_1562 = and(_T_1561, UInt<1>(0h1))
node _T_1563 = eq(d_release_ack, UInt<1>(0h0))
node _T_1564 = and(_T_1562, _T_1563)
when _T_1564 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1565 = dshr(inflight, io.in.d.bits.source)
node _T_1566 = bits(_T_1565, 0, 0)
node _T_1567 = or(_T_1566, same_cycle_resp)
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1571 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1572 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1573 = or(_T_1571, _T_1572)
node _T_1574 = asUInt(reset)
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
when _T_1575 :
node _T_1576 = eq(_T_1573, UInt<1>(0h0))
when _T_1576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1573, UInt<1>(0h1), "") : assert_100
node _T_1577 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1578 = asUInt(reset)
node _T_1579 = eq(_T_1578, UInt<1>(0h0))
when _T_1579 :
node _T_1580 = eq(_T_1577, UInt<1>(0h0))
when _T_1580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1577, UInt<1>(0h1), "") : assert_101
else :
node _T_1581 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1582 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1583 = or(_T_1581, _T_1582)
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(_T_1583, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1583, UInt<1>(0h1), "") : assert_102
node _T_1587 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(_T_1587, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1587, UInt<1>(0h1), "") : assert_103
node _T_1591 = and(io.in.d.valid, d_first_1)
node _T_1592 = and(_T_1591, a_first_1)
node _T_1593 = and(_T_1592, io.in.a.valid)
node _T_1594 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1595 = and(_T_1593, _T_1594)
node _T_1596 = eq(d_release_ack, UInt<1>(0h0))
node _T_1597 = and(_T_1595, _T_1596)
when _T_1597 :
node _T_1598 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1599 = or(_T_1598, io.in.a.ready)
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_104
node _T_1603 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1604 = orr(a_set_wo_ready)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
node _T_1606 = or(_T_1603, _T_1605)
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(_T_1606, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1606, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_30
node _T_1610 = orr(inflight)
node _T_1611 = eq(_T_1610, UInt<1>(0h0))
node _T_1612 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1613 = or(_T_1611, _T_1612)
node _T_1614 = lt(watchdog, plusarg_reader.out)
node _T_1615 = or(_T_1613, _T_1614)
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1619 = and(io.in.a.ready, io.in.a.valid)
node _T_1620 = and(io.in.d.ready, io.in.d.valid)
node _T_1621 = or(_T_1619, _T_1620)
when _T_1621 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<39>, clock, reset, UInt<39>(0h0)
regreset inflight_opcodes_1 : UInt<156>, clock, reset, UInt<156>(0h0)
regreset inflight_sizes_1 : UInt<312>, clock, reset, UInt<312>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<39>
connect c_set, UInt<39>(0h0)
wire c_set_wo_ready : UInt<39>
connect c_set_wo_ready, UInt<39>(0h0)
wire c_opcodes_set : UInt<156>
connect c_opcodes_set, UInt<156>(0h0)
wire c_sizes_set : UInt<312>
connect c_sizes_set, UInt<312>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1622 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1623 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1624 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1625 = and(_T_1623, _T_1624)
node _T_1626 = and(_T_1622, _T_1625)
when _T_1626 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1627 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1628 = and(_T_1627, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1629 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1630 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1631 = and(_T_1629, _T_1630)
node _T_1632 = and(_T_1628, _T_1631)
when _T_1632 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1633 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1634 = bits(_T_1633, 0, 0)
node _T_1635 = eq(_T_1634, UInt<1>(0h0))
node _T_1636 = asUInt(reset)
node _T_1637 = eq(_T_1636, UInt<1>(0h0))
when _T_1637 :
node _T_1638 = eq(_T_1635, UInt<1>(0h0))
when _T_1638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1635, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<39>
connect d_clr_1, UInt<39>(0h0)
wire d_clr_wo_ready_1 : UInt<39>
connect d_clr_wo_ready_1, UInt<39>(0h0)
wire d_opcodes_clr_1 : UInt<156>
connect d_opcodes_clr_1, UInt<156>(0h0)
wire d_sizes_clr_1 : UInt<312>
connect d_sizes_clr_1, UInt<312>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1639 = and(io.in.d.valid, d_first_2)
node _T_1640 = and(_T_1639, UInt<1>(0h1))
node _T_1641 = and(_T_1640, d_release_ack_1)
when _T_1641 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1642 = and(io.in.d.ready, io.in.d.valid)
node _T_1643 = and(_T_1642, d_first_2)
node _T_1644 = and(_T_1643, UInt<1>(0h1))
node _T_1645 = and(_T_1644, d_release_ack_1)
when _T_1645 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1646 = and(io.in.d.valid, d_first_2)
node _T_1647 = and(_T_1646, UInt<1>(0h1))
node _T_1648 = and(_T_1647, d_release_ack_1)
when _T_1648 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1649 = dshr(inflight_1, io.in.d.bits.source)
node _T_1650 = bits(_T_1649, 0, 0)
node _T_1651 = or(_T_1650, same_cycle_resp_1)
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(_T_1651, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1651, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1655 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(_T_1655, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1655, UInt<1>(0h1), "") : assert_109
else :
node _T_1659 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1660 = asUInt(reset)
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(_T_1659, UInt<1>(0h0))
when _T_1662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1659, UInt<1>(0h1), "") : assert_110
node _T_1663 = and(io.in.d.valid, d_first_2)
node _T_1664 = and(_T_1663, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1665 = and(_T_1664, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1666 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1667 = and(_T_1665, _T_1666)
node _T_1668 = and(_T_1667, d_release_ack_1)
node _T_1669 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1670 = and(_T_1668, _T_1669)
when _T_1670 :
node _T_1671 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<6>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1672 = or(_T_1671, _WIRE_27.ready)
node _T_1673 = asUInt(reset)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
when _T_1674 :
node _T_1675 = eq(_T_1672, UInt<1>(0h0))
when _T_1675 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1672, UInt<1>(0h1), "") : assert_111
node _T_1676 = orr(c_set_wo_ready)
when _T_1676 :
node _T_1677 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1678 = asUInt(reset)
node _T_1679 = eq(_T_1678, UInt<1>(0h0))
when _T_1679 :
node _T_1680 = eq(_T_1677, UInt<1>(0h0))
when _T_1680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1677, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_31
node _T_1681 = orr(inflight_1)
node _T_1682 = eq(_T_1681, UInt<1>(0h0))
node _T_1683 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1684 = or(_T_1682, _T_1683)
node _T_1685 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1686 = or(_T_1684, _T_1685)
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(_T_1686, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1686, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<6>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1690 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1691 = and(io.in.d.ready, io.in.d.valid)
node _T_1692 = or(_T_1690, _T_1691)
when _T_1692 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_32 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_33 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_15( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [311:0] c_sizes_set = 312'h0; // @[Monitor.scala:741:34]
wire [155:0] c_opcodes_set = 156'h0; // @[Monitor.scala:740:34]
wire [38:0] c_set = 39'h0; // @[Monitor.scala:738:34]
wire [38:0] c_set_wo_ready = 39'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_39 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_41 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_47 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_53 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_59 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_42 = _source_ok_T_41 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire _source_ok_T_66 = io_in_d_bits_source_0 == 6'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire _source_ok_T_67 = io_in_d_bits_source_0 == 6'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire _source_ok_T_68 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire _source_ok_T_69 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_79 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1619 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1619; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1619; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1692 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1692; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1692; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1692; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [38:0] inflight; // @[Monitor.scala:614:27]
reg [155:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [311:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [38:0] a_set; // @[Monitor.scala:626:34]
wire [38:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [155:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [311:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [155:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [155:0] _a_opcode_lookup_T_6 = {152'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [155:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [311:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [311:0] _a_size_lookup_T_6 = {304'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [311:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[311:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire _T_1545 = _T_1619 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1545 ? _a_set_T[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1545 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1545 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1545 ? _a_opcodes_set_T_1[155:0] : 156'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1545 ? _a_sizes_set_T_1[311:0] : 312'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [38:0] d_clr; // @[Monitor.scala:664:34]
wire [38:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [155:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [311:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1591 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1591 & ~d_release_ack ? _d_clr_wo_ready_T[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire _T_1560 = _T_1692 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1560 ? _d_clr_T[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1560 ? _d_opcodes_clr_T_5[155:0] : 156'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1560 ? _d_sizes_clr_T_5[311:0] : 312'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [38:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [38:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [38:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [155:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [155:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [155:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [311:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [311:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [311:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [38:0] inflight_1; // @[Monitor.scala:726:35]
wire [38:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [155:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [155:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [311:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [311:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [155:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [155:0] _c_opcode_lookup_T_6 = {152'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [155:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[155:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [311:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [311:0] _c_size_lookup_T_6 = {304'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [311:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[311:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [38:0] d_clr_1; // @[Monitor.scala:774:34]
wire [38:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [155:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [311:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1663 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1663 & d_release_ack_1 ? _d_clr_wo_ready_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire _T_1645 = _T_1692 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1645 ? _d_clr_T_1[38:0] : 39'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1645 ? _d_opcodes_clr_T_11[155:0] : 156'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1645 ? _d_sizes_clr_T_11[311:0] : 312'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [38:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [38:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [155:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [155:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [311:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [311:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_241 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_497
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_241( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_497 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_125 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_125( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLError_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_47
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire da : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
regreset idle : UInt<1>, clock, reset, UInt<1>(0h1)
node _a_last_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_last_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _a_last_beats1_decode_T_1 = bits(_a_last_beats1_decode_T, 1, 0)
node _a_last_beats1_decode_T_2 = not(_a_last_beats1_decode_T_1)
node a_last_beats1_decode = shr(_a_last_beats1_decode_T_2, 2)
node _a_last_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node a_last_beats1_opdata = eq(_a_last_beats1_opdata_T, UInt<1>(0h0))
node a_last_beats1 = mux(a_last_beats1_opdata, a_last_beats1_decode, UInt<1>(0h0))
regreset a_last_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_last_counter1_T = sub(a_last_counter, UInt<1>(0h1))
node a_last_counter1 = tail(_a_last_counter1_T, 1)
node a_last_first = eq(a_last_counter, UInt<1>(0h0))
node _a_last_last_T = eq(a_last_counter, UInt<1>(0h1))
node _a_last_last_T_1 = eq(a_last_beats1, UInt<1>(0h0))
node a_last = or(_a_last_last_T, _a_last_last_T_1)
node a_last_done = and(a_last, _a_last_T)
node _a_last_count_T = not(a_last_counter1)
node a_last_count = and(a_last_beats1, _a_last_count_T)
when _a_last_T :
node _a_last_counter_T = mux(a_last_first, a_last_beats1, a_last_counter1)
connect a_last_counter, _a_last_counter_T
node _T = and(da.ready, da.valid)
node _r_beats1_decode_T = dshl(UInt<2>(0h3), da.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 2)
node r_beats1_opdata = bits(da.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node da_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node da_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(da_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(da_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node _T_1 = or(idle, da_first)
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Error.scala:34 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _nodeIn_a_ready_T = and(da.ready, da_last)
node _nodeIn_a_ready_T_1 = and(_nodeIn_a_ready_T, idle)
node _nodeIn_a_ready_T_2 = eq(a_last, UInt<1>(0h0))
node _nodeIn_a_ready_T_3 = or(_nodeIn_a_ready_T_1, _nodeIn_a_ready_T_2)
connect nodeIn.a.ready, _nodeIn_a_ready_T_3
node _da_valid_T = and(nodeIn.a.valid, a_last)
node _da_valid_T_1 = and(_da_valid_T, idle)
connect da.valid, _da_valid_T_1
wire _da_bits_opcode_WIRE : UInt<3>[8]
connect _da_bits_opcode_WIRE[0], UInt<1>(0h0)
connect _da_bits_opcode_WIRE[1], UInt<1>(0h0)
connect _da_bits_opcode_WIRE[2], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[3], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[4], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[5], UInt<2>(0h2)
connect _da_bits_opcode_WIRE[6], UInt<3>(0h4)
connect _da_bits_opcode_WIRE[7], UInt<3>(0h4)
connect da.bits.opcode, _da_bits_opcode_WIRE[nodeIn.a.bits.opcode]
connect da.bits.param, UInt<1>(0h0)
connect da.bits.size, nodeIn.a.bits.size
connect da.bits.source, nodeIn.a.bits.source
connect da.bits.sink, UInt<1>(0h0)
connect da.bits.denied, UInt<1>(0h1)
connect da.bits.data, UInt<1>(0h0)
node da_bits_corrupt_opdata = bits(da.bits.opcode, 0, 0)
connect da.bits.corrupt, da_bits_corrupt_opdata
wire _c_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_WIRE.bits.data, UInt<32>(0h0)
connect _c_WIRE.bits.address, UInt<128>(0h0)
connect _c_WIRE.bits.source, UInt<1>(0h0)
connect _c_WIRE.bits.size, UInt<2>(0h0)
connect _c_WIRE.bits.param, UInt<3>(0h0)
connect _c_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_WIRE.valid, UInt<1>(0h0)
connect _c_WIRE.ready, UInt<1>(0h0)
wire c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect c.bits, _c_WIRE.bits
connect c.valid, _c_WIRE.valid
connect c.ready, _c_WIRE.ready
wire dc : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
node _c_last_T = and(c.ready, c.valid)
node _c_last_beats1_decode_T = dshl(UInt<2>(0h3), c.bits.size)
node _c_last_beats1_decode_T_1 = bits(_c_last_beats1_decode_T, 1, 0)
node _c_last_beats1_decode_T_2 = not(_c_last_beats1_decode_T_1)
node c_last_beats1_decode = shr(_c_last_beats1_decode_T_2, 2)
node c_last_beats1_opdata = bits(c.bits.opcode, 0, 0)
node c_last_beats1 = mux(UInt<1>(0h0), c_last_beats1_decode, UInt<1>(0h0))
regreset c_last_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_last_counter1_T = sub(c_last_counter, UInt<1>(0h1))
node c_last_counter1 = tail(_c_last_counter1_T, 1)
node c_last_first = eq(c_last_counter, UInt<1>(0h0))
node _c_last_last_T = eq(c_last_counter, UInt<1>(0h1))
node _c_last_last_T_1 = eq(c_last_beats1, UInt<1>(0h0))
node c_last = or(_c_last_last_T, _c_last_last_T_1)
node c_last_done = and(c_last, _c_last_T)
node _c_last_count_T = not(c_last_counter1)
node c_last_count = and(c_last_beats1, _c_last_count_T)
when _c_last_T :
node _c_last_counter_T = mux(c_last_first, c_last_beats1, c_last_counter1)
connect c_last_counter, _c_last_counter_T
node _dc_last_T = and(dc.ready, dc.valid)
node _dc_last_beats1_decode_T = dshl(UInt<2>(0h3), dc.bits.size)
node _dc_last_beats1_decode_T_1 = bits(_dc_last_beats1_decode_T, 1, 0)
node _dc_last_beats1_decode_T_2 = not(_dc_last_beats1_decode_T_1)
node dc_last_beats1_decode = shr(_dc_last_beats1_decode_T_2, 2)
node dc_last_beats1_opdata = bits(dc.bits.opcode, 0, 0)
node dc_last_beats1 = mux(dc_last_beats1_opdata, dc_last_beats1_decode, UInt<1>(0h0))
regreset dc_last_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _dc_last_counter1_T = sub(dc_last_counter, UInt<1>(0h1))
node dc_last_counter1 = tail(_dc_last_counter1_T, 1)
node dc_last_first = eq(dc_last_counter, UInt<1>(0h0))
node _dc_last_last_T = eq(dc_last_counter, UInt<1>(0h1))
node _dc_last_last_T_1 = eq(dc_last_beats1, UInt<1>(0h0))
node dc_last = or(_dc_last_last_T, _dc_last_last_T_1)
node dc_last_done = and(dc_last, _dc_last_T)
node _dc_last_count_T = not(dc_last_counter1)
node dc_last_count = and(dc_last_beats1, _dc_last_count_T)
when _dc_last_T :
node _dc_last_counter_T = mux(dc_last_first, dc_last_beats1, dc_last_counter1)
connect dc_last_counter, _dc_last_counter_T
node _T_5 = and(da.ready, da.valid)
node _T_6 = eq(da.bits.opcode, UInt<3>(0h4))
node _T_7 = and(_T_5, _T_6)
when _T_7 :
connect idle, UInt<1>(0h0)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE.bits.sink, UInt<1>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_8 = and(_WIRE_1.ready, _WIRE_1.valid)
when _T_8 :
connect idle, UInt<1>(0h1)
node _c_ready_T = and(dc.ready, dc_last)
node _c_ready_T_1 = eq(c_last, UInt<1>(0h0))
node _c_ready_T_2 = or(_c_ready_T, _c_ready_T_1)
connect c.ready, _c_ready_T_2
node _dc_valid_T = and(c.valid, c_last)
connect dc.valid, _dc_valid_T
connect dc.bits.opcode, UInt<3>(0h6)
wire _dc_bits_param_WIRE : UInt<2>[3]
connect _dc_bits_param_WIRE[0], UInt<2>(0h1)
connect _dc_bits_param_WIRE[1], UInt<2>(0h2)
connect _dc_bits_param_WIRE[2], UInt<2>(0h2)
node _dc_bits_param_T = bits(c.bits.param, 1, 0)
connect dc.bits.param, _dc_bits_param_WIRE[_dc_bits_param_T]
connect dc.bits.size, c.bits.size
connect dc.bits.source, c.bits.source
connect dc.bits.sink, UInt<1>(0h0)
connect dc.bits.denied, UInt<1>(0h0)
connect dc.bits.data, UInt<1>(0h0)
connect dc.bits.corrupt, UInt<1>(0h0)
node _decode_T = dshl(UInt<2>(0h3), dc.bits.size)
node _decode_T_1 = bits(_decode_T, 1, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 2)
node opdata = bits(dc.bits.opcode, 0, 0)
node _T_9 = mux(opdata, decode, UInt<1>(0h0))
node _decode_T_3 = dshl(UInt<2>(0h3), da.bits.size)
node _decode_T_4 = bits(_decode_T_3, 1, 0)
node _decode_T_5 = not(_decode_T_4)
node decode_1 = shr(_decode_T_5, 2)
node opdata_1 = bits(da.bits.opcode, 0, 0)
node _T_10 = mux(opdata_1, decode_1, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle_1, nodeIn.d.ready)
node _readys_T = cat(da.valid, dc.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], dc.valid)
node _winner_T_1 = and(readys[1], da.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_11 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_12 = eq(winner[0], UInt<1>(0h0))
node _T_13 = or(_T_11, _T_12)
node _T_14 = eq(prefixOR_1, UInt<1>(0h0))
node _T_15 = eq(winner[1], UInt<1>(0h0))
node _T_16 = or(_T_14, _T_15)
node _T_17 = and(_T_13, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_1
assert(clock, _T_17, UInt<1>(0h1), "") : assert_1
node _T_21 = or(dc.valid, da.valid)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = or(winner[0], winner[1])
node _T_24 = or(_T_22, _T_23)
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
node _T_27 = eq(_T_24, UInt<1>(0h0))
when _T_27 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_2
assert(clock, _T_24, UInt<1>(0h1), "") : assert_2
node maskedBeats_0 = mux(winner[0], _T_9, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_10, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle_1, winner, state)
connect state, muxState
node allowed = mux(idle_1, readys, state)
node _dc_ready_T = and(nodeIn.d.ready, allowed[0])
connect dc.ready, _dc_ready_T
node _da_ready_T = and(nodeIn.d.ready, allowed[1])
connect da.ready, _da_ready_T
node _nodeIn_d_valid_T = or(dc.valid, da.valid)
node _nodeIn_d_valid_T_1 = mux(state[0], dc.valid, UInt<1>(0h0))
node _nodeIn_d_valid_T_2 = mux(state[1], da.valid, UInt<1>(0h0))
node _nodeIn_d_valid_T_3 = or(_nodeIn_d_valid_T_1, _nodeIn_d_valid_T_2)
wire _nodeIn_d_valid_WIRE : UInt<1>
connect _nodeIn_d_valid_WIRE, _nodeIn_d_valid_T_3
node _nodeIn_d_valid_T_4 = mux(idle_1, _nodeIn_d_valid_T, _nodeIn_d_valid_WIRE)
connect nodeIn.d.valid, _nodeIn_d_valid_T_4
wire _nodeIn_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
node _nodeIn_d_bits_T = mux(muxState[0], dc.bits.corrupt, UInt<1>(0h0))
node _nodeIn_d_bits_T_1 = mux(muxState[1], da.bits.corrupt, UInt<1>(0h0))
node _nodeIn_d_bits_T_2 = or(_nodeIn_d_bits_T, _nodeIn_d_bits_T_1)
wire _nodeIn_d_bits_WIRE_1 : UInt<1>
connect _nodeIn_d_bits_WIRE_1, _nodeIn_d_bits_T_2
connect _nodeIn_d_bits_WIRE.corrupt, _nodeIn_d_bits_WIRE_1
node _nodeIn_d_bits_T_3 = mux(muxState[0], dc.bits.data, UInt<1>(0h0))
node _nodeIn_d_bits_T_4 = mux(muxState[1], da.bits.data, UInt<1>(0h0))
node _nodeIn_d_bits_T_5 = or(_nodeIn_d_bits_T_3, _nodeIn_d_bits_T_4)
wire _nodeIn_d_bits_WIRE_2 : UInt<32>
connect _nodeIn_d_bits_WIRE_2, _nodeIn_d_bits_T_5
connect _nodeIn_d_bits_WIRE.data, _nodeIn_d_bits_WIRE_2
wire _nodeIn_d_bits_WIRE_3 : { }
connect _nodeIn_d_bits_WIRE.echo, _nodeIn_d_bits_WIRE_3
wire _nodeIn_d_bits_WIRE_4 : { }
connect _nodeIn_d_bits_WIRE.user, _nodeIn_d_bits_WIRE_4
node _nodeIn_d_bits_T_6 = mux(muxState[0], dc.bits.denied, UInt<1>(0h0))
node _nodeIn_d_bits_T_7 = mux(muxState[1], da.bits.denied, UInt<1>(0h0))
node _nodeIn_d_bits_T_8 = or(_nodeIn_d_bits_T_6, _nodeIn_d_bits_T_7)
wire _nodeIn_d_bits_WIRE_5 : UInt<1>
connect _nodeIn_d_bits_WIRE_5, _nodeIn_d_bits_T_8
connect _nodeIn_d_bits_WIRE.denied, _nodeIn_d_bits_WIRE_5
node _nodeIn_d_bits_T_9 = mux(muxState[0], dc.bits.sink, UInt<1>(0h0))
node _nodeIn_d_bits_T_10 = mux(muxState[1], da.bits.sink, UInt<1>(0h0))
node _nodeIn_d_bits_T_11 = or(_nodeIn_d_bits_T_9, _nodeIn_d_bits_T_10)
wire _nodeIn_d_bits_WIRE_6 : UInt<1>
connect _nodeIn_d_bits_WIRE_6, _nodeIn_d_bits_T_11
connect _nodeIn_d_bits_WIRE.sink, _nodeIn_d_bits_WIRE_6
node _nodeIn_d_bits_T_12 = mux(muxState[0], dc.bits.source, UInt<1>(0h0))
node _nodeIn_d_bits_T_13 = mux(muxState[1], da.bits.source, UInt<1>(0h0))
node _nodeIn_d_bits_T_14 = or(_nodeIn_d_bits_T_12, _nodeIn_d_bits_T_13)
wire _nodeIn_d_bits_WIRE_7 : UInt<1>
connect _nodeIn_d_bits_WIRE_7, _nodeIn_d_bits_T_14
connect _nodeIn_d_bits_WIRE.source, _nodeIn_d_bits_WIRE_7
node _nodeIn_d_bits_T_15 = mux(muxState[0], dc.bits.size, UInt<1>(0h0))
node _nodeIn_d_bits_T_16 = mux(muxState[1], da.bits.size, UInt<1>(0h0))
node _nodeIn_d_bits_T_17 = or(_nodeIn_d_bits_T_15, _nodeIn_d_bits_T_16)
wire _nodeIn_d_bits_WIRE_8 : UInt<2>
connect _nodeIn_d_bits_WIRE_8, _nodeIn_d_bits_T_17
connect _nodeIn_d_bits_WIRE.size, _nodeIn_d_bits_WIRE_8
node _nodeIn_d_bits_T_18 = mux(muxState[0], dc.bits.param, UInt<1>(0h0))
node _nodeIn_d_bits_T_19 = mux(muxState[1], da.bits.param, UInt<1>(0h0))
node _nodeIn_d_bits_T_20 = or(_nodeIn_d_bits_T_18, _nodeIn_d_bits_T_19)
wire _nodeIn_d_bits_WIRE_9 : UInt<2>
connect _nodeIn_d_bits_WIRE_9, _nodeIn_d_bits_T_20
connect _nodeIn_d_bits_WIRE.param, _nodeIn_d_bits_WIRE_9
node _nodeIn_d_bits_T_21 = mux(muxState[0], dc.bits.opcode, UInt<1>(0h0))
node _nodeIn_d_bits_T_22 = mux(muxState[1], da.bits.opcode, UInt<1>(0h0))
node _nodeIn_d_bits_T_23 = or(_nodeIn_d_bits_T_21, _nodeIn_d_bits_T_22)
wire _nodeIn_d_bits_WIRE_10 : UInt<3>
connect _nodeIn_d_bits_WIRE_10, _nodeIn_d_bits_T_23
connect _nodeIn_d_bits_WIRE.opcode, _nodeIn_d_bits_WIRE_10
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_WIRE.corrupt
connect nodeIn.d.bits.data, _nodeIn_d_bits_WIRE.data
connect nodeIn.d.bits.denied, _nodeIn_d_bits_WIRE.denied
connect nodeIn.d.bits.sink, _nodeIn_d_bits_WIRE.sink
connect nodeIn.d.bits.source, _nodeIn_d_bits_WIRE.source
connect nodeIn.d.bits.size, _nodeIn_d_bits_WIRE.size
connect nodeIn.d.bits.param, _nodeIn_d_bits_WIRE.param
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_WIRE.opcode
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.mask, UInt<4>(0h0)
connect _WIRE_2.bits.address, UInt<128>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLError_1( // @[Error.scala:21:9]
input clock, // @[Error.scala:21:9]
input reset, // @[Error.scala:21:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire da_ready; // @[Arbiter.scala:94:31]
wire [2:0] da_bits_opcode; // @[Error.scala:38:21]
wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
reg idle; // @[Error.scala:29:23]
reg r_counter; // @[Edges.scala:229:27]
wire nodeIn_a_ready = da_ready & idle; // @[Arbiter.scala:94:31]
wire winner_1 = auto_in_a_valid & idle; // @[Error.scala:29:23, :36:35]
assign da_bits_opcode = _GEN[auto_in_a_bits_opcode]; // @[Error.scala:38:21]
reg beatsLeft; // @[Arbiter.scala:60:30] |
Generate the Verilog code corresponding to this FIRRTL code module AccumulatorMem :
input clock : Clock
input reset : Reset
output io : { flip read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { scale : { bits : UInt<32>}, addr : UInt<9>, igelu_qb : SInt<32>, igelu_qc : SInt<32>, iexp_qln2 : SInt<32>, iexp_qln2_inv : SInt<32>, act : UInt<3>, full : UInt<1>, fromDMA : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : SInt<32>[1][16], fromDMA : UInt<1>, scale : { bits : UInt<32>}, igelu_qb : SInt<32>, igelu_qc : SInt<32>, iexp_qln2 : SInt<32>, iexp_qln2_inv : SInt<32>, act : UInt<3>, acc_bank_id : UInt<2>}}}, flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<9>, data : SInt<32>[1][16], acc : UInt<1>, mask : UInt<1>[64]}}, adder : { valid : UInt<1>, op1 : SInt<32>[1][16], op2 : SInt<32>[1][16], flip sum : SInt<32>[1][16]}}
reg pipelined_writes : { valid : UInt<1>, bits : { addr : UInt<9>, data : SInt<32>[1][16], acc : UInt<1>, mask : UInt<1>[64]}}[2], clock
node _pipelined_writes_0_valid_T = and(io.write.ready, io.write.valid)
connect pipelined_writes[0].valid, _pipelined_writes_0_valid_T
connect pipelined_writes[0].bits, io.write.bits
connect pipelined_writes[1], pipelined_writes[0]
wire rdata_for_adder : SInt<32>[1][16]
invalidate rdata_for_adder[0][0]
invalidate rdata_for_adder[1][0]
invalidate rdata_for_adder[2][0]
invalidate rdata_for_adder[3][0]
invalidate rdata_for_adder[4][0]
invalidate rdata_for_adder[5][0]
invalidate rdata_for_adder[6][0]
invalidate rdata_for_adder[7][0]
invalidate rdata_for_adder[8][0]
invalidate rdata_for_adder[9][0]
invalidate rdata_for_adder[10][0]
invalidate rdata_for_adder[11][0]
invalidate rdata_for_adder[12][0]
invalidate rdata_for_adder[13][0]
invalidate rdata_for_adder[14][0]
invalidate rdata_for_adder[15][0]
wire rdata_for_read_resp : SInt<32>[1][16]
invalidate rdata_for_read_resp[0][0]
invalidate rdata_for_read_resp[1][0]
invalidate rdata_for_read_resp[2][0]
invalidate rdata_for_read_resp[3][0]
invalidate rdata_for_read_resp[4][0]
invalidate rdata_for_read_resp[5][0]
invalidate rdata_for_read_resp[6][0]
invalidate rdata_for_read_resp[7][0]
invalidate rdata_for_read_resp[8][0]
invalidate rdata_for_read_resp[9][0]
invalidate rdata_for_read_resp[10][0]
invalidate rdata_for_read_resp[11][0]
invalidate rdata_for_read_resp[12][0]
invalidate rdata_for_read_resp[13][0]
invalidate rdata_for_read_resp[14][0]
invalidate rdata_for_read_resp[15][0]
node _io_adder_valid_T = and(pipelined_writes[0].valid, pipelined_writes[0].bits.acc)
connect io.adder.valid, _io_adder_valid_T
connect io.adder.op1, rdata_for_adder
connect io.adder.op2, pipelined_writes[0].bits.data
wire block_read_req : UInt<1>
connect block_read_req, UInt<1>(0h0)
wire block_write_req : UInt<1>
connect block_write_req, UInt<1>(0h0)
inst mem of TwoPortSyncMem
connect mem.clock, clock
connect mem.reset, reset
connect mem.io.waddr, pipelined_writes[1].bits.addr
connect mem.io.wen, pipelined_writes[1].valid
node _T = mux(pipelined_writes[1].bits.acc, io.adder.sum, pipelined_writes[1].bits.data)
connect mem.io.wdata[0][0], _T[0][0]
connect mem.io.wdata[1][0], _T[1][0]
connect mem.io.wdata[2][0], _T[2][0]
connect mem.io.wdata[3][0], _T[3][0]
connect mem.io.wdata[4][0], _T[4][0]
connect mem.io.wdata[5][0], _T[5][0]
connect mem.io.wdata[6][0], _T[6][0]
connect mem.io.wdata[7][0], _T[7][0]
connect mem.io.wdata[8][0], _T[8][0]
connect mem.io.wdata[9][0], _T[9][0]
connect mem.io.wdata[10][0], _T[10][0]
connect mem.io.wdata[11][0], _T[11][0]
connect mem.io.wdata[12][0], _T[12][0]
connect mem.io.wdata[13][0], _T[13][0]
connect mem.io.wdata[14][0], _T[14][0]
connect mem.io.wdata[15][0], _T[15][0]
connect mem.io.mask[0], pipelined_writes[1].bits.mask[0]
connect mem.io.mask[1], pipelined_writes[1].bits.mask[1]
connect mem.io.mask[2], pipelined_writes[1].bits.mask[2]
connect mem.io.mask[3], pipelined_writes[1].bits.mask[3]
connect mem.io.mask[4], pipelined_writes[1].bits.mask[4]
connect mem.io.mask[5], pipelined_writes[1].bits.mask[5]
connect mem.io.mask[6], pipelined_writes[1].bits.mask[6]
connect mem.io.mask[7], pipelined_writes[1].bits.mask[7]
connect mem.io.mask[8], pipelined_writes[1].bits.mask[8]
connect mem.io.mask[9], pipelined_writes[1].bits.mask[9]
connect mem.io.mask[10], pipelined_writes[1].bits.mask[10]
connect mem.io.mask[11], pipelined_writes[1].bits.mask[11]
connect mem.io.mask[12], pipelined_writes[1].bits.mask[12]
connect mem.io.mask[13], pipelined_writes[1].bits.mask[13]
connect mem.io.mask[14], pipelined_writes[1].bits.mask[14]
connect mem.io.mask[15], pipelined_writes[1].bits.mask[15]
connect mem.io.mask[16], pipelined_writes[1].bits.mask[16]
connect mem.io.mask[17], pipelined_writes[1].bits.mask[17]
connect mem.io.mask[18], pipelined_writes[1].bits.mask[18]
connect mem.io.mask[19], pipelined_writes[1].bits.mask[19]
connect mem.io.mask[20], pipelined_writes[1].bits.mask[20]
connect mem.io.mask[21], pipelined_writes[1].bits.mask[21]
connect mem.io.mask[22], pipelined_writes[1].bits.mask[22]
connect mem.io.mask[23], pipelined_writes[1].bits.mask[23]
connect mem.io.mask[24], pipelined_writes[1].bits.mask[24]
connect mem.io.mask[25], pipelined_writes[1].bits.mask[25]
connect mem.io.mask[26], pipelined_writes[1].bits.mask[26]
connect mem.io.mask[27], pipelined_writes[1].bits.mask[27]
connect mem.io.mask[28], pipelined_writes[1].bits.mask[28]
connect mem.io.mask[29], pipelined_writes[1].bits.mask[29]
connect mem.io.mask[30], pipelined_writes[1].bits.mask[30]
connect mem.io.mask[31], pipelined_writes[1].bits.mask[31]
connect mem.io.mask[32], pipelined_writes[1].bits.mask[32]
connect mem.io.mask[33], pipelined_writes[1].bits.mask[33]
connect mem.io.mask[34], pipelined_writes[1].bits.mask[34]
connect mem.io.mask[35], pipelined_writes[1].bits.mask[35]
connect mem.io.mask[36], pipelined_writes[1].bits.mask[36]
connect mem.io.mask[37], pipelined_writes[1].bits.mask[37]
connect mem.io.mask[38], pipelined_writes[1].bits.mask[38]
connect mem.io.mask[39], pipelined_writes[1].bits.mask[39]
connect mem.io.mask[40], pipelined_writes[1].bits.mask[40]
connect mem.io.mask[41], pipelined_writes[1].bits.mask[41]
connect mem.io.mask[42], pipelined_writes[1].bits.mask[42]
connect mem.io.mask[43], pipelined_writes[1].bits.mask[43]
connect mem.io.mask[44], pipelined_writes[1].bits.mask[44]
connect mem.io.mask[45], pipelined_writes[1].bits.mask[45]
connect mem.io.mask[46], pipelined_writes[1].bits.mask[46]
connect mem.io.mask[47], pipelined_writes[1].bits.mask[47]
connect mem.io.mask[48], pipelined_writes[1].bits.mask[48]
connect mem.io.mask[49], pipelined_writes[1].bits.mask[49]
connect mem.io.mask[50], pipelined_writes[1].bits.mask[50]
connect mem.io.mask[51], pipelined_writes[1].bits.mask[51]
connect mem.io.mask[52], pipelined_writes[1].bits.mask[52]
connect mem.io.mask[53], pipelined_writes[1].bits.mask[53]
connect mem.io.mask[54], pipelined_writes[1].bits.mask[54]
connect mem.io.mask[55], pipelined_writes[1].bits.mask[55]
connect mem.io.mask[56], pipelined_writes[1].bits.mask[56]
connect mem.io.mask[57], pipelined_writes[1].bits.mask[57]
connect mem.io.mask[58], pipelined_writes[1].bits.mask[58]
connect mem.io.mask[59], pipelined_writes[1].bits.mask[59]
connect mem.io.mask[60], pipelined_writes[1].bits.mask[60]
connect mem.io.mask[61], pipelined_writes[1].bits.mask[61]
connect mem.io.mask[62], pipelined_writes[1].bits.mask[62]
connect mem.io.mask[63], pipelined_writes[1].bits.mask[63]
connect rdata_for_adder, mem.io.rdata
connect rdata_for_read_resp, mem.io.rdata
node _mem_io_raddr_T = and(io.write.ready, io.write.valid)
node _mem_io_raddr_T_1 = and(_mem_io_raddr_T, io.write.bits.acc)
node _mem_io_raddr_T_2 = mux(_mem_io_raddr_T_1, io.write.bits.addr, io.read.req.bits.addr)
connect mem.io.raddr, _mem_io_raddr_T_2
node _mem_io_ren_T = and(io.read.req.ready, io.read.req.valid)
node _mem_io_ren_T_1 = and(io.write.ready, io.write.valid)
node _mem_io_ren_T_2 = and(_mem_io_ren_T_1, io.write.bits.acc)
node _mem_io_ren_T_3 = or(_mem_io_ren_T, _mem_io_ren_T_2)
connect mem.io.ren, _mem_io_ren_T_3
inst q of Queue1_AccumulatorReadResp
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.bits.data[0][0], rdata_for_read_resp[0][0]
connect q.io.enq.bits.data[1][0], rdata_for_read_resp[1][0]
connect q.io.enq.bits.data[2][0], rdata_for_read_resp[2][0]
connect q.io.enq.bits.data[3][0], rdata_for_read_resp[3][0]
connect q.io.enq.bits.data[4][0], rdata_for_read_resp[4][0]
connect q.io.enq.bits.data[5][0], rdata_for_read_resp[5][0]
connect q.io.enq.bits.data[6][0], rdata_for_read_resp[6][0]
connect q.io.enq.bits.data[7][0], rdata_for_read_resp[7][0]
connect q.io.enq.bits.data[8][0], rdata_for_read_resp[8][0]
connect q.io.enq.bits.data[9][0], rdata_for_read_resp[9][0]
connect q.io.enq.bits.data[10][0], rdata_for_read_resp[10][0]
connect q.io.enq.bits.data[11][0], rdata_for_read_resp[11][0]
connect q.io.enq.bits.data[12][0], rdata_for_read_resp[12][0]
connect q.io.enq.bits.data[13][0], rdata_for_read_resp[13][0]
connect q.io.enq.bits.data[14][0], rdata_for_read_resp[14][0]
connect q.io.enq.bits.data[15][0], rdata_for_read_resp[15][0]
reg q_io_enq_bits_scale_REG : { bits : UInt<32>}, clock
connect q_io_enq_bits_scale_REG, io.read.req.bits.scale
connect q.io.enq.bits.scale.bits, q_io_enq_bits_scale_REG.bits
reg q_io_enq_bits_igelu_qb_REG : SInt, clock
connect q_io_enq_bits_igelu_qb_REG, io.read.req.bits.igelu_qb
connect q.io.enq.bits.igelu_qb, q_io_enq_bits_igelu_qb_REG
reg q_io_enq_bits_igelu_qc_REG : SInt, clock
connect q_io_enq_bits_igelu_qc_REG, io.read.req.bits.igelu_qc
connect q.io.enq.bits.igelu_qc, q_io_enq_bits_igelu_qc_REG
reg q_io_enq_bits_iexp_qln2_REG : SInt, clock
connect q_io_enq_bits_iexp_qln2_REG, io.read.req.bits.iexp_qln2
connect q.io.enq.bits.iexp_qln2, q_io_enq_bits_iexp_qln2_REG
reg q_io_enq_bits_iexp_qln2_inv_REG : SInt, clock
connect q_io_enq_bits_iexp_qln2_inv_REG, io.read.req.bits.iexp_qln2_inv
connect q.io.enq.bits.iexp_qln2_inv, q_io_enq_bits_iexp_qln2_inv_REG
reg q_io_enq_bits_act_REG : UInt, clock
connect q_io_enq_bits_act_REG, io.read.req.bits.act
connect q.io.enq.bits.act, q_io_enq_bits_act_REG
reg q_io_enq_bits_fromDMA_REG : UInt<1>, clock
connect q_io_enq_bits_fromDMA_REG, io.read.req.bits.fromDMA
connect q.io.enq.bits.fromDMA, q_io_enq_bits_fromDMA_REG
invalidate q.io.enq.bits.acc_bank_id
node _q_io_enq_valid_T = and(io.read.req.ready, io.read.req.valid)
reg q_io_enq_valid_REG : UInt<1>, clock
connect q_io_enq_valid_REG, _q_io_enq_valid_T
connect q.io.enq.valid, q_io_enq_valid_REG
connect io.read.resp.bits.data, q.io.deq.bits.data
connect io.read.resp.bits.fromDMA, q.io.deq.bits.fromDMA
connect io.read.resp.bits.igelu_qb, q.io.deq.bits.igelu_qb
connect io.read.resp.bits.igelu_qc, q.io.deq.bits.igelu_qc
connect io.read.resp.bits.iexp_qln2, q.io.deq.bits.iexp_qln2
connect io.read.resp.bits.iexp_qln2_inv, q.io.deq.bits.iexp_qln2_inv
connect io.read.resp.bits.act, q.io.deq.bits.act
connect io.read.resp.bits.scale, q.io.deq.bits.scale
invalidate io.read.resp.bits.acc_bank_id
connect io.read.resp.valid, q.io.deq.valid
connect q.io.deq.ready, io.read.resp.ready
node _q_will_be_empty_T = and(q.io.enq.ready, q.io.enq.valid)
node _q_will_be_empty_T_1 = add(q.io.count, _q_will_be_empty_T)
node _q_will_be_empty_T_2 = and(q.io.deq.ready, q.io.deq.valid)
node _q_will_be_empty_T_3 = sub(_q_will_be_empty_T_1, _q_will_be_empty_T_2)
node _q_will_be_empty_T_4 = tail(_q_will_be_empty_T_3, 1)
node q_will_be_empty = eq(_q_will_be_empty_T_4, UInt<1>(0h0))
node _io_read_req_ready_T = and(io.write.valid, io.write.bits.acc)
node _io_read_req_ready_T_1 = eq(_io_read_req_ready_T, UInt<1>(0h0))
node _io_read_req_ready_T_2 = eq(pipelined_writes[0].bits.addr, io.read.req.bits.addr)
node _io_read_req_ready_T_3 = and(pipelined_writes[0].valid, _io_read_req_ready_T_2)
node _io_read_req_ready_T_4 = eq(pipelined_writes[1].bits.addr, io.read.req.bits.addr)
node _io_read_req_ready_T_5 = and(pipelined_writes[1].valid, _io_read_req_ready_T_4)
node _io_read_req_ready_T_6 = or(_io_read_req_ready_T_3, _io_read_req_ready_T_5)
node _io_read_req_ready_T_7 = eq(_io_read_req_ready_T_6, UInt<1>(0h0))
node _io_read_req_ready_T_8 = and(_io_read_req_ready_T_1, _io_read_req_ready_T_7)
node _io_read_req_ready_T_9 = eq(block_read_req, UInt<1>(0h0))
node _io_read_req_ready_T_10 = and(_io_read_req_ready_T_8, _io_read_req_ready_T_9)
node _io_read_req_ready_T_11 = and(q_will_be_empty, _io_read_req_ready_T_10)
connect io.read.req.ready, _io_read_req_ready_T_11
node _io_write_ready_T = eq(block_write_req, UInt<1>(0h0))
node _io_write_ready_T_1 = eq(pipelined_writes[0].bits.addr, io.write.bits.addr)
node _io_write_ready_T_2 = and(pipelined_writes[0].valid, _io_write_ready_T_1)
node _io_write_ready_T_3 = and(_io_write_ready_T_2, io.write.bits.acc)
node _io_write_ready_T_4 = eq(pipelined_writes[1].bits.addr, io.write.bits.addr)
node _io_write_ready_T_5 = and(pipelined_writes[1].valid, _io_write_ready_T_4)
node _io_write_ready_T_6 = and(_io_write_ready_T_5, io.write.bits.acc)
node _io_write_ready_T_7 = or(_io_write_ready_T_3, _io_write_ready_T_6)
node _io_write_ready_T_8 = eq(_io_write_ready_T_7, UInt<1>(0h0))
node _io_write_ready_T_9 = and(_io_write_ready_T, _io_write_ready_T_8)
connect io.write.ready, _io_write_ready_T_9
node _T_1 = asUInt(reset)
when _T_1 :
connect pipelined_writes[0].valid, UInt<1>(0h0)
connect pipelined_writes[1].valid, UInt<1>(0h0)
node _T_2 = and(io.read.req.ready, io.read.req.valid)
node _T_3 = and(io.write.ready, io.write.valid)
node _T_4 = and(_T_2, _T_3)
node _T_5 = eq(io.read.req.bits.addr, io.write.bits.addr)
node _T_6 = and(_T_4, _T_5)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed: reading from and writing to same address is not supported\n at AccumulatorMem.scala:342 assert(!(io.read.req.fire && io.write.fire && io.read.req.bits.addr === io.write.bits.addr), \"reading from and writing to same address is not supported\")\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert | module AccumulatorMem( // @[AccumulatorMem.scala:92:7]
input clock, // @[AccumulatorMem.scala:92:7]
input reset, // @[AccumulatorMem.scala:92:7]
output io_read_req_ready, // @[AccumulatorMem.scala:109:14]
input io_read_req_valid, // @[AccumulatorMem.scala:109:14]
input [31:0] io_read_req_bits_scale_bits, // @[AccumulatorMem.scala:109:14]
input [8:0] io_read_req_bits_addr, // @[AccumulatorMem.scala:109:14]
input [31:0] io_read_req_bits_igelu_qb, // @[AccumulatorMem.scala:109:14]
input [31:0] io_read_req_bits_igelu_qc, // @[AccumulatorMem.scala:109:14]
input [31:0] io_read_req_bits_iexp_qln2, // @[AccumulatorMem.scala:109:14]
input [31:0] io_read_req_bits_iexp_qln2_inv, // @[AccumulatorMem.scala:109:14]
input [2:0] io_read_req_bits_act, // @[AccumulatorMem.scala:109:14]
input io_read_req_bits_full, // @[AccumulatorMem.scala:109:14]
input io_read_req_bits_fromDMA, // @[AccumulatorMem.scala:109:14]
input io_read_resp_ready, // @[AccumulatorMem.scala:109:14]
output io_read_resp_valid, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_0_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_1_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_2_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_3_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_4_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_5_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_6_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_7_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_8_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_9_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_10_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_11_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_12_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_13_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_14_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_data_15_0, // @[AccumulatorMem.scala:109:14]
output io_read_resp_bits_fromDMA, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_scale_bits, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_igelu_qb, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_igelu_qc, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_iexp_qln2, // @[AccumulatorMem.scala:109:14]
output [31:0] io_read_resp_bits_iexp_qln2_inv, // @[AccumulatorMem.scala:109:14]
output [2:0] io_read_resp_bits_act, // @[AccumulatorMem.scala:109:14]
output io_write_ready, // @[AccumulatorMem.scala:109:14]
input io_write_valid, // @[AccumulatorMem.scala:109:14]
input [8:0] io_write_bits_addr, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_0_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_1_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_2_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_3_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_4_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_5_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_6_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_7_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_8_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_9_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_10_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_11_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_12_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_13_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_14_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_write_bits_data_15_0, // @[AccumulatorMem.scala:109:14]
input io_write_bits_acc, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_0, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_1, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_2, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_3, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_4, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_5, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_6, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_7, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_8, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_9, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_10, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_11, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_12, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_13, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_14, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_15, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_16, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_17, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_18, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_19, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_20, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_21, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_22, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_23, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_24, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_25, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_26, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_27, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_28, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_29, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_30, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_31, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_32, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_33, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_34, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_35, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_36, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_37, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_38, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_39, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_40, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_41, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_42, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_43, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_44, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_45, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_46, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_47, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_48, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_49, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_50, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_51, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_52, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_53, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_54, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_55, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_56, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_57, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_58, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_59, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_60, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_61, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_62, // @[AccumulatorMem.scala:109:14]
input io_write_bits_mask_63, // @[AccumulatorMem.scala:109:14]
output io_adder_valid, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_0_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_1_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_2_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_3_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_4_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_5_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_6_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_7_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_8_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_9_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_10_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_11_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_12_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_13_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_14_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op1_15_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_0_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_1_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_2_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_3_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_4_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_5_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_6_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_7_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_8_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_9_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_10_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_11_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_12_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_13_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_14_0, // @[AccumulatorMem.scala:109:14]
output [31:0] io_adder_op2_15_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_0_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_1_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_2_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_3_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_4_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_5_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_6_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_7_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_8_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_9_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_10_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_11_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_12_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_13_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_14_0, // @[AccumulatorMem.scala:109:14]
input [31:0] io_adder_sum_15_0 // @[AccumulatorMem.scala:109:14]
);
wire _q_io_enq_ready; // @[AccumulatorMem.scala:294:17]
wire _q_io_deq_valid; // @[AccumulatorMem.scala:294:17]
wire _q_io_count; // @[AccumulatorMem.scala:294:17]
wire [31:0] _mem_io_rdata_0_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_1_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_2_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_3_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_4_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_5_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_6_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_7_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_8_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_9_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_10_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_11_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_12_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_13_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_14_0; // @[SyncMem.scala:105:80]
wire [31:0] _mem_io_rdata_15_0; // @[SyncMem.scala:105:80]
wire io_read_req_valid_0 = io_read_req_valid; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_req_bits_scale_bits_0 = io_read_req_bits_scale_bits; // @[AccumulatorMem.scala:92:7]
wire [8:0] io_read_req_bits_addr_0 = io_read_req_bits_addr; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_req_bits_igelu_qb_0 = io_read_req_bits_igelu_qb; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_req_bits_igelu_qc_0 = io_read_req_bits_igelu_qc; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_req_bits_iexp_qln2_0 = io_read_req_bits_iexp_qln2; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_req_bits_iexp_qln2_inv_0 = io_read_req_bits_iexp_qln2_inv; // @[AccumulatorMem.scala:92:7]
wire [2:0] io_read_req_bits_act_0 = io_read_req_bits_act; // @[AccumulatorMem.scala:92:7]
wire io_read_req_bits_full_0 = io_read_req_bits_full; // @[AccumulatorMem.scala:92:7]
wire io_read_req_bits_fromDMA_0 = io_read_req_bits_fromDMA; // @[AccumulatorMem.scala:92:7]
wire io_read_resp_ready_0 = io_read_resp_ready; // @[AccumulatorMem.scala:92:7]
wire io_write_valid_0 = io_write_valid; // @[AccumulatorMem.scala:92:7]
wire [8:0] io_write_bits_addr_0 = io_write_bits_addr; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_0_0_0 = io_write_bits_data_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_1_0_0 = io_write_bits_data_1_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_2_0_0 = io_write_bits_data_2_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_3_0_0 = io_write_bits_data_3_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_4_0_0 = io_write_bits_data_4_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_5_0_0 = io_write_bits_data_5_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_6_0_0 = io_write_bits_data_6_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_7_0_0 = io_write_bits_data_7_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_8_0_0 = io_write_bits_data_8_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_9_0_0 = io_write_bits_data_9_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_10_0_0 = io_write_bits_data_10_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_11_0_0 = io_write_bits_data_11_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_12_0_0 = io_write_bits_data_12_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_13_0_0 = io_write_bits_data_13_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_14_0_0 = io_write_bits_data_14_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_write_bits_data_15_0_0 = io_write_bits_data_15_0; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_acc_0 = io_write_bits_acc; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_0_0 = io_write_bits_mask_0; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_1_0 = io_write_bits_mask_1; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_2_0 = io_write_bits_mask_2; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_3_0 = io_write_bits_mask_3; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_4_0 = io_write_bits_mask_4; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_5_0 = io_write_bits_mask_5; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_6_0 = io_write_bits_mask_6; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_7_0 = io_write_bits_mask_7; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_8_0 = io_write_bits_mask_8; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_9_0 = io_write_bits_mask_9; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_10_0 = io_write_bits_mask_10; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_11_0 = io_write_bits_mask_11; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_12_0 = io_write_bits_mask_12; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_13_0 = io_write_bits_mask_13; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_14_0 = io_write_bits_mask_14; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_15_0 = io_write_bits_mask_15; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_16_0 = io_write_bits_mask_16; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_17_0 = io_write_bits_mask_17; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_18_0 = io_write_bits_mask_18; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_19_0 = io_write_bits_mask_19; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_20_0 = io_write_bits_mask_20; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_21_0 = io_write_bits_mask_21; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_22_0 = io_write_bits_mask_22; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_23_0 = io_write_bits_mask_23; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_24_0 = io_write_bits_mask_24; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_25_0 = io_write_bits_mask_25; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_26_0 = io_write_bits_mask_26; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_27_0 = io_write_bits_mask_27; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_28_0 = io_write_bits_mask_28; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_29_0 = io_write_bits_mask_29; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_30_0 = io_write_bits_mask_30; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_31_0 = io_write_bits_mask_31; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_32_0 = io_write_bits_mask_32; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_33_0 = io_write_bits_mask_33; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_34_0 = io_write_bits_mask_34; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_35_0 = io_write_bits_mask_35; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_36_0 = io_write_bits_mask_36; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_37_0 = io_write_bits_mask_37; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_38_0 = io_write_bits_mask_38; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_39_0 = io_write_bits_mask_39; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_40_0 = io_write_bits_mask_40; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_41_0 = io_write_bits_mask_41; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_42_0 = io_write_bits_mask_42; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_43_0 = io_write_bits_mask_43; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_44_0 = io_write_bits_mask_44; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_45_0 = io_write_bits_mask_45; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_46_0 = io_write_bits_mask_46; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_47_0 = io_write_bits_mask_47; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_48_0 = io_write_bits_mask_48; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_49_0 = io_write_bits_mask_49; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_50_0 = io_write_bits_mask_50; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_51_0 = io_write_bits_mask_51; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_52_0 = io_write_bits_mask_52; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_53_0 = io_write_bits_mask_53; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_54_0 = io_write_bits_mask_54; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_55_0 = io_write_bits_mask_55; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_56_0 = io_write_bits_mask_56; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_57_0 = io_write_bits_mask_57; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_58_0 = io_write_bits_mask_58; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_59_0 = io_write_bits_mask_59; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_60_0 = io_write_bits_mask_60; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_61_0 = io_write_bits_mask_61; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_62_0 = io_write_bits_mask_62; // @[AccumulatorMem.scala:92:7]
wire io_write_bits_mask_63_0 = io_write_bits_mask_63; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_0_0_0 = io_adder_sum_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_1_0_0 = io_adder_sum_1_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_2_0_0 = io_adder_sum_2_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_3_0_0 = io_adder_sum_3_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_4_0_0 = io_adder_sum_4_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_5_0_0 = io_adder_sum_5_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_6_0_0 = io_adder_sum_6_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_7_0_0 = io_adder_sum_7_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_8_0_0 = io_adder_sum_8_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_9_0_0 = io_adder_sum_9_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_10_0_0 = io_adder_sum_10_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_11_0_0 = io_adder_sum_11_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_12_0_0 = io_adder_sum_12_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_13_0_0 = io_adder_sum_13_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_14_0_0 = io_adder_sum_14_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_sum_15_0_0 = io_adder_sum_15_0; // @[AccumulatorMem.scala:92:7]
wire [1:0] io_read_resp_bits_acc_bank_id = 2'h0; // @[AccumulatorMem.scala:92:7]
wire _io_read_req_ready_T_9 = 1'h1; // @[AccumulatorMem.scala:331:7]
wire _io_write_ready_T = 1'h1; // @[AccumulatorMem.scala:334:21]
wire block_read_req = 1'h0; // @[AccumulatorMem.scala:131:32]
wire block_write_req = 1'h0; // @[AccumulatorMem.scala:132:33]
wire _io_read_req_ready_T_11; // @[AccumulatorMem.scala:327:40]
wire _io_write_ready_T_9; // @[AccumulatorMem.scala:334:38]
wire _io_adder_valid_T; // @[AccumulatorMem.scala:127:47]
wire [31:0] rdata_for_adder_0_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_1_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_2_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_3_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_4_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_5_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_6_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_7_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_8_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_9_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_10_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_11_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_12_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_13_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_14_0; // @[AccumulatorMem.scala:121:29]
wire [31:0] rdata_for_adder_15_0; // @[AccumulatorMem.scala:121:29]
wire io_read_req_ready_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_0_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_1_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_2_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_3_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_4_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_5_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_6_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_7_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_8_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_9_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_10_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_11_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_12_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_13_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_14_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_data_15_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_scale_bits_0; // @[AccumulatorMem.scala:92:7]
wire io_read_resp_bits_fromDMA_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_igelu_qb_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_igelu_qc_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_iexp_qln2_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_read_resp_bits_iexp_qln2_inv_0; // @[AccumulatorMem.scala:92:7]
wire [2:0] io_read_resp_bits_act_0; // @[AccumulatorMem.scala:92:7]
wire io_read_resp_valid_0; // @[AccumulatorMem.scala:92:7]
wire io_write_ready_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_0_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_1_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_2_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_3_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_4_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_5_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_6_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_7_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_8_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_9_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_10_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_11_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_12_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_13_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_14_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op1_15_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_0_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_1_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_2_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_3_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_4_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_5_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_6_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_7_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_8_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_9_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_10_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_11_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_12_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_13_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_14_0_0; // @[AccumulatorMem.scala:92:7]
wire [31:0] io_adder_op2_15_0_0; // @[AccumulatorMem.scala:92:7]
wire io_adder_valid_0; // @[AccumulatorMem.scala:92:7]
reg pipelined_writes_0_valid; // @[AccumulatorMem.scala:113:29]
reg [8:0] pipelined_writes_0_bits_addr; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_0_bits_data_0_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_0_0_0 = pipelined_writes_0_bits_data_0_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_1_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_1_0_0 = pipelined_writes_0_bits_data_1_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_2_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_2_0_0 = pipelined_writes_0_bits_data_2_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_3_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_3_0_0 = pipelined_writes_0_bits_data_3_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_4_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_4_0_0 = pipelined_writes_0_bits_data_4_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_5_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_5_0_0 = pipelined_writes_0_bits_data_5_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_6_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_6_0_0 = pipelined_writes_0_bits_data_6_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_7_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_7_0_0 = pipelined_writes_0_bits_data_7_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_8_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_8_0_0 = pipelined_writes_0_bits_data_8_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_9_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_9_0_0 = pipelined_writes_0_bits_data_9_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_10_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_10_0_0 = pipelined_writes_0_bits_data_10_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_11_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_11_0_0 = pipelined_writes_0_bits_data_11_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_12_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_12_0_0 = pipelined_writes_0_bits_data_12_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_13_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_13_0_0 = pipelined_writes_0_bits_data_13_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_14_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_14_0_0 = pipelined_writes_0_bits_data_14_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg [31:0] pipelined_writes_0_bits_data_15_0; // @[AccumulatorMem.scala:113:29]
assign io_adder_op2_15_0_0 = pipelined_writes_0_bits_data_15_0; // @[AccumulatorMem.scala:92:7, :113:29]
reg pipelined_writes_0_bits_acc; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_0; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_1; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_2; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_3; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_4; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_5; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_6; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_7; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_8; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_9; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_10; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_11; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_12; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_13; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_14; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_15; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_16; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_17; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_18; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_19; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_20; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_21; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_22; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_23; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_24; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_25; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_26; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_27; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_28; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_29; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_30; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_31; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_32; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_33; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_34; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_35; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_36; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_37; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_38; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_39; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_40; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_41; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_42; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_43; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_44; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_45; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_46; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_47; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_48; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_49; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_50; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_51; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_52; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_53; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_54; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_55; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_56; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_57; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_58; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_59; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_60; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_61; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_62; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_0_bits_mask_63; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_valid; // @[AccumulatorMem.scala:113:29]
reg [8:0] pipelined_writes_1_bits_addr; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_0_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_1_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_2_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_3_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_4_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_5_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_6_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_7_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_8_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_9_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_10_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_11_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_12_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_13_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_14_0; // @[AccumulatorMem.scala:113:29]
reg [31:0] pipelined_writes_1_bits_data_15_0; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_acc; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_0; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_1; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_2; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_3; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_4; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_5; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_6; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_7; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_8; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_9; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_10; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_11; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_12; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_13; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_14; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_15; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_16; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_17; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_18; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_19; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_20; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_21; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_22; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_23; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_24; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_25; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_26; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_27; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_28; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_29; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_30; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_31; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_32; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_33; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_34; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_35; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_36; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_37; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_38; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_39; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_40; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_41; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_42; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_43; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_44; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_45; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_46; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_47; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_48; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_49; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_50; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_51; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_52; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_53; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_54; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_55; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_56; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_57; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_58; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_59; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_60; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_61; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_62; // @[AccumulatorMem.scala:113:29]
reg pipelined_writes_1_bits_mask_63; // @[AccumulatorMem.scala:113:29]
wire _T_3 = io_write_ready_0 & io_write_valid_0; // @[Decoupled.scala:51:35]
wire _pipelined_writes_0_valid_T; // @[Decoupled.scala:51:35]
assign _pipelined_writes_0_valid_T = _T_3; // @[Decoupled.scala:51:35]
wire _mem_io_raddr_T; // @[Decoupled.scala:51:35]
assign _mem_io_raddr_T = _T_3; // @[Decoupled.scala:51:35]
wire _mem_io_ren_T_1; // @[Decoupled.scala:51:35]
assign _mem_io_ren_T_1 = _T_3; // @[Decoupled.scala:51:35]
assign io_adder_op1_0_0_0 = rdata_for_adder_0_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_1_0_0 = rdata_for_adder_1_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_2_0_0 = rdata_for_adder_2_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_3_0_0 = rdata_for_adder_3_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_4_0_0 = rdata_for_adder_4_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_5_0_0 = rdata_for_adder_5_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_6_0_0 = rdata_for_adder_6_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_7_0_0 = rdata_for_adder_7_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_8_0_0 = rdata_for_adder_8_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_9_0_0 = rdata_for_adder_9_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_10_0_0 = rdata_for_adder_10_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_11_0_0 = rdata_for_adder_11_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_12_0_0 = rdata_for_adder_12_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_13_0_0 = rdata_for_adder_13_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_14_0_0 = rdata_for_adder_14_0; // @[AccumulatorMem.scala:92:7, :121:29]
assign io_adder_op1_15_0_0 = rdata_for_adder_15_0; // @[AccumulatorMem.scala:92:7, :121:29]
wire [31:0] rdata_for_read_resp_0_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_1_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_2_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_3_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_4_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_5_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_6_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_7_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_8_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_9_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_10_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_11_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_12_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_13_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_14_0; // @[AccumulatorMem.scala:123:33]
wire [31:0] rdata_for_read_resp_15_0; // @[AccumulatorMem.scala:123:33]
assign _io_adder_valid_T = pipelined_writes_0_valid & pipelined_writes_0_bits_acc; // @[AccumulatorMem.scala:113:29, :127:47]
assign io_adder_valid_0 = _io_adder_valid_T; // @[AccumulatorMem.scala:92:7, :127:47]
wire _mem_io_raddr_T_1 = _mem_io_raddr_T & io_write_bits_acc_0; // @[Decoupled.scala:51:35]
wire [8:0] _mem_io_raddr_T_2 = _mem_io_raddr_T_1 ? io_write_bits_addr_0 : io_read_req_bits_addr_0; // @[AccumulatorMem.scala:92:7, :146:{24,39}]
wire _T_2 = io_read_req_ready_0 & io_read_req_valid_0; // @[Decoupled.scala:51:35]
wire _mem_io_ren_T; // @[Decoupled.scala:51:35]
assign _mem_io_ren_T = _T_2; // @[Decoupled.scala:51:35]
wire _q_io_enq_valid_T; // @[Decoupled.scala:51:35]
assign _q_io_enq_valid_T = _T_2; // @[Decoupled.scala:51:35]
wire _mem_io_ren_T_2 = _mem_io_ren_T_1 & io_write_bits_acc_0; // @[Decoupled.scala:51:35]
wire _mem_io_ren_T_3 = _mem_io_ren_T | _mem_io_ren_T_2; // @[Decoupled.scala:51:35]
reg [31:0] q_io_enq_bits_scale_REG_bits; // @[AccumulatorMem.scala:302:33]
reg [31:0] q_io_enq_bits_igelu_qb_REG; // @[AccumulatorMem.scala:303:36]
reg [31:0] q_io_enq_bits_igelu_qc_REG; // @[AccumulatorMem.scala:304:36]
reg [31:0] q_io_enq_bits_iexp_qln2_REG; // @[AccumulatorMem.scala:305:37]
reg [31:0] q_io_enq_bits_iexp_qln2_inv_REG; // @[AccumulatorMem.scala:306:41]
reg [2:0] q_io_enq_bits_act_REG; // @[AccumulatorMem.scala:307:31]
reg q_io_enq_bits_fromDMA_REG; // @[AccumulatorMem.scala:308:35]
reg q_io_enq_valid_REG; // @[AccumulatorMem.scala:310:28]
wire _q_will_be_empty_T = _q_io_enq_ready & q_io_enq_valid_REG; // @[Decoupled.scala:51:35]
wire [1:0] _q_will_be_empty_T_1 = {1'h0, _q_io_count} + {1'h0, _q_will_be_empty_T}; // @[Decoupled.scala:51:35]
wire _q_will_be_empty_T_2 = io_read_resp_ready_0 & _q_io_deq_valid; // @[Decoupled.scala:51:35]
wire [2:0] _q_will_be_empty_T_3 = {1'h0, _q_will_be_empty_T_1} - {2'h0, _q_will_be_empty_T_2}; // @[Decoupled.scala:51:35]
wire [1:0] _q_will_be_empty_T_4 = _q_will_be_empty_T_3[1:0]; // @[AccumulatorMem.scala:326:55]
wire q_will_be_empty = _q_will_be_empty_T_4 == 2'h0; // @[AccumulatorMem.scala:326:{55,71}]
wire _io_read_req_ready_T = io_write_valid_0 & io_write_bits_acc_0; // @[AccumulatorMem.scala:92:7, :329:24]
wire _io_read_req_ready_T_1 = ~_io_read_req_ready_T; // @[AccumulatorMem.scala:329:{7,24}]
wire _io_read_req_ready_T_2 = pipelined_writes_0_bits_addr == io_read_req_bits_addr_0; // @[AccumulatorMem.scala:92:7, :113:29, :330:57]
wire _io_read_req_ready_T_3 = pipelined_writes_0_valid & _io_read_req_ready_T_2; // @[AccumulatorMem.scala:113:29, :330:{42,57}]
wire _io_read_req_ready_T_4 = pipelined_writes_1_bits_addr == io_read_req_bits_addr_0; // @[AccumulatorMem.scala:92:7, :113:29, :330:57]
wire _io_read_req_ready_T_5 = pipelined_writes_1_valid & _io_read_req_ready_T_4; // @[AccumulatorMem.scala:113:29, :330:{42,57}]
wire _io_read_req_ready_T_6 = _io_read_req_ready_T_3 | _io_read_req_ready_T_5; // @[AccumulatorMem.scala:330:{42,92}]
wire _io_read_req_ready_T_7 = ~_io_read_req_ready_T_6; // @[AccumulatorMem.scala:330:{7,92}]
wire _io_read_req_ready_T_8 = _io_read_req_ready_T_1 & _io_read_req_ready_T_7; // @[AccumulatorMem.scala:329:{7,46}, :330:7]
wire _io_read_req_ready_T_10 = _io_read_req_ready_T_8; // @[AccumulatorMem.scala:329:46, :330:98]
assign _io_read_req_ready_T_11 = q_will_be_empty & _io_read_req_ready_T_10; // @[AccumulatorMem.scala:326:71, :327:40, :330:98]
assign io_read_req_ready_0 = _io_read_req_ready_T_11; // @[AccumulatorMem.scala:92:7, :327:40]
wire _io_write_ready_T_1 = pipelined_writes_0_bits_addr == io_write_bits_addr_0; // @[AccumulatorMem.scala:92:7, :113:29, :335:55]
wire _io_write_ready_T_2 = pipelined_writes_0_valid & _io_write_ready_T_1; // @[AccumulatorMem.scala:113:29, :335:{40,55}]
wire _io_write_ready_T_3 = _io_write_ready_T_2 & io_write_bits_acc_0; // @[AccumulatorMem.scala:92:7, :335:{40,78}]
wire _io_write_ready_T_4 = pipelined_writes_1_bits_addr == io_write_bits_addr_0; // @[AccumulatorMem.scala:92:7, :113:29, :335:55]
wire _io_write_ready_T_5 = pipelined_writes_1_valid & _io_write_ready_T_4; // @[AccumulatorMem.scala:113:29, :335:{40,55}]
wire _io_write_ready_T_6 = _io_write_ready_T_5 & io_write_bits_acc_0; // @[AccumulatorMem.scala:92:7, :335:{40,78}]
wire _io_write_ready_T_7 = _io_write_ready_T_3 | _io_write_ready_T_6; // @[AccumulatorMem.scala:335:{78,108}]
wire _io_write_ready_T_8 = ~_io_write_ready_T_7; // @[AccumulatorMem.scala:335:{5,108}]
assign _io_write_ready_T_9 = _io_write_ready_T_8; // @[AccumulatorMem.scala:334:38, :335:5]
assign io_write_ready_0 = _io_write_ready_T_9; // @[AccumulatorMem.scala:92:7, :334:38] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<12>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<12>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<2>, clock
reg probes_toN : UInt<2>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_uncommonBits_T = or(request.source, UInt<4>(0h0))
node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 3, 0)
node _req_clientBit_T = shr(request.source, 4)
node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<1>(0h1))
node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits)
node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2)
node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<4>(0h8))
node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4)
node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<4>(0h0))
node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 3, 0)
node _req_clientBit_T_6 = shr(request.source, 4)
node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<1>(0h0))
node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1)
node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8)
node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<4>(0h8))
node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10)
node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(_T_110, UInt<1>(0h0))
node _T_112 = asUInt(reset)
node _T_113 = eq(_T_112, UInt<1>(0h0))
when _T_113 :
node _T_114 = eq(_T_111, UInt<1>(0h0))
when _T_114 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_111, UInt<1>(0h1), "") : assert_14
node _T_115 = eq(before, UInt<4>(0h8))
node _T_116 = eq(after, UInt<3>(0h5))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_118, UInt<1>(0h1), "") : assert_15
node _T_122 = eq(before, UInt<4>(0h8))
node _T_123 = eq(after, UInt<3>(0h4))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_125, UInt<1>(0h1), "") : assert_16
node _T_129 = eq(before, UInt<4>(0h8))
node _T_130 = eq(after, UInt<3>(0h6))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(_T_131, UInt<1>(0h0))
node _T_133 = asUInt(reset)
node _T_134 = eq(_T_133, UInt<1>(0h0))
when _T_134 :
node _T_135 = eq(_T_132, UInt<1>(0h0))
when _T_135 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_132, UInt<1>(0h1), "") : assert_17
node _T_136 = eq(before, UInt<4>(0h8))
node _T_137 = eq(after, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(before, UInt<4>(0h8))
node _T_140 = eq(after, UInt<2>(0h2))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(_T_141, UInt<1>(0h0))
node _T_143 = asUInt(reset)
node _T_144 = eq(_T_143, UInt<1>(0h0))
when _T_144 :
node _T_145 = eq(_T_142, UInt<1>(0h0))
when _T_145 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_142, UInt<1>(0h1), "") : assert_18
node _T_146 = eq(before, UInt<1>(0h1))
node _T_147 = eq(after, UInt<4>(0h8))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(_T_148, UInt<1>(0h0))
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_149, UInt<1>(0h1), "") : assert_19
node _T_153 = eq(before, UInt<1>(0h1))
node _T_154 = eq(after, UInt<1>(0h0))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(_T_155, UInt<1>(0h0))
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_156, UInt<1>(0h1), "") : assert_20
node _T_160 = eq(before, UInt<1>(0h1))
node _T_161 = eq(after, UInt<3>(0h7))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(_T_162, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_163, UInt<1>(0h1), "") : assert_21
node _T_167 = eq(before, UInt<1>(0h1))
node _T_168 = eq(after, UInt<3>(0h5))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(_T_169, UInt<1>(0h0))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_170, UInt<1>(0h1), "") : assert_22
node _T_174 = eq(before, UInt<1>(0h1))
node _T_175 = eq(after, UInt<3>(0h4))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = asUInt(reset)
node _T_179 = eq(_T_178, UInt<1>(0h0))
when _T_179 :
node _T_180 = eq(_T_177, UInt<1>(0h0))
when _T_180 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_177, UInt<1>(0h1), "") : assert_23
node _T_181 = eq(before, UInt<1>(0h1))
node _T_182 = eq(after, UInt<3>(0h6))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(_T_183, UInt<1>(0h0))
node _T_185 = asUInt(reset)
node _T_186 = eq(_T_185, UInt<1>(0h0))
when _T_186 :
node _T_187 = eq(_T_184, UInt<1>(0h0))
when _T_187 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_184, UInt<1>(0h1), "") : assert_24
node _T_188 = eq(before, UInt<1>(0h1))
node _T_189 = eq(after, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(before, UInt<1>(0h1))
node _T_196 = eq(after, UInt<2>(0h2))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = asUInt(reset)
node _T_200 = eq(_T_199, UInt<1>(0h0))
when _T_200 :
node _T_201 = eq(_T_198, UInt<1>(0h0))
when _T_201 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_198, UInt<1>(0h1), "") : assert_26
node _T_202 = eq(before, UInt<1>(0h0))
node _T_203 = eq(after, UInt<4>(0h8))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(_T_204, UInt<1>(0h0))
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(_T_205, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_205, UInt<1>(0h1), "") : assert_27
node _T_209 = eq(before, UInt<1>(0h0))
node _T_210 = eq(after, UInt<1>(0h1))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(_T_211, UInt<1>(0h0))
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(_T_212, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_212, UInt<1>(0h1), "") : assert_28
node _T_216 = eq(before, UInt<1>(0h0))
node _T_217 = eq(after, UInt<3>(0h7))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(_T_218, UInt<1>(0h0))
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_T_219, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_219, UInt<1>(0h1), "") : assert_29
node _T_223 = eq(before, UInt<1>(0h0))
node _T_224 = eq(after, UInt<3>(0h5))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(_T_225, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_226, UInt<1>(0h1), "") : assert_30
node _T_230 = eq(before, UInt<1>(0h0))
node _T_231 = eq(after, UInt<3>(0h6))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_233, UInt<1>(0h1), "") : assert_31
node _T_237 = eq(before, UInt<1>(0h0))
node _T_238 = eq(after, UInt<3>(0h4))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(_T_239, UInt<1>(0h0))
node _T_241 = asUInt(reset)
node _T_242 = eq(_T_241, UInt<1>(0h0))
when _T_242 :
node _T_243 = eq(_T_240, UInt<1>(0h0))
when _T_243 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_240, UInt<1>(0h1), "") : assert_32
node _T_244 = eq(before, UInt<1>(0h0))
node _T_245 = eq(after, UInt<2>(0h3))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(_T_246, UInt<1>(0h0))
node _T_248 = asUInt(reset)
node _T_249 = eq(_T_248, UInt<1>(0h0))
when _T_249 :
node _T_250 = eq(_T_247, UInt<1>(0h0))
when _T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_247, UInt<1>(0h1), "") : assert_33
node _T_251 = eq(before, UInt<1>(0h0))
node _T_252 = eq(after, UInt<2>(0h2))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_254, UInt<1>(0h1), "") : assert_34
node _T_258 = eq(before, UInt<3>(0h7))
node _T_259 = eq(after, UInt<4>(0h8))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = asUInt(reset)
node _T_263 = eq(_T_262, UInt<1>(0h0))
when _T_263 :
node _T_264 = eq(_T_261, UInt<1>(0h0))
when _T_264 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_261, UInt<1>(0h1), "") : assert_35
node _T_265 = eq(before, UInt<3>(0h7))
node _T_266 = eq(after, UInt<1>(0h1))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_268, UInt<1>(0h1), "") : assert_36
node _T_272 = eq(before, UInt<3>(0h7))
node _T_273 = eq(after, UInt<1>(0h0))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_275, UInt<1>(0h1), "") : assert_37
node _T_279 = eq(before, UInt<3>(0h7))
node _T_280 = eq(after, UInt<3>(0h5))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(_T_281, UInt<1>(0h0))
node _T_283 = asUInt(reset)
node _T_284 = eq(_T_283, UInt<1>(0h0))
when _T_284 :
node _T_285 = eq(_T_282, UInt<1>(0h0))
when _T_285 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_282, UInt<1>(0h1), "") : assert_38
node _T_286 = eq(before, UInt<3>(0h7))
node _T_287 = eq(after, UInt<3>(0h6))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(_T_288, UInt<1>(0h0))
node _T_290 = asUInt(reset)
node _T_291 = eq(_T_290, UInt<1>(0h0))
when _T_291 :
node _T_292 = eq(_T_289, UInt<1>(0h0))
when _T_292 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_289, UInt<1>(0h1), "") : assert_39
node _T_293 = eq(before, UInt<3>(0h7))
node _T_294 = eq(after, UInt<3>(0h4))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_296, UInt<1>(0h1), "") : assert_40
node _T_300 = eq(before, UInt<3>(0h7))
node _T_301 = eq(after, UInt<2>(0h3))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(before, UInt<3>(0h7))
node _T_304 = eq(after, UInt<2>(0h2))
node _T_305 = and(_T_303, _T_304)
node _T_306 = eq(_T_305, UInt<1>(0h0))
node _T_307 = asUInt(reset)
node _T_308 = eq(_T_307, UInt<1>(0h0))
when _T_308 :
node _T_309 = eq(_T_306, UInt<1>(0h0))
when _T_309 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_306, UInt<1>(0h1), "") : assert_41
node _T_310 = eq(before, UInt<3>(0h5))
node _T_311 = eq(after, UInt<4>(0h8))
node _T_312 = and(_T_310, _T_311)
node _T_313 = eq(_T_312, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_313, UInt<1>(0h1), "") : assert_42
node _T_317 = eq(before, UInt<3>(0h5))
node _T_318 = eq(after, UInt<1>(0h1))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(_T_319, UInt<1>(0h0))
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_T_320, UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_320, UInt<1>(0h1), "") : assert_43
node _T_324 = eq(before, UInt<3>(0h5))
node _T_325 = eq(after, UInt<1>(0h0))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(_T_326, UInt<1>(0h0))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_327, UInt<1>(0h1), "") : assert_44
node _T_331 = eq(before, UInt<3>(0h5))
node _T_332 = eq(after, UInt<3>(0h7))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(before, UInt<3>(0h5))
node _T_335 = eq(after, UInt<3>(0h6))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(_T_336, UInt<1>(0h0))
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_337, UInt<1>(0h1), "") : assert_45
node _T_341 = eq(before, UInt<3>(0h5))
node _T_342 = eq(after, UInt<3>(0h4))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(_T_343, UInt<1>(0h0))
node _T_345 = asUInt(reset)
node _T_346 = eq(_T_345, UInt<1>(0h0))
when _T_346 :
node _T_347 = eq(_T_344, UInt<1>(0h0))
when _T_347 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_344, UInt<1>(0h1), "") : assert_46
node _T_348 = eq(before, UInt<3>(0h5))
node _T_349 = eq(after, UInt<2>(0h3))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(before, UInt<3>(0h5))
node _T_352 = eq(after, UInt<2>(0h2))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(_T_353, UInt<1>(0h0))
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_354, UInt<1>(0h1), "") : assert_47
node _T_358 = eq(before, UInt<3>(0h6))
node _T_359 = eq(after, UInt<4>(0h8))
node _T_360 = and(_T_358, _T_359)
node _T_361 = eq(_T_360, UInt<1>(0h0))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_361, UInt<1>(0h1), "") : assert_48
node _T_365 = eq(before, UInt<3>(0h6))
node _T_366 = eq(after, UInt<1>(0h1))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(_T_367, UInt<1>(0h0))
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_368, UInt<1>(0h1), "") : assert_49
node _T_372 = eq(before, UInt<3>(0h6))
node _T_373 = eq(after, UInt<1>(0h0))
node _T_374 = and(_T_372, _T_373)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_375, UInt<1>(0h1), "") : assert_50
node _T_379 = eq(before, UInt<3>(0h6))
node _T_380 = eq(after, UInt<3>(0h7))
node _T_381 = and(_T_379, _T_380)
node _T_382 = eq(_T_381, UInt<1>(0h0))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_382, UInt<1>(0h1), "") : assert_51
node _T_386 = eq(before, UInt<3>(0h6))
node _T_387 = eq(after, UInt<3>(0h5))
node _T_388 = and(_T_386, _T_387)
node _T_389 = eq(_T_388, UInt<1>(0h0))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_389, UInt<1>(0h1), "") : assert_52
node _T_393 = eq(before, UInt<3>(0h6))
node _T_394 = eq(after, UInt<3>(0h4))
node _T_395 = and(_T_393, _T_394)
node _T_396 = eq(_T_395, UInt<1>(0h0))
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(_T_396, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_396, UInt<1>(0h1), "") : assert_53
node _T_400 = eq(before, UInt<3>(0h6))
node _T_401 = eq(after, UInt<2>(0h3))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(_T_402, UInt<1>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_403, UInt<1>(0h1), "") : assert_54
node _T_407 = eq(before, UInt<3>(0h6))
node _T_408 = eq(after, UInt<2>(0h2))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(before, UInt<3>(0h4))
node _T_411 = eq(after, UInt<4>(0h8))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(_T_412, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_413, UInt<1>(0h1), "") : assert_55
node _T_417 = eq(before, UInt<3>(0h4))
node _T_418 = eq(after, UInt<1>(0h1))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(_T_419, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_420, UInt<1>(0h1), "") : assert_56
node _T_424 = eq(before, UInt<3>(0h4))
node _T_425 = eq(after, UInt<1>(0h0))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(_T_426, UInt<1>(0h0))
node _T_428 = asUInt(reset)
node _T_429 = eq(_T_428, UInt<1>(0h0))
when _T_429 :
node _T_430 = eq(_T_427, UInt<1>(0h0))
when _T_430 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_427, UInt<1>(0h1), "") : assert_57
node _T_431 = eq(before, UInt<3>(0h4))
node _T_432 = eq(after, UInt<3>(0h7))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(_T_433, UInt<1>(0h0))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_434, UInt<1>(0h1), "") : assert_58
node _T_438 = eq(before, UInt<3>(0h4))
node _T_439 = eq(after, UInt<3>(0h5))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(_T_440, UInt<1>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_441, UInt<1>(0h1), "") : assert_59
node _T_445 = eq(before, UInt<3>(0h4))
node _T_446 = eq(after, UInt<3>(0h6))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(before, UInt<3>(0h4))
node _T_449 = eq(after, UInt<2>(0h3))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(_T_450, UInt<1>(0h0))
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_451, UInt<1>(0h1), "") : assert_60
node _T_455 = eq(before, UInt<3>(0h4))
node _T_456 = eq(after, UInt<2>(0h2))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(before, UInt<2>(0h3))
node _T_459 = eq(after, UInt<4>(0h8))
node _T_460 = and(_T_458, _T_459)
node _T_461 = eq(_T_460, UInt<1>(0h0))
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_461, UInt<1>(0h1), "") : assert_61
node _T_465 = eq(before, UInt<2>(0h3))
node _T_466 = eq(after, UInt<1>(0h1))
node _T_467 = and(_T_465, _T_466)
node _T_468 = eq(_T_467, UInt<1>(0h0))
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_468, UInt<1>(0h1), "") : assert_62
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<1>(0h0))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_475, UInt<1>(0h1), "") : assert_63
node _T_479 = eq(before, UInt<2>(0h3))
node _T_480 = eq(after, UInt<3>(0h7))
node _T_481 = and(_T_479, _T_480)
node _T_482 = eq(before, UInt<2>(0h3))
node _T_483 = eq(after, UInt<3>(0h5))
node _T_484 = and(_T_482, _T_483)
node _T_485 = eq(before, UInt<2>(0h3))
node _T_486 = eq(after, UInt<3>(0h6))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(before, UInt<2>(0h3))
node _T_489 = eq(after, UInt<3>(0h4))
node _T_490 = and(_T_488, _T_489)
node _T_491 = eq(before, UInt<2>(0h3))
node _T_492 = eq(after, UInt<2>(0h2))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(before, UInt<2>(0h2))
node _T_495 = eq(after, UInt<4>(0h8))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(_T_496, UInt<1>(0h0))
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(_T_497, UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_497, UInt<1>(0h1), "") : assert_64
node _T_501 = eq(before, UInt<2>(0h2))
node _T_502 = eq(after, UInt<1>(0h1))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(_T_503, UInt<1>(0h0))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_504, UInt<1>(0h1), "") : assert_65
node _T_508 = eq(before, UInt<2>(0h2))
node _T_509 = eq(after, UInt<1>(0h0))
node _T_510 = and(_T_508, _T_509)
node _T_511 = eq(_T_510, UInt<1>(0h0))
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(_T_511, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_511, UInt<1>(0h1), "") : assert_66
node _T_515 = eq(before, UInt<2>(0h2))
node _T_516 = eq(after, UInt<3>(0h7))
node _T_517 = and(_T_515, _T_516)
node _T_518 = eq(_T_517, UInt<1>(0h0))
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_518, UInt<1>(0h1), "") : assert_67
node _T_522 = eq(before, UInt<2>(0h2))
node _T_523 = eq(after, UInt<3>(0h5))
node _T_524 = and(_T_522, _T_523)
node _T_525 = eq(_T_524, UInt<1>(0h0))
node _T_526 = asUInt(reset)
node _T_527 = eq(_T_526, UInt<1>(0h0))
when _T_527 :
node _T_528 = eq(_T_525, UInt<1>(0h0))
when _T_528 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68
assert(clock, _T_525, UInt<1>(0h1), "") : assert_68
node _T_529 = eq(before, UInt<2>(0h2))
node _T_530 = eq(after, UInt<3>(0h6))
node _T_531 = and(_T_529, _T_530)
node _T_532 = eq(before, UInt<2>(0h2))
node _T_533 = eq(after, UInt<3>(0h4))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(before, UInt<2>(0h2))
node _T_536 = eq(after, UInt<2>(0h3))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(_T_537, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69
assert(clock, _T_538, UInt<1>(0h1), "") : assert_69
node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<4>(0h0))
node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 3, 0)
node _probe_bit_T = shr(io.sinkc.bits.source, 4)
node _probe_bit_T_1 = eq(_probe_bit_T, UInt<1>(0h1))
node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits)
node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2)
node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<4>(0h8))
node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4)
node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<4>(0h0))
node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 3, 0)
node _probe_bit_T_6 = shr(io.sinkc.bits.source, 4)
node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<1>(0h0))
node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1)
node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8)
node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<4>(0h8))
node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10)
node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_542 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_543 = and(probe_toN, _T_542)
node _T_544 = eq(probe_toN, UInt<1>(0h0))
node _T_545 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_546 = and(_T_544, _T_545)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_547 = eq(set_pprobeack, UInt<1>(0h0))
node _T_548 = and(_T_547, w_rprobeackfirst)
node _T_549 = and(set_pprobeack, w_rprobeackfirst)
node _T_550 = neq(meta.state, UInt<2>(0h0))
node _T_551 = eq(io.sinkc.bits.tag, meta.tag)
node _T_552 = and(_T_550, _T_551)
node _T_553 = and(_T_552, io.sinkc.bits.data)
when _T_553 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_554 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_555 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_556 = or(_T_554, _T_555)
when _T_556 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_557 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_558 = eq(request.offset, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
node _T_560 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_561 = neq(request.offset, UInt<1>(0h0))
node _T_562 = and(_T_560, _T_561)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_563 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_563 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<4>(0h0))
node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 3, 0)
node _new_clientBit_T = shr(new_request.source, 4)
node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<1>(0h1))
node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits)
node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2)
node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<4>(0h8))
node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4)
node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<4>(0h0))
node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 3, 0)
node _new_clientBit_T_6 = shr(new_request.source, 4)
node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<1>(0h0))
node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1)
node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8)
node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<4>(0h8))
node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10)
node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_564 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_564 :
node _T_565 = eq(prior, UInt<4>(0h8))
node _T_566 = eq(prior, UInt<1>(0h1))
node _T_567 = eq(_T_566, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_70
assert(clock, _T_567, UInt<1>(0h1), "") : assert_70
node _T_571 = eq(prior, UInt<1>(0h0))
node _T_572 = eq(_T_571, UInt<1>(0h0))
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_71
assert(clock, _T_572, UInt<1>(0h1), "") : assert_71
node _T_576 = eq(prior, UInt<3>(0h7))
node _T_577 = eq(prior, UInt<3>(0h5))
node _T_578 = eq(prior, UInt<3>(0h4))
node _T_579 = eq(prior, UInt<3>(0h6))
node _T_580 = eq(prior, UInt<2>(0h3))
node _T_581 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_582 = eq(request_valid, UInt<1>(0h0))
node _T_583 = and(io.schedule.ready, io.schedule.valid)
node _T_584 = and(no_wait, _T_583)
node _T_585 = or(_T_582, _T_584)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_72
assert(clock, _T_585, UInt<1>(0h1), "") : assert_72
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_589 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_590 = or(io.directory.valid, _T_589)
when _T_590 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_591 = and(new_request.prio[2], UInt<1>(0h1))
when _T_591 :
connect s_execute, UInt<1>(0h0)
node _T_592 = bits(new_request.opcode, 0, 0)
node _T_593 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_594 = and(_T_592, _T_593)
when _T_594 :
connect s_writeback, UInt<1>(0h0)
node _T_595 = eq(new_request.param, UInt<3>(0h0))
node _T_596 = eq(new_request.param, UInt<3>(0h4))
node _T_597 = or(_T_595, _T_596)
node _T_598 = eq(new_meta.state, UInt<2>(0h2))
node _T_599 = and(_T_597, _T_598)
when _T_599 :
connect s_writeback, UInt<1>(0h0)
node _T_600 = eq(new_request.param, UInt<3>(0h1))
node _T_601 = eq(new_request.param, UInt<3>(0h2))
node _T_602 = or(_T_600, _T_601)
node _T_603 = eq(new_request.param, UInt<3>(0h5))
node _T_604 = or(_T_602, _T_603)
node _T_605 = and(new_meta.clients, new_clientBit)
node _T_606 = neq(_T_605, UInt<1>(0h0))
node _T_607 = and(_T_604, _T_606)
when _T_607 :
connect s_writeback, UInt<1>(0h0)
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(new_meta.hit, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_73
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_73
else :
node _T_611 = and(new_request.control, UInt<1>(0h1))
when _T_611 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_612 = neq(new_meta.clients, UInt<1>(0h0))
node _T_613 = and(UInt<1>(0h1), _T_612)
when _T_613 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_614 = eq(new_meta.hit, UInt<1>(0h0))
node _T_615 = neq(new_meta.state, UInt<2>(0h0))
node _T_616 = and(_T_614, _T_615)
when _T_616 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_617 = neq(new_meta.clients, UInt<1>(0h0))
node _T_618 = and(UInt<1>(0h1), _T_617)
when _T_618 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_619 = eq(new_meta.hit, UInt<1>(0h0))
node _T_620 = eq(new_meta.state, UInt<2>(0h1))
node _T_621 = and(_T_620, new_needT)
node _T_622 = or(_T_619, _T_621)
when _T_622 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_623 = eq(new_meta.state, UInt<2>(0h2))
node _T_624 = or(new_needT, _T_623)
node _T_625 = and(new_meta.hit, _T_624)
node _T_626 = not(new_skipProbe)
node _T_627 = and(new_meta.clients, _T_626)
node _T_628 = neq(_T_627, UInt<1>(0h0))
node _T_629 = and(_T_625, _T_628)
node _T_630 = and(UInt<1>(0h1), _T_629)
when _T_630 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_631 = eq(new_request.opcode, UInt<3>(0h6))
node _T_632 = eq(new_request.opcode, UInt<3>(0h7))
node _T_633 = or(_T_631, _T_632)
when _T_633 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_634 = bits(new_request.opcode, 2, 2)
node _T_635 = eq(_T_634, UInt<1>(0h0))
node _T_636 = and(_T_635, new_meta.hit)
node _T_637 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_638 = and(_T_636, _T_637)
when _T_638 :
connect s_writeback, UInt<1>(0h0) | module MSHR( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [4:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29]
reg [11:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [1:0] meta_clients; // @[MSHR.scala:100:17]
reg [11:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [1:0] probes_done; // @[MSHR.scala:150:24]
reg [1:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10]
wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10]
wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48]
wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [1:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [1:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_590 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_31 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst mulFullRaw of MulFullRawFN_31
connect mulFullRaw.io.a.sig, io.a.sig
connect mulFullRaw.io.a.sExp, io.a.sExp
connect mulFullRaw.io.a.sign, io.a.sign
connect mulFullRaw.io.a.isZero, io.a.isZero
connect mulFullRaw.io.a.isInf, io.a.isInf
connect mulFullRaw.io.a.isNaN, io.a.isNaN
connect mulFullRaw.io.b.sig, io.b.sig
connect mulFullRaw.io.b.sExp, io.b.sExp
connect mulFullRaw.io.b.sign, io.b.sign
connect mulFullRaw.io.b.isZero, io.b.isZero
connect mulFullRaw.io.b.isInf, io.b.isInf
connect mulFullRaw.io.b.isNaN, io.b.isNaN
connect io.invalidExc, mulFullRaw.io.invalidExc
connect io.rawOut, mulFullRaw.io.rawOut
node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22)
node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0)
node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1)
node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2)
connect io.rawOut.sig, _io_rawOut_sig_T_3 | module MulRawFN_31( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_31 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_270 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_270( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_54 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_54
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_134
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_54( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_54 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_134 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_416 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_160
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_416( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_160 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Atomics_4 :
input clock : Clock
input reset : Reset
output io : { flip write : UInt<1>, flip a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, flip data_in : UInt<128>, data_out : UInt<128>}
node adder = bits(io.a.param, 2, 2)
node unsigned = bits(io.a.param, 1, 1)
node take_max = bits(io.a.param, 0, 0)
node _signBit_T = not(io.a.mask)
node _signBit_T_1 = shr(_signBit_T, 1)
node _signBit_T_2 = cat(UInt<1>(0h1), _signBit_T_1)
node signBit = and(io.a.mask, _signBit_T_2)
node _inv_d_T = not(io.data_in)
node inv_d = mux(adder, io.data_in, _inv_d_T)
node _sum_T = bits(io.a.mask, 0, 0)
node _sum_T_1 = bits(io.a.mask, 1, 1)
node _sum_T_2 = bits(io.a.mask, 2, 2)
node _sum_T_3 = bits(io.a.mask, 3, 3)
node _sum_T_4 = bits(io.a.mask, 4, 4)
node _sum_T_5 = bits(io.a.mask, 5, 5)
node _sum_T_6 = bits(io.a.mask, 6, 6)
node _sum_T_7 = bits(io.a.mask, 7, 7)
node _sum_T_8 = bits(io.a.mask, 8, 8)
node _sum_T_9 = bits(io.a.mask, 9, 9)
node _sum_T_10 = bits(io.a.mask, 10, 10)
node _sum_T_11 = bits(io.a.mask, 11, 11)
node _sum_T_12 = bits(io.a.mask, 12, 12)
node _sum_T_13 = bits(io.a.mask, 13, 13)
node _sum_T_14 = bits(io.a.mask, 14, 14)
node _sum_T_15 = bits(io.a.mask, 15, 15)
node _sum_T_16 = mux(_sum_T, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_17 = mux(_sum_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_18 = mux(_sum_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_19 = mux(_sum_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_20 = mux(_sum_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_21 = mux(_sum_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_22 = mux(_sum_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_23 = mux(_sum_T_7, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_24 = mux(_sum_T_8, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_25 = mux(_sum_T_9, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_26 = mux(_sum_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_27 = mux(_sum_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_28 = mux(_sum_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_29 = mux(_sum_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_30 = mux(_sum_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_31 = mux(_sum_T_15, UInt<8>(0hff), UInt<8>(0h0))
node sum_lo_lo_lo = cat(_sum_T_17, _sum_T_16)
node sum_lo_lo_hi = cat(_sum_T_19, _sum_T_18)
node sum_lo_lo = cat(sum_lo_lo_hi, sum_lo_lo_lo)
node sum_lo_hi_lo = cat(_sum_T_21, _sum_T_20)
node sum_lo_hi_hi = cat(_sum_T_23, _sum_T_22)
node sum_lo_hi = cat(sum_lo_hi_hi, sum_lo_hi_lo)
node sum_lo = cat(sum_lo_hi, sum_lo_lo)
node sum_hi_lo_lo = cat(_sum_T_25, _sum_T_24)
node sum_hi_lo_hi = cat(_sum_T_27, _sum_T_26)
node sum_hi_lo = cat(sum_hi_lo_hi, sum_hi_lo_lo)
node sum_hi_hi_lo = cat(_sum_T_29, _sum_T_28)
node sum_hi_hi_hi = cat(_sum_T_31, _sum_T_30)
node sum_hi_hi = cat(sum_hi_hi_hi, sum_hi_hi_lo)
node sum_hi = cat(sum_hi_hi, sum_hi_lo)
node _sum_T_32 = cat(sum_hi, sum_lo)
node _sum_T_33 = and(_sum_T_32, io.a.data)
node _sum_T_34 = add(_sum_T_33, inv_d)
node sum = tail(_sum_T_34, 1)
node _sign_a_T = bits(io.a.data, 0, 0)
node _sign_a_T_1 = bits(io.a.data, 1, 1)
node _sign_a_T_2 = bits(io.a.data, 2, 2)
node _sign_a_T_3 = bits(io.a.data, 3, 3)
node _sign_a_T_4 = bits(io.a.data, 4, 4)
node _sign_a_T_5 = bits(io.a.data, 5, 5)
node _sign_a_T_6 = bits(io.a.data, 6, 6)
node _sign_a_T_7 = bits(io.a.data, 7, 7)
node _sign_a_T_8 = bits(io.a.data, 8, 8)
node _sign_a_T_9 = bits(io.a.data, 9, 9)
node _sign_a_T_10 = bits(io.a.data, 10, 10)
node _sign_a_T_11 = bits(io.a.data, 11, 11)
node _sign_a_T_12 = bits(io.a.data, 12, 12)
node _sign_a_T_13 = bits(io.a.data, 13, 13)
node _sign_a_T_14 = bits(io.a.data, 14, 14)
node _sign_a_T_15 = bits(io.a.data, 15, 15)
node _sign_a_T_16 = bits(io.a.data, 16, 16)
node _sign_a_T_17 = bits(io.a.data, 17, 17)
node _sign_a_T_18 = bits(io.a.data, 18, 18)
node _sign_a_T_19 = bits(io.a.data, 19, 19)
node _sign_a_T_20 = bits(io.a.data, 20, 20)
node _sign_a_T_21 = bits(io.a.data, 21, 21)
node _sign_a_T_22 = bits(io.a.data, 22, 22)
node _sign_a_T_23 = bits(io.a.data, 23, 23)
node _sign_a_T_24 = bits(io.a.data, 24, 24)
node _sign_a_T_25 = bits(io.a.data, 25, 25)
node _sign_a_T_26 = bits(io.a.data, 26, 26)
node _sign_a_T_27 = bits(io.a.data, 27, 27)
node _sign_a_T_28 = bits(io.a.data, 28, 28)
node _sign_a_T_29 = bits(io.a.data, 29, 29)
node _sign_a_T_30 = bits(io.a.data, 30, 30)
node _sign_a_T_31 = bits(io.a.data, 31, 31)
node _sign_a_T_32 = bits(io.a.data, 32, 32)
node _sign_a_T_33 = bits(io.a.data, 33, 33)
node _sign_a_T_34 = bits(io.a.data, 34, 34)
node _sign_a_T_35 = bits(io.a.data, 35, 35)
node _sign_a_T_36 = bits(io.a.data, 36, 36)
node _sign_a_T_37 = bits(io.a.data, 37, 37)
node _sign_a_T_38 = bits(io.a.data, 38, 38)
node _sign_a_T_39 = bits(io.a.data, 39, 39)
node _sign_a_T_40 = bits(io.a.data, 40, 40)
node _sign_a_T_41 = bits(io.a.data, 41, 41)
node _sign_a_T_42 = bits(io.a.data, 42, 42)
node _sign_a_T_43 = bits(io.a.data, 43, 43)
node _sign_a_T_44 = bits(io.a.data, 44, 44)
node _sign_a_T_45 = bits(io.a.data, 45, 45)
node _sign_a_T_46 = bits(io.a.data, 46, 46)
node _sign_a_T_47 = bits(io.a.data, 47, 47)
node _sign_a_T_48 = bits(io.a.data, 48, 48)
node _sign_a_T_49 = bits(io.a.data, 49, 49)
node _sign_a_T_50 = bits(io.a.data, 50, 50)
node _sign_a_T_51 = bits(io.a.data, 51, 51)
node _sign_a_T_52 = bits(io.a.data, 52, 52)
node _sign_a_T_53 = bits(io.a.data, 53, 53)
node _sign_a_T_54 = bits(io.a.data, 54, 54)
node _sign_a_T_55 = bits(io.a.data, 55, 55)
node _sign_a_T_56 = bits(io.a.data, 56, 56)
node _sign_a_T_57 = bits(io.a.data, 57, 57)
node _sign_a_T_58 = bits(io.a.data, 58, 58)
node _sign_a_T_59 = bits(io.a.data, 59, 59)
node _sign_a_T_60 = bits(io.a.data, 60, 60)
node _sign_a_T_61 = bits(io.a.data, 61, 61)
node _sign_a_T_62 = bits(io.a.data, 62, 62)
node _sign_a_T_63 = bits(io.a.data, 63, 63)
node _sign_a_T_64 = bits(io.a.data, 64, 64)
node _sign_a_T_65 = bits(io.a.data, 65, 65)
node _sign_a_T_66 = bits(io.a.data, 66, 66)
node _sign_a_T_67 = bits(io.a.data, 67, 67)
node _sign_a_T_68 = bits(io.a.data, 68, 68)
node _sign_a_T_69 = bits(io.a.data, 69, 69)
node _sign_a_T_70 = bits(io.a.data, 70, 70)
node _sign_a_T_71 = bits(io.a.data, 71, 71)
node _sign_a_T_72 = bits(io.a.data, 72, 72)
node _sign_a_T_73 = bits(io.a.data, 73, 73)
node _sign_a_T_74 = bits(io.a.data, 74, 74)
node _sign_a_T_75 = bits(io.a.data, 75, 75)
node _sign_a_T_76 = bits(io.a.data, 76, 76)
node _sign_a_T_77 = bits(io.a.data, 77, 77)
node _sign_a_T_78 = bits(io.a.data, 78, 78)
node _sign_a_T_79 = bits(io.a.data, 79, 79)
node _sign_a_T_80 = bits(io.a.data, 80, 80)
node _sign_a_T_81 = bits(io.a.data, 81, 81)
node _sign_a_T_82 = bits(io.a.data, 82, 82)
node _sign_a_T_83 = bits(io.a.data, 83, 83)
node _sign_a_T_84 = bits(io.a.data, 84, 84)
node _sign_a_T_85 = bits(io.a.data, 85, 85)
node _sign_a_T_86 = bits(io.a.data, 86, 86)
node _sign_a_T_87 = bits(io.a.data, 87, 87)
node _sign_a_T_88 = bits(io.a.data, 88, 88)
node _sign_a_T_89 = bits(io.a.data, 89, 89)
node _sign_a_T_90 = bits(io.a.data, 90, 90)
node _sign_a_T_91 = bits(io.a.data, 91, 91)
node _sign_a_T_92 = bits(io.a.data, 92, 92)
node _sign_a_T_93 = bits(io.a.data, 93, 93)
node _sign_a_T_94 = bits(io.a.data, 94, 94)
node _sign_a_T_95 = bits(io.a.data, 95, 95)
node _sign_a_T_96 = bits(io.a.data, 96, 96)
node _sign_a_T_97 = bits(io.a.data, 97, 97)
node _sign_a_T_98 = bits(io.a.data, 98, 98)
node _sign_a_T_99 = bits(io.a.data, 99, 99)
node _sign_a_T_100 = bits(io.a.data, 100, 100)
node _sign_a_T_101 = bits(io.a.data, 101, 101)
node _sign_a_T_102 = bits(io.a.data, 102, 102)
node _sign_a_T_103 = bits(io.a.data, 103, 103)
node _sign_a_T_104 = bits(io.a.data, 104, 104)
node _sign_a_T_105 = bits(io.a.data, 105, 105)
node _sign_a_T_106 = bits(io.a.data, 106, 106)
node _sign_a_T_107 = bits(io.a.data, 107, 107)
node _sign_a_T_108 = bits(io.a.data, 108, 108)
node _sign_a_T_109 = bits(io.a.data, 109, 109)
node _sign_a_T_110 = bits(io.a.data, 110, 110)
node _sign_a_T_111 = bits(io.a.data, 111, 111)
node _sign_a_T_112 = bits(io.a.data, 112, 112)
node _sign_a_T_113 = bits(io.a.data, 113, 113)
node _sign_a_T_114 = bits(io.a.data, 114, 114)
node _sign_a_T_115 = bits(io.a.data, 115, 115)
node _sign_a_T_116 = bits(io.a.data, 116, 116)
node _sign_a_T_117 = bits(io.a.data, 117, 117)
node _sign_a_T_118 = bits(io.a.data, 118, 118)
node _sign_a_T_119 = bits(io.a.data, 119, 119)
node _sign_a_T_120 = bits(io.a.data, 120, 120)
node _sign_a_T_121 = bits(io.a.data, 121, 121)
node _sign_a_T_122 = bits(io.a.data, 122, 122)
node _sign_a_T_123 = bits(io.a.data, 123, 123)
node _sign_a_T_124 = bits(io.a.data, 124, 124)
node _sign_a_T_125 = bits(io.a.data, 125, 125)
node _sign_a_T_126 = bits(io.a.data, 126, 126)
node _sign_a_T_127 = bits(io.a.data, 127, 127)
node sign_a_lo_lo_lo = cat(_sign_a_T_15, _sign_a_T_7)
node sign_a_lo_lo_hi = cat(_sign_a_T_31, _sign_a_T_23)
node sign_a_lo_lo = cat(sign_a_lo_lo_hi, sign_a_lo_lo_lo)
node sign_a_lo_hi_lo = cat(_sign_a_T_47, _sign_a_T_39)
node sign_a_lo_hi_hi = cat(_sign_a_T_63, _sign_a_T_55)
node sign_a_lo_hi = cat(sign_a_lo_hi_hi, sign_a_lo_hi_lo)
node sign_a_lo = cat(sign_a_lo_hi, sign_a_lo_lo)
node sign_a_hi_lo_lo = cat(_sign_a_T_79, _sign_a_T_71)
node sign_a_hi_lo_hi = cat(_sign_a_T_95, _sign_a_T_87)
node sign_a_hi_lo = cat(sign_a_hi_lo_hi, sign_a_hi_lo_lo)
node sign_a_hi_hi_lo = cat(_sign_a_T_111, _sign_a_T_103)
node sign_a_hi_hi_hi = cat(_sign_a_T_127, _sign_a_T_119)
node sign_a_hi_hi = cat(sign_a_hi_hi_hi, sign_a_hi_hi_lo)
node sign_a_hi = cat(sign_a_hi_hi, sign_a_hi_lo)
node _sign_a_T_128 = cat(sign_a_hi, sign_a_lo)
node _sign_a_T_129 = and(_sign_a_T_128, signBit)
node sign_a = orr(_sign_a_T_129)
node _sign_d_T = bits(io.data_in, 0, 0)
node _sign_d_T_1 = bits(io.data_in, 1, 1)
node _sign_d_T_2 = bits(io.data_in, 2, 2)
node _sign_d_T_3 = bits(io.data_in, 3, 3)
node _sign_d_T_4 = bits(io.data_in, 4, 4)
node _sign_d_T_5 = bits(io.data_in, 5, 5)
node _sign_d_T_6 = bits(io.data_in, 6, 6)
node _sign_d_T_7 = bits(io.data_in, 7, 7)
node _sign_d_T_8 = bits(io.data_in, 8, 8)
node _sign_d_T_9 = bits(io.data_in, 9, 9)
node _sign_d_T_10 = bits(io.data_in, 10, 10)
node _sign_d_T_11 = bits(io.data_in, 11, 11)
node _sign_d_T_12 = bits(io.data_in, 12, 12)
node _sign_d_T_13 = bits(io.data_in, 13, 13)
node _sign_d_T_14 = bits(io.data_in, 14, 14)
node _sign_d_T_15 = bits(io.data_in, 15, 15)
node _sign_d_T_16 = bits(io.data_in, 16, 16)
node _sign_d_T_17 = bits(io.data_in, 17, 17)
node _sign_d_T_18 = bits(io.data_in, 18, 18)
node _sign_d_T_19 = bits(io.data_in, 19, 19)
node _sign_d_T_20 = bits(io.data_in, 20, 20)
node _sign_d_T_21 = bits(io.data_in, 21, 21)
node _sign_d_T_22 = bits(io.data_in, 22, 22)
node _sign_d_T_23 = bits(io.data_in, 23, 23)
node _sign_d_T_24 = bits(io.data_in, 24, 24)
node _sign_d_T_25 = bits(io.data_in, 25, 25)
node _sign_d_T_26 = bits(io.data_in, 26, 26)
node _sign_d_T_27 = bits(io.data_in, 27, 27)
node _sign_d_T_28 = bits(io.data_in, 28, 28)
node _sign_d_T_29 = bits(io.data_in, 29, 29)
node _sign_d_T_30 = bits(io.data_in, 30, 30)
node _sign_d_T_31 = bits(io.data_in, 31, 31)
node _sign_d_T_32 = bits(io.data_in, 32, 32)
node _sign_d_T_33 = bits(io.data_in, 33, 33)
node _sign_d_T_34 = bits(io.data_in, 34, 34)
node _sign_d_T_35 = bits(io.data_in, 35, 35)
node _sign_d_T_36 = bits(io.data_in, 36, 36)
node _sign_d_T_37 = bits(io.data_in, 37, 37)
node _sign_d_T_38 = bits(io.data_in, 38, 38)
node _sign_d_T_39 = bits(io.data_in, 39, 39)
node _sign_d_T_40 = bits(io.data_in, 40, 40)
node _sign_d_T_41 = bits(io.data_in, 41, 41)
node _sign_d_T_42 = bits(io.data_in, 42, 42)
node _sign_d_T_43 = bits(io.data_in, 43, 43)
node _sign_d_T_44 = bits(io.data_in, 44, 44)
node _sign_d_T_45 = bits(io.data_in, 45, 45)
node _sign_d_T_46 = bits(io.data_in, 46, 46)
node _sign_d_T_47 = bits(io.data_in, 47, 47)
node _sign_d_T_48 = bits(io.data_in, 48, 48)
node _sign_d_T_49 = bits(io.data_in, 49, 49)
node _sign_d_T_50 = bits(io.data_in, 50, 50)
node _sign_d_T_51 = bits(io.data_in, 51, 51)
node _sign_d_T_52 = bits(io.data_in, 52, 52)
node _sign_d_T_53 = bits(io.data_in, 53, 53)
node _sign_d_T_54 = bits(io.data_in, 54, 54)
node _sign_d_T_55 = bits(io.data_in, 55, 55)
node _sign_d_T_56 = bits(io.data_in, 56, 56)
node _sign_d_T_57 = bits(io.data_in, 57, 57)
node _sign_d_T_58 = bits(io.data_in, 58, 58)
node _sign_d_T_59 = bits(io.data_in, 59, 59)
node _sign_d_T_60 = bits(io.data_in, 60, 60)
node _sign_d_T_61 = bits(io.data_in, 61, 61)
node _sign_d_T_62 = bits(io.data_in, 62, 62)
node _sign_d_T_63 = bits(io.data_in, 63, 63)
node _sign_d_T_64 = bits(io.data_in, 64, 64)
node _sign_d_T_65 = bits(io.data_in, 65, 65)
node _sign_d_T_66 = bits(io.data_in, 66, 66)
node _sign_d_T_67 = bits(io.data_in, 67, 67)
node _sign_d_T_68 = bits(io.data_in, 68, 68)
node _sign_d_T_69 = bits(io.data_in, 69, 69)
node _sign_d_T_70 = bits(io.data_in, 70, 70)
node _sign_d_T_71 = bits(io.data_in, 71, 71)
node _sign_d_T_72 = bits(io.data_in, 72, 72)
node _sign_d_T_73 = bits(io.data_in, 73, 73)
node _sign_d_T_74 = bits(io.data_in, 74, 74)
node _sign_d_T_75 = bits(io.data_in, 75, 75)
node _sign_d_T_76 = bits(io.data_in, 76, 76)
node _sign_d_T_77 = bits(io.data_in, 77, 77)
node _sign_d_T_78 = bits(io.data_in, 78, 78)
node _sign_d_T_79 = bits(io.data_in, 79, 79)
node _sign_d_T_80 = bits(io.data_in, 80, 80)
node _sign_d_T_81 = bits(io.data_in, 81, 81)
node _sign_d_T_82 = bits(io.data_in, 82, 82)
node _sign_d_T_83 = bits(io.data_in, 83, 83)
node _sign_d_T_84 = bits(io.data_in, 84, 84)
node _sign_d_T_85 = bits(io.data_in, 85, 85)
node _sign_d_T_86 = bits(io.data_in, 86, 86)
node _sign_d_T_87 = bits(io.data_in, 87, 87)
node _sign_d_T_88 = bits(io.data_in, 88, 88)
node _sign_d_T_89 = bits(io.data_in, 89, 89)
node _sign_d_T_90 = bits(io.data_in, 90, 90)
node _sign_d_T_91 = bits(io.data_in, 91, 91)
node _sign_d_T_92 = bits(io.data_in, 92, 92)
node _sign_d_T_93 = bits(io.data_in, 93, 93)
node _sign_d_T_94 = bits(io.data_in, 94, 94)
node _sign_d_T_95 = bits(io.data_in, 95, 95)
node _sign_d_T_96 = bits(io.data_in, 96, 96)
node _sign_d_T_97 = bits(io.data_in, 97, 97)
node _sign_d_T_98 = bits(io.data_in, 98, 98)
node _sign_d_T_99 = bits(io.data_in, 99, 99)
node _sign_d_T_100 = bits(io.data_in, 100, 100)
node _sign_d_T_101 = bits(io.data_in, 101, 101)
node _sign_d_T_102 = bits(io.data_in, 102, 102)
node _sign_d_T_103 = bits(io.data_in, 103, 103)
node _sign_d_T_104 = bits(io.data_in, 104, 104)
node _sign_d_T_105 = bits(io.data_in, 105, 105)
node _sign_d_T_106 = bits(io.data_in, 106, 106)
node _sign_d_T_107 = bits(io.data_in, 107, 107)
node _sign_d_T_108 = bits(io.data_in, 108, 108)
node _sign_d_T_109 = bits(io.data_in, 109, 109)
node _sign_d_T_110 = bits(io.data_in, 110, 110)
node _sign_d_T_111 = bits(io.data_in, 111, 111)
node _sign_d_T_112 = bits(io.data_in, 112, 112)
node _sign_d_T_113 = bits(io.data_in, 113, 113)
node _sign_d_T_114 = bits(io.data_in, 114, 114)
node _sign_d_T_115 = bits(io.data_in, 115, 115)
node _sign_d_T_116 = bits(io.data_in, 116, 116)
node _sign_d_T_117 = bits(io.data_in, 117, 117)
node _sign_d_T_118 = bits(io.data_in, 118, 118)
node _sign_d_T_119 = bits(io.data_in, 119, 119)
node _sign_d_T_120 = bits(io.data_in, 120, 120)
node _sign_d_T_121 = bits(io.data_in, 121, 121)
node _sign_d_T_122 = bits(io.data_in, 122, 122)
node _sign_d_T_123 = bits(io.data_in, 123, 123)
node _sign_d_T_124 = bits(io.data_in, 124, 124)
node _sign_d_T_125 = bits(io.data_in, 125, 125)
node _sign_d_T_126 = bits(io.data_in, 126, 126)
node _sign_d_T_127 = bits(io.data_in, 127, 127)
node sign_d_lo_lo_lo = cat(_sign_d_T_15, _sign_d_T_7)
node sign_d_lo_lo_hi = cat(_sign_d_T_31, _sign_d_T_23)
node sign_d_lo_lo = cat(sign_d_lo_lo_hi, sign_d_lo_lo_lo)
node sign_d_lo_hi_lo = cat(_sign_d_T_47, _sign_d_T_39)
node sign_d_lo_hi_hi = cat(_sign_d_T_63, _sign_d_T_55)
node sign_d_lo_hi = cat(sign_d_lo_hi_hi, sign_d_lo_hi_lo)
node sign_d_lo = cat(sign_d_lo_hi, sign_d_lo_lo)
node sign_d_hi_lo_lo = cat(_sign_d_T_79, _sign_d_T_71)
node sign_d_hi_lo_hi = cat(_sign_d_T_95, _sign_d_T_87)
node sign_d_hi_lo = cat(sign_d_hi_lo_hi, sign_d_hi_lo_lo)
node sign_d_hi_hi_lo = cat(_sign_d_T_111, _sign_d_T_103)
node sign_d_hi_hi_hi = cat(_sign_d_T_127, _sign_d_T_119)
node sign_d_hi_hi = cat(sign_d_hi_hi_hi, sign_d_hi_hi_lo)
node sign_d_hi = cat(sign_d_hi_hi, sign_d_hi_lo)
node _sign_d_T_128 = cat(sign_d_hi, sign_d_lo)
node _sign_d_T_129 = and(_sign_d_T_128, signBit)
node sign_d = orr(_sign_d_T_129)
node _sign_s_T = bits(sum, 0, 0)
node _sign_s_T_1 = bits(sum, 1, 1)
node _sign_s_T_2 = bits(sum, 2, 2)
node _sign_s_T_3 = bits(sum, 3, 3)
node _sign_s_T_4 = bits(sum, 4, 4)
node _sign_s_T_5 = bits(sum, 5, 5)
node _sign_s_T_6 = bits(sum, 6, 6)
node _sign_s_T_7 = bits(sum, 7, 7)
node _sign_s_T_8 = bits(sum, 8, 8)
node _sign_s_T_9 = bits(sum, 9, 9)
node _sign_s_T_10 = bits(sum, 10, 10)
node _sign_s_T_11 = bits(sum, 11, 11)
node _sign_s_T_12 = bits(sum, 12, 12)
node _sign_s_T_13 = bits(sum, 13, 13)
node _sign_s_T_14 = bits(sum, 14, 14)
node _sign_s_T_15 = bits(sum, 15, 15)
node _sign_s_T_16 = bits(sum, 16, 16)
node _sign_s_T_17 = bits(sum, 17, 17)
node _sign_s_T_18 = bits(sum, 18, 18)
node _sign_s_T_19 = bits(sum, 19, 19)
node _sign_s_T_20 = bits(sum, 20, 20)
node _sign_s_T_21 = bits(sum, 21, 21)
node _sign_s_T_22 = bits(sum, 22, 22)
node _sign_s_T_23 = bits(sum, 23, 23)
node _sign_s_T_24 = bits(sum, 24, 24)
node _sign_s_T_25 = bits(sum, 25, 25)
node _sign_s_T_26 = bits(sum, 26, 26)
node _sign_s_T_27 = bits(sum, 27, 27)
node _sign_s_T_28 = bits(sum, 28, 28)
node _sign_s_T_29 = bits(sum, 29, 29)
node _sign_s_T_30 = bits(sum, 30, 30)
node _sign_s_T_31 = bits(sum, 31, 31)
node _sign_s_T_32 = bits(sum, 32, 32)
node _sign_s_T_33 = bits(sum, 33, 33)
node _sign_s_T_34 = bits(sum, 34, 34)
node _sign_s_T_35 = bits(sum, 35, 35)
node _sign_s_T_36 = bits(sum, 36, 36)
node _sign_s_T_37 = bits(sum, 37, 37)
node _sign_s_T_38 = bits(sum, 38, 38)
node _sign_s_T_39 = bits(sum, 39, 39)
node _sign_s_T_40 = bits(sum, 40, 40)
node _sign_s_T_41 = bits(sum, 41, 41)
node _sign_s_T_42 = bits(sum, 42, 42)
node _sign_s_T_43 = bits(sum, 43, 43)
node _sign_s_T_44 = bits(sum, 44, 44)
node _sign_s_T_45 = bits(sum, 45, 45)
node _sign_s_T_46 = bits(sum, 46, 46)
node _sign_s_T_47 = bits(sum, 47, 47)
node _sign_s_T_48 = bits(sum, 48, 48)
node _sign_s_T_49 = bits(sum, 49, 49)
node _sign_s_T_50 = bits(sum, 50, 50)
node _sign_s_T_51 = bits(sum, 51, 51)
node _sign_s_T_52 = bits(sum, 52, 52)
node _sign_s_T_53 = bits(sum, 53, 53)
node _sign_s_T_54 = bits(sum, 54, 54)
node _sign_s_T_55 = bits(sum, 55, 55)
node _sign_s_T_56 = bits(sum, 56, 56)
node _sign_s_T_57 = bits(sum, 57, 57)
node _sign_s_T_58 = bits(sum, 58, 58)
node _sign_s_T_59 = bits(sum, 59, 59)
node _sign_s_T_60 = bits(sum, 60, 60)
node _sign_s_T_61 = bits(sum, 61, 61)
node _sign_s_T_62 = bits(sum, 62, 62)
node _sign_s_T_63 = bits(sum, 63, 63)
node _sign_s_T_64 = bits(sum, 64, 64)
node _sign_s_T_65 = bits(sum, 65, 65)
node _sign_s_T_66 = bits(sum, 66, 66)
node _sign_s_T_67 = bits(sum, 67, 67)
node _sign_s_T_68 = bits(sum, 68, 68)
node _sign_s_T_69 = bits(sum, 69, 69)
node _sign_s_T_70 = bits(sum, 70, 70)
node _sign_s_T_71 = bits(sum, 71, 71)
node _sign_s_T_72 = bits(sum, 72, 72)
node _sign_s_T_73 = bits(sum, 73, 73)
node _sign_s_T_74 = bits(sum, 74, 74)
node _sign_s_T_75 = bits(sum, 75, 75)
node _sign_s_T_76 = bits(sum, 76, 76)
node _sign_s_T_77 = bits(sum, 77, 77)
node _sign_s_T_78 = bits(sum, 78, 78)
node _sign_s_T_79 = bits(sum, 79, 79)
node _sign_s_T_80 = bits(sum, 80, 80)
node _sign_s_T_81 = bits(sum, 81, 81)
node _sign_s_T_82 = bits(sum, 82, 82)
node _sign_s_T_83 = bits(sum, 83, 83)
node _sign_s_T_84 = bits(sum, 84, 84)
node _sign_s_T_85 = bits(sum, 85, 85)
node _sign_s_T_86 = bits(sum, 86, 86)
node _sign_s_T_87 = bits(sum, 87, 87)
node _sign_s_T_88 = bits(sum, 88, 88)
node _sign_s_T_89 = bits(sum, 89, 89)
node _sign_s_T_90 = bits(sum, 90, 90)
node _sign_s_T_91 = bits(sum, 91, 91)
node _sign_s_T_92 = bits(sum, 92, 92)
node _sign_s_T_93 = bits(sum, 93, 93)
node _sign_s_T_94 = bits(sum, 94, 94)
node _sign_s_T_95 = bits(sum, 95, 95)
node _sign_s_T_96 = bits(sum, 96, 96)
node _sign_s_T_97 = bits(sum, 97, 97)
node _sign_s_T_98 = bits(sum, 98, 98)
node _sign_s_T_99 = bits(sum, 99, 99)
node _sign_s_T_100 = bits(sum, 100, 100)
node _sign_s_T_101 = bits(sum, 101, 101)
node _sign_s_T_102 = bits(sum, 102, 102)
node _sign_s_T_103 = bits(sum, 103, 103)
node _sign_s_T_104 = bits(sum, 104, 104)
node _sign_s_T_105 = bits(sum, 105, 105)
node _sign_s_T_106 = bits(sum, 106, 106)
node _sign_s_T_107 = bits(sum, 107, 107)
node _sign_s_T_108 = bits(sum, 108, 108)
node _sign_s_T_109 = bits(sum, 109, 109)
node _sign_s_T_110 = bits(sum, 110, 110)
node _sign_s_T_111 = bits(sum, 111, 111)
node _sign_s_T_112 = bits(sum, 112, 112)
node _sign_s_T_113 = bits(sum, 113, 113)
node _sign_s_T_114 = bits(sum, 114, 114)
node _sign_s_T_115 = bits(sum, 115, 115)
node _sign_s_T_116 = bits(sum, 116, 116)
node _sign_s_T_117 = bits(sum, 117, 117)
node _sign_s_T_118 = bits(sum, 118, 118)
node _sign_s_T_119 = bits(sum, 119, 119)
node _sign_s_T_120 = bits(sum, 120, 120)
node _sign_s_T_121 = bits(sum, 121, 121)
node _sign_s_T_122 = bits(sum, 122, 122)
node _sign_s_T_123 = bits(sum, 123, 123)
node _sign_s_T_124 = bits(sum, 124, 124)
node _sign_s_T_125 = bits(sum, 125, 125)
node _sign_s_T_126 = bits(sum, 126, 126)
node _sign_s_T_127 = bits(sum, 127, 127)
node sign_s_lo_lo_lo = cat(_sign_s_T_15, _sign_s_T_7)
node sign_s_lo_lo_hi = cat(_sign_s_T_31, _sign_s_T_23)
node sign_s_lo_lo = cat(sign_s_lo_lo_hi, sign_s_lo_lo_lo)
node sign_s_lo_hi_lo = cat(_sign_s_T_47, _sign_s_T_39)
node sign_s_lo_hi_hi = cat(_sign_s_T_63, _sign_s_T_55)
node sign_s_lo_hi = cat(sign_s_lo_hi_hi, sign_s_lo_hi_lo)
node sign_s_lo = cat(sign_s_lo_hi, sign_s_lo_lo)
node sign_s_hi_lo_lo = cat(_sign_s_T_79, _sign_s_T_71)
node sign_s_hi_lo_hi = cat(_sign_s_T_95, _sign_s_T_87)
node sign_s_hi_lo = cat(sign_s_hi_lo_hi, sign_s_hi_lo_lo)
node sign_s_hi_hi_lo = cat(_sign_s_T_111, _sign_s_T_103)
node sign_s_hi_hi_hi = cat(_sign_s_T_127, _sign_s_T_119)
node sign_s_hi_hi = cat(sign_s_hi_hi_hi, sign_s_hi_hi_lo)
node sign_s_hi = cat(sign_s_hi_hi, sign_s_hi_lo)
node _sign_s_T_128 = cat(sign_s_hi, sign_s_lo)
node _sign_s_T_129 = and(_sign_s_T_128, signBit)
node sign_s = orr(_sign_s_T_129)
node a_bigger_uneq = eq(unsigned, sign_a)
node _a_bigger_T = eq(sign_a, sign_d)
node _a_bigger_T_1 = eq(sign_s, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T, _a_bigger_T_1, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
wire _lut_WIRE : UInt<4>[4]
connect _lut_WIRE[0], UInt<3>(0h6)
connect _lut_WIRE[1], UInt<4>(0he)
connect _lut_WIRE[2], UInt<4>(0h8)
connect _lut_WIRE[3], UInt<4>(0hc)
node _lut_T = bits(io.a.param, 1, 0)
node _logical_T = bits(io.a.data, 0, 0)
node _logical_T_1 = bits(io.a.data, 1, 1)
node _logical_T_2 = bits(io.a.data, 2, 2)
node _logical_T_3 = bits(io.a.data, 3, 3)
node _logical_T_4 = bits(io.a.data, 4, 4)
node _logical_T_5 = bits(io.a.data, 5, 5)
node _logical_T_6 = bits(io.a.data, 6, 6)
node _logical_T_7 = bits(io.a.data, 7, 7)
node _logical_T_8 = bits(io.a.data, 8, 8)
node _logical_T_9 = bits(io.a.data, 9, 9)
node _logical_T_10 = bits(io.a.data, 10, 10)
node _logical_T_11 = bits(io.a.data, 11, 11)
node _logical_T_12 = bits(io.a.data, 12, 12)
node _logical_T_13 = bits(io.a.data, 13, 13)
node _logical_T_14 = bits(io.a.data, 14, 14)
node _logical_T_15 = bits(io.a.data, 15, 15)
node _logical_T_16 = bits(io.a.data, 16, 16)
node _logical_T_17 = bits(io.a.data, 17, 17)
node _logical_T_18 = bits(io.a.data, 18, 18)
node _logical_T_19 = bits(io.a.data, 19, 19)
node _logical_T_20 = bits(io.a.data, 20, 20)
node _logical_T_21 = bits(io.a.data, 21, 21)
node _logical_T_22 = bits(io.a.data, 22, 22)
node _logical_T_23 = bits(io.a.data, 23, 23)
node _logical_T_24 = bits(io.a.data, 24, 24)
node _logical_T_25 = bits(io.a.data, 25, 25)
node _logical_T_26 = bits(io.a.data, 26, 26)
node _logical_T_27 = bits(io.a.data, 27, 27)
node _logical_T_28 = bits(io.a.data, 28, 28)
node _logical_T_29 = bits(io.a.data, 29, 29)
node _logical_T_30 = bits(io.a.data, 30, 30)
node _logical_T_31 = bits(io.a.data, 31, 31)
node _logical_T_32 = bits(io.a.data, 32, 32)
node _logical_T_33 = bits(io.a.data, 33, 33)
node _logical_T_34 = bits(io.a.data, 34, 34)
node _logical_T_35 = bits(io.a.data, 35, 35)
node _logical_T_36 = bits(io.a.data, 36, 36)
node _logical_T_37 = bits(io.a.data, 37, 37)
node _logical_T_38 = bits(io.a.data, 38, 38)
node _logical_T_39 = bits(io.a.data, 39, 39)
node _logical_T_40 = bits(io.a.data, 40, 40)
node _logical_T_41 = bits(io.a.data, 41, 41)
node _logical_T_42 = bits(io.a.data, 42, 42)
node _logical_T_43 = bits(io.a.data, 43, 43)
node _logical_T_44 = bits(io.a.data, 44, 44)
node _logical_T_45 = bits(io.a.data, 45, 45)
node _logical_T_46 = bits(io.a.data, 46, 46)
node _logical_T_47 = bits(io.a.data, 47, 47)
node _logical_T_48 = bits(io.a.data, 48, 48)
node _logical_T_49 = bits(io.a.data, 49, 49)
node _logical_T_50 = bits(io.a.data, 50, 50)
node _logical_T_51 = bits(io.a.data, 51, 51)
node _logical_T_52 = bits(io.a.data, 52, 52)
node _logical_T_53 = bits(io.a.data, 53, 53)
node _logical_T_54 = bits(io.a.data, 54, 54)
node _logical_T_55 = bits(io.a.data, 55, 55)
node _logical_T_56 = bits(io.a.data, 56, 56)
node _logical_T_57 = bits(io.a.data, 57, 57)
node _logical_T_58 = bits(io.a.data, 58, 58)
node _logical_T_59 = bits(io.a.data, 59, 59)
node _logical_T_60 = bits(io.a.data, 60, 60)
node _logical_T_61 = bits(io.a.data, 61, 61)
node _logical_T_62 = bits(io.a.data, 62, 62)
node _logical_T_63 = bits(io.a.data, 63, 63)
node _logical_T_64 = bits(io.a.data, 64, 64)
node _logical_T_65 = bits(io.a.data, 65, 65)
node _logical_T_66 = bits(io.a.data, 66, 66)
node _logical_T_67 = bits(io.a.data, 67, 67)
node _logical_T_68 = bits(io.a.data, 68, 68)
node _logical_T_69 = bits(io.a.data, 69, 69)
node _logical_T_70 = bits(io.a.data, 70, 70)
node _logical_T_71 = bits(io.a.data, 71, 71)
node _logical_T_72 = bits(io.a.data, 72, 72)
node _logical_T_73 = bits(io.a.data, 73, 73)
node _logical_T_74 = bits(io.a.data, 74, 74)
node _logical_T_75 = bits(io.a.data, 75, 75)
node _logical_T_76 = bits(io.a.data, 76, 76)
node _logical_T_77 = bits(io.a.data, 77, 77)
node _logical_T_78 = bits(io.a.data, 78, 78)
node _logical_T_79 = bits(io.a.data, 79, 79)
node _logical_T_80 = bits(io.a.data, 80, 80)
node _logical_T_81 = bits(io.a.data, 81, 81)
node _logical_T_82 = bits(io.a.data, 82, 82)
node _logical_T_83 = bits(io.a.data, 83, 83)
node _logical_T_84 = bits(io.a.data, 84, 84)
node _logical_T_85 = bits(io.a.data, 85, 85)
node _logical_T_86 = bits(io.a.data, 86, 86)
node _logical_T_87 = bits(io.a.data, 87, 87)
node _logical_T_88 = bits(io.a.data, 88, 88)
node _logical_T_89 = bits(io.a.data, 89, 89)
node _logical_T_90 = bits(io.a.data, 90, 90)
node _logical_T_91 = bits(io.a.data, 91, 91)
node _logical_T_92 = bits(io.a.data, 92, 92)
node _logical_T_93 = bits(io.a.data, 93, 93)
node _logical_T_94 = bits(io.a.data, 94, 94)
node _logical_T_95 = bits(io.a.data, 95, 95)
node _logical_T_96 = bits(io.a.data, 96, 96)
node _logical_T_97 = bits(io.a.data, 97, 97)
node _logical_T_98 = bits(io.a.data, 98, 98)
node _logical_T_99 = bits(io.a.data, 99, 99)
node _logical_T_100 = bits(io.a.data, 100, 100)
node _logical_T_101 = bits(io.a.data, 101, 101)
node _logical_T_102 = bits(io.a.data, 102, 102)
node _logical_T_103 = bits(io.a.data, 103, 103)
node _logical_T_104 = bits(io.a.data, 104, 104)
node _logical_T_105 = bits(io.a.data, 105, 105)
node _logical_T_106 = bits(io.a.data, 106, 106)
node _logical_T_107 = bits(io.a.data, 107, 107)
node _logical_T_108 = bits(io.a.data, 108, 108)
node _logical_T_109 = bits(io.a.data, 109, 109)
node _logical_T_110 = bits(io.a.data, 110, 110)
node _logical_T_111 = bits(io.a.data, 111, 111)
node _logical_T_112 = bits(io.a.data, 112, 112)
node _logical_T_113 = bits(io.a.data, 113, 113)
node _logical_T_114 = bits(io.a.data, 114, 114)
node _logical_T_115 = bits(io.a.data, 115, 115)
node _logical_T_116 = bits(io.a.data, 116, 116)
node _logical_T_117 = bits(io.a.data, 117, 117)
node _logical_T_118 = bits(io.a.data, 118, 118)
node _logical_T_119 = bits(io.a.data, 119, 119)
node _logical_T_120 = bits(io.a.data, 120, 120)
node _logical_T_121 = bits(io.a.data, 121, 121)
node _logical_T_122 = bits(io.a.data, 122, 122)
node _logical_T_123 = bits(io.a.data, 123, 123)
node _logical_T_124 = bits(io.a.data, 124, 124)
node _logical_T_125 = bits(io.a.data, 125, 125)
node _logical_T_126 = bits(io.a.data, 126, 126)
node _logical_T_127 = bits(io.a.data, 127, 127)
node _logical_T_128 = bits(io.data_in, 0, 0)
node _logical_T_129 = bits(io.data_in, 1, 1)
node _logical_T_130 = bits(io.data_in, 2, 2)
node _logical_T_131 = bits(io.data_in, 3, 3)
node _logical_T_132 = bits(io.data_in, 4, 4)
node _logical_T_133 = bits(io.data_in, 5, 5)
node _logical_T_134 = bits(io.data_in, 6, 6)
node _logical_T_135 = bits(io.data_in, 7, 7)
node _logical_T_136 = bits(io.data_in, 8, 8)
node _logical_T_137 = bits(io.data_in, 9, 9)
node _logical_T_138 = bits(io.data_in, 10, 10)
node _logical_T_139 = bits(io.data_in, 11, 11)
node _logical_T_140 = bits(io.data_in, 12, 12)
node _logical_T_141 = bits(io.data_in, 13, 13)
node _logical_T_142 = bits(io.data_in, 14, 14)
node _logical_T_143 = bits(io.data_in, 15, 15)
node _logical_T_144 = bits(io.data_in, 16, 16)
node _logical_T_145 = bits(io.data_in, 17, 17)
node _logical_T_146 = bits(io.data_in, 18, 18)
node _logical_T_147 = bits(io.data_in, 19, 19)
node _logical_T_148 = bits(io.data_in, 20, 20)
node _logical_T_149 = bits(io.data_in, 21, 21)
node _logical_T_150 = bits(io.data_in, 22, 22)
node _logical_T_151 = bits(io.data_in, 23, 23)
node _logical_T_152 = bits(io.data_in, 24, 24)
node _logical_T_153 = bits(io.data_in, 25, 25)
node _logical_T_154 = bits(io.data_in, 26, 26)
node _logical_T_155 = bits(io.data_in, 27, 27)
node _logical_T_156 = bits(io.data_in, 28, 28)
node _logical_T_157 = bits(io.data_in, 29, 29)
node _logical_T_158 = bits(io.data_in, 30, 30)
node _logical_T_159 = bits(io.data_in, 31, 31)
node _logical_T_160 = bits(io.data_in, 32, 32)
node _logical_T_161 = bits(io.data_in, 33, 33)
node _logical_T_162 = bits(io.data_in, 34, 34)
node _logical_T_163 = bits(io.data_in, 35, 35)
node _logical_T_164 = bits(io.data_in, 36, 36)
node _logical_T_165 = bits(io.data_in, 37, 37)
node _logical_T_166 = bits(io.data_in, 38, 38)
node _logical_T_167 = bits(io.data_in, 39, 39)
node _logical_T_168 = bits(io.data_in, 40, 40)
node _logical_T_169 = bits(io.data_in, 41, 41)
node _logical_T_170 = bits(io.data_in, 42, 42)
node _logical_T_171 = bits(io.data_in, 43, 43)
node _logical_T_172 = bits(io.data_in, 44, 44)
node _logical_T_173 = bits(io.data_in, 45, 45)
node _logical_T_174 = bits(io.data_in, 46, 46)
node _logical_T_175 = bits(io.data_in, 47, 47)
node _logical_T_176 = bits(io.data_in, 48, 48)
node _logical_T_177 = bits(io.data_in, 49, 49)
node _logical_T_178 = bits(io.data_in, 50, 50)
node _logical_T_179 = bits(io.data_in, 51, 51)
node _logical_T_180 = bits(io.data_in, 52, 52)
node _logical_T_181 = bits(io.data_in, 53, 53)
node _logical_T_182 = bits(io.data_in, 54, 54)
node _logical_T_183 = bits(io.data_in, 55, 55)
node _logical_T_184 = bits(io.data_in, 56, 56)
node _logical_T_185 = bits(io.data_in, 57, 57)
node _logical_T_186 = bits(io.data_in, 58, 58)
node _logical_T_187 = bits(io.data_in, 59, 59)
node _logical_T_188 = bits(io.data_in, 60, 60)
node _logical_T_189 = bits(io.data_in, 61, 61)
node _logical_T_190 = bits(io.data_in, 62, 62)
node _logical_T_191 = bits(io.data_in, 63, 63)
node _logical_T_192 = bits(io.data_in, 64, 64)
node _logical_T_193 = bits(io.data_in, 65, 65)
node _logical_T_194 = bits(io.data_in, 66, 66)
node _logical_T_195 = bits(io.data_in, 67, 67)
node _logical_T_196 = bits(io.data_in, 68, 68)
node _logical_T_197 = bits(io.data_in, 69, 69)
node _logical_T_198 = bits(io.data_in, 70, 70)
node _logical_T_199 = bits(io.data_in, 71, 71)
node _logical_T_200 = bits(io.data_in, 72, 72)
node _logical_T_201 = bits(io.data_in, 73, 73)
node _logical_T_202 = bits(io.data_in, 74, 74)
node _logical_T_203 = bits(io.data_in, 75, 75)
node _logical_T_204 = bits(io.data_in, 76, 76)
node _logical_T_205 = bits(io.data_in, 77, 77)
node _logical_T_206 = bits(io.data_in, 78, 78)
node _logical_T_207 = bits(io.data_in, 79, 79)
node _logical_T_208 = bits(io.data_in, 80, 80)
node _logical_T_209 = bits(io.data_in, 81, 81)
node _logical_T_210 = bits(io.data_in, 82, 82)
node _logical_T_211 = bits(io.data_in, 83, 83)
node _logical_T_212 = bits(io.data_in, 84, 84)
node _logical_T_213 = bits(io.data_in, 85, 85)
node _logical_T_214 = bits(io.data_in, 86, 86)
node _logical_T_215 = bits(io.data_in, 87, 87)
node _logical_T_216 = bits(io.data_in, 88, 88)
node _logical_T_217 = bits(io.data_in, 89, 89)
node _logical_T_218 = bits(io.data_in, 90, 90)
node _logical_T_219 = bits(io.data_in, 91, 91)
node _logical_T_220 = bits(io.data_in, 92, 92)
node _logical_T_221 = bits(io.data_in, 93, 93)
node _logical_T_222 = bits(io.data_in, 94, 94)
node _logical_T_223 = bits(io.data_in, 95, 95)
node _logical_T_224 = bits(io.data_in, 96, 96)
node _logical_T_225 = bits(io.data_in, 97, 97)
node _logical_T_226 = bits(io.data_in, 98, 98)
node _logical_T_227 = bits(io.data_in, 99, 99)
node _logical_T_228 = bits(io.data_in, 100, 100)
node _logical_T_229 = bits(io.data_in, 101, 101)
node _logical_T_230 = bits(io.data_in, 102, 102)
node _logical_T_231 = bits(io.data_in, 103, 103)
node _logical_T_232 = bits(io.data_in, 104, 104)
node _logical_T_233 = bits(io.data_in, 105, 105)
node _logical_T_234 = bits(io.data_in, 106, 106)
node _logical_T_235 = bits(io.data_in, 107, 107)
node _logical_T_236 = bits(io.data_in, 108, 108)
node _logical_T_237 = bits(io.data_in, 109, 109)
node _logical_T_238 = bits(io.data_in, 110, 110)
node _logical_T_239 = bits(io.data_in, 111, 111)
node _logical_T_240 = bits(io.data_in, 112, 112)
node _logical_T_241 = bits(io.data_in, 113, 113)
node _logical_T_242 = bits(io.data_in, 114, 114)
node _logical_T_243 = bits(io.data_in, 115, 115)
node _logical_T_244 = bits(io.data_in, 116, 116)
node _logical_T_245 = bits(io.data_in, 117, 117)
node _logical_T_246 = bits(io.data_in, 118, 118)
node _logical_T_247 = bits(io.data_in, 119, 119)
node _logical_T_248 = bits(io.data_in, 120, 120)
node _logical_T_249 = bits(io.data_in, 121, 121)
node _logical_T_250 = bits(io.data_in, 122, 122)
node _logical_T_251 = bits(io.data_in, 123, 123)
node _logical_T_252 = bits(io.data_in, 124, 124)
node _logical_T_253 = bits(io.data_in, 125, 125)
node _logical_T_254 = bits(io.data_in, 126, 126)
node _logical_T_255 = bits(io.data_in, 127, 127)
node _logical_T_256 = cat(_logical_T, _logical_T_128)
node _logical_T_257 = dshr(_lut_WIRE[_lut_T], _logical_T_256)
node _logical_T_258 = bits(_logical_T_257, 0, 0)
node _logical_T_259 = cat(_logical_T_1, _logical_T_129)
node _logical_T_260 = dshr(_lut_WIRE[_lut_T], _logical_T_259)
node _logical_T_261 = bits(_logical_T_260, 0, 0)
node _logical_T_262 = cat(_logical_T_2, _logical_T_130)
node _logical_T_263 = dshr(_lut_WIRE[_lut_T], _logical_T_262)
node _logical_T_264 = bits(_logical_T_263, 0, 0)
node _logical_T_265 = cat(_logical_T_3, _logical_T_131)
node _logical_T_266 = dshr(_lut_WIRE[_lut_T], _logical_T_265)
node _logical_T_267 = bits(_logical_T_266, 0, 0)
node _logical_T_268 = cat(_logical_T_4, _logical_T_132)
node _logical_T_269 = dshr(_lut_WIRE[_lut_T], _logical_T_268)
node _logical_T_270 = bits(_logical_T_269, 0, 0)
node _logical_T_271 = cat(_logical_T_5, _logical_T_133)
node _logical_T_272 = dshr(_lut_WIRE[_lut_T], _logical_T_271)
node _logical_T_273 = bits(_logical_T_272, 0, 0)
node _logical_T_274 = cat(_logical_T_6, _logical_T_134)
node _logical_T_275 = dshr(_lut_WIRE[_lut_T], _logical_T_274)
node _logical_T_276 = bits(_logical_T_275, 0, 0)
node _logical_T_277 = cat(_logical_T_7, _logical_T_135)
node _logical_T_278 = dshr(_lut_WIRE[_lut_T], _logical_T_277)
node _logical_T_279 = bits(_logical_T_278, 0, 0)
node _logical_T_280 = cat(_logical_T_8, _logical_T_136)
node _logical_T_281 = dshr(_lut_WIRE[_lut_T], _logical_T_280)
node _logical_T_282 = bits(_logical_T_281, 0, 0)
node _logical_T_283 = cat(_logical_T_9, _logical_T_137)
node _logical_T_284 = dshr(_lut_WIRE[_lut_T], _logical_T_283)
node _logical_T_285 = bits(_logical_T_284, 0, 0)
node _logical_T_286 = cat(_logical_T_10, _logical_T_138)
node _logical_T_287 = dshr(_lut_WIRE[_lut_T], _logical_T_286)
node _logical_T_288 = bits(_logical_T_287, 0, 0)
node _logical_T_289 = cat(_logical_T_11, _logical_T_139)
node _logical_T_290 = dshr(_lut_WIRE[_lut_T], _logical_T_289)
node _logical_T_291 = bits(_logical_T_290, 0, 0)
node _logical_T_292 = cat(_logical_T_12, _logical_T_140)
node _logical_T_293 = dshr(_lut_WIRE[_lut_T], _logical_T_292)
node _logical_T_294 = bits(_logical_T_293, 0, 0)
node _logical_T_295 = cat(_logical_T_13, _logical_T_141)
node _logical_T_296 = dshr(_lut_WIRE[_lut_T], _logical_T_295)
node _logical_T_297 = bits(_logical_T_296, 0, 0)
node _logical_T_298 = cat(_logical_T_14, _logical_T_142)
node _logical_T_299 = dshr(_lut_WIRE[_lut_T], _logical_T_298)
node _logical_T_300 = bits(_logical_T_299, 0, 0)
node _logical_T_301 = cat(_logical_T_15, _logical_T_143)
node _logical_T_302 = dshr(_lut_WIRE[_lut_T], _logical_T_301)
node _logical_T_303 = bits(_logical_T_302, 0, 0)
node _logical_T_304 = cat(_logical_T_16, _logical_T_144)
node _logical_T_305 = dshr(_lut_WIRE[_lut_T], _logical_T_304)
node _logical_T_306 = bits(_logical_T_305, 0, 0)
node _logical_T_307 = cat(_logical_T_17, _logical_T_145)
node _logical_T_308 = dshr(_lut_WIRE[_lut_T], _logical_T_307)
node _logical_T_309 = bits(_logical_T_308, 0, 0)
node _logical_T_310 = cat(_logical_T_18, _logical_T_146)
node _logical_T_311 = dshr(_lut_WIRE[_lut_T], _logical_T_310)
node _logical_T_312 = bits(_logical_T_311, 0, 0)
node _logical_T_313 = cat(_logical_T_19, _logical_T_147)
node _logical_T_314 = dshr(_lut_WIRE[_lut_T], _logical_T_313)
node _logical_T_315 = bits(_logical_T_314, 0, 0)
node _logical_T_316 = cat(_logical_T_20, _logical_T_148)
node _logical_T_317 = dshr(_lut_WIRE[_lut_T], _logical_T_316)
node _logical_T_318 = bits(_logical_T_317, 0, 0)
node _logical_T_319 = cat(_logical_T_21, _logical_T_149)
node _logical_T_320 = dshr(_lut_WIRE[_lut_T], _logical_T_319)
node _logical_T_321 = bits(_logical_T_320, 0, 0)
node _logical_T_322 = cat(_logical_T_22, _logical_T_150)
node _logical_T_323 = dshr(_lut_WIRE[_lut_T], _logical_T_322)
node _logical_T_324 = bits(_logical_T_323, 0, 0)
node _logical_T_325 = cat(_logical_T_23, _logical_T_151)
node _logical_T_326 = dshr(_lut_WIRE[_lut_T], _logical_T_325)
node _logical_T_327 = bits(_logical_T_326, 0, 0)
node _logical_T_328 = cat(_logical_T_24, _logical_T_152)
node _logical_T_329 = dshr(_lut_WIRE[_lut_T], _logical_T_328)
node _logical_T_330 = bits(_logical_T_329, 0, 0)
node _logical_T_331 = cat(_logical_T_25, _logical_T_153)
node _logical_T_332 = dshr(_lut_WIRE[_lut_T], _logical_T_331)
node _logical_T_333 = bits(_logical_T_332, 0, 0)
node _logical_T_334 = cat(_logical_T_26, _logical_T_154)
node _logical_T_335 = dshr(_lut_WIRE[_lut_T], _logical_T_334)
node _logical_T_336 = bits(_logical_T_335, 0, 0)
node _logical_T_337 = cat(_logical_T_27, _logical_T_155)
node _logical_T_338 = dshr(_lut_WIRE[_lut_T], _logical_T_337)
node _logical_T_339 = bits(_logical_T_338, 0, 0)
node _logical_T_340 = cat(_logical_T_28, _logical_T_156)
node _logical_T_341 = dshr(_lut_WIRE[_lut_T], _logical_T_340)
node _logical_T_342 = bits(_logical_T_341, 0, 0)
node _logical_T_343 = cat(_logical_T_29, _logical_T_157)
node _logical_T_344 = dshr(_lut_WIRE[_lut_T], _logical_T_343)
node _logical_T_345 = bits(_logical_T_344, 0, 0)
node _logical_T_346 = cat(_logical_T_30, _logical_T_158)
node _logical_T_347 = dshr(_lut_WIRE[_lut_T], _logical_T_346)
node _logical_T_348 = bits(_logical_T_347, 0, 0)
node _logical_T_349 = cat(_logical_T_31, _logical_T_159)
node _logical_T_350 = dshr(_lut_WIRE[_lut_T], _logical_T_349)
node _logical_T_351 = bits(_logical_T_350, 0, 0)
node _logical_T_352 = cat(_logical_T_32, _logical_T_160)
node _logical_T_353 = dshr(_lut_WIRE[_lut_T], _logical_T_352)
node _logical_T_354 = bits(_logical_T_353, 0, 0)
node _logical_T_355 = cat(_logical_T_33, _logical_T_161)
node _logical_T_356 = dshr(_lut_WIRE[_lut_T], _logical_T_355)
node _logical_T_357 = bits(_logical_T_356, 0, 0)
node _logical_T_358 = cat(_logical_T_34, _logical_T_162)
node _logical_T_359 = dshr(_lut_WIRE[_lut_T], _logical_T_358)
node _logical_T_360 = bits(_logical_T_359, 0, 0)
node _logical_T_361 = cat(_logical_T_35, _logical_T_163)
node _logical_T_362 = dshr(_lut_WIRE[_lut_T], _logical_T_361)
node _logical_T_363 = bits(_logical_T_362, 0, 0)
node _logical_T_364 = cat(_logical_T_36, _logical_T_164)
node _logical_T_365 = dshr(_lut_WIRE[_lut_T], _logical_T_364)
node _logical_T_366 = bits(_logical_T_365, 0, 0)
node _logical_T_367 = cat(_logical_T_37, _logical_T_165)
node _logical_T_368 = dshr(_lut_WIRE[_lut_T], _logical_T_367)
node _logical_T_369 = bits(_logical_T_368, 0, 0)
node _logical_T_370 = cat(_logical_T_38, _logical_T_166)
node _logical_T_371 = dshr(_lut_WIRE[_lut_T], _logical_T_370)
node _logical_T_372 = bits(_logical_T_371, 0, 0)
node _logical_T_373 = cat(_logical_T_39, _logical_T_167)
node _logical_T_374 = dshr(_lut_WIRE[_lut_T], _logical_T_373)
node _logical_T_375 = bits(_logical_T_374, 0, 0)
node _logical_T_376 = cat(_logical_T_40, _logical_T_168)
node _logical_T_377 = dshr(_lut_WIRE[_lut_T], _logical_T_376)
node _logical_T_378 = bits(_logical_T_377, 0, 0)
node _logical_T_379 = cat(_logical_T_41, _logical_T_169)
node _logical_T_380 = dshr(_lut_WIRE[_lut_T], _logical_T_379)
node _logical_T_381 = bits(_logical_T_380, 0, 0)
node _logical_T_382 = cat(_logical_T_42, _logical_T_170)
node _logical_T_383 = dshr(_lut_WIRE[_lut_T], _logical_T_382)
node _logical_T_384 = bits(_logical_T_383, 0, 0)
node _logical_T_385 = cat(_logical_T_43, _logical_T_171)
node _logical_T_386 = dshr(_lut_WIRE[_lut_T], _logical_T_385)
node _logical_T_387 = bits(_logical_T_386, 0, 0)
node _logical_T_388 = cat(_logical_T_44, _logical_T_172)
node _logical_T_389 = dshr(_lut_WIRE[_lut_T], _logical_T_388)
node _logical_T_390 = bits(_logical_T_389, 0, 0)
node _logical_T_391 = cat(_logical_T_45, _logical_T_173)
node _logical_T_392 = dshr(_lut_WIRE[_lut_T], _logical_T_391)
node _logical_T_393 = bits(_logical_T_392, 0, 0)
node _logical_T_394 = cat(_logical_T_46, _logical_T_174)
node _logical_T_395 = dshr(_lut_WIRE[_lut_T], _logical_T_394)
node _logical_T_396 = bits(_logical_T_395, 0, 0)
node _logical_T_397 = cat(_logical_T_47, _logical_T_175)
node _logical_T_398 = dshr(_lut_WIRE[_lut_T], _logical_T_397)
node _logical_T_399 = bits(_logical_T_398, 0, 0)
node _logical_T_400 = cat(_logical_T_48, _logical_T_176)
node _logical_T_401 = dshr(_lut_WIRE[_lut_T], _logical_T_400)
node _logical_T_402 = bits(_logical_T_401, 0, 0)
node _logical_T_403 = cat(_logical_T_49, _logical_T_177)
node _logical_T_404 = dshr(_lut_WIRE[_lut_T], _logical_T_403)
node _logical_T_405 = bits(_logical_T_404, 0, 0)
node _logical_T_406 = cat(_logical_T_50, _logical_T_178)
node _logical_T_407 = dshr(_lut_WIRE[_lut_T], _logical_T_406)
node _logical_T_408 = bits(_logical_T_407, 0, 0)
node _logical_T_409 = cat(_logical_T_51, _logical_T_179)
node _logical_T_410 = dshr(_lut_WIRE[_lut_T], _logical_T_409)
node _logical_T_411 = bits(_logical_T_410, 0, 0)
node _logical_T_412 = cat(_logical_T_52, _logical_T_180)
node _logical_T_413 = dshr(_lut_WIRE[_lut_T], _logical_T_412)
node _logical_T_414 = bits(_logical_T_413, 0, 0)
node _logical_T_415 = cat(_logical_T_53, _logical_T_181)
node _logical_T_416 = dshr(_lut_WIRE[_lut_T], _logical_T_415)
node _logical_T_417 = bits(_logical_T_416, 0, 0)
node _logical_T_418 = cat(_logical_T_54, _logical_T_182)
node _logical_T_419 = dshr(_lut_WIRE[_lut_T], _logical_T_418)
node _logical_T_420 = bits(_logical_T_419, 0, 0)
node _logical_T_421 = cat(_logical_T_55, _logical_T_183)
node _logical_T_422 = dshr(_lut_WIRE[_lut_T], _logical_T_421)
node _logical_T_423 = bits(_logical_T_422, 0, 0)
node _logical_T_424 = cat(_logical_T_56, _logical_T_184)
node _logical_T_425 = dshr(_lut_WIRE[_lut_T], _logical_T_424)
node _logical_T_426 = bits(_logical_T_425, 0, 0)
node _logical_T_427 = cat(_logical_T_57, _logical_T_185)
node _logical_T_428 = dshr(_lut_WIRE[_lut_T], _logical_T_427)
node _logical_T_429 = bits(_logical_T_428, 0, 0)
node _logical_T_430 = cat(_logical_T_58, _logical_T_186)
node _logical_T_431 = dshr(_lut_WIRE[_lut_T], _logical_T_430)
node _logical_T_432 = bits(_logical_T_431, 0, 0)
node _logical_T_433 = cat(_logical_T_59, _logical_T_187)
node _logical_T_434 = dshr(_lut_WIRE[_lut_T], _logical_T_433)
node _logical_T_435 = bits(_logical_T_434, 0, 0)
node _logical_T_436 = cat(_logical_T_60, _logical_T_188)
node _logical_T_437 = dshr(_lut_WIRE[_lut_T], _logical_T_436)
node _logical_T_438 = bits(_logical_T_437, 0, 0)
node _logical_T_439 = cat(_logical_T_61, _logical_T_189)
node _logical_T_440 = dshr(_lut_WIRE[_lut_T], _logical_T_439)
node _logical_T_441 = bits(_logical_T_440, 0, 0)
node _logical_T_442 = cat(_logical_T_62, _logical_T_190)
node _logical_T_443 = dshr(_lut_WIRE[_lut_T], _logical_T_442)
node _logical_T_444 = bits(_logical_T_443, 0, 0)
node _logical_T_445 = cat(_logical_T_63, _logical_T_191)
node _logical_T_446 = dshr(_lut_WIRE[_lut_T], _logical_T_445)
node _logical_T_447 = bits(_logical_T_446, 0, 0)
node _logical_T_448 = cat(_logical_T_64, _logical_T_192)
node _logical_T_449 = dshr(_lut_WIRE[_lut_T], _logical_T_448)
node _logical_T_450 = bits(_logical_T_449, 0, 0)
node _logical_T_451 = cat(_logical_T_65, _logical_T_193)
node _logical_T_452 = dshr(_lut_WIRE[_lut_T], _logical_T_451)
node _logical_T_453 = bits(_logical_T_452, 0, 0)
node _logical_T_454 = cat(_logical_T_66, _logical_T_194)
node _logical_T_455 = dshr(_lut_WIRE[_lut_T], _logical_T_454)
node _logical_T_456 = bits(_logical_T_455, 0, 0)
node _logical_T_457 = cat(_logical_T_67, _logical_T_195)
node _logical_T_458 = dshr(_lut_WIRE[_lut_T], _logical_T_457)
node _logical_T_459 = bits(_logical_T_458, 0, 0)
node _logical_T_460 = cat(_logical_T_68, _logical_T_196)
node _logical_T_461 = dshr(_lut_WIRE[_lut_T], _logical_T_460)
node _logical_T_462 = bits(_logical_T_461, 0, 0)
node _logical_T_463 = cat(_logical_T_69, _logical_T_197)
node _logical_T_464 = dshr(_lut_WIRE[_lut_T], _logical_T_463)
node _logical_T_465 = bits(_logical_T_464, 0, 0)
node _logical_T_466 = cat(_logical_T_70, _logical_T_198)
node _logical_T_467 = dshr(_lut_WIRE[_lut_T], _logical_T_466)
node _logical_T_468 = bits(_logical_T_467, 0, 0)
node _logical_T_469 = cat(_logical_T_71, _logical_T_199)
node _logical_T_470 = dshr(_lut_WIRE[_lut_T], _logical_T_469)
node _logical_T_471 = bits(_logical_T_470, 0, 0)
node _logical_T_472 = cat(_logical_T_72, _logical_T_200)
node _logical_T_473 = dshr(_lut_WIRE[_lut_T], _logical_T_472)
node _logical_T_474 = bits(_logical_T_473, 0, 0)
node _logical_T_475 = cat(_logical_T_73, _logical_T_201)
node _logical_T_476 = dshr(_lut_WIRE[_lut_T], _logical_T_475)
node _logical_T_477 = bits(_logical_T_476, 0, 0)
node _logical_T_478 = cat(_logical_T_74, _logical_T_202)
node _logical_T_479 = dshr(_lut_WIRE[_lut_T], _logical_T_478)
node _logical_T_480 = bits(_logical_T_479, 0, 0)
node _logical_T_481 = cat(_logical_T_75, _logical_T_203)
node _logical_T_482 = dshr(_lut_WIRE[_lut_T], _logical_T_481)
node _logical_T_483 = bits(_logical_T_482, 0, 0)
node _logical_T_484 = cat(_logical_T_76, _logical_T_204)
node _logical_T_485 = dshr(_lut_WIRE[_lut_T], _logical_T_484)
node _logical_T_486 = bits(_logical_T_485, 0, 0)
node _logical_T_487 = cat(_logical_T_77, _logical_T_205)
node _logical_T_488 = dshr(_lut_WIRE[_lut_T], _logical_T_487)
node _logical_T_489 = bits(_logical_T_488, 0, 0)
node _logical_T_490 = cat(_logical_T_78, _logical_T_206)
node _logical_T_491 = dshr(_lut_WIRE[_lut_T], _logical_T_490)
node _logical_T_492 = bits(_logical_T_491, 0, 0)
node _logical_T_493 = cat(_logical_T_79, _logical_T_207)
node _logical_T_494 = dshr(_lut_WIRE[_lut_T], _logical_T_493)
node _logical_T_495 = bits(_logical_T_494, 0, 0)
node _logical_T_496 = cat(_logical_T_80, _logical_T_208)
node _logical_T_497 = dshr(_lut_WIRE[_lut_T], _logical_T_496)
node _logical_T_498 = bits(_logical_T_497, 0, 0)
node _logical_T_499 = cat(_logical_T_81, _logical_T_209)
node _logical_T_500 = dshr(_lut_WIRE[_lut_T], _logical_T_499)
node _logical_T_501 = bits(_logical_T_500, 0, 0)
node _logical_T_502 = cat(_logical_T_82, _logical_T_210)
node _logical_T_503 = dshr(_lut_WIRE[_lut_T], _logical_T_502)
node _logical_T_504 = bits(_logical_T_503, 0, 0)
node _logical_T_505 = cat(_logical_T_83, _logical_T_211)
node _logical_T_506 = dshr(_lut_WIRE[_lut_T], _logical_T_505)
node _logical_T_507 = bits(_logical_T_506, 0, 0)
node _logical_T_508 = cat(_logical_T_84, _logical_T_212)
node _logical_T_509 = dshr(_lut_WIRE[_lut_T], _logical_T_508)
node _logical_T_510 = bits(_logical_T_509, 0, 0)
node _logical_T_511 = cat(_logical_T_85, _logical_T_213)
node _logical_T_512 = dshr(_lut_WIRE[_lut_T], _logical_T_511)
node _logical_T_513 = bits(_logical_T_512, 0, 0)
node _logical_T_514 = cat(_logical_T_86, _logical_T_214)
node _logical_T_515 = dshr(_lut_WIRE[_lut_T], _logical_T_514)
node _logical_T_516 = bits(_logical_T_515, 0, 0)
node _logical_T_517 = cat(_logical_T_87, _logical_T_215)
node _logical_T_518 = dshr(_lut_WIRE[_lut_T], _logical_T_517)
node _logical_T_519 = bits(_logical_T_518, 0, 0)
node _logical_T_520 = cat(_logical_T_88, _logical_T_216)
node _logical_T_521 = dshr(_lut_WIRE[_lut_T], _logical_T_520)
node _logical_T_522 = bits(_logical_T_521, 0, 0)
node _logical_T_523 = cat(_logical_T_89, _logical_T_217)
node _logical_T_524 = dshr(_lut_WIRE[_lut_T], _logical_T_523)
node _logical_T_525 = bits(_logical_T_524, 0, 0)
node _logical_T_526 = cat(_logical_T_90, _logical_T_218)
node _logical_T_527 = dshr(_lut_WIRE[_lut_T], _logical_T_526)
node _logical_T_528 = bits(_logical_T_527, 0, 0)
node _logical_T_529 = cat(_logical_T_91, _logical_T_219)
node _logical_T_530 = dshr(_lut_WIRE[_lut_T], _logical_T_529)
node _logical_T_531 = bits(_logical_T_530, 0, 0)
node _logical_T_532 = cat(_logical_T_92, _logical_T_220)
node _logical_T_533 = dshr(_lut_WIRE[_lut_T], _logical_T_532)
node _logical_T_534 = bits(_logical_T_533, 0, 0)
node _logical_T_535 = cat(_logical_T_93, _logical_T_221)
node _logical_T_536 = dshr(_lut_WIRE[_lut_T], _logical_T_535)
node _logical_T_537 = bits(_logical_T_536, 0, 0)
node _logical_T_538 = cat(_logical_T_94, _logical_T_222)
node _logical_T_539 = dshr(_lut_WIRE[_lut_T], _logical_T_538)
node _logical_T_540 = bits(_logical_T_539, 0, 0)
node _logical_T_541 = cat(_logical_T_95, _logical_T_223)
node _logical_T_542 = dshr(_lut_WIRE[_lut_T], _logical_T_541)
node _logical_T_543 = bits(_logical_T_542, 0, 0)
node _logical_T_544 = cat(_logical_T_96, _logical_T_224)
node _logical_T_545 = dshr(_lut_WIRE[_lut_T], _logical_T_544)
node _logical_T_546 = bits(_logical_T_545, 0, 0)
node _logical_T_547 = cat(_logical_T_97, _logical_T_225)
node _logical_T_548 = dshr(_lut_WIRE[_lut_T], _logical_T_547)
node _logical_T_549 = bits(_logical_T_548, 0, 0)
node _logical_T_550 = cat(_logical_T_98, _logical_T_226)
node _logical_T_551 = dshr(_lut_WIRE[_lut_T], _logical_T_550)
node _logical_T_552 = bits(_logical_T_551, 0, 0)
node _logical_T_553 = cat(_logical_T_99, _logical_T_227)
node _logical_T_554 = dshr(_lut_WIRE[_lut_T], _logical_T_553)
node _logical_T_555 = bits(_logical_T_554, 0, 0)
node _logical_T_556 = cat(_logical_T_100, _logical_T_228)
node _logical_T_557 = dshr(_lut_WIRE[_lut_T], _logical_T_556)
node _logical_T_558 = bits(_logical_T_557, 0, 0)
node _logical_T_559 = cat(_logical_T_101, _logical_T_229)
node _logical_T_560 = dshr(_lut_WIRE[_lut_T], _logical_T_559)
node _logical_T_561 = bits(_logical_T_560, 0, 0)
node _logical_T_562 = cat(_logical_T_102, _logical_T_230)
node _logical_T_563 = dshr(_lut_WIRE[_lut_T], _logical_T_562)
node _logical_T_564 = bits(_logical_T_563, 0, 0)
node _logical_T_565 = cat(_logical_T_103, _logical_T_231)
node _logical_T_566 = dshr(_lut_WIRE[_lut_T], _logical_T_565)
node _logical_T_567 = bits(_logical_T_566, 0, 0)
node _logical_T_568 = cat(_logical_T_104, _logical_T_232)
node _logical_T_569 = dshr(_lut_WIRE[_lut_T], _logical_T_568)
node _logical_T_570 = bits(_logical_T_569, 0, 0)
node _logical_T_571 = cat(_logical_T_105, _logical_T_233)
node _logical_T_572 = dshr(_lut_WIRE[_lut_T], _logical_T_571)
node _logical_T_573 = bits(_logical_T_572, 0, 0)
node _logical_T_574 = cat(_logical_T_106, _logical_T_234)
node _logical_T_575 = dshr(_lut_WIRE[_lut_T], _logical_T_574)
node _logical_T_576 = bits(_logical_T_575, 0, 0)
node _logical_T_577 = cat(_logical_T_107, _logical_T_235)
node _logical_T_578 = dshr(_lut_WIRE[_lut_T], _logical_T_577)
node _logical_T_579 = bits(_logical_T_578, 0, 0)
node _logical_T_580 = cat(_logical_T_108, _logical_T_236)
node _logical_T_581 = dshr(_lut_WIRE[_lut_T], _logical_T_580)
node _logical_T_582 = bits(_logical_T_581, 0, 0)
node _logical_T_583 = cat(_logical_T_109, _logical_T_237)
node _logical_T_584 = dshr(_lut_WIRE[_lut_T], _logical_T_583)
node _logical_T_585 = bits(_logical_T_584, 0, 0)
node _logical_T_586 = cat(_logical_T_110, _logical_T_238)
node _logical_T_587 = dshr(_lut_WIRE[_lut_T], _logical_T_586)
node _logical_T_588 = bits(_logical_T_587, 0, 0)
node _logical_T_589 = cat(_logical_T_111, _logical_T_239)
node _logical_T_590 = dshr(_lut_WIRE[_lut_T], _logical_T_589)
node _logical_T_591 = bits(_logical_T_590, 0, 0)
node _logical_T_592 = cat(_logical_T_112, _logical_T_240)
node _logical_T_593 = dshr(_lut_WIRE[_lut_T], _logical_T_592)
node _logical_T_594 = bits(_logical_T_593, 0, 0)
node _logical_T_595 = cat(_logical_T_113, _logical_T_241)
node _logical_T_596 = dshr(_lut_WIRE[_lut_T], _logical_T_595)
node _logical_T_597 = bits(_logical_T_596, 0, 0)
node _logical_T_598 = cat(_logical_T_114, _logical_T_242)
node _logical_T_599 = dshr(_lut_WIRE[_lut_T], _logical_T_598)
node _logical_T_600 = bits(_logical_T_599, 0, 0)
node _logical_T_601 = cat(_logical_T_115, _logical_T_243)
node _logical_T_602 = dshr(_lut_WIRE[_lut_T], _logical_T_601)
node _logical_T_603 = bits(_logical_T_602, 0, 0)
node _logical_T_604 = cat(_logical_T_116, _logical_T_244)
node _logical_T_605 = dshr(_lut_WIRE[_lut_T], _logical_T_604)
node _logical_T_606 = bits(_logical_T_605, 0, 0)
node _logical_T_607 = cat(_logical_T_117, _logical_T_245)
node _logical_T_608 = dshr(_lut_WIRE[_lut_T], _logical_T_607)
node _logical_T_609 = bits(_logical_T_608, 0, 0)
node _logical_T_610 = cat(_logical_T_118, _logical_T_246)
node _logical_T_611 = dshr(_lut_WIRE[_lut_T], _logical_T_610)
node _logical_T_612 = bits(_logical_T_611, 0, 0)
node _logical_T_613 = cat(_logical_T_119, _logical_T_247)
node _logical_T_614 = dshr(_lut_WIRE[_lut_T], _logical_T_613)
node _logical_T_615 = bits(_logical_T_614, 0, 0)
node _logical_T_616 = cat(_logical_T_120, _logical_T_248)
node _logical_T_617 = dshr(_lut_WIRE[_lut_T], _logical_T_616)
node _logical_T_618 = bits(_logical_T_617, 0, 0)
node _logical_T_619 = cat(_logical_T_121, _logical_T_249)
node _logical_T_620 = dshr(_lut_WIRE[_lut_T], _logical_T_619)
node _logical_T_621 = bits(_logical_T_620, 0, 0)
node _logical_T_622 = cat(_logical_T_122, _logical_T_250)
node _logical_T_623 = dshr(_lut_WIRE[_lut_T], _logical_T_622)
node _logical_T_624 = bits(_logical_T_623, 0, 0)
node _logical_T_625 = cat(_logical_T_123, _logical_T_251)
node _logical_T_626 = dshr(_lut_WIRE[_lut_T], _logical_T_625)
node _logical_T_627 = bits(_logical_T_626, 0, 0)
node _logical_T_628 = cat(_logical_T_124, _logical_T_252)
node _logical_T_629 = dshr(_lut_WIRE[_lut_T], _logical_T_628)
node _logical_T_630 = bits(_logical_T_629, 0, 0)
node _logical_T_631 = cat(_logical_T_125, _logical_T_253)
node _logical_T_632 = dshr(_lut_WIRE[_lut_T], _logical_T_631)
node _logical_T_633 = bits(_logical_T_632, 0, 0)
node _logical_T_634 = cat(_logical_T_126, _logical_T_254)
node _logical_T_635 = dshr(_lut_WIRE[_lut_T], _logical_T_634)
node _logical_T_636 = bits(_logical_T_635, 0, 0)
node _logical_T_637 = cat(_logical_T_127, _logical_T_255)
node _logical_T_638 = dshr(_lut_WIRE[_lut_T], _logical_T_637)
node _logical_T_639 = bits(_logical_T_638, 0, 0)
node logical_lo_lo_lo_lo_lo_lo = cat(_logical_T_261, _logical_T_258)
node logical_lo_lo_lo_lo_lo_hi = cat(_logical_T_267, _logical_T_264)
node logical_lo_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo)
node logical_lo_lo_lo_lo_hi_lo = cat(_logical_T_273, _logical_T_270)
node logical_lo_lo_lo_lo_hi_hi = cat(_logical_T_279, _logical_T_276)
node logical_lo_lo_lo_lo_hi = cat(logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo)
node logical_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo)
node logical_lo_lo_lo_hi_lo_lo = cat(_logical_T_285, _logical_T_282)
node logical_lo_lo_lo_hi_lo_hi = cat(_logical_T_291, _logical_T_288)
node logical_lo_lo_lo_hi_lo = cat(logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo)
node logical_lo_lo_lo_hi_hi_lo = cat(_logical_T_297, _logical_T_294)
node logical_lo_lo_lo_hi_hi_hi = cat(_logical_T_303, _logical_T_300)
node logical_lo_lo_lo_hi_hi = cat(logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo)
node logical_lo_lo_lo_hi = cat(logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo)
node logical_lo_lo_lo = cat(logical_lo_lo_lo_hi, logical_lo_lo_lo_lo)
node logical_lo_lo_hi_lo_lo_lo = cat(_logical_T_309, _logical_T_306)
node logical_lo_lo_hi_lo_lo_hi = cat(_logical_T_315, _logical_T_312)
node logical_lo_lo_hi_lo_lo = cat(logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo)
node logical_lo_lo_hi_lo_hi_lo = cat(_logical_T_321, _logical_T_318)
node logical_lo_lo_hi_lo_hi_hi = cat(_logical_T_327, _logical_T_324)
node logical_lo_lo_hi_lo_hi = cat(logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo)
node logical_lo_lo_hi_lo = cat(logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo)
node logical_lo_lo_hi_hi_lo_lo = cat(_logical_T_333, _logical_T_330)
node logical_lo_lo_hi_hi_lo_hi = cat(_logical_T_339, _logical_T_336)
node logical_lo_lo_hi_hi_lo = cat(logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo)
node logical_lo_lo_hi_hi_hi_lo = cat(_logical_T_345, _logical_T_342)
node logical_lo_lo_hi_hi_hi_hi = cat(_logical_T_351, _logical_T_348)
node logical_lo_lo_hi_hi_hi = cat(logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo)
node logical_lo_lo_hi_hi = cat(logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo)
node logical_lo_lo_hi = cat(logical_lo_lo_hi_hi, logical_lo_lo_hi_lo)
node logical_lo_lo = cat(logical_lo_lo_hi, logical_lo_lo_lo)
node logical_lo_hi_lo_lo_lo_lo = cat(_logical_T_357, _logical_T_354)
node logical_lo_hi_lo_lo_lo_hi = cat(_logical_T_363, _logical_T_360)
node logical_lo_hi_lo_lo_lo = cat(logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo)
node logical_lo_hi_lo_lo_hi_lo = cat(_logical_T_369, _logical_T_366)
node logical_lo_hi_lo_lo_hi_hi = cat(_logical_T_375, _logical_T_372)
node logical_lo_hi_lo_lo_hi = cat(logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo)
node logical_lo_hi_lo_lo = cat(logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo)
node logical_lo_hi_lo_hi_lo_lo = cat(_logical_T_381, _logical_T_378)
node logical_lo_hi_lo_hi_lo_hi = cat(_logical_T_387, _logical_T_384)
node logical_lo_hi_lo_hi_lo = cat(logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo)
node logical_lo_hi_lo_hi_hi_lo = cat(_logical_T_393, _logical_T_390)
node logical_lo_hi_lo_hi_hi_hi = cat(_logical_T_399, _logical_T_396)
node logical_lo_hi_lo_hi_hi = cat(logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo)
node logical_lo_hi_lo_hi = cat(logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo)
node logical_lo_hi_lo = cat(logical_lo_hi_lo_hi, logical_lo_hi_lo_lo)
node logical_lo_hi_hi_lo_lo_lo = cat(_logical_T_405, _logical_T_402)
node logical_lo_hi_hi_lo_lo_hi = cat(_logical_T_411, _logical_T_408)
node logical_lo_hi_hi_lo_lo = cat(logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo)
node logical_lo_hi_hi_lo_hi_lo = cat(_logical_T_417, _logical_T_414)
node logical_lo_hi_hi_lo_hi_hi = cat(_logical_T_423, _logical_T_420)
node logical_lo_hi_hi_lo_hi = cat(logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo)
node logical_lo_hi_hi_lo = cat(logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo)
node logical_lo_hi_hi_hi_lo_lo = cat(_logical_T_429, _logical_T_426)
node logical_lo_hi_hi_hi_lo_hi = cat(_logical_T_435, _logical_T_432)
node logical_lo_hi_hi_hi_lo = cat(logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo)
node logical_lo_hi_hi_hi_hi_lo = cat(_logical_T_441, _logical_T_438)
node logical_lo_hi_hi_hi_hi_hi = cat(_logical_T_447, _logical_T_444)
node logical_lo_hi_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo)
node logical_lo_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo)
node logical_lo_hi_hi = cat(logical_lo_hi_hi_hi, logical_lo_hi_hi_lo)
node logical_lo_hi = cat(logical_lo_hi_hi, logical_lo_hi_lo)
node logical_lo = cat(logical_lo_hi, logical_lo_lo)
node logical_hi_lo_lo_lo_lo_lo = cat(_logical_T_453, _logical_T_450)
node logical_hi_lo_lo_lo_lo_hi = cat(_logical_T_459, _logical_T_456)
node logical_hi_lo_lo_lo_lo = cat(logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo)
node logical_hi_lo_lo_lo_hi_lo = cat(_logical_T_465, _logical_T_462)
node logical_hi_lo_lo_lo_hi_hi = cat(_logical_T_471, _logical_T_468)
node logical_hi_lo_lo_lo_hi = cat(logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo)
node logical_hi_lo_lo_lo = cat(logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo)
node logical_hi_lo_lo_hi_lo_lo = cat(_logical_T_477, _logical_T_474)
node logical_hi_lo_lo_hi_lo_hi = cat(_logical_T_483, _logical_T_480)
node logical_hi_lo_lo_hi_lo = cat(logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo)
node logical_hi_lo_lo_hi_hi_lo = cat(_logical_T_489, _logical_T_486)
node logical_hi_lo_lo_hi_hi_hi = cat(_logical_T_495, _logical_T_492)
node logical_hi_lo_lo_hi_hi = cat(logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo)
node logical_hi_lo_lo_hi = cat(logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo)
node logical_hi_lo_lo = cat(logical_hi_lo_lo_hi, logical_hi_lo_lo_lo)
node logical_hi_lo_hi_lo_lo_lo = cat(_logical_T_501, _logical_T_498)
node logical_hi_lo_hi_lo_lo_hi = cat(_logical_T_507, _logical_T_504)
node logical_hi_lo_hi_lo_lo = cat(logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo)
node logical_hi_lo_hi_lo_hi_lo = cat(_logical_T_513, _logical_T_510)
node logical_hi_lo_hi_lo_hi_hi = cat(_logical_T_519, _logical_T_516)
node logical_hi_lo_hi_lo_hi = cat(logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo)
node logical_hi_lo_hi_lo = cat(logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo)
node logical_hi_lo_hi_hi_lo_lo = cat(_logical_T_525, _logical_T_522)
node logical_hi_lo_hi_hi_lo_hi = cat(_logical_T_531, _logical_T_528)
node logical_hi_lo_hi_hi_lo = cat(logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo)
node logical_hi_lo_hi_hi_hi_lo = cat(_logical_T_537, _logical_T_534)
node logical_hi_lo_hi_hi_hi_hi = cat(_logical_T_543, _logical_T_540)
node logical_hi_lo_hi_hi_hi = cat(logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo)
node logical_hi_lo_hi_hi = cat(logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo)
node logical_hi_lo_hi = cat(logical_hi_lo_hi_hi, logical_hi_lo_hi_lo)
node logical_hi_lo = cat(logical_hi_lo_hi, logical_hi_lo_lo)
node logical_hi_hi_lo_lo_lo_lo = cat(_logical_T_549, _logical_T_546)
node logical_hi_hi_lo_lo_lo_hi = cat(_logical_T_555, _logical_T_552)
node logical_hi_hi_lo_lo_lo = cat(logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo)
node logical_hi_hi_lo_lo_hi_lo = cat(_logical_T_561, _logical_T_558)
node logical_hi_hi_lo_lo_hi_hi = cat(_logical_T_567, _logical_T_564)
node logical_hi_hi_lo_lo_hi = cat(logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo)
node logical_hi_hi_lo_lo = cat(logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo)
node logical_hi_hi_lo_hi_lo_lo = cat(_logical_T_573, _logical_T_570)
node logical_hi_hi_lo_hi_lo_hi = cat(_logical_T_579, _logical_T_576)
node logical_hi_hi_lo_hi_lo = cat(logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo)
node logical_hi_hi_lo_hi_hi_lo = cat(_logical_T_585, _logical_T_582)
node logical_hi_hi_lo_hi_hi_hi = cat(_logical_T_591, _logical_T_588)
node logical_hi_hi_lo_hi_hi = cat(logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo)
node logical_hi_hi_lo_hi = cat(logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo)
node logical_hi_hi_lo = cat(logical_hi_hi_lo_hi, logical_hi_hi_lo_lo)
node logical_hi_hi_hi_lo_lo_lo = cat(_logical_T_597, _logical_T_594)
node logical_hi_hi_hi_lo_lo_hi = cat(_logical_T_603, _logical_T_600)
node logical_hi_hi_hi_lo_lo = cat(logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo)
node logical_hi_hi_hi_lo_hi_lo = cat(_logical_T_609, _logical_T_606)
node logical_hi_hi_hi_lo_hi_hi = cat(_logical_T_615, _logical_T_612)
node logical_hi_hi_hi_lo_hi = cat(logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo)
node logical_hi_hi_hi_lo = cat(logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo)
node logical_hi_hi_hi_hi_lo_lo = cat(_logical_T_621, _logical_T_618)
node logical_hi_hi_hi_hi_lo_hi = cat(_logical_T_627, _logical_T_624)
node logical_hi_hi_hi_hi_lo = cat(logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo)
node logical_hi_hi_hi_hi_hi_lo = cat(_logical_T_633, _logical_T_630)
node logical_hi_hi_hi_hi_hi_hi = cat(_logical_T_639, _logical_T_636)
node logical_hi_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo)
node logical_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo)
node logical_hi_hi_hi = cat(logical_hi_hi_hi_hi, logical_hi_hi_hi_lo)
node logical_hi_hi = cat(logical_hi_hi_hi, logical_hi_hi_lo)
node logical_hi = cat(logical_hi_hi, logical_hi_lo)
node logical = cat(logical_hi, logical_lo)
node _select_T = mux(pick_a, UInt<1>(0h1), UInt<1>(0h0))
node _select_T_1 = mux(adder, UInt<2>(0h2), _select_T)
wire _select_WIRE : UInt<2>[8]
connect _select_WIRE[0], UInt<1>(0h1)
connect _select_WIRE[1], UInt<1>(0h1)
connect _select_WIRE[2], _select_T_1
connect _select_WIRE[3], UInt<2>(0h3)
connect _select_WIRE[4], UInt<1>(0h0)
connect _select_WIRE[5], UInt<1>(0h0)
connect _select_WIRE[6], UInt<1>(0h0)
connect _select_WIRE[7], UInt<1>(0h0)
node select = mux(io.write, UInt<1>(0h1), _select_WIRE[io.a.opcode])
node _selects_T = bits(io.a.mask, 0, 0)
node _selects_T_1 = bits(io.a.mask, 1, 1)
node _selects_T_2 = bits(io.a.mask, 2, 2)
node _selects_T_3 = bits(io.a.mask, 3, 3)
node _selects_T_4 = bits(io.a.mask, 4, 4)
node _selects_T_5 = bits(io.a.mask, 5, 5)
node _selects_T_6 = bits(io.a.mask, 6, 6)
node _selects_T_7 = bits(io.a.mask, 7, 7)
node _selects_T_8 = bits(io.a.mask, 8, 8)
node _selects_T_9 = bits(io.a.mask, 9, 9)
node _selects_T_10 = bits(io.a.mask, 10, 10)
node _selects_T_11 = bits(io.a.mask, 11, 11)
node _selects_T_12 = bits(io.a.mask, 12, 12)
node _selects_T_13 = bits(io.a.mask, 13, 13)
node _selects_T_14 = bits(io.a.mask, 14, 14)
node _selects_T_15 = bits(io.a.mask, 15, 15)
node selects_0 = mux(_selects_T, select, UInt<1>(0h0))
node selects_1 = mux(_selects_T_1, select, UInt<1>(0h0))
node selects_2 = mux(_selects_T_2, select, UInt<1>(0h0))
node selects_3 = mux(_selects_T_3, select, UInt<1>(0h0))
node selects_4 = mux(_selects_T_4, select, UInt<1>(0h0))
node selects_5 = mux(_selects_T_5, select, UInt<1>(0h0))
node selects_6 = mux(_selects_T_6, select, UInt<1>(0h0))
node selects_7 = mux(_selects_T_7, select, UInt<1>(0h0))
node selects_8 = mux(_selects_T_8, select, UInt<1>(0h0))
node selects_9 = mux(_selects_T_9, select, UInt<1>(0h0))
node selects_10 = mux(_selects_T_10, select, UInt<1>(0h0))
node selects_11 = mux(_selects_T_11, select, UInt<1>(0h0))
node selects_12 = mux(_selects_T_12, select, UInt<1>(0h0))
node selects_13 = mux(_selects_T_13, select, UInt<1>(0h0))
node selects_14 = mux(_selects_T_14, select, UInt<1>(0h0))
node selects_15 = mux(_selects_T_15, select, UInt<1>(0h0))
node _io_data_out_T = bits(io.data_in, 7, 0)
node _io_data_out_T_1 = bits(io.a.data, 7, 0)
node _io_data_out_T_2 = bits(sum, 7, 0)
node _io_data_out_T_3 = bits(logical, 7, 0)
wire _io_data_out_WIRE : UInt<8>[4]
connect _io_data_out_WIRE[0], _io_data_out_T
connect _io_data_out_WIRE[1], _io_data_out_T_1
connect _io_data_out_WIRE[2], _io_data_out_T_2
connect _io_data_out_WIRE[3], _io_data_out_T_3
node _io_data_out_T_4 = bits(io.data_in, 15, 8)
node _io_data_out_T_5 = bits(io.a.data, 15, 8)
node _io_data_out_T_6 = bits(sum, 15, 8)
node _io_data_out_T_7 = bits(logical, 15, 8)
wire _io_data_out_WIRE_1 : UInt<8>[4]
connect _io_data_out_WIRE_1[0], _io_data_out_T_4
connect _io_data_out_WIRE_1[1], _io_data_out_T_5
connect _io_data_out_WIRE_1[2], _io_data_out_T_6
connect _io_data_out_WIRE_1[3], _io_data_out_T_7
node _io_data_out_T_8 = bits(io.data_in, 23, 16)
node _io_data_out_T_9 = bits(io.a.data, 23, 16)
node _io_data_out_T_10 = bits(sum, 23, 16)
node _io_data_out_T_11 = bits(logical, 23, 16)
wire _io_data_out_WIRE_2 : UInt<8>[4]
connect _io_data_out_WIRE_2[0], _io_data_out_T_8
connect _io_data_out_WIRE_2[1], _io_data_out_T_9
connect _io_data_out_WIRE_2[2], _io_data_out_T_10
connect _io_data_out_WIRE_2[3], _io_data_out_T_11
node _io_data_out_T_12 = bits(io.data_in, 31, 24)
node _io_data_out_T_13 = bits(io.a.data, 31, 24)
node _io_data_out_T_14 = bits(sum, 31, 24)
node _io_data_out_T_15 = bits(logical, 31, 24)
wire _io_data_out_WIRE_3 : UInt<8>[4]
connect _io_data_out_WIRE_3[0], _io_data_out_T_12
connect _io_data_out_WIRE_3[1], _io_data_out_T_13
connect _io_data_out_WIRE_3[2], _io_data_out_T_14
connect _io_data_out_WIRE_3[3], _io_data_out_T_15
node _io_data_out_T_16 = bits(io.data_in, 39, 32)
node _io_data_out_T_17 = bits(io.a.data, 39, 32)
node _io_data_out_T_18 = bits(sum, 39, 32)
node _io_data_out_T_19 = bits(logical, 39, 32)
wire _io_data_out_WIRE_4 : UInt<8>[4]
connect _io_data_out_WIRE_4[0], _io_data_out_T_16
connect _io_data_out_WIRE_4[1], _io_data_out_T_17
connect _io_data_out_WIRE_4[2], _io_data_out_T_18
connect _io_data_out_WIRE_4[3], _io_data_out_T_19
node _io_data_out_T_20 = bits(io.data_in, 47, 40)
node _io_data_out_T_21 = bits(io.a.data, 47, 40)
node _io_data_out_T_22 = bits(sum, 47, 40)
node _io_data_out_T_23 = bits(logical, 47, 40)
wire _io_data_out_WIRE_5 : UInt<8>[4]
connect _io_data_out_WIRE_5[0], _io_data_out_T_20
connect _io_data_out_WIRE_5[1], _io_data_out_T_21
connect _io_data_out_WIRE_5[2], _io_data_out_T_22
connect _io_data_out_WIRE_5[3], _io_data_out_T_23
node _io_data_out_T_24 = bits(io.data_in, 55, 48)
node _io_data_out_T_25 = bits(io.a.data, 55, 48)
node _io_data_out_T_26 = bits(sum, 55, 48)
node _io_data_out_T_27 = bits(logical, 55, 48)
wire _io_data_out_WIRE_6 : UInt<8>[4]
connect _io_data_out_WIRE_6[0], _io_data_out_T_24
connect _io_data_out_WIRE_6[1], _io_data_out_T_25
connect _io_data_out_WIRE_6[2], _io_data_out_T_26
connect _io_data_out_WIRE_6[3], _io_data_out_T_27
node _io_data_out_T_28 = bits(io.data_in, 63, 56)
node _io_data_out_T_29 = bits(io.a.data, 63, 56)
node _io_data_out_T_30 = bits(sum, 63, 56)
node _io_data_out_T_31 = bits(logical, 63, 56)
wire _io_data_out_WIRE_7 : UInt<8>[4]
connect _io_data_out_WIRE_7[0], _io_data_out_T_28
connect _io_data_out_WIRE_7[1], _io_data_out_T_29
connect _io_data_out_WIRE_7[2], _io_data_out_T_30
connect _io_data_out_WIRE_7[3], _io_data_out_T_31
node _io_data_out_T_32 = bits(io.data_in, 71, 64)
node _io_data_out_T_33 = bits(io.a.data, 71, 64)
node _io_data_out_T_34 = bits(sum, 71, 64)
node _io_data_out_T_35 = bits(logical, 71, 64)
wire _io_data_out_WIRE_8 : UInt<8>[4]
connect _io_data_out_WIRE_8[0], _io_data_out_T_32
connect _io_data_out_WIRE_8[1], _io_data_out_T_33
connect _io_data_out_WIRE_8[2], _io_data_out_T_34
connect _io_data_out_WIRE_8[3], _io_data_out_T_35
node _io_data_out_T_36 = bits(io.data_in, 79, 72)
node _io_data_out_T_37 = bits(io.a.data, 79, 72)
node _io_data_out_T_38 = bits(sum, 79, 72)
node _io_data_out_T_39 = bits(logical, 79, 72)
wire _io_data_out_WIRE_9 : UInt<8>[4]
connect _io_data_out_WIRE_9[0], _io_data_out_T_36
connect _io_data_out_WIRE_9[1], _io_data_out_T_37
connect _io_data_out_WIRE_9[2], _io_data_out_T_38
connect _io_data_out_WIRE_9[3], _io_data_out_T_39
node _io_data_out_T_40 = bits(io.data_in, 87, 80)
node _io_data_out_T_41 = bits(io.a.data, 87, 80)
node _io_data_out_T_42 = bits(sum, 87, 80)
node _io_data_out_T_43 = bits(logical, 87, 80)
wire _io_data_out_WIRE_10 : UInt<8>[4]
connect _io_data_out_WIRE_10[0], _io_data_out_T_40
connect _io_data_out_WIRE_10[1], _io_data_out_T_41
connect _io_data_out_WIRE_10[2], _io_data_out_T_42
connect _io_data_out_WIRE_10[3], _io_data_out_T_43
node _io_data_out_T_44 = bits(io.data_in, 95, 88)
node _io_data_out_T_45 = bits(io.a.data, 95, 88)
node _io_data_out_T_46 = bits(sum, 95, 88)
node _io_data_out_T_47 = bits(logical, 95, 88)
wire _io_data_out_WIRE_11 : UInt<8>[4]
connect _io_data_out_WIRE_11[0], _io_data_out_T_44
connect _io_data_out_WIRE_11[1], _io_data_out_T_45
connect _io_data_out_WIRE_11[2], _io_data_out_T_46
connect _io_data_out_WIRE_11[3], _io_data_out_T_47
node _io_data_out_T_48 = bits(io.data_in, 103, 96)
node _io_data_out_T_49 = bits(io.a.data, 103, 96)
node _io_data_out_T_50 = bits(sum, 103, 96)
node _io_data_out_T_51 = bits(logical, 103, 96)
wire _io_data_out_WIRE_12 : UInt<8>[4]
connect _io_data_out_WIRE_12[0], _io_data_out_T_48
connect _io_data_out_WIRE_12[1], _io_data_out_T_49
connect _io_data_out_WIRE_12[2], _io_data_out_T_50
connect _io_data_out_WIRE_12[3], _io_data_out_T_51
node _io_data_out_T_52 = bits(io.data_in, 111, 104)
node _io_data_out_T_53 = bits(io.a.data, 111, 104)
node _io_data_out_T_54 = bits(sum, 111, 104)
node _io_data_out_T_55 = bits(logical, 111, 104)
wire _io_data_out_WIRE_13 : UInt<8>[4]
connect _io_data_out_WIRE_13[0], _io_data_out_T_52
connect _io_data_out_WIRE_13[1], _io_data_out_T_53
connect _io_data_out_WIRE_13[2], _io_data_out_T_54
connect _io_data_out_WIRE_13[3], _io_data_out_T_55
node _io_data_out_T_56 = bits(io.data_in, 119, 112)
node _io_data_out_T_57 = bits(io.a.data, 119, 112)
node _io_data_out_T_58 = bits(sum, 119, 112)
node _io_data_out_T_59 = bits(logical, 119, 112)
wire _io_data_out_WIRE_14 : UInt<8>[4]
connect _io_data_out_WIRE_14[0], _io_data_out_T_56
connect _io_data_out_WIRE_14[1], _io_data_out_T_57
connect _io_data_out_WIRE_14[2], _io_data_out_T_58
connect _io_data_out_WIRE_14[3], _io_data_out_T_59
node _io_data_out_T_60 = bits(io.data_in, 127, 120)
node _io_data_out_T_61 = bits(io.a.data, 127, 120)
node _io_data_out_T_62 = bits(sum, 127, 120)
node _io_data_out_T_63 = bits(logical, 127, 120)
wire _io_data_out_WIRE_15 : UInt<8>[4]
connect _io_data_out_WIRE_15[0], _io_data_out_T_60
connect _io_data_out_WIRE_15[1], _io_data_out_T_61
connect _io_data_out_WIRE_15[2], _io_data_out_T_62
connect _io_data_out_WIRE_15[3], _io_data_out_T_63
node io_data_out_lo_lo_lo = cat(_io_data_out_WIRE_1[selects_1], _io_data_out_WIRE[selects_0])
node io_data_out_lo_lo_hi = cat(_io_data_out_WIRE_3[selects_3], _io_data_out_WIRE_2[selects_2])
node io_data_out_lo_lo = cat(io_data_out_lo_lo_hi, io_data_out_lo_lo_lo)
node io_data_out_lo_hi_lo = cat(_io_data_out_WIRE_5[selects_5], _io_data_out_WIRE_4[selects_4])
node io_data_out_lo_hi_hi = cat(_io_data_out_WIRE_7[selects_7], _io_data_out_WIRE_6[selects_6])
node io_data_out_lo_hi = cat(io_data_out_lo_hi_hi, io_data_out_lo_hi_lo)
node io_data_out_lo = cat(io_data_out_lo_hi, io_data_out_lo_lo)
node io_data_out_hi_lo_lo = cat(_io_data_out_WIRE_9[selects_9], _io_data_out_WIRE_8[selects_8])
node io_data_out_hi_lo_hi = cat(_io_data_out_WIRE_11[selects_11], _io_data_out_WIRE_10[selects_10])
node io_data_out_hi_lo = cat(io_data_out_hi_lo_hi, io_data_out_hi_lo_lo)
node io_data_out_hi_hi_lo = cat(_io_data_out_WIRE_13[selects_13], _io_data_out_WIRE_12[selects_12])
node io_data_out_hi_hi_hi = cat(_io_data_out_WIRE_15[selects_15], _io_data_out_WIRE_14[selects_14])
node io_data_out_hi_hi = cat(io_data_out_hi_hi_hi, io_data_out_hi_hi_lo)
node io_data_out_hi = cat(io_data_out_hi_hi, io_data_out_hi_lo)
node _io_data_out_T_64 = cat(io_data_out_hi, io_data_out_lo)
connect io.data_out, _io_data_out_T_64 | module Atomics_4( // @[Atomics.scala:8:7]
input clock, // @[Atomics.scala:8:7]
input reset, // @[Atomics.scala:8:7]
input io_write, // @[Atomics.scala:10:14]
input [2:0] io_a_opcode, // @[Atomics.scala:10:14]
input [2:0] io_a_param, // @[Atomics.scala:10:14]
input [15:0] io_a_mask, // @[Atomics.scala:10:14]
input [127:0] io_a_data, // @[Atomics.scala:10:14]
input [127:0] io_data_in, // @[Atomics.scala:10:14]
output [127:0] io_data_out // @[Atomics.scala:10:14]
);
wire io_write_0 = io_write; // @[Atomics.scala:8:7]
wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7]
wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7]
wire [15:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7]
wire [127:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7]
wire [127:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7]
wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};
wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20]
wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42]
wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14]
wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14]
wire [5:0] io_a_source = 6'h0; // @[Atomics.scala:8:7, :10:14]
wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14]
wire [127:0] _io_data_out_T_64; // @[Atomics.scala:58:21]
wire [127:0] io_data_out_0; // @[Atomics.scala:8:7]
wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28]
wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28]
wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28]
wire [15:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38]
wire [14:0] _signBit_T_1 = _signBit_T[15:1]; // @[Atomics.scala:22:{38,49}]
wire [15:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}]
wire [15:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}]
wire [127:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38]
wire [127:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}]
wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire [7:0] _sum_T_16 = {8{_sum_T}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_17 = {8{_sum_T_1}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_18 = {8{_sum_T_2}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_19 = {8{_sum_T_3}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_20 = {8{_sum_T_4}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_21 = {8{_sum_T_5}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_22 = {8{_sum_T_6}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_23 = {8{_sum_T_7}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_24 = {8{_sum_T_8}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_25 = {8{_sum_T_9}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_26 = {8{_sum_T_10}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_27 = {8{_sum_T_11}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_28 = {8{_sum_T_12}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_29 = {8{_sum_T_13}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_30 = {8{_sum_T_14}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_31 = {8{_sum_T_15}}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_lo_lo = {_sum_T_17, _sum_T_16}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_lo_hi = {_sum_T_19, _sum_T_18}; // @[Atomics.scala:24:29]
wire [31:0] sum_lo_lo = {sum_lo_lo_hi, sum_lo_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_hi_lo = {_sum_T_21, _sum_T_20}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_hi_hi = {_sum_T_23, _sum_T_22}; // @[Atomics.scala:24:29]
wire [31:0] sum_lo_hi = {sum_lo_hi_hi, sum_lo_hi_lo}; // @[Atomics.scala:24:29]
wire [63:0] sum_lo = {sum_lo_hi, sum_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_lo_lo = {_sum_T_25, _sum_T_24}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_lo_hi = {_sum_T_27, _sum_T_26}; // @[Atomics.scala:24:29]
wire [31:0] sum_hi_lo = {sum_hi_lo_hi, sum_hi_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_hi_lo = {_sum_T_29, _sum_T_28}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_hi_hi = {_sum_T_31, _sum_T_30}; // @[Atomics.scala:24:29]
wire [31:0] sum_hi_hi = {sum_hi_hi_hi, sum_hi_hi_lo}; // @[Atomics.scala:24:29]
wire [63:0] sum_hi = {sum_hi_hi, sum_hi_lo}; // @[Atomics.scala:24:29]
wire [127:0] _sum_T_32 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29]
wire [127:0] _sum_T_33 = _sum_T_32 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}]
wire [128:0] _sum_T_34 = {1'h0, _sum_T_33} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}]
wire [127:0] sum = _sum_T_34[127:0]; // @[Atomics.scala:24:57]
wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire [1:0] sign_a_lo_lo_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_lo_lo_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_lo_lo = {sign_a_lo_lo_hi, sign_a_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_lo_hi_lo = {_sign_a_T_47, _sign_a_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_lo_hi_hi = {_sign_a_T_63, _sign_a_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_lo_hi = {sign_a_lo_hi_hi, sign_a_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_a_lo = {sign_a_lo_hi, sign_a_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_hi_lo_lo = {_sign_a_T_79, _sign_a_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_hi_lo_hi = {_sign_a_T_95, _sign_a_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_hi_lo = {sign_a_hi_lo_hi, sign_a_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_hi_hi_lo = {_sign_a_T_111, _sign_a_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_hi_hi_hi = {_sign_a_T_127, _sign_a_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_hi_hi = {sign_a_hi_hi_hi, sign_a_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_a_hi = {sign_a_hi_hi, sign_a_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_a_T_128 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_a_T_129 = _sign_a_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_a = |_sign_a_T_129; // @[Atomics.scala:25:{83,94}]
wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_128 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_129 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_130 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_131 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_132 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_133 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_134 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_135 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_136 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_137 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_138 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_139 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_140 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_141 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_142 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_143 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_144 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_145 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_146 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_147 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_148 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_149 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_150 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_151 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_152 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_153 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_154 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_155 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_156 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_157 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_158 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_159 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_32 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_160 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_33 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_161 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_34 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_162 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_35 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_163 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_36 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_164 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_37 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_165 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_38 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_166 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_39 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_167 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_40 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_168 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_41 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_169 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_42 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_170 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_43 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_171 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_44 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_172 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_45 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_173 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_46 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_174 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_47 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_175 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_48 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_176 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_49 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_177 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_50 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_178 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_51 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_179 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_52 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_180 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_53 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_181 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_54 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_182 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_55 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_183 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_56 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_184 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_57 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_185 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_58 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_186 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_59 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_187 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_60 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_188 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_61 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_189 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_62 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_190 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_63 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_191 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_64 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_192 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_65 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_193 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_66 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_194 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_67 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_195 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_68 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_196 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_69 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_197 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_70 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_198 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_71 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_199 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_72 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_200 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_73 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_201 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_74 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_202 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_75 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_203 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_76 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_204 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_77 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_205 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_78 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_206 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_79 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_207 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_80 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_208 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_81 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_209 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_82 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_210 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_83 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_211 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_84 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_212 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_85 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_213 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_86 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_214 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_87 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_215 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_88 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_216 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_89 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_217 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_90 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_218 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_91 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_219 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_92 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_220 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_93 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_221 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_94 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_222 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_95 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_223 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_96 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_224 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_97 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_225 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_98 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_226 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_99 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_227 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_100 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_228 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_101 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_229 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_102 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_230 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_103 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_231 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_104 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_232 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_105 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_233 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_106 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_234 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_107 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_235 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_108 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_236 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_109 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_237 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_110 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_238 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_111 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_239 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_112 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_240 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_113 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_241 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_114 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_242 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_115 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_243 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_116 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_244 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_117 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_245 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_118 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_246 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_119 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_247 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_120 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_248 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_121 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_249 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_122 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_250 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_123 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_251 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_124 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_252 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_125 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_253 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_126 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_254 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_127 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_255 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire [1:0] sign_d_lo_lo_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_lo_lo_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_lo_lo = {sign_d_lo_lo_hi, sign_d_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_lo_hi_lo = {_sign_d_T_47, _sign_d_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_lo_hi_hi = {_sign_d_T_63, _sign_d_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_lo_hi = {sign_d_lo_hi_hi, sign_d_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_d_lo = {sign_d_lo_hi, sign_d_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_hi_lo_lo = {_sign_d_T_79, _sign_d_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_hi_lo_hi = {_sign_d_T_95, _sign_d_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_hi_lo = {sign_d_hi_lo_hi, sign_d_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_hi_hi_lo = {_sign_d_T_111, _sign_d_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_hi_hi_hi = {_sign_d_T_127, _sign_d_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_hi_hi = {sign_d_hi_hi_hi, sign_d_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_d_hi = {sign_d_hi_hi, sign_d_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_d_T_128 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_d_T_129 = _sign_d_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_d = |_sign_d_T_129; // @[Atomics.scala:25:{83,94}]
wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_32 = sum[32]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_33 = sum[33]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_34 = sum[34]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_35 = sum[35]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_36 = sum[36]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_37 = sum[37]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_38 = sum[38]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_39 = sum[39]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_40 = sum[40]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_41 = sum[41]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_42 = sum[42]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_43 = sum[43]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_44 = sum[44]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_45 = sum[45]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_46 = sum[46]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_47 = sum[47]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_48 = sum[48]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_49 = sum[49]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_50 = sum[50]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_51 = sum[51]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_52 = sum[52]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_53 = sum[53]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_54 = sum[54]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_55 = sum[55]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_56 = sum[56]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_57 = sum[57]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_58 = sum[58]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_59 = sum[59]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_60 = sum[60]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_61 = sum[61]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_62 = sum[62]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_63 = sum[63]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_64 = sum[64]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_65 = sum[65]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_66 = sum[66]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_67 = sum[67]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_68 = sum[68]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_69 = sum[69]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_70 = sum[70]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_71 = sum[71]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_72 = sum[72]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_73 = sum[73]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_74 = sum[74]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_75 = sum[75]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_76 = sum[76]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_77 = sum[77]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_78 = sum[78]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_79 = sum[79]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_80 = sum[80]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_81 = sum[81]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_82 = sum[82]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_83 = sum[83]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_84 = sum[84]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_85 = sum[85]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_86 = sum[86]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_87 = sum[87]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_88 = sum[88]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_89 = sum[89]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_90 = sum[90]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_91 = sum[91]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_92 = sum[92]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_93 = sum[93]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_94 = sum[94]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_95 = sum[95]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_96 = sum[96]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_97 = sum[97]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_98 = sum[98]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_99 = sum[99]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_100 = sum[100]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_101 = sum[101]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_102 = sum[102]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_103 = sum[103]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_104 = sum[104]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_105 = sum[105]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_106 = sum[106]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_107 = sum[107]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_108 = sum[108]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_109 = sum[109]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_110 = sum[110]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_111 = sum[111]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_112 = sum[112]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_113 = sum[113]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_114 = sum[114]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_115 = sum[115]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_116 = sum[116]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_117 = sum[117]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_118 = sum[118]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_119 = sum[119]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_120 = sum[120]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_121 = sum[121]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_122 = sum[122]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_123 = sum[123]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_124 = sum[124]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_125 = sum[125]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_126 = sum[126]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_127 = sum[127]; // @[Atomics.scala:24:57, :25:36]
wire [1:0] sign_s_lo_lo_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_lo_lo_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_lo_lo = {sign_s_lo_lo_hi, sign_s_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_lo_hi_lo = {_sign_s_T_47, _sign_s_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_lo_hi_hi = {_sign_s_T_63, _sign_s_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_lo_hi = {sign_s_lo_hi_hi, sign_s_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_s_lo = {sign_s_lo_hi, sign_s_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_hi_lo_lo = {_sign_s_T_79, _sign_s_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_hi_lo_hi = {_sign_s_T_95, _sign_s_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_hi_lo = {sign_s_hi_lo_hi, sign_s_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_hi_hi_lo = {_sign_s_T_111, _sign_s_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_hi_hi_hi = {_sign_s_T_127, _sign_s_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_hi_hi = {sign_s_hi_hi_hi, sign_s_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_s_hi = {sign_s_hi_hi, sign_s_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_s_T_128 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_s_T_129 = _sign_s_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_s = |_sign_s_T_129; // @[Atomics.scala:25:{83,94}]
wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32]
wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29]
wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41]
wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}]
wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25]
wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24]
wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15]
wire [1:0] _logical_T_256 = {_logical_T, _logical_T_128}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_257 = _GEN[_lut_T] >> _logical_T_256; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_258 = _logical_T_257[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_259 = {_logical_T_1, _logical_T_129}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_260 = _GEN[_lut_T] >> _logical_T_259; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_261 = _logical_T_260[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_262 = {_logical_T_2, _logical_T_130}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_263 = _GEN[_lut_T] >> _logical_T_262; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_264 = _logical_T_263[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_265 = {_logical_T_3, _logical_T_131}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_266 = _GEN[_lut_T] >> _logical_T_265; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_267 = _logical_T_266[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_268 = {_logical_T_4, _logical_T_132}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_269 = _GEN[_lut_T] >> _logical_T_268; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_270 = _logical_T_269[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_271 = {_logical_T_5, _logical_T_133}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_272 = _GEN[_lut_T] >> _logical_T_271; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_273 = _logical_T_272[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_274 = {_logical_T_6, _logical_T_134}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_275 = _GEN[_lut_T] >> _logical_T_274; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_276 = _logical_T_275[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_277 = {_logical_T_7, _logical_T_135}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_278 = _GEN[_lut_T] >> _logical_T_277; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_279 = _logical_T_278[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_280 = {_logical_T_8, _logical_T_136}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_281 = _GEN[_lut_T] >> _logical_T_280; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_282 = _logical_T_281[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_283 = {_logical_T_9, _logical_T_137}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_284 = _GEN[_lut_T] >> _logical_T_283; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_285 = _logical_T_284[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_286 = {_logical_T_10, _logical_T_138}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_287 = _GEN[_lut_T] >> _logical_T_286; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_288 = _logical_T_287[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_289 = {_logical_T_11, _logical_T_139}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_290 = _GEN[_lut_T] >> _logical_T_289; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_291 = _logical_T_290[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_292 = {_logical_T_12, _logical_T_140}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_293 = _GEN[_lut_T] >> _logical_T_292; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_294 = _logical_T_293[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_295 = {_logical_T_13, _logical_T_141}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_296 = _GEN[_lut_T] >> _logical_T_295; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_297 = _logical_T_296[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_298 = {_logical_T_14, _logical_T_142}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_299 = _GEN[_lut_T] >> _logical_T_298; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_300 = _logical_T_299[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_301 = {_logical_T_15, _logical_T_143}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_302 = _GEN[_lut_T] >> _logical_T_301; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_303 = _logical_T_302[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_304 = {_logical_T_16, _logical_T_144}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_305 = _GEN[_lut_T] >> _logical_T_304; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_306 = _logical_T_305[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_307 = {_logical_T_17, _logical_T_145}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_308 = _GEN[_lut_T] >> _logical_T_307; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_309 = _logical_T_308[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_310 = {_logical_T_18, _logical_T_146}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_311 = _GEN[_lut_T] >> _logical_T_310; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_312 = _logical_T_311[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_313 = {_logical_T_19, _logical_T_147}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_314 = _GEN[_lut_T] >> _logical_T_313; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_315 = _logical_T_314[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_316 = {_logical_T_20, _logical_T_148}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_317 = _GEN[_lut_T] >> _logical_T_316; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_318 = _logical_T_317[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_319 = {_logical_T_21, _logical_T_149}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_320 = _GEN[_lut_T] >> _logical_T_319; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_321 = _logical_T_320[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_322 = {_logical_T_22, _logical_T_150}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_323 = _GEN[_lut_T] >> _logical_T_322; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_324 = _logical_T_323[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_325 = {_logical_T_23, _logical_T_151}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_326 = _GEN[_lut_T] >> _logical_T_325; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_327 = _logical_T_326[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_328 = {_logical_T_24, _logical_T_152}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_329 = _GEN[_lut_T] >> _logical_T_328; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_330 = _logical_T_329[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_331 = {_logical_T_25, _logical_T_153}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_332 = _GEN[_lut_T] >> _logical_T_331; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_333 = _logical_T_332[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_334 = {_logical_T_26, _logical_T_154}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_335 = _GEN[_lut_T] >> _logical_T_334; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_336 = _logical_T_335[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_337 = {_logical_T_27, _logical_T_155}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_338 = _GEN[_lut_T] >> _logical_T_337; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_339 = _logical_T_338[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_340 = {_logical_T_28, _logical_T_156}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_341 = _GEN[_lut_T] >> _logical_T_340; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_342 = _logical_T_341[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_343 = {_logical_T_29, _logical_T_157}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_344 = _GEN[_lut_T] >> _logical_T_343; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_345 = _logical_T_344[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_346 = {_logical_T_30, _logical_T_158}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_347 = _GEN[_lut_T] >> _logical_T_346; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_348 = _logical_T_347[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_349 = {_logical_T_31, _logical_T_159}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_350 = _GEN[_lut_T] >> _logical_T_349; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_351 = _logical_T_350[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_352 = {_logical_T_32, _logical_T_160}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_353 = _GEN[_lut_T] >> _logical_T_352; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_354 = _logical_T_353[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_355 = {_logical_T_33, _logical_T_161}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_356 = _GEN[_lut_T] >> _logical_T_355; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_357 = _logical_T_356[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_358 = {_logical_T_34, _logical_T_162}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_359 = _GEN[_lut_T] >> _logical_T_358; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_360 = _logical_T_359[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_361 = {_logical_T_35, _logical_T_163}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_362 = _GEN[_lut_T] >> _logical_T_361; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_363 = _logical_T_362[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_364 = {_logical_T_36, _logical_T_164}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_365 = _GEN[_lut_T] >> _logical_T_364; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_366 = _logical_T_365[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_367 = {_logical_T_37, _logical_T_165}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_368 = _GEN[_lut_T] >> _logical_T_367; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_369 = _logical_T_368[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_370 = {_logical_T_38, _logical_T_166}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_371 = _GEN[_lut_T] >> _logical_T_370; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_372 = _logical_T_371[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_373 = {_logical_T_39, _logical_T_167}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_374 = _GEN[_lut_T] >> _logical_T_373; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_375 = _logical_T_374[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_376 = {_logical_T_40, _logical_T_168}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_377 = _GEN[_lut_T] >> _logical_T_376; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_378 = _logical_T_377[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_379 = {_logical_T_41, _logical_T_169}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_380 = _GEN[_lut_T] >> _logical_T_379; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_381 = _logical_T_380[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_382 = {_logical_T_42, _logical_T_170}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_383 = _GEN[_lut_T] >> _logical_T_382; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_384 = _logical_T_383[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_385 = {_logical_T_43, _logical_T_171}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_386 = _GEN[_lut_T] >> _logical_T_385; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_387 = _logical_T_386[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_388 = {_logical_T_44, _logical_T_172}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_389 = _GEN[_lut_T] >> _logical_T_388; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_390 = _logical_T_389[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_391 = {_logical_T_45, _logical_T_173}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_392 = _GEN[_lut_T] >> _logical_T_391; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_393 = _logical_T_392[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_394 = {_logical_T_46, _logical_T_174}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_395 = _GEN[_lut_T] >> _logical_T_394; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_396 = _logical_T_395[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_397 = {_logical_T_47, _logical_T_175}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_398 = _GEN[_lut_T] >> _logical_T_397; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_399 = _logical_T_398[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_400 = {_logical_T_48, _logical_T_176}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_401 = _GEN[_lut_T] >> _logical_T_400; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_402 = _logical_T_401[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_403 = {_logical_T_49, _logical_T_177}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_404 = _GEN[_lut_T] >> _logical_T_403; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_405 = _logical_T_404[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_406 = {_logical_T_50, _logical_T_178}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_407 = _GEN[_lut_T] >> _logical_T_406; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_408 = _logical_T_407[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_409 = {_logical_T_51, _logical_T_179}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_410 = _GEN[_lut_T] >> _logical_T_409; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_411 = _logical_T_410[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_412 = {_logical_T_52, _logical_T_180}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_413 = _GEN[_lut_T] >> _logical_T_412; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_414 = _logical_T_413[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_415 = {_logical_T_53, _logical_T_181}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_416 = _GEN[_lut_T] >> _logical_T_415; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_417 = _logical_T_416[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_418 = {_logical_T_54, _logical_T_182}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_419 = _GEN[_lut_T] >> _logical_T_418; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_420 = _logical_T_419[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_421 = {_logical_T_55, _logical_T_183}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_422 = _GEN[_lut_T] >> _logical_T_421; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_423 = _logical_T_422[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_424 = {_logical_T_56, _logical_T_184}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_425 = _GEN[_lut_T] >> _logical_T_424; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_426 = _logical_T_425[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_427 = {_logical_T_57, _logical_T_185}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_428 = _GEN[_lut_T] >> _logical_T_427; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_429 = _logical_T_428[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_430 = {_logical_T_58, _logical_T_186}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_431 = _GEN[_lut_T] >> _logical_T_430; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_432 = _logical_T_431[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_433 = {_logical_T_59, _logical_T_187}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_434 = _GEN[_lut_T] >> _logical_T_433; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_435 = _logical_T_434[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_436 = {_logical_T_60, _logical_T_188}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_437 = _GEN[_lut_T] >> _logical_T_436; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_438 = _logical_T_437[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_439 = {_logical_T_61, _logical_T_189}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_440 = _GEN[_lut_T] >> _logical_T_439; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_441 = _logical_T_440[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_442 = {_logical_T_62, _logical_T_190}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_443 = _GEN[_lut_T] >> _logical_T_442; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_444 = _logical_T_443[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_445 = {_logical_T_63, _logical_T_191}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_446 = _GEN[_lut_T] >> _logical_T_445; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_447 = _logical_T_446[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_448 = {_logical_T_64, _logical_T_192}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_449 = _GEN[_lut_T] >> _logical_T_448; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_450 = _logical_T_449[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_451 = {_logical_T_65, _logical_T_193}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_452 = _GEN[_lut_T] >> _logical_T_451; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_453 = _logical_T_452[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_454 = {_logical_T_66, _logical_T_194}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_455 = _GEN[_lut_T] >> _logical_T_454; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_456 = _logical_T_455[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_457 = {_logical_T_67, _logical_T_195}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_458 = _GEN[_lut_T] >> _logical_T_457; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_459 = _logical_T_458[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_460 = {_logical_T_68, _logical_T_196}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_461 = _GEN[_lut_T] >> _logical_T_460; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_462 = _logical_T_461[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_463 = {_logical_T_69, _logical_T_197}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_464 = _GEN[_lut_T] >> _logical_T_463; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_465 = _logical_T_464[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_466 = {_logical_T_70, _logical_T_198}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_467 = _GEN[_lut_T] >> _logical_T_466; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_468 = _logical_T_467[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_469 = {_logical_T_71, _logical_T_199}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_470 = _GEN[_lut_T] >> _logical_T_469; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_471 = _logical_T_470[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_472 = {_logical_T_72, _logical_T_200}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_473 = _GEN[_lut_T] >> _logical_T_472; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_474 = _logical_T_473[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_475 = {_logical_T_73, _logical_T_201}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_476 = _GEN[_lut_T] >> _logical_T_475; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_477 = _logical_T_476[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_478 = {_logical_T_74, _logical_T_202}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_479 = _GEN[_lut_T] >> _logical_T_478; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_480 = _logical_T_479[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_481 = {_logical_T_75, _logical_T_203}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_482 = _GEN[_lut_T] >> _logical_T_481; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_483 = _logical_T_482[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_484 = {_logical_T_76, _logical_T_204}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_485 = _GEN[_lut_T] >> _logical_T_484; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_486 = _logical_T_485[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_487 = {_logical_T_77, _logical_T_205}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_488 = _GEN[_lut_T] >> _logical_T_487; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_489 = _logical_T_488[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_490 = {_logical_T_78, _logical_T_206}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_491 = _GEN[_lut_T] >> _logical_T_490; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_492 = _logical_T_491[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_493 = {_logical_T_79, _logical_T_207}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_494 = _GEN[_lut_T] >> _logical_T_493; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_495 = _logical_T_494[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_496 = {_logical_T_80, _logical_T_208}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_497 = _GEN[_lut_T] >> _logical_T_496; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_498 = _logical_T_497[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_499 = {_logical_T_81, _logical_T_209}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_500 = _GEN[_lut_T] >> _logical_T_499; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_501 = _logical_T_500[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_502 = {_logical_T_82, _logical_T_210}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_503 = _GEN[_lut_T] >> _logical_T_502; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_504 = _logical_T_503[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_505 = {_logical_T_83, _logical_T_211}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_506 = _GEN[_lut_T] >> _logical_T_505; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_507 = _logical_T_506[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_508 = {_logical_T_84, _logical_T_212}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_509 = _GEN[_lut_T] >> _logical_T_508; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_510 = _logical_T_509[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_511 = {_logical_T_85, _logical_T_213}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_512 = _GEN[_lut_T] >> _logical_T_511; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_513 = _logical_T_512[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_514 = {_logical_T_86, _logical_T_214}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_515 = _GEN[_lut_T] >> _logical_T_514; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_516 = _logical_T_515[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_517 = {_logical_T_87, _logical_T_215}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_518 = _GEN[_lut_T] >> _logical_T_517; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_519 = _logical_T_518[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_520 = {_logical_T_88, _logical_T_216}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_521 = _GEN[_lut_T] >> _logical_T_520; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_522 = _logical_T_521[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_523 = {_logical_T_89, _logical_T_217}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_524 = _GEN[_lut_T] >> _logical_T_523; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_525 = _logical_T_524[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_526 = {_logical_T_90, _logical_T_218}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_527 = _GEN[_lut_T] >> _logical_T_526; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_528 = _logical_T_527[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_529 = {_logical_T_91, _logical_T_219}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_530 = _GEN[_lut_T] >> _logical_T_529; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_531 = _logical_T_530[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_532 = {_logical_T_92, _logical_T_220}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_533 = _GEN[_lut_T] >> _logical_T_532; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_534 = _logical_T_533[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_535 = {_logical_T_93, _logical_T_221}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_536 = _GEN[_lut_T] >> _logical_T_535; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_537 = _logical_T_536[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_538 = {_logical_T_94, _logical_T_222}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_539 = _GEN[_lut_T] >> _logical_T_538; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_540 = _logical_T_539[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_541 = {_logical_T_95, _logical_T_223}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_542 = _GEN[_lut_T] >> _logical_T_541; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_543 = _logical_T_542[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_544 = {_logical_T_96, _logical_T_224}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_545 = _GEN[_lut_T] >> _logical_T_544; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_546 = _logical_T_545[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_547 = {_logical_T_97, _logical_T_225}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_548 = _GEN[_lut_T] >> _logical_T_547; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_549 = _logical_T_548[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_550 = {_logical_T_98, _logical_T_226}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_551 = _GEN[_lut_T] >> _logical_T_550; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_552 = _logical_T_551[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_553 = {_logical_T_99, _logical_T_227}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_554 = _GEN[_lut_T] >> _logical_T_553; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_555 = _logical_T_554[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_556 = {_logical_T_100, _logical_T_228}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_557 = _GEN[_lut_T] >> _logical_T_556; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_558 = _logical_T_557[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_559 = {_logical_T_101, _logical_T_229}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_560 = _GEN[_lut_T] >> _logical_T_559; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_561 = _logical_T_560[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_562 = {_logical_T_102, _logical_T_230}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_563 = _GEN[_lut_T] >> _logical_T_562; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_564 = _logical_T_563[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_565 = {_logical_T_103, _logical_T_231}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_566 = _GEN[_lut_T] >> _logical_T_565; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_567 = _logical_T_566[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_568 = {_logical_T_104, _logical_T_232}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_569 = _GEN[_lut_T] >> _logical_T_568; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_570 = _logical_T_569[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_571 = {_logical_T_105, _logical_T_233}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_572 = _GEN[_lut_T] >> _logical_T_571; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_573 = _logical_T_572[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_574 = {_logical_T_106, _logical_T_234}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_575 = _GEN[_lut_T] >> _logical_T_574; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_576 = _logical_T_575[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_577 = {_logical_T_107, _logical_T_235}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_578 = _GEN[_lut_T] >> _logical_T_577; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_579 = _logical_T_578[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_580 = {_logical_T_108, _logical_T_236}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_581 = _GEN[_lut_T] >> _logical_T_580; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_582 = _logical_T_581[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_583 = {_logical_T_109, _logical_T_237}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_584 = _GEN[_lut_T] >> _logical_T_583; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_585 = _logical_T_584[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_586 = {_logical_T_110, _logical_T_238}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_587 = _GEN[_lut_T] >> _logical_T_586; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_588 = _logical_T_587[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_589 = {_logical_T_111, _logical_T_239}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_590 = _GEN[_lut_T] >> _logical_T_589; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_591 = _logical_T_590[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_592 = {_logical_T_112, _logical_T_240}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_593 = _GEN[_lut_T] >> _logical_T_592; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_594 = _logical_T_593[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_595 = {_logical_T_113, _logical_T_241}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_596 = _GEN[_lut_T] >> _logical_T_595; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_597 = _logical_T_596[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_598 = {_logical_T_114, _logical_T_242}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_599 = _GEN[_lut_T] >> _logical_T_598; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_600 = _logical_T_599[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_601 = {_logical_T_115, _logical_T_243}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_602 = _GEN[_lut_T] >> _logical_T_601; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_603 = _logical_T_602[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_604 = {_logical_T_116, _logical_T_244}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_605 = _GEN[_lut_T] >> _logical_T_604; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_606 = _logical_T_605[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_607 = {_logical_T_117, _logical_T_245}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_608 = _GEN[_lut_T] >> _logical_T_607; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_609 = _logical_T_608[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_610 = {_logical_T_118, _logical_T_246}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_611 = _GEN[_lut_T] >> _logical_T_610; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_612 = _logical_T_611[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_613 = {_logical_T_119, _logical_T_247}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_614 = _GEN[_lut_T] >> _logical_T_613; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_615 = _logical_T_614[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_616 = {_logical_T_120, _logical_T_248}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_617 = _GEN[_lut_T] >> _logical_T_616; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_618 = _logical_T_617[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_619 = {_logical_T_121, _logical_T_249}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_620 = _GEN[_lut_T] >> _logical_T_619; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_621 = _logical_T_620[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_622 = {_logical_T_122, _logical_T_250}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_623 = _GEN[_lut_T] >> _logical_T_622; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_624 = _logical_T_623[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_625 = {_logical_T_123, _logical_T_251}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_626 = _GEN[_lut_T] >> _logical_T_625; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_627 = _logical_T_626[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_628 = {_logical_T_124, _logical_T_252}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_629 = _GEN[_lut_T] >> _logical_T_628; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_630 = _logical_T_629[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_631 = {_logical_T_125, _logical_T_253}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_632 = _GEN[_lut_T] >> _logical_T_631; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_633 = _logical_T_632[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_634 = {_logical_T_126, _logical_T_254}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_635 = _GEN[_lut_T] >> _logical_T_634; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_636 = _logical_T_635[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_637 = {_logical_T_127, _logical_T_255}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_638 = _GEN[_lut_T] >> _logical_T_637; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_639 = _logical_T_638[0]; // @[Atomics.scala:41:8]
wire [1:0] logical_lo_lo_lo_lo_lo_lo = {_logical_T_261, _logical_T_258}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_lo_lo_hi = {_logical_T_267, _logical_T_264}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_lo_lo = {logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_lo_hi_lo = {_logical_T_273, _logical_T_270}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_lo_hi_hi = {_logical_T_279, _logical_T_276}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_lo_hi = {logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_lo_lo = {logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_hi_lo_lo = {_logical_T_285, _logical_T_282}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_hi_lo_hi = {_logical_T_291, _logical_T_288}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_hi_lo = {logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_hi_hi_lo = {_logical_T_297, _logical_T_294}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_hi_hi_hi = {_logical_T_303, _logical_T_300}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_hi_hi = {logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_lo_hi = {logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_lo_lo_lo = {_logical_T_309, _logical_T_306}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_lo_lo_hi = {_logical_T_315, _logical_T_312}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_lo_lo = {logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_lo_hi_lo = {_logical_T_321, _logical_T_318}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_lo_hi_hi = {_logical_T_327, _logical_T_324}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_lo_hi = {logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_hi_lo = {logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_hi_lo_lo = {_logical_T_333, _logical_T_330}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_hi_lo_hi = {_logical_T_339, _logical_T_336}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_hi_lo = {logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_hi_hi_lo = {_logical_T_345, _logical_T_342}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_hi_hi_hi = {_logical_T_351, _logical_T_348}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_hi_hi = {logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_hi_hi = {logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_lo_lo_lo = {_logical_T_357, _logical_T_354}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_lo_lo_hi = {_logical_T_363, _logical_T_360}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_lo_lo = {logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_lo_hi_lo = {_logical_T_369, _logical_T_366}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_lo_hi_hi = {_logical_T_375, _logical_T_372}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_lo_hi = {logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_lo_lo = {logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_hi_lo_lo = {_logical_T_381, _logical_T_378}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_hi_lo_hi = {_logical_T_387, _logical_T_384}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_hi_lo = {logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_hi_hi_lo = {_logical_T_393, _logical_T_390}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_hi_hi_hi = {_logical_T_399, _logical_T_396}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_hi_hi = {logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_lo_hi = {logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_lo_lo_lo = {_logical_T_405, _logical_T_402}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_lo_lo_hi = {_logical_T_411, _logical_T_408}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_lo_lo = {logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_lo_hi_lo = {_logical_T_417, _logical_T_414}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_lo_hi_hi = {_logical_T_423, _logical_T_420}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_lo_hi = {logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_hi_lo = {logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_hi_lo_lo = {_logical_T_429, _logical_T_426}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_hi_lo_hi = {_logical_T_435, _logical_T_432}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_hi_lo = {logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_hi_hi_lo = {_logical_T_441, _logical_T_438}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_hi_hi_hi = {_logical_T_447, _logical_T_444}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_hi_hi = {logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_hi_hi = {logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [63:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_lo_lo_lo = {_logical_T_453, _logical_T_450}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_lo_lo_hi = {_logical_T_459, _logical_T_456}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_lo_lo = {logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_lo_hi_lo = {_logical_T_465, _logical_T_462}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_lo_hi_hi = {_logical_T_471, _logical_T_468}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_lo_hi = {logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_lo_lo = {logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_hi_lo_lo = {_logical_T_477, _logical_T_474}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_hi_lo_hi = {_logical_T_483, _logical_T_480}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_hi_lo = {logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_hi_hi_lo = {_logical_T_489, _logical_T_486}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_hi_hi_hi = {_logical_T_495, _logical_T_492}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_hi_hi = {logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_lo_hi = {logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_lo_lo_lo = {_logical_T_501, _logical_T_498}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_lo_lo_hi = {_logical_T_507, _logical_T_504}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_lo_lo = {logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_lo_hi_lo = {_logical_T_513, _logical_T_510}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_lo_hi_hi = {_logical_T_519, _logical_T_516}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_lo_hi = {logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_hi_lo = {logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_hi_lo_lo = {_logical_T_525, _logical_T_522}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_hi_lo_hi = {_logical_T_531, _logical_T_528}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_hi_lo = {logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_hi_hi_lo = {_logical_T_537, _logical_T_534}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_hi_hi_hi = {_logical_T_543, _logical_T_540}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_hi_hi = {logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_hi_hi = {logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_lo_lo_lo = {_logical_T_549, _logical_T_546}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_lo_lo_hi = {_logical_T_555, _logical_T_552}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_lo_lo = {logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_lo_hi_lo = {_logical_T_561, _logical_T_558}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_lo_hi_hi = {_logical_T_567, _logical_T_564}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_lo_hi = {logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_lo_lo = {logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_hi_lo_lo = {_logical_T_573, _logical_T_570}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_hi_lo_hi = {_logical_T_579, _logical_T_576}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_hi_lo = {logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_hi_hi_lo = {_logical_T_585, _logical_T_582}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_hi_hi_hi = {_logical_T_591, _logical_T_588}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_hi_hi = {logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_lo_hi = {logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_lo_lo_lo = {_logical_T_597, _logical_T_594}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_lo_lo_hi = {_logical_T_603, _logical_T_600}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_lo_lo = {logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_lo_hi_lo = {_logical_T_609, _logical_T_606}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_lo_hi_hi = {_logical_T_615, _logical_T_612}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_lo_hi = {logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_hi_lo = {logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_hi_lo_lo = {_logical_T_621, _logical_T_618}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_hi_lo_hi = {_logical_T_627, _logical_T_624}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_hi_lo = {logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_hi_hi_lo = {_logical_T_633, _logical_T_630}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_hi_hi_hi = {_logical_T_639, _logical_T_636}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [63:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20]
wire [127:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20]
wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}]
wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8]
wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}]
wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19]
wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_4 = _selects_T_4 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_5 = _selects_T_5 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_6 = _selects_T_6 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_7 = _selects_T_7 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_8 = _selects_T_8 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_9 = _selects_T_9 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_10 = _selects_T_10 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_11 = _selects_T_11 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_12 = _selects_T_12 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_13 = _selects_T_13 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_14 = _selects_T_14 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_15 = _selects_T_15 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_16 = io_data_in_0[39:32]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_4_0 = _io_data_out_T_16; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_17 = io_a_data_0[39:32]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_4_1 = _io_data_out_T_17; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_18 = sum[39:32]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_4_2 = _io_data_out_T_18; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_19 = logical[39:32]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_4_3 = _io_data_out_T_19; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_20 = io_data_in_0[47:40]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_5_0 = _io_data_out_T_20; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_21 = io_a_data_0[47:40]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_5_1 = _io_data_out_T_21; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_22 = sum[47:40]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_5_2 = _io_data_out_T_22; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_23 = logical[47:40]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_5_3 = _io_data_out_T_23; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_24 = io_data_in_0[55:48]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_6_0 = _io_data_out_T_24; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_25 = io_a_data_0[55:48]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_6_1 = _io_data_out_T_25; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_26 = sum[55:48]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_6_2 = _io_data_out_T_26; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_27 = logical[55:48]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_6_3 = _io_data_out_T_27; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_28 = io_data_in_0[63:56]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_7_0 = _io_data_out_T_28; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_29 = io_a_data_0[63:56]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_7_1 = _io_data_out_T_29; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_30 = sum[63:56]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_7_2 = _io_data_out_T_30; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_31 = logical[63:56]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_7_3 = _io_data_out_T_31; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_32 = io_data_in_0[71:64]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_8_0 = _io_data_out_T_32; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_33 = io_a_data_0[71:64]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_8_1 = _io_data_out_T_33; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_34 = sum[71:64]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_8_2 = _io_data_out_T_34; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_35 = logical[71:64]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_8_3 = _io_data_out_T_35; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_36 = io_data_in_0[79:72]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_9_0 = _io_data_out_T_36; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_37 = io_a_data_0[79:72]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_9_1 = _io_data_out_T_37; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_38 = sum[79:72]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_9_2 = _io_data_out_T_38; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_39 = logical[79:72]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_9_3 = _io_data_out_T_39; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_40 = io_data_in_0[87:80]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_10_0 = _io_data_out_T_40; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_41 = io_a_data_0[87:80]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_10_1 = _io_data_out_T_41; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_42 = sum[87:80]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_10_2 = _io_data_out_T_42; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_43 = logical[87:80]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_10_3 = _io_data_out_T_43; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_44 = io_data_in_0[95:88]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_11_0 = _io_data_out_T_44; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_45 = io_a_data_0[95:88]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_11_1 = _io_data_out_T_45; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_46 = sum[95:88]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_11_2 = _io_data_out_T_46; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_47 = logical[95:88]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_11_3 = _io_data_out_T_47; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_48 = io_data_in_0[103:96]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_12_0 = _io_data_out_T_48; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_49 = io_a_data_0[103:96]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_12_1 = _io_data_out_T_49; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_50 = sum[103:96]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_12_2 = _io_data_out_T_50; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_51 = logical[103:96]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_12_3 = _io_data_out_T_51; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_52 = io_data_in_0[111:104]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_13_0 = _io_data_out_T_52; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_53 = io_a_data_0[111:104]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_13_1 = _io_data_out_T_53; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_54 = sum[111:104]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_13_2 = _io_data_out_T_54; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_55 = logical[111:104]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_13_3 = _io_data_out_T_55; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_56 = io_data_in_0[119:112]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_14_0 = _io_data_out_T_56; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_57 = io_a_data_0[119:112]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_14_1 = _io_data_out_T_57; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_58 = sum[119:112]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_14_2 = _io_data_out_T_58; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_59 = logical[119:112]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_14_3 = _io_data_out_T_59; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_60 = io_data_in_0[127:120]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_15_0 = _io_data_out_T_60; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_61 = io_a_data_0[127:120]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_15_1 = _io_data_out_T_61; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_62 = sum[127:120]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_15_2 = _io_data_out_T_62; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_63 = logical[127:120]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_15_3 = _io_data_out_T_63; // @[Atomics.scala:59:{12,59}]
wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_lo_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_lo_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_lo_lo = {io_data_out_lo_lo_hi, io_data_out_lo_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_5 = {{_io_data_out_WIRE_5_3}, {_io_data_out_WIRE_5_2}, {_io_data_out_WIRE_5_1}, {_io_data_out_WIRE_5_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_6 = {{_io_data_out_WIRE_4_3}, {_io_data_out_WIRE_4_2}, {_io_data_out_WIRE_4_1}, {_io_data_out_WIRE_4_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_hi_lo = {_GEN_5[selects_5], _GEN_6[selects_4]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_7 = {{_io_data_out_WIRE_7_3}, {_io_data_out_WIRE_7_2}, {_io_data_out_WIRE_7_1}, {_io_data_out_WIRE_7_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_8 = {{_io_data_out_WIRE_6_3}, {_io_data_out_WIRE_6_2}, {_io_data_out_WIRE_6_1}, {_io_data_out_WIRE_6_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_hi_hi = {_GEN_7[selects_7], _GEN_8[selects_6]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_lo_hi = {io_data_out_lo_hi_hi, io_data_out_lo_hi_lo}; // @[Atomics.scala:58:21]
wire [63:0] io_data_out_lo = {io_data_out_lo_hi, io_data_out_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_9 = {{_io_data_out_WIRE_9_3}, {_io_data_out_WIRE_9_2}, {_io_data_out_WIRE_9_1}, {_io_data_out_WIRE_9_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_10 = {{_io_data_out_WIRE_8_3}, {_io_data_out_WIRE_8_2}, {_io_data_out_WIRE_8_1}, {_io_data_out_WIRE_8_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_lo_lo = {_GEN_9[selects_9], _GEN_10[selects_8]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_11 = {{_io_data_out_WIRE_11_3}, {_io_data_out_WIRE_11_2}, {_io_data_out_WIRE_11_1}, {_io_data_out_WIRE_11_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_12 = {{_io_data_out_WIRE_10_3}, {_io_data_out_WIRE_10_2}, {_io_data_out_WIRE_10_1}, {_io_data_out_WIRE_10_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_lo_hi = {_GEN_11[selects_11], _GEN_12[selects_10]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_hi_lo = {io_data_out_hi_lo_hi, io_data_out_hi_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_13 = {{_io_data_out_WIRE_13_3}, {_io_data_out_WIRE_13_2}, {_io_data_out_WIRE_13_1}, {_io_data_out_WIRE_13_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_14 = {{_io_data_out_WIRE_12_3}, {_io_data_out_WIRE_12_2}, {_io_data_out_WIRE_12_1}, {_io_data_out_WIRE_12_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_hi_lo = {_GEN_13[selects_13], _GEN_14[selects_12]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_15 = {{_io_data_out_WIRE_15_3}, {_io_data_out_WIRE_15_2}, {_io_data_out_WIRE_15_1}, {_io_data_out_WIRE_15_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_16 = {{_io_data_out_WIRE_14_3}, {_io_data_out_WIRE_14_2}, {_io_data_out_WIRE_14_1}, {_io_data_out_WIRE_14_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_hi_hi = {_GEN_15[selects_15], _GEN_16[selects_14]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_hi_hi = {io_data_out_hi_hi_hi, io_data_out_hi_hi_lo}; // @[Atomics.scala:58:21]
wire [63:0] io_data_out_hi = {io_data_out_hi_hi, io_data_out_hi_lo}; // @[Atomics.scala:58:21]
assign _io_data_out_T_64 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21]
assign io_data_out_0 = _io_data_out_T_64; // @[Atomics.scala:8:7, :58:21]
assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_131 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_141
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_131( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_141 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_91 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = or(_T_54, UInt<1>(0h0))
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_60 = or(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_60, UInt<1>(0h1), "") : assert_4
node _T_64 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_65 = or(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_65, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_91( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_117 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_117
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_117( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_117 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBFromNoC :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<47>, clock
node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0))
node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T)
node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready)
connect io.flit.ready, _io_flit_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_address_WIRE : UInt<32>
connect _protocol_bits_address_WIRE, const
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T = shr(const, 32)
wire _protocol_bits_source_WIRE : UInt<6>
connect _protocol_bits_source_WIRE, _T
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_1 = shr(_T, 6)
wire _protocol_bits_size_WIRE : UInt<4>
connect _protocol_bits_size_WIRE, _T_1
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_2 = shr(_T_1, 4)
wire _protocol_bits_param_WIRE : UInt<2>
connect _protocol_bits_param_WIRE, _T_2
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_3 = shr(_T_2, 2)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_3
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_4 = shr(_T_3, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_5 = shr(io.flit.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_5
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_6 = shr(_T_5, 64)
wire _protocol_bits_mask_WIRE : UInt<8>
connect _protocol_bits_mask_WIRE, _T_6
connect protocol.bits.mask, _protocol_bits_mask_WIRE
node _T_7 = shr(_T_6, 8)
node _T_8 = and(io.flit.ready, io.flit.valid)
node _T_9 = and(_T_8, io.flit.bits.head)
when _T_9 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.flit.bits.payload
node _T_10 = and(io.flit.ready, io.flit.valid)
node _T_11 = and(_T_10, io.flit.bits.tail)
when _T_11 :
connect is_const, UInt<1>(0h1)
connect io.protocol, protocol
node _io_protocol_bits_source_T = bits(protocol.bits.source, 4, 0)
connect io.protocol.bits.source, _io_protocol_bits_source_T
when io.flit.bits.head :
node _io_protocol_bits_mask_T = not(UInt<8>(0h0))
connect io.protocol.bits.mask, _io_protocol_bits_mask_T | module TLBFromNoC( // @[TilelinkAdapters.scala:145:7]
input clock, // @[TilelinkAdapters.scala:145:7]
input reset, // @[TilelinkAdapters.scala:145:7]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail; // @[TilelinkAdapters.scala:68:25, :71:{30,33}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:145:7]
if (reset) // @[TilelinkAdapters.scala:145:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :145:7]
else // @[TilelinkAdapters.scala:145:7]
is_const <= _GEN & io_flit_bits_tail | ~(_GEN & io_flit_bits_head) & is_const; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 13, 0)
node _source_ok_T = shr(io.in.a.bits.source, 14)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<14>(0h200f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits = bits(_uncommonBits_T, 13, 0)
node _T_4 = shr(io.in.a.bits.source, 14)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<14>(0h200f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 13, 0)
node _T_24 = shr(io.in.a.bits.source, 14)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<14>(0h200f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 13, 0)
node _T_86 = shr(io.in.a.bits.source, 14)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<14>(0h200f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 13, 0)
node _T_152 = shr(io.in.a.bits.source, 14)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<14>(0h200f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 13, 0)
node _T_199 = shr(io.in.a.bits.source, 14)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<14>(0h200f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 13, 0)
node _T_240 = shr(io.in.a.bits.source, 14)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<14>(0h200f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 13, 0)
node _T_283 = shr(io.in.a.bits.source, 14)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<14>(0h200f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 13, 0)
node _T_321 = shr(io.in.a.bits.source, 14)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<14>(0h200f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<14>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 13, 0)
node _T_359 = shr(io.in.a.bits.source, 14)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<14>(0h200f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<14>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 13, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 14)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<14>(0h200f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<14>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<14>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<8208>, clock, reset, UInt<8208>(0h0)
regreset inflight_opcodes : UInt<32832>, clock, reset, UInt<32832>(0h0)
regreset inflight_sizes : UInt<32832>, clock, reset, UInt<32832>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<8208>
connect a_set, UInt<8208>(0h0)
wire a_set_wo_ready : UInt<8208>
connect a_set_wo_ready, UInt<8208>(0h0)
wire a_opcodes_set : UInt<32832>
connect a_opcodes_set, UInt<32832>(0h0)
wire a_sizes_set : UInt<32832>
connect a_sizes_set, UInt<32832>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<8208>
connect d_clr, UInt<8208>(0h0)
wire d_clr_wo_ready : UInt<8208>
connect d_clr_wo_ready, UInt<8208>(0h0)
wire d_opcodes_clr : UInt<32832>
connect d_opcodes_clr, UInt<32832>(0h0)
wire d_sizes_clr : UInt<32832>
connect d_sizes_clr, UInt<32832>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_102
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<8208>, clock, reset, UInt<8208>(0h0)
regreset inflight_opcodes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0)
regreset inflight_sizes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<14>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<8208>
connect c_set, UInt<8208>(0h0)
wire c_set_wo_ready : UInt<8208>
connect c_set_wo_ready, UInt<8208>(0h0)
wire c_opcodes_set : UInt<32832>
connect c_opcodes_set, UInt<32832>(0h0)
wire c_sizes_set : UInt<32832>
connect c_sizes_set, UInt<32832>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<14>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<14>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<14>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<14>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<14>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<14>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<8208>
connect d_clr_1, UInt<8208>(0h0)
wire d_clr_wo_ready_1 : UInt<8208>
connect d_clr_wo_ready_1, UInt<8208>(0h0)
wire d_opcodes_clr_1 : UInt<32832>
connect d_opcodes_clr_1, UInt<32832>(0h0)
wire d_sizes_clr_1 : UInt<32832>
connect d_sizes_clr_1, UInt<32832>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<14>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<14>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<14>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<14>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_103
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<14>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52]
wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79]
wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77]
wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35]
wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35]
wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34]
wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34]
wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34]
wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [13:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [13:0] source_1; // @[Monitor.scala:541:22]
reg [8207:0] inflight; // @[Monitor.scala:614:27]
reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [8207:0] a_set; // @[Monitor.scala:626:34]
wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [16383:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [8207:0] d_clr; // @[Monitor.scala:664:34]
wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [8207:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [32831:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [32831:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [8207:0] inflight_1; // @[Monitor.scala:726:35]
wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [8207:0] d_clr_1; // @[Monitor.scala:774:34]
wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35]
wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113]
wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<10>(0h200)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = and(_T_19, _T_24)
node _T_26 = or(UInt<1>(0h0), _T_25)
node _T_27 = and(_T_18, _T_26)
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(UInt<1>(0h0), _T_33)
node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<10>(0h200)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = and(_T_34, _T_39)
node _T_41 = or(UInt<1>(0h0), _T_40)
node _T_42 = and(UInt<1>(0h0), _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_42, UInt<1>(0h1), "") : assert_3
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(is_aligned, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_56, UInt<1>(0h1), "") : assert_7
node _T_60 = not(io.in.a.bits.mask)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_61, UInt<1>(0h1), "") : assert_8
node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_69 :
node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_71 = and(UInt<1>(0h0), _T_70)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<10>(0h200)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = and(_T_73, _T_78)
node _T_80 = or(UInt<1>(0h0), _T_79)
node _T_81 = and(_T_72, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_81, UInt<1>(0h1), "") : assert_10
node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_87 = and(_T_85, _T_86)
node _T_88 = or(UInt<1>(0h0), _T_87)
node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h200)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = and(_T_88, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = and(UInt<1>(0h0), _T_95)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_103, UInt<1>(0h1), "") : assert_13
node _T_107 = asUInt(reset)
node _T_108 = eq(_T_107, UInt<1>(0h0))
when _T_108 :
node _T_109 = eq(is_aligned, UInt<1>(0h0))
when _T_109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_110, UInt<1>(0h1), "") : assert_15
node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_114, UInt<1>(0h1), "") : assert_16
node _T_118 = not(io.in.a.bits.mask)
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_119, UInt<1>(0h1), "") : assert_17
node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_123, UInt<1>(0h1), "") : assert_18
node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_127 :
node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = or(UInt<1>(0h0), _T_130)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_131, UInt<1>(0h1), "") : assert_19
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<10>(0h200)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = and(_T_138, _T_143)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = asUInt(reset)
node _T_147 = eq(_T_146, UInt<1>(0h0))
when _T_147 :
node _T_148 = eq(_T_145, UInt<1>(0h0))
when _T_148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_145, UInt<1>(0h1), "") : assert_20
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_155, UInt<1>(0h1), "") : assert_23
node _T_159 = eq(io.in.a.bits.mask, mask)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_159, UInt<1>(0h1), "") : assert_24
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_163, UInt<1>(0h1), "") : assert_25
node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_170 = and(_T_168, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<10>(0h200)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = and(_T_175, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_183, UInt<1>(0h1), "") : assert_26
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(is_aligned, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_193, UInt<1>(0h1), "") : assert_29
node _T_197 = eq(io.in.a.bits.mask, mask)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_197, UInt<1>(0h1), "") : assert_30
node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_201 :
node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_203 = and(UInt<1>(0h0), _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_207 = and(_T_205, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<10>(0h200)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = and(_T_208, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(_T_204, _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_216, UInt<1>(0h1), "") : assert_31
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(is_aligned, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_226, UInt<1>(0h1), "") : assert_34
node _T_230 = not(mask)
node _T_231 = and(io.in.a.bits.mask, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_232, UInt<1>(0h1), "") : assert_35
node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_236 :
node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_238 = and(UInt<1>(0h0), _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<10>(0h200)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = and(_T_240, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = and(_T_239, _T_247)
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_248, UInt<1>(0h1), "") : assert_36
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(is_aligned, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_258, UInt<1>(0h1), "") : assert_39
node _T_262 = eq(io.in.a.bits.mask, mask)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_262, UInt<1>(0h1), "") : assert_40
node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_266 :
node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_268 = and(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<10>(0h200)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_T_269, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_278, UInt<1>(0h1), "") : assert_41
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_288, UInt<1>(0h1), "") : assert_44
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_292, UInt<1>(0h1), "") : assert_45
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_296 :
node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_298 = and(UInt<1>(0h0), _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<10>(0h200)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = and(_T_300, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = and(_T_299, _T_307)
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_308, UInt<1>(0h1), "") : assert_46
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_318, UInt<1>(0h1), "") : assert_49
node _T_322 = eq(io.in.a.bits.mask, mask)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_322, UInt<1>(0h1), "") : assert_50
node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_326, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_330, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_334 :
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_338, UInt<1>(0h1), "") : assert_54
node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_342, UInt<1>(0h1), "") : assert_55
node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_346, UInt<1>(0h1), "") : assert_56
node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_350, UInt<1>(0h1), "") : assert_57
node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_354 :
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(sink_ok, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_361, UInt<1>(0h1), "") : assert_60
node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_365, UInt<1>(0h1), "") : assert_61
node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_369, UInt<1>(0h1), "") : assert_62
node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_373, UInt<1>(0h1), "") : assert_63
node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_378 = or(UInt<1>(0h1), _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_378, UInt<1>(0h1), "") : assert_64
node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_382 :
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(sink_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_389, UInt<1>(0h1), "") : assert_67
node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_393, UInt<1>(0h1), "") : assert_68
node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_397, UInt<1>(0h1), "") : assert_69
node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_402 = or(_T_401, io.in.d.bits.corrupt)
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_402, UInt<1>(0h1), "") : assert_70
node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_407 = or(UInt<1>(0h1), _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_407, UInt<1>(0h1), "") : assert_71
node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_411 :
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_415, UInt<1>(0h1), "") : assert_73
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_419, UInt<1>(0h1), "") : assert_74
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = or(UInt<1>(0h1), _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_424, UInt<1>(0h1), "") : assert_75
node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_428 :
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_432, UInt<1>(0h1), "") : assert_77
node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_437 = or(_T_436, io.in.d.bits.corrupt)
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_437, UInt<1>(0h1), "") : assert_78
node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_442 = or(UInt<1>(0h1), _T_441)
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_442, UInt<1>(0h1), "") : assert_79
node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_450, UInt<1>(0h1), "") : assert_81
node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_454, UInt<1>(0h1), "") : assert_82
node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_459 = or(UInt<1>(0h1), _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_459, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_463, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_467, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_471, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_475 = eq(a_first, UInt<1>(0h0))
node _T_476 = and(io.in.a.valid, _T_475)
when _T_476 :
node _T_477 = eq(io.in.a.bits.opcode, opcode)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_477, UInt<1>(0h1), "") : assert_87
node _T_481 = eq(io.in.a.bits.param, param)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_481, UInt<1>(0h1), "") : assert_88
node _T_485 = eq(io.in.a.bits.size, size)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_485, UInt<1>(0h1), "") : assert_89
node _T_489 = eq(io.in.a.bits.source, source)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_489, UInt<1>(0h1), "") : assert_90
node _T_493 = eq(io.in.a.bits.address, address)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_493, UInt<1>(0h1), "") : assert_91
node _T_497 = and(io.in.a.ready, io.in.a.valid)
node _T_498 = and(_T_497, a_first)
when _T_498 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_499 = eq(d_first, UInt<1>(0h0))
node _T_500 = and(io.in.d.valid, _T_499)
when _T_500 :
node _T_501 = eq(io.in.d.bits.opcode, opcode_1)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_501, UInt<1>(0h1), "") : assert_92
node _T_505 = eq(io.in.d.bits.param, param_1)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_505, UInt<1>(0h1), "") : assert_93
node _T_509 = eq(io.in.d.bits.size, size_1)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_509, UInt<1>(0h1), "") : assert_94
node _T_513 = eq(io.in.d.bits.source, source_1)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_513, UInt<1>(0h1), "") : assert_95
node _T_517 = eq(io.in.d.bits.sink, sink)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_517, UInt<1>(0h1), "") : assert_96
node _T_521 = eq(io.in.d.bits.denied, denied)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_521, UInt<1>(0h1), "") : assert_97
node _T_525 = and(io.in.d.ready, io.in.d.valid)
node _T_526 = and(_T_525, d_first)
when _T_526 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_527 = and(io.in.a.valid, a_first_1)
node _T_528 = and(_T_527, UInt<1>(0h1))
when _T_528 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_529 = and(io.in.a.ready, io.in.a.valid)
node _T_530 = and(_T_529, a_first_1)
node _T_531 = and(_T_530, UInt<1>(0h1))
when _T_531 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_532 = dshr(inflight, io.in.a.bits.source)
node _T_533 = bits(_T_532, 0, 0)
node _T_534 = eq(_T_533, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_534, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_538 = and(io.in.d.valid, d_first_1)
node _T_539 = and(_T_538, UInt<1>(0h1))
node _T_540 = eq(d_release_ack, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
when _T_541 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_542 = and(io.in.d.ready, io.in.d.valid)
node _T_543 = and(_T_542, d_first_1)
node _T_544 = and(_T_543, UInt<1>(0h1))
node _T_545 = eq(d_release_ack, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
when _T_546 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_551 = dshr(inflight, io.in.d.bits.source)
node _T_552 = bits(_T_551, 0, 0)
node _T_553 = or(_T_552, same_cycle_resp)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_553, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_559 = or(_T_557, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_559, UInt<1>(0h1), "") : assert_100
node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_563, UInt<1>(0h1), "") : assert_101
else :
node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_569, UInt<1>(0h1), "") : assert_102
node _T_573 = eq(io.in.d.bits.size, a_size_lookup)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_573, UInt<1>(0h1), "") : assert_103
node _T_577 = and(io.in.d.valid, d_first_1)
node _T_578 = and(_T_577, a_first_1)
node _T_579 = and(_T_578, io.in.a.valid)
node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(d_release_ack, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
node _T_584 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_585 = or(_T_584, io.in.a.ready)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_585, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_90
node _T_589 = orr(inflight)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_592 = or(_T_590, _T_591)
node _T_593 = lt(watchdog, plusarg_reader.out)
node _T_594 = or(_T_592, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_594, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_598 = and(io.in.a.ready, io.in.a.valid)
node _T_599 = and(io.in.d.ready, io.in.d.valid)
node _T_600 = or(_T_598, _T_599)
when _T_600 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_601 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_604 = and(_T_602, _T_603)
node _T_605 = and(_T_601, _T_604)
when _T_605 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_607 = and(_T_606, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_610 = and(_T_608, _T_609)
node _T_611 = and(_T_607, _T_610)
when _T_611 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_612 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_614, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_618 = and(io.in.d.valid, d_first_2)
node _T_619 = and(_T_618, UInt<1>(0h1))
node _T_620 = and(_T_619, d_release_ack_1)
when _T_620 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_621 = and(io.in.d.ready, io.in.d.valid)
node _T_622 = and(_T_621, d_first_2)
node _T_623 = and(_T_622, UInt<1>(0h1))
node _T_624 = and(_T_623, d_release_ack_1)
when _T_624 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_625 = and(io.in.d.valid, d_first_2)
node _T_626 = and(_T_625, UInt<1>(0h1))
node _T_627 = and(_T_626, d_release_ack_1)
when _T_627 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_628 = dshr(inflight_1, io.in.d.bits.source)
node _T_629 = bits(_T_628, 0, 0)
node _T_630 = or(_T_629, same_cycle_resp_1)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_630, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_634, UInt<1>(0h1), "") : assert_108
else :
node _T_638 = eq(io.in.d.bits.size, c_size_lookup)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_638, UInt<1>(0h1), "") : assert_109
node _T_642 = and(io.in.d.valid, d_first_2)
node _T_643 = and(_T_642, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_644 = and(_T_643, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_646 = and(_T_644, _T_645)
node _T_647 = and(_T_646, d_release_ack_1)
node _T_648 = eq(c_probe_ack, UInt<1>(0h0))
node _T_649 = and(_T_647, _T_648)
when _T_649 :
node _T_650 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_651 = or(_T_650, _WIRE_23.ready)
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_651, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_91
node _T_655 = orr(inflight_1)
node _T_656 = eq(_T_655, UInt<1>(0h0))
node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_658 = or(_T_656, _T_657)
node _T_659 = lt(watchdog_1, plusarg_reader_1.out)
node _T_660 = or(_T_658, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_660, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_665 = and(io.in.d.ready, io.in.d.valid)
node _T_666 = or(_T_664, _T_665)
when _T_666 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_598; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain :
output auto : { flip plic_int_in : UInt<1>[1], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst plic of TLPLIC
connect plic.clock, childClock
connect plic.reset, childReset
inst intsource of IntSyncCrossingSource_n1x1_3
connect intsource.clock, childClock
connect intsource.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
wire intInClockXingOut : { sync : UInt<1>[1]}
invalidate intInClockXingOut.sync[0]
wire intInClockXingIn : { sync : UInt<1>[1]}
invalidate intInClockXingIn.sync[0]
connect intInClockXingOut, intInClockXingIn
connect intsource.auto.in[0], plic.auto.int_out[0]
connect intInClockXingIn, intsource.auto.out
connect clockNodeIn, auto.clock_in
connect auto.int_in_clock_xing_out, intInClockXingOut
connect plic.auto.in, auto.plic_in
connect plic.auto.int_in[0], auto.plic_int_in[0]
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset
extmodule plusarg_reader_64 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_65 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module PLICClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _plic_auto_int_out_0; // @[Plic.scala:367:46]
wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
TLPLIC plic ( // @[Plic.scala:367:46]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9]
.auto_int_out_0 (_plic_auto_int_out_0),
.auto_in_a_ready (auto_plic_in_a_ready_0),
.auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_plic_in_d_valid_0),
.auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0),
.auto_in_d_bits_size (auto_plic_in_d_bits_size_0),
.auto_in_d_bits_source (auto_plic_in_d_bits_source_0),
.auto_in_d_bits_data (auto_plic_in_d_bits_data_0)
); // @[Plic.scala:367:46]
IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (_plic_auto_int_out_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (intInClockXingIn_sync_0)
); // @[Crossing.scala:29:31]
assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_0 = auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module HellaFlowQueue_1 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<7>}
wire do_flow : UInt<1>
node _do_enq_T = and(io.enq.ready, io.enq.valid)
node _do_enq_T_1 = eq(do_flow, UInt<1>(0h0))
node do_enq = and(_do_enq_T, _do_enq_T_1)
node _do_deq_T = and(io.deq.ready, io.deq.valid)
node _do_deq_T_1 = eq(do_flow, UInt<1>(0h0))
node do_deq = and(_do_deq_T, _do_deq_T_1)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enq_ptr : UInt<6>, clock, reset, UInt<6>(0h0)
wire enq_ptr_wrap : UInt<1>
connect enq_ptr_wrap, UInt<1>(0h0)
when do_enq :
node enq_ptr_wrap_wrap = eq(enq_ptr, UInt<6>(0h3f))
node _enq_ptr_wrap_value_T = add(enq_ptr, UInt<1>(0h1))
node _enq_ptr_wrap_value_T_1 = tail(_enq_ptr_wrap_value_T, 1)
connect enq_ptr, _enq_ptr_wrap_value_T_1
connect enq_ptr_wrap, enq_ptr_wrap_wrap
regreset deq_ptr : UInt<6>, clock, reset, UInt<6>(0h0)
wire deq_done : UInt<1>
connect deq_done, UInt<1>(0h0)
when do_deq :
node wrap_wrap = eq(deq_ptr, UInt<6>(0h3f))
node _wrap_value_T = add(deq_ptr, UInt<1>(0h1))
node _wrap_value_T_1 = tail(_wrap_value_T, 1)
connect deq_ptr, _wrap_value_T_1
connect deq_done, wrap_wrap
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node ptr_match = eq(enq_ptr, deq_ptr)
node _empty_T = eq(maybe_full, UInt<1>(0h0))
node empty = and(ptr_match, _empty_T)
node full = and(ptr_match, maybe_full)
node _atLeastTwo_T = sub(enq_ptr, deq_ptr)
node _atLeastTwo_T_1 = tail(_atLeastTwo_T, 1)
node _atLeastTwo_T_2 = geq(_atLeastTwo_T_1, UInt<2>(0h2))
node atLeastTwo = or(full, _atLeastTwo_T_2)
node _do_flow_T = and(empty, io.deq.ready)
connect do_flow, _do_flow_T
smem ram : UInt<64> [64]
when do_enq :
write mport MPORT = ram[enq_ptr], clock
connect MPORT, io.enq.bits
node _ren_T = eq(io.deq.valid, UInt<1>(0h0))
node _ren_T_1 = eq(empty, UInt<1>(0h0))
node _ren_T_2 = and(_ren_T, _ren_T_1)
node _ren_T_3 = or(atLeastTwo, _ren_T_2)
node ren = and(io.deq.ready, _ren_T_3)
node _raddr_T = add(deq_ptr, UInt<1>(0h1))
node _raddr_T_1 = tail(_raddr_T, 1)
node _raddr_T_2 = mux(deq_done, UInt<1>(0h0), _raddr_T_1)
node raddr = mux(io.deq.valid, _raddr_T_2, deq_ptr)
reg ram_out_valid : UInt<1>, clock
connect ram_out_valid, ren
node _io_deq_valid_T = mux(empty, io.enq.valid, ram_out_valid)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire _io_deq_bits_WIRE : UInt<6>
invalidate _io_deq_bits_WIRE
when ren :
connect _io_deq_bits_WIRE, raddr
read mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock
node _io_deq_bits_T = mux(empty, io.enq.bits, io_deq_bits_MPORT)
connect io.deq.bits, _io_deq_bits_T
invalidate io.count | module HellaFlowQueue_1( // @[HellaQueue.scala:8:7]
input clock, // @[HellaQueue.scala:8:7]
input reset, // @[HellaQueue.scala:8:7]
output io_enq_ready, // @[HellaQueue.scala:9:14]
input io_enq_valid, // @[HellaQueue.scala:9:14]
input [63:0] io_enq_bits, // @[HellaQueue.scala:9:14]
input io_deq_ready, // @[HellaQueue.scala:9:14]
output io_deq_valid, // @[HellaQueue.scala:9:14]
output [63:0] io_deq_bits // @[HellaQueue.scala:9:14]
);
wire [63:0] _ram_R0_data; // @[HellaQueue.scala:27:24]
wire io_enq_valid_0 = io_enq_valid; // @[HellaQueue.scala:8:7]
wire [63:0] io_enq_bits_0 = io_enq_bits; // @[HellaQueue.scala:8:7]
wire io_deq_ready_0 = io_deq_ready; // @[HellaQueue.scala:8:7]
wire [6:0] io_count = 7'h0; // @[HellaQueue.scala:8:7]
wire _io_enq_ready_T; // @[HellaQueue.scala:37:19]
wire _io_deq_valid_T; // @[HellaQueue.scala:36:22]
wire [63:0] _io_deq_bits_T; // @[HellaQueue.scala:38:21]
wire io_enq_ready_0; // @[HellaQueue.scala:8:7]
wire io_deq_valid_0; // @[HellaQueue.scala:8:7]
wire [63:0] io_deq_bits_0; // @[HellaQueue.scala:8:7]
wire _do_flow_T; // @[HellaQueue.scala:25:20]
wire do_flow; // @[HellaQueue.scala:12:21]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _do_enq_T_1 = ~do_flow; // @[HellaQueue.scala:12:21, :13:31]
wire do_enq = _do_enq_T & _do_enq_T_1; // @[Decoupled.scala:51:35]
wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire _do_deq_T_1 = ~do_flow; // @[HellaQueue.scala:12:21, :13:31, :14:31]
wire do_deq = _do_deq_T & _do_deq_T_1; // @[Decoupled.scala:51:35]
reg maybe_full; // @[HellaQueue.scala:16:27]
reg [5:0] enq_ptr; // @[Counter.scala:61:40]
wire enq_ptr_wrap; // @[Counter.scala:117:24]
wire enq_ptr_wrap_wrap = &enq_ptr; // @[Counter.scala:61:40, :73:24]
wire [6:0] _GEN = {1'h0, enq_ptr}; // @[Counter.scala:61:40, :77:24]
wire [6:0] _enq_ptr_wrap_value_T = _GEN + 7'h1; // @[Counter.scala:77:24]
wire [5:0] _enq_ptr_wrap_value_T_1 = _enq_ptr_wrap_value_T[5:0]; // @[Counter.scala:77:24]
assign enq_ptr_wrap = do_enq & enq_ptr_wrap_wrap; // @[Counter.scala:73:24, :117:24, :118:{16,23}]
reg [5:0] deq_ptr; // @[Counter.scala:61:40]
wire deq_done; // @[Counter.scala:117:24]
wire wrap_wrap = &deq_ptr; // @[Counter.scala:61:40, :73:24]
wire [6:0] _GEN_0 = {1'h0, deq_ptr}; // @[Counter.scala:61:40, :77:24]
wire [6:0] _GEN_1 = _GEN_0 + 7'h1; // @[Counter.scala:77:24]
wire [6:0] _wrap_value_T; // @[Counter.scala:77:24]
assign _wrap_value_T = _GEN_1; // @[Counter.scala:77:24]
wire [6:0] _raddr_T; // @[HellaQueue.scala:33:60]
assign _raddr_T = _GEN_1; // @[Counter.scala:77:24]
wire [5:0] _wrap_value_T_1 = _wrap_value_T[5:0]; // @[Counter.scala:77:24]
assign deq_done = do_deq & wrap_wrap; // @[Counter.scala:73:24, :117:24, :118:{16,23}]
wire ptr_match = enq_ptr == deq_ptr; // @[Counter.scala:61:40]
wire _empty_T = ~maybe_full; // @[HellaQueue.scala:16:27, :22:28]
wire empty = ptr_match & _empty_T; // @[HellaQueue.scala:21:27, :22:{25,28}]
wire full = ptr_match & maybe_full; // @[HellaQueue.scala:16:27, :21:27, :23:24]
wire [6:0] _atLeastTwo_T = _GEN - _GEN_0; // @[Counter.scala:77:24]
wire [5:0] _atLeastTwo_T_1 = _atLeastTwo_T[5:0]; // @[HellaQueue.scala:24:36]
wire _atLeastTwo_T_2 = |(_atLeastTwo_T_1[5:1]); // @[HellaQueue.scala:24:{36,46}]
wire atLeastTwo = full | _atLeastTwo_T_2; // @[HellaQueue.scala:23:24, :24:{25,46}]
assign _do_flow_T = empty & io_deq_ready_0; // @[HellaQueue.scala:8:7, :22:25, :25:20]
assign do_flow = _do_flow_T; // @[HellaQueue.scala:12:21, :25:20]
wire _ren_T = ~io_deq_valid_0; // @[HellaQueue.scala:8:7, :32:44]
wire _ren_T_1 = ~empty; // @[HellaQueue.scala:22:25, :32:61]
wire _ren_T_2 = _ren_T & _ren_T_1; // @[HellaQueue.scala:32:{44,58,61}]
wire _ren_T_3 = atLeastTwo | _ren_T_2; // @[HellaQueue.scala:24:25, :32:{41,58}]
wire ren = io_deq_ready_0 & _ren_T_3; // @[HellaQueue.scala:8:7, :32:{26,41}]
wire [5:0] _raddr_T_1 = _raddr_T[5:0]; // @[HellaQueue.scala:33:60]
wire [5:0] _raddr_T_2 = deq_done ? 6'h0 : _raddr_T_1; // @[Counter.scala:117:24]
wire [5:0] raddr = io_deq_valid_0 ? _raddr_T_2 : deq_ptr; // @[Counter.scala:61:40]
wire [5:0] _io_deq_bits_WIRE = raddr; // @[HellaQueue.scala:33:18, :38:50]
reg ram_out_valid; // @[HellaQueue.scala:34:30]
assign _io_deq_valid_T = empty ? io_enq_valid_0 : ram_out_valid; // @[HellaQueue.scala:8:7, :22:25, :34:30, :36:22]
assign io_deq_valid_0 = _io_deq_valid_T; // @[HellaQueue.scala:8:7, :36:22]
assign _io_enq_ready_T = ~full; // @[HellaQueue.scala:23:24, :37:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[HellaQueue.scala:8:7, :37:19]
assign _io_deq_bits_T = empty ? io_enq_bits_0 : _ram_R0_data; // @[HellaQueue.scala:8:7, :22:25, :27:24, :38:21]
assign io_deq_bits_0 = _io_deq_bits_T; // @[HellaQueue.scala:8:7, :38:21]
always @(posedge clock) begin // @[HellaQueue.scala:8:7]
if (reset) begin // @[HellaQueue.scala:8:7]
maybe_full <= 1'h0; // @[HellaQueue.scala:16:27]
enq_ptr <= 6'h0; // @[Counter.scala:61:40]
deq_ptr <= 6'h0; // @[Counter.scala:61:40]
end
else begin // @[HellaQueue.scala:8:7]
if (~(do_enq == do_deq)) // @[HellaQueue.scala:13:28, :14:28, :16:27, :19:{16,28,41}]
maybe_full <= do_enq; // @[HellaQueue.scala:13:28, :16:27]
if (do_enq) // @[HellaQueue.scala:13:28]
enq_ptr <= _enq_ptr_wrap_value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[HellaQueue.scala:14:28]
deq_ptr <= _wrap_value_T_1; // @[Counter.scala:61:40, :77:24]
end
ram_out_valid <= ren; // @[HellaQueue.scala:32:26, :34:30]
always @(posedge)
ram_0 ram ( // @[HellaQueue.scala:27:24]
.R0_addr (_io_deq_bits_WIRE), // @[HellaQueue.scala:38:50]
.R0_en (ren), // @[HellaQueue.scala:32:26]
.R0_clk (clock),
.R0_data (_ram_R0_data),
.W0_addr (enq_ptr), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[HellaQueue.scala:13:28]
.W0_clk (clock),
.W0_data (io_enq_bits_0) // @[HellaQueue.scala:8:7]
); // @[HellaQueue.scala:27:24]
assign io_enq_ready = io_enq_ready_0; // @[HellaQueue.scala:8:7]
assign io_deq_valid = io_deq_valid_0; // @[HellaQueue.scala:8:7]
assign io_deq_bits = io_deq_bits_0; // @[HellaQueue.scala:8:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_104
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_105
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_106 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_107 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_52( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_898; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_115 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_136
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_115( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_136 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_11 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}}
inst input_buffer of InputBuffer_11
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter6_RouteComputerReq_11
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<6>}[6], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id)
when _T_10 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_11 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_12 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_13 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_13 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_14 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_14 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_15 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_15 :
connect states[5].g, UInt<3>(0h2)
node _T_16 = and(io.router_req.ready, io.router_req.valid)
when _T_16 :
node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<6>, clock, reset, UInt<6>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}[6]
wire vcalloc_vals : UInt<1>[6]
node vcalloc_filter_lo_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_vals[0])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[3])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_vals[0])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[3])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_16, UInt<12>(0h800), UInt<12>(0h0))
node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_15, UInt<12>(0h400), _vcalloc_filter_T_17)
node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_14, UInt<12>(0h200), _vcalloc_filter_T_18)
node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_13, UInt<12>(0h100), _vcalloc_filter_T_19)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_12, UInt<12>(0h80), _vcalloc_filter_T_20)
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_11, UInt<12>(0h40), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_10, UInt<12>(0h20), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_9, UInt<12>(0h10), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_8, UInt<12>(0h8), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_7, UInt<12>(0h4), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_6, UInt<12>(0h2), _vcalloc_filter_T_26)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<12>(0h1), _vcalloc_filter_T_27)
node _vcalloc_sel_T = bits(vcalloc_filter, 5, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 6)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_27 = and(io.router_req.ready, io.router_req.valid)
when _T_27 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_28 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_29 = or(_T_28, vcalloc_vals[2])
node _T_30 = or(_T_29, vcalloc_vals[3])
node _T_31 = or(_T_30, vcalloc_vals[4])
node _T_32 = or(_T_31, vcalloc_vals[5])
when _T_32 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = bits(vcalloc_sel, 0, 0)
node _mask_T_10 = bits(vcalloc_sel, 1, 1)
node _mask_T_11 = bits(vcalloc_sel, 2, 2)
node _mask_T_12 = bits(vcalloc_sel, 3, 3)
node _mask_T_13 = bits(vcalloc_sel, 4, 4)
node _mask_T_14 = bits(vcalloc_sel, 5, 5)
node _mask_T_15 = mux(_mask_T_9, _mask_T_3, UInt<1>(0h0))
node _mask_T_16 = mux(_mask_T_10, _mask_T_4, UInt<1>(0h0))
node _mask_T_17 = mux(_mask_T_11, _mask_T_5, UInt<1>(0h0))
node _mask_T_18 = mux(_mask_T_12, _mask_T_6, UInt<1>(0h0))
node _mask_T_19 = mux(_mask_T_13, _mask_T_7, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_14, _mask_T_8, UInt<1>(0h0))
node _mask_T_21 = or(_mask_T_15, _mask_T_16)
node _mask_T_22 = or(_mask_T_21, _mask_T_17)
node _mask_T_23 = or(_mask_T_22, _mask_T_18)
node _mask_T_24 = or(_mask_T_23, _mask_T_19)
node _mask_T_25 = or(_mask_T_24, _mask_T_20)
wire _mask_WIRE : UInt<6>
connect _mask_WIRE, _mask_T_25
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_4
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[6]
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_7)
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_8)
node _io_vcalloc_req_bits_T_14 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_11)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_16
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18)
node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_20)
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_21)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_22)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_30)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_31)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_32)
node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_33)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_38
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_44)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_49
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_52)
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_53)
node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_60
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_62)
node _io_vcalloc_req_bits_T_68 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_63)
node _io_vcalloc_req_bits_T_69 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_70 = or(_io_vcalloc_req_bits_T_69, _io_vcalloc_req_bits_T_65)
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_70, _io_vcalloc_req_bits_T_66)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_71
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>[1]
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_75)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_76)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_77)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_9[0], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_9
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1]
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_90 = or(_io_vcalloc_req_bits_T_89, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_90, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_88)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_93
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_11
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_95)
node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_96)
node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_97)
node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_98)
node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_99)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_104
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_13
wire _io_vcalloc_req_bits_WIRE_14 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_107)
node _io_vcalloc_req_bits_T_113 = or(_io_vcalloc_req_bits_T_112, _io_vcalloc_req_bits_T_108)
node _io_vcalloc_req_bits_T_114 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_109)
node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_114, _io_vcalloc_req_bits_T_110)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_115
connect _io_vcalloc_req_bits_WIRE_14.egress_node_id, _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_120)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_121)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_126
connect _io_vcalloc_req_bits_WIRE_14.egress_node, _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_128)
node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_133, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_132)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_137
connect _io_vcalloc_req_bits_WIRE_14.ingress_node_id, _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_138 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_139 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_139)
node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_144, _io_vcalloc_req_bits_T_140)
node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_141)
node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_142)
node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_143)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_148
connect _io_vcalloc_req_bits_WIRE_14.ingress_node, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_154 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_151)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_152)
node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_153)
node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_154)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_159
connect _io_vcalloc_req_bits_WIRE_14.vnet_id, _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_14
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_33 = bits(vcalloc_sel, 1, 1)
node _T_34 = and(vcalloc_vals[1], _T_33)
node _T_35 = and(_T_34, io.vcalloc_req.ready)
when _T_35 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_36 = bits(vcalloc_sel, 2, 2)
node _T_37 = and(vcalloc_vals[2], _T_36)
node _T_38 = and(_T_37, io.vcalloc_req.ready)
when _T_38 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_39 = bits(vcalloc_sel, 3, 3)
node _T_40 = and(vcalloc_vals[3], _T_39)
node _T_41 = and(_T_40, io.vcalloc_req.ready)
when _T_41 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_42 = bits(vcalloc_sel, 4, 4)
node _T_43 = and(vcalloc_vals[4], _T_42)
node _T_44 = and(_T_43, io.vcalloc_req.ready)
when _T_44 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_45 = bits(vcalloc_sel, 5, 5)
node _T_46 = and(vcalloc_vals[5], _T_45)
node _T_47 = and(_T_46, io.vcalloc_req.ready)
when _T_47 :
connect states[5].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[3], _io_debug_va_stall_T_5)
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(_io_debug_va_stall_T_3, _io_debug_va_stall_T_7)
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 2, 0)
node _io_debug_va_stall_T_10 = sub(_io_debug_va_stall_T_9, io.vcalloc_req.ready)
node _io_debug_va_stall_T_11 = tail(_io_debug_va_stall_T_10, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_11
node _T_48 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_48 :
node _T_49 = bits(vcalloc_sel, 0, 0)
when _T_49 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_50 = eq(states[0].g, UInt<3>(0h2))
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_50, UInt<1>(0h1), "") : assert_3
node _T_54 = bits(vcalloc_sel, 1, 1)
when _T_54 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_55 = eq(states[1].g, UInt<3>(0h2))
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_55, UInt<1>(0h1), "") : assert_4
node _T_59 = bits(vcalloc_sel, 2, 2)
when _T_59 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_60 = eq(states[2].g, UInt<3>(0h2))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_60, UInt<1>(0h1), "") : assert_5
node _T_64 = bits(vcalloc_sel, 3, 3)
when _T_64 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_65 = eq(states[3].g, UInt<3>(0h2))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_65, UInt<1>(0h1), "") : assert_6
node _T_69 = bits(vcalloc_sel, 4, 4)
when _T_69 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_70 = eq(states[4].g, UInt<3>(0h2))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_70, UInt<1>(0h1), "") : assert_7
node _T_74 = bits(vcalloc_sel, 5, 5)
when _T_74 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].g, UInt<3>(0h3)
node _T_75 = eq(states[5].g, UInt<3>(0h2))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_75, UInt<1>(0h1), "") : assert_8
inst salloc_arb of SwitchArbiter_37
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
node credit_available_lo_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1])
node credit_available_lo = cat(credit_available_lo_hi, states[1].vc_sel.`0`[0])
node credit_available_hi_hi = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[3])
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_hi_1 = cat(states[1].vc_sel.`2`[0], states[1].vc_sel.`1`[0])
node _credit_available_T_1 = cat(credit_available_hi_1, _credit_available_T)
node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, io.out_credit_available.`0`[0])
node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_2 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[3])
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_1)
node credit_available_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_79 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_80 = and(_T_79, input_buffer.io.deq[1].bits.tail)
when _T_80 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_hi_2 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, states[2].vc_sel.`0`[0])
node credit_available_hi_hi_2 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_4 = cat(credit_available_hi_hi_2, states[2].vc_sel.`0`[3])
node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_2)
node credit_available_hi_5 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0])
node _credit_available_T_6 = cat(credit_available_hi_5, _credit_available_T_5)
node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, io.out_credit_available.`0`[0])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_6 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[3])
node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_3)
node credit_available_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_8 = cat(credit_available_hi_7, _credit_available_T_7)
node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8)
node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_81 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_82 = and(_T_81, input_buffer.io.deq[2].bits.tail)
when _T_82 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_hi_4 = cat(states[3].vc_sel.`0`[2], states[3].vc_sel.`0`[1])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, states[3].vc_sel.`0`[0])
node credit_available_hi_hi_4 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_8 = cat(credit_available_hi_hi_4, states[3].vc_sel.`0`[3])
node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_4)
node credit_available_hi_9 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0])
node _credit_available_T_11 = cat(credit_available_hi_9, _credit_available_T_10)
node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, io.out_credit_available.`0`[0])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_10 = cat(credit_available_hi_hi_5, io.out_credit_available.`0`[3])
node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_5)
node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_13 = cat(credit_available_hi_11, _credit_available_T_12)
node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13)
node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_83 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_84 = and(_T_83, input_buffer.io.deq[3].bits.tail)
when _T_84 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_hi_6 = cat(states[4].vc_sel.`0`[2], states[4].vc_sel.`0`[1])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, states[4].vc_sel.`0`[0])
node credit_available_hi_hi_6 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_12 = cat(credit_available_hi_hi_6, states[4].vc_sel.`0`[3])
node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_6)
node credit_available_hi_13 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0])
node _credit_available_T_16 = cat(credit_available_hi_13, _credit_available_T_15)
node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, io.out_credit_available.`0`[0])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_14 = cat(credit_available_hi_hi_7, io.out_credit_available.`0`[3])
node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_7)
node credit_available_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_18 = cat(credit_available_hi_15, _credit_available_T_17)
node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18)
node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_85 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_86 = and(_T_85, input_buffer.io.deq[4].bits.tail)
when _T_86 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_hi_8 = cat(states[5].vc_sel.`0`[2], states[5].vc_sel.`0`[1])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, states[5].vc_sel.`0`[0])
node credit_available_hi_hi_8 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_16 = cat(credit_available_hi_hi_8, states[5].vc_sel.`0`[3])
node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_8)
node credit_available_hi_17 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0])
node _credit_available_T_21 = cat(credit_available_hi_17, _credit_available_T_20)
node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, io.out_credit_available.`0`[0])
node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_18 = cat(credit_available_hi_hi_9, io.out_credit_available.`0`[3])
node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_9)
node credit_available_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_23 = cat(credit_available_hi_19, _credit_available_T_22)
node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23)
node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_87 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_88 = and(_T_87, input_buffer.io.deq[5].bits.tail)
when _T_88 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0)
node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_13)
node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_17)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_21
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_8)
node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_9)
node _io_in_vc_free_T_15 = or(_io_in_vc_free_T_14, _io_in_vc_free_T_10)
node _io_in_vc_free_T_16 = or(_io_in_vc_free_T_15, _io_in_vc_free_T_11)
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_16, _io_in_vc_free_T_12)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_17
node _io_in_vc_free_T_18 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_18, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_19
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 5, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _vc_sel_WIRE : UInt<1>[6]
node _vc_sel_T_6 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_7 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_8 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = or(_vc_sel_T_6, _vc_sel_T_7)
node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_8)
node _vc_sel_T_14 = or(_vc_sel_T_13, _vc_sel_T_9)
node _vc_sel_T_15 = or(_vc_sel_T_14, _vc_sel_T_10)
node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_11)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_16
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_22 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_23 = or(_vc_sel_T_17, _vc_sel_T_18)
node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_19)
node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_20)
node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_21)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_22)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_27
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_31 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_32 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_34 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_30)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_31)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_32)
node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_33)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_38
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_39 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_45 = or(_vc_sel_T_39, _vc_sel_T_40)
node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_41)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_42)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_43)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_44)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_49
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_56 = or(_vc_sel_T_50, _vc_sel_T_51)
node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_52)
node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_53)
node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_54)
node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_55)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_60
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_61 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_62 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_63 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_64 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_65 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_66 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_67 = or(_vc_sel_T_61, _vc_sel_T_62)
node _vc_sel_T_68 = or(_vc_sel_T_67, _vc_sel_T_63)
node _vc_sel_T_69 = or(_vc_sel_T_68, _vc_sel_T_64)
node _vc_sel_T_70 = or(_vc_sel_T_69, _vc_sel_T_65)
node _vc_sel_T_71 = or(_vc_sel_T_70, _vc_sel_T_66)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_71
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_7 : UInt<1>[1]
node _vc_sel_T_72 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_76 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_77 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_78 = or(_vc_sel_T_72, _vc_sel_T_73)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_74)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_75)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_76)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_77)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_82
connect _vc_sel_WIRE_7[0], _vc_sel_WIRE_8
connect vc_sel.`1`, _vc_sel_WIRE_7
wire _vc_sel_WIRE_9 : UInt<1>[1]
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_89 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_90 = or(_vc_sel_T_89, _vc_sel_T_85)
node _vc_sel_T_91 = or(_vc_sel_T_90, _vc_sel_T_86)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_87)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_88)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_93
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
connect vc_sel.`2`, _vc_sel_WIRE_9
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node channel_oh_0 = or(_channel_oh_T_3, vc_sel.`0`[5])
node virt_channel_lo_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node virt_channel_lo = cat(virt_channel_lo_hi, vc_sel.`0`[0])
node virt_channel_hi_hi = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[3])
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 5, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_11 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_10)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_12
node _T_89 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_89 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_7)
node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_8)
node _salloc_outs_0_flit_payload_T_14 = or(_salloc_outs_0_flit_payload_T_13, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_15 = or(_salloc_outs_0_flit_payload_T_14, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_15, _salloc_outs_0_flit_payload_T_11)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_16
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_7)
node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_8)
node _salloc_outs_0_flit_head_T_14 = or(_salloc_outs_0_flit_head_T_13, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_15 = or(_salloc_outs_0_flit_head_T_14, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_15, _salloc_outs_0_flit_head_T_11)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_16
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_7)
node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_8)
node _salloc_outs_0_flit_tail_T_14 = or(_salloc_outs_0_flit_tail_T_13, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_15 = or(_salloc_outs_0_flit_tail_T_14, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_15, _salloc_outs_0_flit_tail_T_11)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_16
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_7)
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_8)
node _salloc_outs_0_flit_flow_T_14 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_11)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_16
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_22 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_18)
node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_20)
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_21)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_22)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_30)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_31)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_32)
node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_33)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_38
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_44)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_49
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_51)
node _salloc_outs_0_flit_flow_T_57 = or(_salloc_outs_0_flit_flow_T_56, _salloc_outs_0_flit_flow_T_52)
node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_57, _salloc_outs_0_flit_flow_T_53)
node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_55)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_60
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
node _T_90 = asUInt(reset)
when _T_90 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0) | module InputUnit_11( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [5:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [5:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [5:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [5:0] mask; // @[InputUnit.scala:250:21]
wire [5:0] _vcalloc_filter_T_3 = {vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [11:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 12'h1 : _vcalloc_filter_T_3[1] ? 12'h2 : _vcalloc_filter_T_3[2] ? 12'h4 : _vcalloc_filter_T_3[3] ? 12'h8 : _vcalloc_filter_T_3[4] ? 12'h10 : _vcalloc_filter_T_3[5] ? 12'h20 : vcalloc_vals_1 ? 12'h80 : vcalloc_vals_2 ? 12'h100 : vcalloc_vals_3 ? 12'h200 : vcalloc_vals_4 ? 12'h400 : {vcalloc_vals_5, 11'h0}; // @[OneHot.scala:85:71]
wire [5:0] vcalloc_sel = vcalloc_filter[5:0] | vcalloc_filter[11:6]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_7 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0))
node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0))
node ordered = and(_ordered_T, _ordered_T_1)
node bothInfs = and(rawA.isInf, rawB.isInf)
node bothZeros = and(rawA.isZero, rawB.isZero)
node eqExps = eq(rawA.sExp, rawB.sExp)
node _common_ltMags_T = lt(rawA.sExp, rawB.sExp)
node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig)
node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1)
node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2)
node _common_eqMags_T = eq(rawA.sig, rawB.sig)
node common_eqMags = and(eqExps, _common_eqMags_T)
node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0))
node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1)
node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0))
node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0))
node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4)
node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0))
node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6)
node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags)
node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9)
node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10)
node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11)
node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12)
node _ordered_eq_T = eq(rawA.sign, rawB.sign)
node _ordered_eq_T_1 = or(bothInfs, common_eqMags)
node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1)
node ordered_eq = or(bothZeros, _ordered_eq_T_2)
node _invalid_T = bits(rawA.sig, 22, 22)
node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0))
node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1)
node _invalid_T_3 = bits(rawB.sig, 22, 22)
node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0))
node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4)
node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5)
node _invalid_T_7 = eq(ordered, UInt<1>(0h0))
node _invalid_T_8 = and(io.signaling, _invalid_T_7)
node invalid = or(_invalid_T_6, _invalid_T_8)
node _io_lt_T = and(ordered, ordered_lt)
connect io.lt, _io_lt_T
node _io_eq_T = and(ordered, ordered_eq)
connect io.eq, _io_eq_T
node _io_gt_T = eq(ordered_lt, UInt<1>(0h0))
node _io_gt_T_1 = and(ordered, _io_gt_T)
node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0))
node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2)
connect io.gt, _io_gt_T_3
node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T | module CompareRecFN_7( // @[CompareRecFN.scala:42:7]
input [32:0] io_b, // @[CompareRecFN.scala:44:16]
output io_gt // @[CompareRecFN.scala:44:16]
);
wire [32:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7]
wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _ordered_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _ordered_lt_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _invalid_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire io_signaling = 1'h0; // @[CompareRecFN.scala:42:7]
wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire bothInfs = 1'h0; // @[CompareRecFN.scala:58:33]
wire _ordered_lt_T_2 = 1'h0; // @[CompareRecFN.scala:67:25]
wire _ordered_lt_T_5 = 1'h0; // @[CompareRecFN.scala:69:35]
wire _ordered_lt_T_7 = 1'h0; // @[CompareRecFN.scala:69:54]
wire _invalid_T = 1'h0; // @[common.scala:82:56]
wire _invalid_T_2 = 1'h0; // @[common.scala:82:46]
wire _invalid_T_8 = 1'h0; // @[CompareRecFN.scala:76:27]
wire [32:0] io_a = 33'h15800000; // @[CompareRecFN.scala:42:7, :44:16]
wire _io_lt_T; // @[CompareRecFN.scala:78:22]
wire _io_eq_T; // @[CompareRecFN.scala:79:22]
wire _io_gt_T_3; // @[CompareRecFN.scala:80:38]
wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34]
wire io_lt; // @[CompareRecFN.scala:42:7]
wire io_eq; // @[CompareRecFN.scala:42:7]
wire io_gt_0; // @[CompareRecFN.scala:42:7]
wire [4:0] io_exceptionFlags; // @[CompareRecFN.scala:42:7]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire bothZeros = rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire ordered = _ordered_T_1; // @[CompareRecFN.scala:57:{32,35}]
wire eqExps = rawB_sExp == 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _common_ltMags_T = $signed(rawB_sExp) > 10'sh2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _common_ltMags_T_1 = |rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}]
wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}]
wire _common_eqMags_T = rawB_sig == 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}]
wire _ordered_eq_T_1 = common_eqMags; // @[CompareRecFN.scala:63:32, :72:62]
wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9]
wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38]
wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57]
wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}]
wire _ordered_lt_T_10 = _ordered_lt_T_9; // @[CompareRecFN.scala:69:74, :70:41]
wire _ordered_lt_T_11 = _ordered_lt_T_10; // @[CompareRecFN.scala:68:30, :69:74]
wire _ordered_lt_T_12 = _ordered_lt_T_11; // @[CompareRecFN.scala:67:41, :68:30]
wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41]
wire _ordered_eq_T = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}]
wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}]
wire _invalid_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}]
wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_6 = _invalid_T_5; // @[common.scala:82:46]
wire invalid = _invalid_T_6; // @[CompareRecFN.scala:75:{32,58}]
wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30]
assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22]
assign io_lt = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22]
assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22]
assign io_eq = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22]
wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25]
wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}]
wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41]
assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}]
assign io_gt_0 = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38]
assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34]
assign io_exceptionFlags = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34]
assign io_gt = io_gt_0; // @[CompareRecFN.scala:42:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e11_s53_2 :
output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 63, 52)
node _rawC_isZero_T = bits(rawC_exp, 11, 9)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 11, 10)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 9, 9)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 64, 64)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 51, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 12, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[14]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28)
node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T)
connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1
node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32)
node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T)
connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1
node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36)
node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T)
connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1
node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40)
node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T)
connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1
node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44)
node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T)
connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1
node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48)
node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T)
connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1
node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52)
node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T)
connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1
node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo)
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo)
node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7])
node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10])
node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo)
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0)
node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4)
node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4)
node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0)
node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4)
node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6)
node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0)
node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2)
node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15)
node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2)
node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16)
node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0)
node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2)
node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16)
node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21)
node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22)
node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0)
node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1)
node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25)
node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1)
node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26)
node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0)
node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1)
node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26)
node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31)
node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32)
node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8)
node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0)
node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0)
node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0)
node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1)
node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38)
node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2)
node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0)
node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1)
node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42)
node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43)
node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4)
node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45)
node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46)
node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47)
node reduced4CExtra = orr(_reduced4CExtra_T_48)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 106, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e11_s53_2( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20]
wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}]
wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32]
wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42]
wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34]
wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54]
wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20]
wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22]
wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54]
wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54]
wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57]
wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57]
wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20]
wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20]
wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20]
wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20]
wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11]
wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53]
wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMasterToNoC_7 :
input clock : Clock
input reset : Reset
output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}}
inst a of TLAToNoC_7
connect a.clock, clock
connect a.reset, reset
inst b of TLBFromNoC_7
connect b.clock, clock
connect b.reset, reset
inst c of TLCToNoC_7
connect c.clock, clock
connect c.reset, reset
inst d of TLDFromNoC_7
connect d.clock, clock
connect d.reset, reset
inst e of TLEToNoC_7
connect e.clock, clock
connect e.reset, reset
connect a.io.protocol, io.tilelink.a
connect io.tilelink.b.bits, b.io.protocol.bits
connect io.tilelink.b.valid, b.io.protocol.valid
connect b.io.protocol.ready, io.tilelink.b.ready
connect c.io.protocol, io.tilelink.c
connect io.tilelink.d.bits, d.io.protocol.bits
connect io.tilelink.d.valid, d.io.protocol.valid
connect d.io.protocol.ready, io.tilelink.d.ready
connect e.io.protocol, io.tilelink.e
connect io.flits.a.bits, a.io.flit.bits
connect io.flits.a.valid, a.io.flit.valid
connect a.io.flit.ready, io.flits.a.ready
connect b.io.flit, io.flits.b
connect io.flits.c.bits, c.io.flit.bits
connect io.flits.c.valid, c.io.flit.valid
connect c.io.flit.ready, io.flits.c.ready
connect d.io.flit, io.flits.d
connect io.flits.e.bits, e.io.flit.bits
connect io.flits.e.valid, e.io.flit.valid
connect e.io.flit.ready, io.flits.e.ready | module TLMasterToNoC_7( // @[Tilelink.scala:37:7]
input clock, // @[Tilelink.scala:37:7]
input reset, // @[Tilelink.scala:37:7]
output io_tilelink_a_ready, // @[Tilelink.scala:44:14]
input io_tilelink_a_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14]
input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_b_ready, // @[Tilelink.scala:44:14]
output io_tilelink_b_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14]
output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14]
output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_c_ready, // @[Tilelink.scala:44:14]
input io_tilelink_c_valid, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14]
input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14]
input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14]
input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14]
input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14]
input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14]
input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14]
input io_tilelink_d_ready, // @[Tilelink.scala:44:14]
output io_tilelink_d_valid, // @[Tilelink.scala:44:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14]
output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14]
output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14]
output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14]
output io_tilelink_e_ready, // @[Tilelink.scala:44:14]
input io_tilelink_e_valid, // @[Tilelink.scala:44:14]
input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14]
input io_flits_a_ready, // @[Tilelink.scala:44:14]
output io_flits_a_valid, // @[Tilelink.scala:44:14]
output io_flits_a_bits_head, // @[Tilelink.scala:44:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_b_ready, // @[Tilelink.scala:44:14]
input io_flits_b_valid, // @[Tilelink.scala:44:14]
input io_flits_b_bits_head, // @[Tilelink.scala:44:14]
input io_flits_b_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_c_ready, // @[Tilelink.scala:44:14]
output io_flits_c_valid, // @[Tilelink.scala:44:14]
output io_flits_c_bits_head, // @[Tilelink.scala:44:14]
output io_flits_c_bits_tail, // @[Tilelink.scala:44:14]
output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14]
output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14]
output io_flits_d_ready, // @[Tilelink.scala:44:14]
input io_flits_d_valid, // @[Tilelink.scala:44:14]
input io_flits_d_bits_head, // @[Tilelink.scala:44:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:44:14]
input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14]
input io_flits_e_ready, // @[Tilelink.scala:44:14]
output io_flits_e_valid, // @[Tilelink.scala:44:14]
output io_flits_e_bits_head, // @[Tilelink.scala:44:14]
output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14]
output [5:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14]
);
wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17]
wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17]
TLAToNoC_7 a ( // @[Tilelink.scala:54:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:54:17]
TLBFromNoC_1 b ( // @[Tilelink.scala:55:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_b_ready),
.io_protocol_valid (io_tilelink_b_valid),
.io_protocol_bits_opcode (io_tilelink_b_bits_opcode),
.io_protocol_bits_param (io_tilelink_b_bits_param),
.io_protocol_bits_size (io_tilelink_b_bits_size),
.io_protocol_bits_source (io_tilelink_b_bits_source),
.io_protocol_bits_address (io_tilelink_b_bits_address),
.io_protocol_bits_mask (io_tilelink_b_bits_mask),
.io_protocol_bits_data (io_tilelink_b_bits_data),
.io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt),
.io_flit_ready (io_flits_b_ready),
.io_flit_valid (io_flits_b_valid),
.io_flit_bits_head (io_flits_b_bits_head),
.io_flit_bits_tail (io_flits_b_bits_tail),
.io_flit_bits_payload (io_flits_b_bits_payload)
); // @[Tilelink.scala:55:17]
TLCToNoC_7 c ( // @[Tilelink.scala:56:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (_c_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_c_bits_egress_id)
); // @[Tilelink.scala:56:17]
TLDFromNoC_1 d ( // @[Tilelink.scala:57:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14]
); // @[Tilelink.scala:57:17]
TLEToNoC e ( // @[Tilelink.scala:58:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_e_ready),
.io_protocol_valid (io_tilelink_e_valid),
.io_protocol_bits_sink (io_tilelink_e_bits_sink),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_payload (_e_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_e_bits_egress_id)
); // @[Tilelink.scala:58:17]
assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14]
assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_64 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_64( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_12 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_12( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module FAMicroBTBBranchPredictorBank :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 3)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 3)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
wire s1_meta : { hits : UInt<1>[4], write_way : UInt<4>}
node lo = cat(s1_meta.hits[1], s1_meta.hits[0])
node hi = cat(s1_meta.hits[3], s1_meta.hits[2])
node _T = cat(hi, lo)
node _T_1 = cat(_T, s1_meta.write_way)
wire _meta_WIRE : { is_br : UInt<1>, tag : UInt<37>, ctr : UInt<2>}[4][16]
connect _meta_WIRE[0][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[0][0].tag, UInt<37>(0h0)
connect _meta_WIRE[0][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[0][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[0][1].tag, UInt<37>(0h0)
connect _meta_WIRE[0][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[0][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[0][2].tag, UInt<37>(0h0)
connect _meta_WIRE[0][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[0][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[0][3].tag, UInt<37>(0h0)
connect _meta_WIRE[0][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[1][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[1][0].tag, UInt<37>(0h0)
connect _meta_WIRE[1][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[1][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[1][1].tag, UInt<37>(0h0)
connect _meta_WIRE[1][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[1][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[1][2].tag, UInt<37>(0h0)
connect _meta_WIRE[1][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[1][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[1][3].tag, UInt<37>(0h0)
connect _meta_WIRE[1][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[2][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[2][0].tag, UInt<37>(0h0)
connect _meta_WIRE[2][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[2][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[2][1].tag, UInt<37>(0h0)
connect _meta_WIRE[2][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[2][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[2][2].tag, UInt<37>(0h0)
connect _meta_WIRE[2][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[2][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[2][3].tag, UInt<37>(0h0)
connect _meta_WIRE[2][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[3][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[3][0].tag, UInt<37>(0h0)
connect _meta_WIRE[3][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[3][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[3][1].tag, UInt<37>(0h0)
connect _meta_WIRE[3][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[3][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[3][2].tag, UInt<37>(0h0)
connect _meta_WIRE[3][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[3][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[3][3].tag, UInt<37>(0h0)
connect _meta_WIRE[3][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[4][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[4][0].tag, UInt<37>(0h0)
connect _meta_WIRE[4][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[4][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[4][1].tag, UInt<37>(0h0)
connect _meta_WIRE[4][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[4][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[4][2].tag, UInt<37>(0h0)
connect _meta_WIRE[4][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[4][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[4][3].tag, UInt<37>(0h0)
connect _meta_WIRE[4][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[5][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[5][0].tag, UInt<37>(0h0)
connect _meta_WIRE[5][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[5][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[5][1].tag, UInt<37>(0h0)
connect _meta_WIRE[5][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[5][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[5][2].tag, UInt<37>(0h0)
connect _meta_WIRE[5][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[5][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[5][3].tag, UInt<37>(0h0)
connect _meta_WIRE[5][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[6][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[6][0].tag, UInt<37>(0h0)
connect _meta_WIRE[6][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[6][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[6][1].tag, UInt<37>(0h0)
connect _meta_WIRE[6][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[6][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[6][2].tag, UInt<37>(0h0)
connect _meta_WIRE[6][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[6][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[6][3].tag, UInt<37>(0h0)
connect _meta_WIRE[6][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[7][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[7][0].tag, UInt<37>(0h0)
connect _meta_WIRE[7][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[7][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[7][1].tag, UInt<37>(0h0)
connect _meta_WIRE[7][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[7][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[7][2].tag, UInt<37>(0h0)
connect _meta_WIRE[7][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[7][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[7][3].tag, UInt<37>(0h0)
connect _meta_WIRE[7][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[8][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[8][0].tag, UInt<37>(0h0)
connect _meta_WIRE[8][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[8][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[8][1].tag, UInt<37>(0h0)
connect _meta_WIRE[8][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[8][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[8][2].tag, UInt<37>(0h0)
connect _meta_WIRE[8][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[8][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[8][3].tag, UInt<37>(0h0)
connect _meta_WIRE[8][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[9][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[9][0].tag, UInt<37>(0h0)
connect _meta_WIRE[9][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[9][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[9][1].tag, UInt<37>(0h0)
connect _meta_WIRE[9][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[9][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[9][2].tag, UInt<37>(0h0)
connect _meta_WIRE[9][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[9][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[9][3].tag, UInt<37>(0h0)
connect _meta_WIRE[9][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[10][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[10][0].tag, UInt<37>(0h0)
connect _meta_WIRE[10][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[10][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[10][1].tag, UInt<37>(0h0)
connect _meta_WIRE[10][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[10][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[10][2].tag, UInt<37>(0h0)
connect _meta_WIRE[10][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[10][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[10][3].tag, UInt<37>(0h0)
connect _meta_WIRE[10][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[11][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[11][0].tag, UInt<37>(0h0)
connect _meta_WIRE[11][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[11][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[11][1].tag, UInt<37>(0h0)
connect _meta_WIRE[11][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[11][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[11][2].tag, UInt<37>(0h0)
connect _meta_WIRE[11][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[11][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[11][3].tag, UInt<37>(0h0)
connect _meta_WIRE[11][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[12][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[12][0].tag, UInt<37>(0h0)
connect _meta_WIRE[12][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[12][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[12][1].tag, UInt<37>(0h0)
connect _meta_WIRE[12][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[12][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[12][2].tag, UInt<37>(0h0)
connect _meta_WIRE[12][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[12][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[12][3].tag, UInt<37>(0h0)
connect _meta_WIRE[12][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[13][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[13][0].tag, UInt<37>(0h0)
connect _meta_WIRE[13][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[13][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[13][1].tag, UInt<37>(0h0)
connect _meta_WIRE[13][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[13][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[13][2].tag, UInt<37>(0h0)
connect _meta_WIRE[13][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[13][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[13][3].tag, UInt<37>(0h0)
connect _meta_WIRE[13][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[14][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[14][0].tag, UInt<37>(0h0)
connect _meta_WIRE[14][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[14][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[14][1].tag, UInt<37>(0h0)
connect _meta_WIRE[14][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[14][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[14][2].tag, UInt<37>(0h0)
connect _meta_WIRE[14][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[14][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[14][3].tag, UInt<37>(0h0)
connect _meta_WIRE[14][3].is_br, UInt<1>(0h0)
connect _meta_WIRE[15][0].ctr, UInt<2>(0h0)
connect _meta_WIRE[15][0].tag, UInt<37>(0h0)
connect _meta_WIRE[15][0].is_br, UInt<1>(0h0)
connect _meta_WIRE[15][1].ctr, UInt<2>(0h0)
connect _meta_WIRE[15][1].tag, UInt<37>(0h0)
connect _meta_WIRE[15][1].is_br, UInt<1>(0h0)
connect _meta_WIRE[15][2].ctr, UInt<2>(0h0)
connect _meta_WIRE[15][2].tag, UInt<37>(0h0)
connect _meta_WIRE[15][2].is_br, UInt<1>(0h0)
connect _meta_WIRE[15][3].ctr, UInt<2>(0h0)
connect _meta_WIRE[15][3].tag, UInt<37>(0h0)
connect _meta_WIRE[15][3].is_br, UInt<1>(0h0)
regreset meta : { is_br : UInt<1>, tag : UInt<37>, ctr : UInt<2>}[4][16], clock, reset, _meta_WIRE
reg btb : { offset : SInt<13>}[4][16], clock
wire s1_resp : { valid : UInt<1>, bits : UInt<40>}[4]
wire s1_taken : UInt<1>[4]
wire s1_is_br : UInt<1>[4]
wire s1_is_jal : UInt<1>[4]
node _s1_hit_ohs_T = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_1 = eq(meta[0][0].tag, _s1_hit_ohs_T)
node _s1_hit_ohs_T_2 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_3 = eq(meta[1][0].tag, _s1_hit_ohs_T_2)
node _s1_hit_ohs_T_4 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_5 = eq(meta[2][0].tag, _s1_hit_ohs_T_4)
node _s1_hit_ohs_T_6 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_7 = eq(meta[3][0].tag, _s1_hit_ohs_T_6)
node _s1_hit_ohs_T_8 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_9 = eq(meta[4][0].tag, _s1_hit_ohs_T_8)
node _s1_hit_ohs_T_10 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_11 = eq(meta[5][0].tag, _s1_hit_ohs_T_10)
node _s1_hit_ohs_T_12 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_13 = eq(meta[6][0].tag, _s1_hit_ohs_T_12)
node _s1_hit_ohs_T_14 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_15 = eq(meta[7][0].tag, _s1_hit_ohs_T_14)
node _s1_hit_ohs_T_16 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_17 = eq(meta[8][0].tag, _s1_hit_ohs_T_16)
node _s1_hit_ohs_T_18 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_19 = eq(meta[9][0].tag, _s1_hit_ohs_T_18)
node _s1_hit_ohs_T_20 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_21 = eq(meta[10][0].tag, _s1_hit_ohs_T_20)
node _s1_hit_ohs_T_22 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_23 = eq(meta[11][0].tag, _s1_hit_ohs_T_22)
node _s1_hit_ohs_T_24 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_25 = eq(meta[12][0].tag, _s1_hit_ohs_T_24)
node _s1_hit_ohs_T_26 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_27 = eq(meta[13][0].tag, _s1_hit_ohs_T_26)
node _s1_hit_ohs_T_28 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_29 = eq(meta[14][0].tag, _s1_hit_ohs_T_28)
node _s1_hit_ohs_T_30 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_31 = eq(meta[15][0].tag, _s1_hit_ohs_T_30)
wire _s1_hit_ohs_WIRE : UInt<1>[16]
connect _s1_hit_ohs_WIRE[0], _s1_hit_ohs_T_1
connect _s1_hit_ohs_WIRE[1], _s1_hit_ohs_T_3
connect _s1_hit_ohs_WIRE[2], _s1_hit_ohs_T_5
connect _s1_hit_ohs_WIRE[3], _s1_hit_ohs_T_7
connect _s1_hit_ohs_WIRE[4], _s1_hit_ohs_T_9
connect _s1_hit_ohs_WIRE[5], _s1_hit_ohs_T_11
connect _s1_hit_ohs_WIRE[6], _s1_hit_ohs_T_13
connect _s1_hit_ohs_WIRE[7], _s1_hit_ohs_T_15
connect _s1_hit_ohs_WIRE[8], _s1_hit_ohs_T_17
connect _s1_hit_ohs_WIRE[9], _s1_hit_ohs_T_19
connect _s1_hit_ohs_WIRE[10], _s1_hit_ohs_T_21
connect _s1_hit_ohs_WIRE[11], _s1_hit_ohs_T_23
connect _s1_hit_ohs_WIRE[12], _s1_hit_ohs_T_25
connect _s1_hit_ohs_WIRE[13], _s1_hit_ohs_T_27
connect _s1_hit_ohs_WIRE[14], _s1_hit_ohs_T_29
connect _s1_hit_ohs_WIRE[15], _s1_hit_ohs_T_31
node _s1_hit_ohs_T_32 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_33 = eq(meta[0][1].tag, _s1_hit_ohs_T_32)
node _s1_hit_ohs_T_34 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_35 = eq(meta[1][1].tag, _s1_hit_ohs_T_34)
node _s1_hit_ohs_T_36 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_37 = eq(meta[2][1].tag, _s1_hit_ohs_T_36)
node _s1_hit_ohs_T_38 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_39 = eq(meta[3][1].tag, _s1_hit_ohs_T_38)
node _s1_hit_ohs_T_40 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_41 = eq(meta[4][1].tag, _s1_hit_ohs_T_40)
node _s1_hit_ohs_T_42 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_43 = eq(meta[5][1].tag, _s1_hit_ohs_T_42)
node _s1_hit_ohs_T_44 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_45 = eq(meta[6][1].tag, _s1_hit_ohs_T_44)
node _s1_hit_ohs_T_46 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_47 = eq(meta[7][1].tag, _s1_hit_ohs_T_46)
node _s1_hit_ohs_T_48 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_49 = eq(meta[8][1].tag, _s1_hit_ohs_T_48)
node _s1_hit_ohs_T_50 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_51 = eq(meta[9][1].tag, _s1_hit_ohs_T_50)
node _s1_hit_ohs_T_52 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_53 = eq(meta[10][1].tag, _s1_hit_ohs_T_52)
node _s1_hit_ohs_T_54 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_55 = eq(meta[11][1].tag, _s1_hit_ohs_T_54)
node _s1_hit_ohs_T_56 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_57 = eq(meta[12][1].tag, _s1_hit_ohs_T_56)
node _s1_hit_ohs_T_58 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_59 = eq(meta[13][1].tag, _s1_hit_ohs_T_58)
node _s1_hit_ohs_T_60 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_61 = eq(meta[14][1].tag, _s1_hit_ohs_T_60)
node _s1_hit_ohs_T_62 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_63 = eq(meta[15][1].tag, _s1_hit_ohs_T_62)
wire _s1_hit_ohs_WIRE_1 : UInt<1>[16]
connect _s1_hit_ohs_WIRE_1[0], _s1_hit_ohs_T_33
connect _s1_hit_ohs_WIRE_1[1], _s1_hit_ohs_T_35
connect _s1_hit_ohs_WIRE_1[2], _s1_hit_ohs_T_37
connect _s1_hit_ohs_WIRE_1[3], _s1_hit_ohs_T_39
connect _s1_hit_ohs_WIRE_1[4], _s1_hit_ohs_T_41
connect _s1_hit_ohs_WIRE_1[5], _s1_hit_ohs_T_43
connect _s1_hit_ohs_WIRE_1[6], _s1_hit_ohs_T_45
connect _s1_hit_ohs_WIRE_1[7], _s1_hit_ohs_T_47
connect _s1_hit_ohs_WIRE_1[8], _s1_hit_ohs_T_49
connect _s1_hit_ohs_WIRE_1[9], _s1_hit_ohs_T_51
connect _s1_hit_ohs_WIRE_1[10], _s1_hit_ohs_T_53
connect _s1_hit_ohs_WIRE_1[11], _s1_hit_ohs_T_55
connect _s1_hit_ohs_WIRE_1[12], _s1_hit_ohs_T_57
connect _s1_hit_ohs_WIRE_1[13], _s1_hit_ohs_T_59
connect _s1_hit_ohs_WIRE_1[14], _s1_hit_ohs_T_61
connect _s1_hit_ohs_WIRE_1[15], _s1_hit_ohs_T_63
node _s1_hit_ohs_T_64 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_65 = eq(meta[0][2].tag, _s1_hit_ohs_T_64)
node _s1_hit_ohs_T_66 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_67 = eq(meta[1][2].tag, _s1_hit_ohs_T_66)
node _s1_hit_ohs_T_68 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_69 = eq(meta[2][2].tag, _s1_hit_ohs_T_68)
node _s1_hit_ohs_T_70 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_71 = eq(meta[3][2].tag, _s1_hit_ohs_T_70)
node _s1_hit_ohs_T_72 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_73 = eq(meta[4][2].tag, _s1_hit_ohs_T_72)
node _s1_hit_ohs_T_74 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_75 = eq(meta[5][2].tag, _s1_hit_ohs_T_74)
node _s1_hit_ohs_T_76 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_77 = eq(meta[6][2].tag, _s1_hit_ohs_T_76)
node _s1_hit_ohs_T_78 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_79 = eq(meta[7][2].tag, _s1_hit_ohs_T_78)
node _s1_hit_ohs_T_80 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_81 = eq(meta[8][2].tag, _s1_hit_ohs_T_80)
node _s1_hit_ohs_T_82 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_83 = eq(meta[9][2].tag, _s1_hit_ohs_T_82)
node _s1_hit_ohs_T_84 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_85 = eq(meta[10][2].tag, _s1_hit_ohs_T_84)
node _s1_hit_ohs_T_86 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_87 = eq(meta[11][2].tag, _s1_hit_ohs_T_86)
node _s1_hit_ohs_T_88 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_89 = eq(meta[12][2].tag, _s1_hit_ohs_T_88)
node _s1_hit_ohs_T_90 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_91 = eq(meta[13][2].tag, _s1_hit_ohs_T_90)
node _s1_hit_ohs_T_92 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_93 = eq(meta[14][2].tag, _s1_hit_ohs_T_92)
node _s1_hit_ohs_T_94 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_95 = eq(meta[15][2].tag, _s1_hit_ohs_T_94)
wire _s1_hit_ohs_WIRE_2 : UInt<1>[16]
connect _s1_hit_ohs_WIRE_2[0], _s1_hit_ohs_T_65
connect _s1_hit_ohs_WIRE_2[1], _s1_hit_ohs_T_67
connect _s1_hit_ohs_WIRE_2[2], _s1_hit_ohs_T_69
connect _s1_hit_ohs_WIRE_2[3], _s1_hit_ohs_T_71
connect _s1_hit_ohs_WIRE_2[4], _s1_hit_ohs_T_73
connect _s1_hit_ohs_WIRE_2[5], _s1_hit_ohs_T_75
connect _s1_hit_ohs_WIRE_2[6], _s1_hit_ohs_T_77
connect _s1_hit_ohs_WIRE_2[7], _s1_hit_ohs_T_79
connect _s1_hit_ohs_WIRE_2[8], _s1_hit_ohs_T_81
connect _s1_hit_ohs_WIRE_2[9], _s1_hit_ohs_T_83
connect _s1_hit_ohs_WIRE_2[10], _s1_hit_ohs_T_85
connect _s1_hit_ohs_WIRE_2[11], _s1_hit_ohs_T_87
connect _s1_hit_ohs_WIRE_2[12], _s1_hit_ohs_T_89
connect _s1_hit_ohs_WIRE_2[13], _s1_hit_ohs_T_91
connect _s1_hit_ohs_WIRE_2[14], _s1_hit_ohs_T_93
connect _s1_hit_ohs_WIRE_2[15], _s1_hit_ohs_T_95
node _s1_hit_ohs_T_96 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_97 = eq(meta[0][3].tag, _s1_hit_ohs_T_96)
node _s1_hit_ohs_T_98 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_99 = eq(meta[1][3].tag, _s1_hit_ohs_T_98)
node _s1_hit_ohs_T_100 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_101 = eq(meta[2][3].tag, _s1_hit_ohs_T_100)
node _s1_hit_ohs_T_102 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_103 = eq(meta[3][3].tag, _s1_hit_ohs_T_102)
node _s1_hit_ohs_T_104 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_105 = eq(meta[4][3].tag, _s1_hit_ohs_T_104)
node _s1_hit_ohs_T_106 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_107 = eq(meta[5][3].tag, _s1_hit_ohs_T_106)
node _s1_hit_ohs_T_108 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_109 = eq(meta[6][3].tag, _s1_hit_ohs_T_108)
node _s1_hit_ohs_T_110 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_111 = eq(meta[7][3].tag, _s1_hit_ohs_T_110)
node _s1_hit_ohs_T_112 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_113 = eq(meta[8][3].tag, _s1_hit_ohs_T_112)
node _s1_hit_ohs_T_114 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_115 = eq(meta[9][3].tag, _s1_hit_ohs_T_114)
node _s1_hit_ohs_T_116 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_117 = eq(meta[10][3].tag, _s1_hit_ohs_T_116)
node _s1_hit_ohs_T_118 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_119 = eq(meta[11][3].tag, _s1_hit_ohs_T_118)
node _s1_hit_ohs_T_120 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_121 = eq(meta[12][3].tag, _s1_hit_ohs_T_120)
node _s1_hit_ohs_T_122 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_123 = eq(meta[13][3].tag, _s1_hit_ohs_T_122)
node _s1_hit_ohs_T_124 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_125 = eq(meta[14][3].tag, _s1_hit_ohs_T_124)
node _s1_hit_ohs_T_126 = bits(s1_idx, 36, 0)
node _s1_hit_ohs_T_127 = eq(meta[15][3].tag, _s1_hit_ohs_T_126)
wire _s1_hit_ohs_WIRE_3 : UInt<1>[16]
connect _s1_hit_ohs_WIRE_3[0], _s1_hit_ohs_T_97
connect _s1_hit_ohs_WIRE_3[1], _s1_hit_ohs_T_99
connect _s1_hit_ohs_WIRE_3[2], _s1_hit_ohs_T_101
connect _s1_hit_ohs_WIRE_3[3], _s1_hit_ohs_T_103
connect _s1_hit_ohs_WIRE_3[4], _s1_hit_ohs_T_105
connect _s1_hit_ohs_WIRE_3[5], _s1_hit_ohs_T_107
connect _s1_hit_ohs_WIRE_3[6], _s1_hit_ohs_T_109
connect _s1_hit_ohs_WIRE_3[7], _s1_hit_ohs_T_111
connect _s1_hit_ohs_WIRE_3[8], _s1_hit_ohs_T_113
connect _s1_hit_ohs_WIRE_3[9], _s1_hit_ohs_T_115
connect _s1_hit_ohs_WIRE_3[10], _s1_hit_ohs_T_117
connect _s1_hit_ohs_WIRE_3[11], _s1_hit_ohs_T_119
connect _s1_hit_ohs_WIRE_3[12], _s1_hit_ohs_T_121
connect _s1_hit_ohs_WIRE_3[13], _s1_hit_ohs_T_123
connect _s1_hit_ohs_WIRE_3[14], _s1_hit_ohs_T_125
connect _s1_hit_ohs_WIRE_3[15], _s1_hit_ohs_T_127
wire s1_hit_ohs : UInt<1>[16][4]
connect s1_hit_ohs[0], _s1_hit_ohs_WIRE
connect s1_hit_ohs[1], _s1_hit_ohs_WIRE_1
connect s1_hit_ohs[2], _s1_hit_ohs_WIRE_2
connect s1_hit_ohs[3], _s1_hit_ohs_WIRE_3
node _s1_hits_T = or(s1_hit_ohs[0][0], s1_hit_ohs[0][1])
node _s1_hits_T_1 = or(_s1_hits_T, s1_hit_ohs[0][2])
node _s1_hits_T_2 = or(_s1_hits_T_1, s1_hit_ohs[0][3])
node _s1_hits_T_3 = or(_s1_hits_T_2, s1_hit_ohs[0][4])
node _s1_hits_T_4 = or(_s1_hits_T_3, s1_hit_ohs[0][5])
node _s1_hits_T_5 = or(_s1_hits_T_4, s1_hit_ohs[0][6])
node _s1_hits_T_6 = or(_s1_hits_T_5, s1_hit_ohs[0][7])
node _s1_hits_T_7 = or(_s1_hits_T_6, s1_hit_ohs[0][8])
node _s1_hits_T_8 = or(_s1_hits_T_7, s1_hit_ohs[0][9])
node _s1_hits_T_9 = or(_s1_hits_T_8, s1_hit_ohs[0][10])
node _s1_hits_T_10 = or(_s1_hits_T_9, s1_hit_ohs[0][11])
node _s1_hits_T_11 = or(_s1_hits_T_10, s1_hit_ohs[0][12])
node _s1_hits_T_12 = or(_s1_hits_T_11, s1_hit_ohs[0][13])
node _s1_hits_T_13 = or(_s1_hits_T_12, s1_hit_ohs[0][14])
node s1_hits_0 = or(_s1_hits_T_13, s1_hit_ohs[0][15])
node _s1_hits_T_14 = or(s1_hit_ohs[1][0], s1_hit_ohs[1][1])
node _s1_hits_T_15 = or(_s1_hits_T_14, s1_hit_ohs[1][2])
node _s1_hits_T_16 = or(_s1_hits_T_15, s1_hit_ohs[1][3])
node _s1_hits_T_17 = or(_s1_hits_T_16, s1_hit_ohs[1][4])
node _s1_hits_T_18 = or(_s1_hits_T_17, s1_hit_ohs[1][5])
node _s1_hits_T_19 = or(_s1_hits_T_18, s1_hit_ohs[1][6])
node _s1_hits_T_20 = or(_s1_hits_T_19, s1_hit_ohs[1][7])
node _s1_hits_T_21 = or(_s1_hits_T_20, s1_hit_ohs[1][8])
node _s1_hits_T_22 = or(_s1_hits_T_21, s1_hit_ohs[1][9])
node _s1_hits_T_23 = or(_s1_hits_T_22, s1_hit_ohs[1][10])
node _s1_hits_T_24 = or(_s1_hits_T_23, s1_hit_ohs[1][11])
node _s1_hits_T_25 = or(_s1_hits_T_24, s1_hit_ohs[1][12])
node _s1_hits_T_26 = or(_s1_hits_T_25, s1_hit_ohs[1][13])
node _s1_hits_T_27 = or(_s1_hits_T_26, s1_hit_ohs[1][14])
node s1_hits_1 = or(_s1_hits_T_27, s1_hit_ohs[1][15])
node _s1_hits_T_28 = or(s1_hit_ohs[2][0], s1_hit_ohs[2][1])
node _s1_hits_T_29 = or(_s1_hits_T_28, s1_hit_ohs[2][2])
node _s1_hits_T_30 = or(_s1_hits_T_29, s1_hit_ohs[2][3])
node _s1_hits_T_31 = or(_s1_hits_T_30, s1_hit_ohs[2][4])
node _s1_hits_T_32 = or(_s1_hits_T_31, s1_hit_ohs[2][5])
node _s1_hits_T_33 = or(_s1_hits_T_32, s1_hit_ohs[2][6])
node _s1_hits_T_34 = or(_s1_hits_T_33, s1_hit_ohs[2][7])
node _s1_hits_T_35 = or(_s1_hits_T_34, s1_hit_ohs[2][8])
node _s1_hits_T_36 = or(_s1_hits_T_35, s1_hit_ohs[2][9])
node _s1_hits_T_37 = or(_s1_hits_T_36, s1_hit_ohs[2][10])
node _s1_hits_T_38 = or(_s1_hits_T_37, s1_hit_ohs[2][11])
node _s1_hits_T_39 = or(_s1_hits_T_38, s1_hit_ohs[2][12])
node _s1_hits_T_40 = or(_s1_hits_T_39, s1_hit_ohs[2][13])
node _s1_hits_T_41 = or(_s1_hits_T_40, s1_hit_ohs[2][14])
node s1_hits_2 = or(_s1_hits_T_41, s1_hit_ohs[2][15])
node _s1_hits_T_42 = or(s1_hit_ohs[3][0], s1_hit_ohs[3][1])
node _s1_hits_T_43 = or(_s1_hits_T_42, s1_hit_ohs[3][2])
node _s1_hits_T_44 = or(_s1_hits_T_43, s1_hit_ohs[3][3])
node _s1_hits_T_45 = or(_s1_hits_T_44, s1_hit_ohs[3][4])
node _s1_hits_T_46 = or(_s1_hits_T_45, s1_hit_ohs[3][5])
node _s1_hits_T_47 = or(_s1_hits_T_46, s1_hit_ohs[3][6])
node _s1_hits_T_48 = or(_s1_hits_T_47, s1_hit_ohs[3][7])
node _s1_hits_T_49 = or(_s1_hits_T_48, s1_hit_ohs[3][8])
node _s1_hits_T_50 = or(_s1_hits_T_49, s1_hit_ohs[3][9])
node _s1_hits_T_51 = or(_s1_hits_T_50, s1_hit_ohs[3][10])
node _s1_hits_T_52 = or(_s1_hits_T_51, s1_hit_ohs[3][11])
node _s1_hits_T_53 = or(_s1_hits_T_52, s1_hit_ohs[3][12])
node _s1_hits_T_54 = or(_s1_hits_T_53, s1_hit_ohs[3][13])
node _s1_hits_T_55 = or(_s1_hits_T_54, s1_hit_ohs[3][14])
node s1_hits_3 = or(_s1_hits_T_55, s1_hit_ohs[3][15])
node _s1_hit_ways_T = mux(s1_hit_ohs[0][14], UInt<4>(0he), UInt<4>(0hf))
node _s1_hit_ways_T_1 = mux(s1_hit_ohs[0][13], UInt<4>(0hd), _s1_hit_ways_T)
node _s1_hit_ways_T_2 = mux(s1_hit_ohs[0][12], UInt<4>(0hc), _s1_hit_ways_T_1)
node _s1_hit_ways_T_3 = mux(s1_hit_ohs[0][11], UInt<4>(0hb), _s1_hit_ways_T_2)
node _s1_hit_ways_T_4 = mux(s1_hit_ohs[0][10], UInt<4>(0ha), _s1_hit_ways_T_3)
node _s1_hit_ways_T_5 = mux(s1_hit_ohs[0][9], UInt<4>(0h9), _s1_hit_ways_T_4)
node _s1_hit_ways_T_6 = mux(s1_hit_ohs[0][8], UInt<4>(0h8), _s1_hit_ways_T_5)
node _s1_hit_ways_T_7 = mux(s1_hit_ohs[0][7], UInt<3>(0h7), _s1_hit_ways_T_6)
node _s1_hit_ways_T_8 = mux(s1_hit_ohs[0][6], UInt<3>(0h6), _s1_hit_ways_T_7)
node _s1_hit_ways_T_9 = mux(s1_hit_ohs[0][5], UInt<3>(0h5), _s1_hit_ways_T_8)
node _s1_hit_ways_T_10 = mux(s1_hit_ohs[0][4], UInt<3>(0h4), _s1_hit_ways_T_9)
node _s1_hit_ways_T_11 = mux(s1_hit_ohs[0][3], UInt<2>(0h3), _s1_hit_ways_T_10)
node _s1_hit_ways_T_12 = mux(s1_hit_ohs[0][2], UInt<2>(0h2), _s1_hit_ways_T_11)
node _s1_hit_ways_T_13 = mux(s1_hit_ohs[0][1], UInt<1>(0h1), _s1_hit_ways_T_12)
node s1_hit_ways_0 = mux(s1_hit_ohs[0][0], UInt<1>(0h0), _s1_hit_ways_T_13)
node _s1_hit_ways_T_14 = mux(s1_hit_ohs[1][14], UInt<4>(0he), UInt<4>(0hf))
node _s1_hit_ways_T_15 = mux(s1_hit_ohs[1][13], UInt<4>(0hd), _s1_hit_ways_T_14)
node _s1_hit_ways_T_16 = mux(s1_hit_ohs[1][12], UInt<4>(0hc), _s1_hit_ways_T_15)
node _s1_hit_ways_T_17 = mux(s1_hit_ohs[1][11], UInt<4>(0hb), _s1_hit_ways_T_16)
node _s1_hit_ways_T_18 = mux(s1_hit_ohs[1][10], UInt<4>(0ha), _s1_hit_ways_T_17)
node _s1_hit_ways_T_19 = mux(s1_hit_ohs[1][9], UInt<4>(0h9), _s1_hit_ways_T_18)
node _s1_hit_ways_T_20 = mux(s1_hit_ohs[1][8], UInt<4>(0h8), _s1_hit_ways_T_19)
node _s1_hit_ways_T_21 = mux(s1_hit_ohs[1][7], UInt<3>(0h7), _s1_hit_ways_T_20)
node _s1_hit_ways_T_22 = mux(s1_hit_ohs[1][6], UInt<3>(0h6), _s1_hit_ways_T_21)
node _s1_hit_ways_T_23 = mux(s1_hit_ohs[1][5], UInt<3>(0h5), _s1_hit_ways_T_22)
node _s1_hit_ways_T_24 = mux(s1_hit_ohs[1][4], UInt<3>(0h4), _s1_hit_ways_T_23)
node _s1_hit_ways_T_25 = mux(s1_hit_ohs[1][3], UInt<2>(0h3), _s1_hit_ways_T_24)
node _s1_hit_ways_T_26 = mux(s1_hit_ohs[1][2], UInt<2>(0h2), _s1_hit_ways_T_25)
node _s1_hit_ways_T_27 = mux(s1_hit_ohs[1][1], UInt<1>(0h1), _s1_hit_ways_T_26)
node s1_hit_ways_1 = mux(s1_hit_ohs[1][0], UInt<1>(0h0), _s1_hit_ways_T_27)
node _s1_hit_ways_T_28 = mux(s1_hit_ohs[2][14], UInt<4>(0he), UInt<4>(0hf))
node _s1_hit_ways_T_29 = mux(s1_hit_ohs[2][13], UInt<4>(0hd), _s1_hit_ways_T_28)
node _s1_hit_ways_T_30 = mux(s1_hit_ohs[2][12], UInt<4>(0hc), _s1_hit_ways_T_29)
node _s1_hit_ways_T_31 = mux(s1_hit_ohs[2][11], UInt<4>(0hb), _s1_hit_ways_T_30)
node _s1_hit_ways_T_32 = mux(s1_hit_ohs[2][10], UInt<4>(0ha), _s1_hit_ways_T_31)
node _s1_hit_ways_T_33 = mux(s1_hit_ohs[2][9], UInt<4>(0h9), _s1_hit_ways_T_32)
node _s1_hit_ways_T_34 = mux(s1_hit_ohs[2][8], UInt<4>(0h8), _s1_hit_ways_T_33)
node _s1_hit_ways_T_35 = mux(s1_hit_ohs[2][7], UInt<3>(0h7), _s1_hit_ways_T_34)
node _s1_hit_ways_T_36 = mux(s1_hit_ohs[2][6], UInt<3>(0h6), _s1_hit_ways_T_35)
node _s1_hit_ways_T_37 = mux(s1_hit_ohs[2][5], UInt<3>(0h5), _s1_hit_ways_T_36)
node _s1_hit_ways_T_38 = mux(s1_hit_ohs[2][4], UInt<3>(0h4), _s1_hit_ways_T_37)
node _s1_hit_ways_T_39 = mux(s1_hit_ohs[2][3], UInt<2>(0h3), _s1_hit_ways_T_38)
node _s1_hit_ways_T_40 = mux(s1_hit_ohs[2][2], UInt<2>(0h2), _s1_hit_ways_T_39)
node _s1_hit_ways_T_41 = mux(s1_hit_ohs[2][1], UInt<1>(0h1), _s1_hit_ways_T_40)
node s1_hit_ways_2 = mux(s1_hit_ohs[2][0], UInt<1>(0h0), _s1_hit_ways_T_41)
node _s1_hit_ways_T_42 = mux(s1_hit_ohs[3][14], UInt<4>(0he), UInt<4>(0hf))
node _s1_hit_ways_T_43 = mux(s1_hit_ohs[3][13], UInt<4>(0hd), _s1_hit_ways_T_42)
node _s1_hit_ways_T_44 = mux(s1_hit_ohs[3][12], UInt<4>(0hc), _s1_hit_ways_T_43)
node _s1_hit_ways_T_45 = mux(s1_hit_ohs[3][11], UInt<4>(0hb), _s1_hit_ways_T_44)
node _s1_hit_ways_T_46 = mux(s1_hit_ohs[3][10], UInt<4>(0ha), _s1_hit_ways_T_45)
node _s1_hit_ways_T_47 = mux(s1_hit_ohs[3][9], UInt<4>(0h9), _s1_hit_ways_T_46)
node _s1_hit_ways_T_48 = mux(s1_hit_ohs[3][8], UInt<4>(0h8), _s1_hit_ways_T_47)
node _s1_hit_ways_T_49 = mux(s1_hit_ohs[3][7], UInt<3>(0h7), _s1_hit_ways_T_48)
node _s1_hit_ways_T_50 = mux(s1_hit_ohs[3][6], UInt<3>(0h6), _s1_hit_ways_T_49)
node _s1_hit_ways_T_51 = mux(s1_hit_ohs[3][5], UInt<3>(0h5), _s1_hit_ways_T_50)
node _s1_hit_ways_T_52 = mux(s1_hit_ohs[3][4], UInt<3>(0h4), _s1_hit_ways_T_51)
node _s1_hit_ways_T_53 = mux(s1_hit_ohs[3][3], UInt<2>(0h3), _s1_hit_ways_T_52)
node _s1_hit_ways_T_54 = mux(s1_hit_ohs[3][2], UInt<2>(0h2), _s1_hit_ways_T_53)
node _s1_hit_ways_T_55 = mux(s1_hit_ohs[3][1], UInt<1>(0h1), _s1_hit_ways_T_54)
node s1_hit_ways_3 = mux(s1_hit_ohs[3][0], UInt<1>(0h0), _s1_hit_ways_T_55)
node _s1_resp_0_valid_T = and(s1_valid, s1_hits_0)
connect s1_resp[0].valid, _s1_resp_0_valid_T
node _s1_resp_0_bits_T = asSInt(s1_pc)
node _s1_resp_0_bits_T_1 = add(_s1_resp_0_bits_T, asSInt(UInt<1>(0h0)))
node _s1_resp_0_bits_T_2 = tail(_s1_resp_0_bits_T_1, 1)
node _s1_resp_0_bits_T_3 = asSInt(_s1_resp_0_bits_T_2)
node _s1_resp_0_bits_T_4 = add(_s1_resp_0_bits_T_3, btb[s1_hit_ways_0][0].offset)
node _s1_resp_0_bits_T_5 = tail(_s1_resp_0_bits_T_4, 1)
node _s1_resp_0_bits_T_6 = asSInt(_s1_resp_0_bits_T_5)
node _s1_resp_0_bits_T_7 = asUInt(_s1_resp_0_bits_T_6)
connect s1_resp[0].bits, _s1_resp_0_bits_T_7
node _s1_is_br_0_T = and(s1_resp[0].valid, meta[s1_hit_ways_0][0].is_br)
connect s1_is_br[0], _s1_is_br_0_T
node _s1_is_jal_0_T = eq(meta[s1_hit_ways_0][0].is_br, UInt<1>(0h0))
node _s1_is_jal_0_T_1 = and(s1_resp[0].valid, _s1_is_jal_0_T)
connect s1_is_jal[0], _s1_is_jal_0_T_1
node _s1_taken_0_T = eq(meta[s1_hit_ways_0][0].is_br, UInt<1>(0h0))
node _s1_taken_0_T_1 = bits(meta[s1_hit_ways_0][0].ctr, 1, 1)
node _s1_taken_0_T_2 = or(_s1_taken_0_T, _s1_taken_0_T_1)
connect s1_taken[0], _s1_taken_0_T_2
connect s1_meta.hits[0], s1_hits_0
node _s1_resp_1_valid_T = and(s1_valid, s1_hits_1)
connect s1_resp[1].valid, _s1_resp_1_valid_T
node _s1_resp_1_bits_T = asSInt(s1_pc)
node _s1_resp_1_bits_T_1 = add(_s1_resp_1_bits_T, asSInt(UInt<3>(0h2)))
node _s1_resp_1_bits_T_2 = tail(_s1_resp_1_bits_T_1, 1)
node _s1_resp_1_bits_T_3 = asSInt(_s1_resp_1_bits_T_2)
node _s1_resp_1_bits_T_4 = add(_s1_resp_1_bits_T_3, btb[s1_hit_ways_1][1].offset)
node _s1_resp_1_bits_T_5 = tail(_s1_resp_1_bits_T_4, 1)
node _s1_resp_1_bits_T_6 = asSInt(_s1_resp_1_bits_T_5)
node _s1_resp_1_bits_T_7 = asUInt(_s1_resp_1_bits_T_6)
connect s1_resp[1].bits, _s1_resp_1_bits_T_7
node _s1_is_br_1_T = and(s1_resp[1].valid, meta[s1_hit_ways_1][1].is_br)
connect s1_is_br[1], _s1_is_br_1_T
node _s1_is_jal_1_T = eq(meta[s1_hit_ways_1][1].is_br, UInt<1>(0h0))
node _s1_is_jal_1_T_1 = and(s1_resp[1].valid, _s1_is_jal_1_T)
connect s1_is_jal[1], _s1_is_jal_1_T_1
node _s1_taken_1_T = eq(meta[s1_hit_ways_1][1].is_br, UInt<1>(0h0))
node _s1_taken_1_T_1 = bits(meta[s1_hit_ways_1][1].ctr, 1, 1)
node _s1_taken_1_T_2 = or(_s1_taken_1_T, _s1_taken_1_T_1)
connect s1_taken[1], _s1_taken_1_T_2
connect s1_meta.hits[1], s1_hits_1
node _s1_resp_2_valid_T = and(s1_valid, s1_hits_2)
connect s1_resp[2].valid, _s1_resp_2_valid_T
node _s1_resp_2_bits_T = asSInt(s1_pc)
node _s1_resp_2_bits_T_1 = add(_s1_resp_2_bits_T, asSInt(UInt<4>(0h4)))
node _s1_resp_2_bits_T_2 = tail(_s1_resp_2_bits_T_1, 1)
node _s1_resp_2_bits_T_3 = asSInt(_s1_resp_2_bits_T_2)
node _s1_resp_2_bits_T_4 = add(_s1_resp_2_bits_T_3, btb[s1_hit_ways_2][2].offset)
node _s1_resp_2_bits_T_5 = tail(_s1_resp_2_bits_T_4, 1)
node _s1_resp_2_bits_T_6 = asSInt(_s1_resp_2_bits_T_5)
node _s1_resp_2_bits_T_7 = asUInt(_s1_resp_2_bits_T_6)
connect s1_resp[2].bits, _s1_resp_2_bits_T_7
node _s1_is_br_2_T = and(s1_resp[2].valid, meta[s1_hit_ways_2][2].is_br)
connect s1_is_br[2], _s1_is_br_2_T
node _s1_is_jal_2_T = eq(meta[s1_hit_ways_2][2].is_br, UInt<1>(0h0))
node _s1_is_jal_2_T_1 = and(s1_resp[2].valid, _s1_is_jal_2_T)
connect s1_is_jal[2], _s1_is_jal_2_T_1
node _s1_taken_2_T = eq(meta[s1_hit_ways_2][2].is_br, UInt<1>(0h0))
node _s1_taken_2_T_1 = bits(meta[s1_hit_ways_2][2].ctr, 1, 1)
node _s1_taken_2_T_2 = or(_s1_taken_2_T, _s1_taken_2_T_1)
connect s1_taken[2], _s1_taken_2_T_2
connect s1_meta.hits[2], s1_hits_2
node _s1_resp_3_valid_T = and(s1_valid, s1_hits_3)
connect s1_resp[3].valid, _s1_resp_3_valid_T
node _s1_resp_3_bits_T = asSInt(s1_pc)
node _s1_resp_3_bits_T_1 = add(_s1_resp_3_bits_T, asSInt(UInt<4>(0h6)))
node _s1_resp_3_bits_T_2 = tail(_s1_resp_3_bits_T_1, 1)
node _s1_resp_3_bits_T_3 = asSInt(_s1_resp_3_bits_T_2)
node _s1_resp_3_bits_T_4 = add(_s1_resp_3_bits_T_3, btb[s1_hit_ways_3][3].offset)
node _s1_resp_3_bits_T_5 = tail(_s1_resp_3_bits_T_4, 1)
node _s1_resp_3_bits_T_6 = asSInt(_s1_resp_3_bits_T_5)
node _s1_resp_3_bits_T_7 = asUInt(_s1_resp_3_bits_T_6)
connect s1_resp[3].bits, _s1_resp_3_bits_T_7
node _s1_is_br_3_T = and(s1_resp[3].valid, meta[s1_hit_ways_3][3].is_br)
connect s1_is_br[3], _s1_is_br_3_T
node _s1_is_jal_3_T = eq(meta[s1_hit_ways_3][3].is_br, UInt<1>(0h0))
node _s1_is_jal_3_T_1 = and(s1_resp[3].valid, _s1_is_jal_3_T)
connect s1_is_jal[3], _s1_is_jal_3_T_1
node _s1_taken_3_T = eq(meta[s1_hit_ways_3][3].is_br, UInt<1>(0h0))
node _s1_taken_3_T_1 = bits(meta[s1_hit_ways_3][3].ctr, 1, 1)
node _s1_taken_3_T_2 = or(_s1_taken_3_T, _s1_taken_3_T_1)
connect s1_taken[3], _s1_taken_3_T_2
connect s1_meta.hits[3], s1_hits_3
wire _alloc_way_r_metas_WIRE : UInt<37>[4]
connect _alloc_way_r_metas_WIRE[0], meta[0][0].tag
connect _alloc_way_r_metas_WIRE[1], meta[0][1].tag
connect _alloc_way_r_metas_WIRE[2], meta[0][2].tag
connect _alloc_way_r_metas_WIRE[3], meta[0][3].tag
wire _alloc_way_r_metas_WIRE_1 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_1[0], meta[1][0].tag
connect _alloc_way_r_metas_WIRE_1[1], meta[1][1].tag
connect _alloc_way_r_metas_WIRE_1[2], meta[1][2].tag
connect _alloc_way_r_metas_WIRE_1[3], meta[1][3].tag
wire _alloc_way_r_metas_WIRE_2 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_2[0], meta[2][0].tag
connect _alloc_way_r_metas_WIRE_2[1], meta[2][1].tag
connect _alloc_way_r_metas_WIRE_2[2], meta[2][2].tag
connect _alloc_way_r_metas_WIRE_2[3], meta[2][3].tag
wire _alloc_way_r_metas_WIRE_3 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_3[0], meta[3][0].tag
connect _alloc_way_r_metas_WIRE_3[1], meta[3][1].tag
connect _alloc_way_r_metas_WIRE_3[2], meta[3][2].tag
connect _alloc_way_r_metas_WIRE_3[3], meta[3][3].tag
wire _alloc_way_r_metas_WIRE_4 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_4[0], meta[4][0].tag
connect _alloc_way_r_metas_WIRE_4[1], meta[4][1].tag
connect _alloc_way_r_metas_WIRE_4[2], meta[4][2].tag
connect _alloc_way_r_metas_WIRE_4[3], meta[4][3].tag
wire _alloc_way_r_metas_WIRE_5 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_5[0], meta[5][0].tag
connect _alloc_way_r_metas_WIRE_5[1], meta[5][1].tag
connect _alloc_way_r_metas_WIRE_5[2], meta[5][2].tag
connect _alloc_way_r_metas_WIRE_5[3], meta[5][3].tag
wire _alloc_way_r_metas_WIRE_6 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_6[0], meta[6][0].tag
connect _alloc_way_r_metas_WIRE_6[1], meta[6][1].tag
connect _alloc_way_r_metas_WIRE_6[2], meta[6][2].tag
connect _alloc_way_r_metas_WIRE_6[3], meta[6][3].tag
wire _alloc_way_r_metas_WIRE_7 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_7[0], meta[7][0].tag
connect _alloc_way_r_metas_WIRE_7[1], meta[7][1].tag
connect _alloc_way_r_metas_WIRE_7[2], meta[7][2].tag
connect _alloc_way_r_metas_WIRE_7[3], meta[7][3].tag
wire _alloc_way_r_metas_WIRE_8 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_8[0], meta[8][0].tag
connect _alloc_way_r_metas_WIRE_8[1], meta[8][1].tag
connect _alloc_way_r_metas_WIRE_8[2], meta[8][2].tag
connect _alloc_way_r_metas_WIRE_8[3], meta[8][3].tag
wire _alloc_way_r_metas_WIRE_9 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_9[0], meta[9][0].tag
connect _alloc_way_r_metas_WIRE_9[1], meta[9][1].tag
connect _alloc_way_r_metas_WIRE_9[2], meta[9][2].tag
connect _alloc_way_r_metas_WIRE_9[3], meta[9][3].tag
wire _alloc_way_r_metas_WIRE_10 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_10[0], meta[10][0].tag
connect _alloc_way_r_metas_WIRE_10[1], meta[10][1].tag
connect _alloc_way_r_metas_WIRE_10[2], meta[10][2].tag
connect _alloc_way_r_metas_WIRE_10[3], meta[10][3].tag
wire _alloc_way_r_metas_WIRE_11 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_11[0], meta[11][0].tag
connect _alloc_way_r_metas_WIRE_11[1], meta[11][1].tag
connect _alloc_way_r_metas_WIRE_11[2], meta[11][2].tag
connect _alloc_way_r_metas_WIRE_11[3], meta[11][3].tag
wire _alloc_way_r_metas_WIRE_12 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_12[0], meta[12][0].tag
connect _alloc_way_r_metas_WIRE_12[1], meta[12][1].tag
connect _alloc_way_r_metas_WIRE_12[2], meta[12][2].tag
connect _alloc_way_r_metas_WIRE_12[3], meta[12][3].tag
wire _alloc_way_r_metas_WIRE_13 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_13[0], meta[13][0].tag
connect _alloc_way_r_metas_WIRE_13[1], meta[13][1].tag
connect _alloc_way_r_metas_WIRE_13[2], meta[13][2].tag
connect _alloc_way_r_metas_WIRE_13[3], meta[13][3].tag
wire _alloc_way_r_metas_WIRE_14 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_14[0], meta[14][0].tag
connect _alloc_way_r_metas_WIRE_14[1], meta[14][1].tag
connect _alloc_way_r_metas_WIRE_14[2], meta[14][2].tag
connect _alloc_way_r_metas_WIRE_14[3], meta[14][3].tag
wire _alloc_way_r_metas_WIRE_15 : UInt<37>[4]
connect _alloc_way_r_metas_WIRE_15[0], meta[15][0].tag
connect _alloc_way_r_metas_WIRE_15[1], meta[15][1].tag
connect _alloc_way_r_metas_WIRE_15[2], meta[15][2].tag
connect _alloc_way_r_metas_WIRE_15[3], meta[15][3].tag
wire _alloc_way_r_metas_WIRE_16 : UInt<37>[4][16]
connect _alloc_way_r_metas_WIRE_16[0], _alloc_way_r_metas_WIRE
connect _alloc_way_r_metas_WIRE_16[1], _alloc_way_r_metas_WIRE_1
connect _alloc_way_r_metas_WIRE_16[2], _alloc_way_r_metas_WIRE_2
connect _alloc_way_r_metas_WIRE_16[3], _alloc_way_r_metas_WIRE_3
connect _alloc_way_r_metas_WIRE_16[4], _alloc_way_r_metas_WIRE_4
connect _alloc_way_r_metas_WIRE_16[5], _alloc_way_r_metas_WIRE_5
connect _alloc_way_r_metas_WIRE_16[6], _alloc_way_r_metas_WIRE_6
connect _alloc_way_r_metas_WIRE_16[7], _alloc_way_r_metas_WIRE_7
connect _alloc_way_r_metas_WIRE_16[8], _alloc_way_r_metas_WIRE_8
connect _alloc_way_r_metas_WIRE_16[9], _alloc_way_r_metas_WIRE_9
connect _alloc_way_r_metas_WIRE_16[10], _alloc_way_r_metas_WIRE_10
connect _alloc_way_r_metas_WIRE_16[11], _alloc_way_r_metas_WIRE_11
connect _alloc_way_r_metas_WIRE_16[12], _alloc_way_r_metas_WIRE_12
connect _alloc_way_r_metas_WIRE_16[13], _alloc_way_r_metas_WIRE_13
connect _alloc_way_r_metas_WIRE_16[14], _alloc_way_r_metas_WIRE_14
connect _alloc_way_r_metas_WIRE_16[15], _alloc_way_r_metas_WIRE_15
node alloc_way_r_metas_lo = cat(_alloc_way_r_metas_WIRE_16[0][1], _alloc_way_r_metas_WIRE_16[0][0])
node alloc_way_r_metas_hi = cat(_alloc_way_r_metas_WIRE_16[0][3], _alloc_way_r_metas_WIRE_16[0][2])
node _alloc_way_r_metas_T = cat(alloc_way_r_metas_hi, alloc_way_r_metas_lo)
node alloc_way_r_metas_lo_1 = cat(_alloc_way_r_metas_WIRE_16[1][1], _alloc_way_r_metas_WIRE_16[1][0])
node alloc_way_r_metas_hi_1 = cat(_alloc_way_r_metas_WIRE_16[1][3], _alloc_way_r_metas_WIRE_16[1][2])
node _alloc_way_r_metas_T_1 = cat(alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1)
node alloc_way_r_metas_lo_2 = cat(_alloc_way_r_metas_WIRE_16[2][1], _alloc_way_r_metas_WIRE_16[2][0])
node alloc_way_r_metas_hi_2 = cat(_alloc_way_r_metas_WIRE_16[2][3], _alloc_way_r_metas_WIRE_16[2][2])
node _alloc_way_r_metas_T_2 = cat(alloc_way_r_metas_hi_2, alloc_way_r_metas_lo_2)
node alloc_way_r_metas_lo_3 = cat(_alloc_way_r_metas_WIRE_16[3][1], _alloc_way_r_metas_WIRE_16[3][0])
node alloc_way_r_metas_hi_3 = cat(_alloc_way_r_metas_WIRE_16[3][3], _alloc_way_r_metas_WIRE_16[3][2])
node _alloc_way_r_metas_T_3 = cat(alloc_way_r_metas_hi_3, alloc_way_r_metas_lo_3)
node alloc_way_r_metas_lo_4 = cat(_alloc_way_r_metas_WIRE_16[4][1], _alloc_way_r_metas_WIRE_16[4][0])
node alloc_way_r_metas_hi_4 = cat(_alloc_way_r_metas_WIRE_16[4][3], _alloc_way_r_metas_WIRE_16[4][2])
node _alloc_way_r_metas_T_4 = cat(alloc_way_r_metas_hi_4, alloc_way_r_metas_lo_4)
node alloc_way_r_metas_lo_5 = cat(_alloc_way_r_metas_WIRE_16[5][1], _alloc_way_r_metas_WIRE_16[5][0])
node alloc_way_r_metas_hi_5 = cat(_alloc_way_r_metas_WIRE_16[5][3], _alloc_way_r_metas_WIRE_16[5][2])
node _alloc_way_r_metas_T_5 = cat(alloc_way_r_metas_hi_5, alloc_way_r_metas_lo_5)
node alloc_way_r_metas_lo_6 = cat(_alloc_way_r_metas_WIRE_16[6][1], _alloc_way_r_metas_WIRE_16[6][0])
node alloc_way_r_metas_hi_6 = cat(_alloc_way_r_metas_WIRE_16[6][3], _alloc_way_r_metas_WIRE_16[6][2])
node _alloc_way_r_metas_T_6 = cat(alloc_way_r_metas_hi_6, alloc_way_r_metas_lo_6)
node alloc_way_r_metas_lo_7 = cat(_alloc_way_r_metas_WIRE_16[7][1], _alloc_way_r_metas_WIRE_16[7][0])
node alloc_way_r_metas_hi_7 = cat(_alloc_way_r_metas_WIRE_16[7][3], _alloc_way_r_metas_WIRE_16[7][2])
node _alloc_way_r_metas_T_7 = cat(alloc_way_r_metas_hi_7, alloc_way_r_metas_lo_7)
node alloc_way_r_metas_lo_8 = cat(_alloc_way_r_metas_WIRE_16[8][1], _alloc_way_r_metas_WIRE_16[8][0])
node alloc_way_r_metas_hi_8 = cat(_alloc_way_r_metas_WIRE_16[8][3], _alloc_way_r_metas_WIRE_16[8][2])
node _alloc_way_r_metas_T_8 = cat(alloc_way_r_metas_hi_8, alloc_way_r_metas_lo_8)
node alloc_way_r_metas_lo_9 = cat(_alloc_way_r_metas_WIRE_16[9][1], _alloc_way_r_metas_WIRE_16[9][0])
node alloc_way_r_metas_hi_9 = cat(_alloc_way_r_metas_WIRE_16[9][3], _alloc_way_r_metas_WIRE_16[9][2])
node _alloc_way_r_metas_T_9 = cat(alloc_way_r_metas_hi_9, alloc_way_r_metas_lo_9)
node alloc_way_r_metas_lo_10 = cat(_alloc_way_r_metas_WIRE_16[10][1], _alloc_way_r_metas_WIRE_16[10][0])
node alloc_way_r_metas_hi_10 = cat(_alloc_way_r_metas_WIRE_16[10][3], _alloc_way_r_metas_WIRE_16[10][2])
node _alloc_way_r_metas_T_10 = cat(alloc_way_r_metas_hi_10, alloc_way_r_metas_lo_10)
node alloc_way_r_metas_lo_11 = cat(_alloc_way_r_metas_WIRE_16[11][1], _alloc_way_r_metas_WIRE_16[11][0])
node alloc_way_r_metas_hi_11 = cat(_alloc_way_r_metas_WIRE_16[11][3], _alloc_way_r_metas_WIRE_16[11][2])
node _alloc_way_r_metas_T_11 = cat(alloc_way_r_metas_hi_11, alloc_way_r_metas_lo_11)
node alloc_way_r_metas_lo_12 = cat(_alloc_way_r_metas_WIRE_16[12][1], _alloc_way_r_metas_WIRE_16[12][0])
node alloc_way_r_metas_hi_12 = cat(_alloc_way_r_metas_WIRE_16[12][3], _alloc_way_r_metas_WIRE_16[12][2])
node _alloc_way_r_metas_T_12 = cat(alloc_way_r_metas_hi_12, alloc_way_r_metas_lo_12)
node alloc_way_r_metas_lo_13 = cat(_alloc_way_r_metas_WIRE_16[13][1], _alloc_way_r_metas_WIRE_16[13][0])
node alloc_way_r_metas_hi_13 = cat(_alloc_way_r_metas_WIRE_16[13][3], _alloc_way_r_metas_WIRE_16[13][2])
node _alloc_way_r_metas_T_13 = cat(alloc_way_r_metas_hi_13, alloc_way_r_metas_lo_13)
node alloc_way_r_metas_lo_14 = cat(_alloc_way_r_metas_WIRE_16[14][1], _alloc_way_r_metas_WIRE_16[14][0])
node alloc_way_r_metas_hi_14 = cat(_alloc_way_r_metas_WIRE_16[14][3], _alloc_way_r_metas_WIRE_16[14][2])
node _alloc_way_r_metas_T_14 = cat(alloc_way_r_metas_hi_14, alloc_way_r_metas_lo_14)
node alloc_way_r_metas_lo_15 = cat(_alloc_way_r_metas_WIRE_16[15][1], _alloc_way_r_metas_WIRE_16[15][0])
node alloc_way_r_metas_hi_15 = cat(_alloc_way_r_metas_WIRE_16[15][3], _alloc_way_r_metas_WIRE_16[15][2])
node _alloc_way_r_metas_T_15 = cat(alloc_way_r_metas_hi_15, alloc_way_r_metas_lo_15)
node alloc_way_r_metas_lo_lo_lo = cat(_alloc_way_r_metas_T_1, _alloc_way_r_metas_T)
node alloc_way_r_metas_lo_lo_hi = cat(_alloc_way_r_metas_T_3, _alloc_way_r_metas_T_2)
node alloc_way_r_metas_lo_lo = cat(alloc_way_r_metas_lo_lo_hi, alloc_way_r_metas_lo_lo_lo)
node alloc_way_r_metas_lo_hi_lo = cat(_alloc_way_r_metas_T_5, _alloc_way_r_metas_T_4)
node alloc_way_r_metas_lo_hi_hi = cat(_alloc_way_r_metas_T_7, _alloc_way_r_metas_T_6)
node alloc_way_r_metas_lo_hi = cat(alloc_way_r_metas_lo_hi_hi, alloc_way_r_metas_lo_hi_lo)
node alloc_way_r_metas_lo_16 = cat(alloc_way_r_metas_lo_hi, alloc_way_r_metas_lo_lo)
node alloc_way_r_metas_hi_lo_lo = cat(_alloc_way_r_metas_T_9, _alloc_way_r_metas_T_8)
node alloc_way_r_metas_hi_lo_hi = cat(_alloc_way_r_metas_T_11, _alloc_way_r_metas_T_10)
node alloc_way_r_metas_hi_lo = cat(alloc_way_r_metas_hi_lo_hi, alloc_way_r_metas_hi_lo_lo)
node alloc_way_r_metas_hi_hi_lo = cat(_alloc_way_r_metas_T_13, _alloc_way_r_metas_T_12)
node alloc_way_r_metas_hi_hi_hi = cat(_alloc_way_r_metas_T_15, _alloc_way_r_metas_T_14)
node alloc_way_r_metas_hi_hi = cat(alloc_way_r_metas_hi_hi_hi, alloc_way_r_metas_hi_hi_lo)
node alloc_way_r_metas_hi_16 = cat(alloc_way_r_metas_hi_hi, alloc_way_r_metas_hi_lo)
node _alloc_way_r_metas_T_16 = cat(alloc_way_r_metas_hi_16, alloc_way_r_metas_lo_16)
node _alloc_way_r_metas_T_17 = bits(s1_idx, 36, 0)
node alloc_way_r_metas = cat(_alloc_way_r_metas_T_16, _alloc_way_r_metas_T_17)
node alloc_way_chunks_0 = bits(alloc_way_r_metas, 3, 0)
node alloc_way_chunks_1 = bits(alloc_way_r_metas, 7, 4)
node alloc_way_chunks_2 = bits(alloc_way_r_metas, 11, 8)
node alloc_way_chunks_3 = bits(alloc_way_r_metas, 15, 12)
node alloc_way_chunks_4 = bits(alloc_way_r_metas, 19, 16)
node alloc_way_chunks_5 = bits(alloc_way_r_metas, 23, 20)
node alloc_way_chunks_6 = bits(alloc_way_r_metas, 27, 24)
node alloc_way_chunks_7 = bits(alloc_way_r_metas, 31, 28)
node alloc_way_chunks_8 = bits(alloc_way_r_metas, 35, 32)
node alloc_way_chunks_9 = bits(alloc_way_r_metas, 39, 36)
node alloc_way_chunks_10 = bits(alloc_way_r_metas, 43, 40)
node alloc_way_chunks_11 = bits(alloc_way_r_metas, 47, 44)
node alloc_way_chunks_12 = bits(alloc_way_r_metas, 51, 48)
node alloc_way_chunks_13 = bits(alloc_way_r_metas, 55, 52)
node alloc_way_chunks_14 = bits(alloc_way_r_metas, 59, 56)
node alloc_way_chunks_15 = bits(alloc_way_r_metas, 63, 60)
node alloc_way_chunks_16 = bits(alloc_way_r_metas, 67, 64)
node alloc_way_chunks_17 = bits(alloc_way_r_metas, 71, 68)
node alloc_way_chunks_18 = bits(alloc_way_r_metas, 75, 72)
node alloc_way_chunks_19 = bits(alloc_way_r_metas, 79, 76)
node alloc_way_chunks_20 = bits(alloc_way_r_metas, 83, 80)
node alloc_way_chunks_21 = bits(alloc_way_r_metas, 87, 84)
node alloc_way_chunks_22 = bits(alloc_way_r_metas, 91, 88)
node alloc_way_chunks_23 = bits(alloc_way_r_metas, 95, 92)
node alloc_way_chunks_24 = bits(alloc_way_r_metas, 99, 96)
node alloc_way_chunks_25 = bits(alloc_way_r_metas, 103, 100)
node alloc_way_chunks_26 = bits(alloc_way_r_metas, 107, 104)
node alloc_way_chunks_27 = bits(alloc_way_r_metas, 111, 108)
node alloc_way_chunks_28 = bits(alloc_way_r_metas, 115, 112)
node alloc_way_chunks_29 = bits(alloc_way_r_metas, 119, 116)
node alloc_way_chunks_30 = bits(alloc_way_r_metas, 123, 120)
node alloc_way_chunks_31 = bits(alloc_way_r_metas, 127, 124)
node alloc_way_chunks_32 = bits(alloc_way_r_metas, 131, 128)
node alloc_way_chunks_33 = bits(alloc_way_r_metas, 135, 132)
node alloc_way_chunks_34 = bits(alloc_way_r_metas, 139, 136)
node alloc_way_chunks_35 = bits(alloc_way_r_metas, 143, 140)
node alloc_way_chunks_36 = bits(alloc_way_r_metas, 147, 144)
node alloc_way_chunks_37 = bits(alloc_way_r_metas, 151, 148)
node alloc_way_chunks_38 = bits(alloc_way_r_metas, 155, 152)
node alloc_way_chunks_39 = bits(alloc_way_r_metas, 159, 156)
node alloc_way_chunks_40 = bits(alloc_way_r_metas, 163, 160)
node alloc_way_chunks_41 = bits(alloc_way_r_metas, 167, 164)
node alloc_way_chunks_42 = bits(alloc_way_r_metas, 171, 168)
node alloc_way_chunks_43 = bits(alloc_way_r_metas, 175, 172)
node alloc_way_chunks_44 = bits(alloc_way_r_metas, 179, 176)
node alloc_way_chunks_45 = bits(alloc_way_r_metas, 183, 180)
node alloc_way_chunks_46 = bits(alloc_way_r_metas, 187, 184)
node alloc_way_chunks_47 = bits(alloc_way_r_metas, 191, 188)
node alloc_way_chunks_48 = bits(alloc_way_r_metas, 195, 192)
node alloc_way_chunks_49 = bits(alloc_way_r_metas, 199, 196)
node alloc_way_chunks_50 = bits(alloc_way_r_metas, 203, 200)
node alloc_way_chunks_51 = bits(alloc_way_r_metas, 207, 204)
node alloc_way_chunks_52 = bits(alloc_way_r_metas, 211, 208)
node alloc_way_chunks_53 = bits(alloc_way_r_metas, 215, 212)
node alloc_way_chunks_54 = bits(alloc_way_r_metas, 219, 216)
node alloc_way_chunks_55 = bits(alloc_way_r_metas, 223, 220)
node alloc_way_chunks_56 = bits(alloc_way_r_metas, 227, 224)
node alloc_way_chunks_57 = bits(alloc_way_r_metas, 231, 228)
node alloc_way_chunks_58 = bits(alloc_way_r_metas, 235, 232)
node alloc_way_chunks_59 = bits(alloc_way_r_metas, 239, 236)
node alloc_way_chunks_60 = bits(alloc_way_r_metas, 243, 240)
node alloc_way_chunks_61 = bits(alloc_way_r_metas, 247, 244)
node alloc_way_chunks_62 = bits(alloc_way_r_metas, 251, 248)
node alloc_way_chunks_63 = bits(alloc_way_r_metas, 255, 252)
node alloc_way_chunks_64 = bits(alloc_way_r_metas, 259, 256)
node alloc_way_chunks_65 = bits(alloc_way_r_metas, 263, 260)
node alloc_way_chunks_66 = bits(alloc_way_r_metas, 267, 264)
node alloc_way_chunks_67 = bits(alloc_way_r_metas, 271, 268)
node alloc_way_chunks_68 = bits(alloc_way_r_metas, 275, 272)
node alloc_way_chunks_69 = bits(alloc_way_r_metas, 279, 276)
node alloc_way_chunks_70 = bits(alloc_way_r_metas, 283, 280)
node alloc_way_chunks_71 = bits(alloc_way_r_metas, 287, 284)
node alloc_way_chunks_72 = bits(alloc_way_r_metas, 291, 288)
node alloc_way_chunks_73 = bits(alloc_way_r_metas, 295, 292)
node alloc_way_chunks_74 = bits(alloc_way_r_metas, 299, 296)
node alloc_way_chunks_75 = bits(alloc_way_r_metas, 303, 300)
node alloc_way_chunks_76 = bits(alloc_way_r_metas, 307, 304)
node alloc_way_chunks_77 = bits(alloc_way_r_metas, 311, 308)
node alloc_way_chunks_78 = bits(alloc_way_r_metas, 315, 312)
node alloc_way_chunks_79 = bits(alloc_way_r_metas, 319, 316)
node alloc_way_chunks_80 = bits(alloc_way_r_metas, 323, 320)
node alloc_way_chunks_81 = bits(alloc_way_r_metas, 327, 324)
node alloc_way_chunks_82 = bits(alloc_way_r_metas, 331, 328)
node alloc_way_chunks_83 = bits(alloc_way_r_metas, 335, 332)
node alloc_way_chunks_84 = bits(alloc_way_r_metas, 339, 336)
node alloc_way_chunks_85 = bits(alloc_way_r_metas, 343, 340)
node alloc_way_chunks_86 = bits(alloc_way_r_metas, 347, 344)
node alloc_way_chunks_87 = bits(alloc_way_r_metas, 351, 348)
node alloc_way_chunks_88 = bits(alloc_way_r_metas, 355, 352)
node alloc_way_chunks_89 = bits(alloc_way_r_metas, 359, 356)
node alloc_way_chunks_90 = bits(alloc_way_r_metas, 363, 360)
node alloc_way_chunks_91 = bits(alloc_way_r_metas, 367, 364)
node alloc_way_chunks_92 = bits(alloc_way_r_metas, 371, 368)
node alloc_way_chunks_93 = bits(alloc_way_r_metas, 375, 372)
node alloc_way_chunks_94 = bits(alloc_way_r_metas, 379, 376)
node alloc_way_chunks_95 = bits(alloc_way_r_metas, 383, 380)
node alloc_way_chunks_96 = bits(alloc_way_r_metas, 387, 384)
node alloc_way_chunks_97 = bits(alloc_way_r_metas, 391, 388)
node alloc_way_chunks_98 = bits(alloc_way_r_metas, 395, 392)
node alloc_way_chunks_99 = bits(alloc_way_r_metas, 399, 396)
node alloc_way_chunks_100 = bits(alloc_way_r_metas, 403, 400)
node alloc_way_chunks_101 = bits(alloc_way_r_metas, 407, 404)
node alloc_way_chunks_102 = bits(alloc_way_r_metas, 411, 408)
node alloc_way_chunks_103 = bits(alloc_way_r_metas, 415, 412)
node alloc_way_chunks_104 = bits(alloc_way_r_metas, 419, 416)
node alloc_way_chunks_105 = bits(alloc_way_r_metas, 423, 420)
node alloc_way_chunks_106 = bits(alloc_way_r_metas, 427, 424)
node alloc_way_chunks_107 = bits(alloc_way_r_metas, 431, 428)
node alloc_way_chunks_108 = bits(alloc_way_r_metas, 435, 432)
node alloc_way_chunks_109 = bits(alloc_way_r_metas, 439, 436)
node alloc_way_chunks_110 = bits(alloc_way_r_metas, 443, 440)
node alloc_way_chunks_111 = bits(alloc_way_r_metas, 447, 444)
node alloc_way_chunks_112 = bits(alloc_way_r_metas, 451, 448)
node alloc_way_chunks_113 = bits(alloc_way_r_metas, 455, 452)
node alloc_way_chunks_114 = bits(alloc_way_r_metas, 459, 456)
node alloc_way_chunks_115 = bits(alloc_way_r_metas, 463, 460)
node alloc_way_chunks_116 = bits(alloc_way_r_metas, 467, 464)
node alloc_way_chunks_117 = bits(alloc_way_r_metas, 471, 468)
node alloc_way_chunks_118 = bits(alloc_way_r_metas, 475, 472)
node alloc_way_chunks_119 = bits(alloc_way_r_metas, 479, 476)
node alloc_way_chunks_120 = bits(alloc_way_r_metas, 483, 480)
node alloc_way_chunks_121 = bits(alloc_way_r_metas, 487, 484)
node alloc_way_chunks_122 = bits(alloc_way_r_metas, 491, 488)
node alloc_way_chunks_123 = bits(alloc_way_r_metas, 495, 492)
node alloc_way_chunks_124 = bits(alloc_way_r_metas, 499, 496)
node alloc_way_chunks_125 = bits(alloc_way_r_metas, 503, 500)
node alloc_way_chunks_126 = bits(alloc_way_r_metas, 507, 504)
node alloc_way_chunks_127 = bits(alloc_way_r_metas, 511, 508)
node alloc_way_chunks_128 = bits(alloc_way_r_metas, 515, 512)
node alloc_way_chunks_129 = bits(alloc_way_r_metas, 519, 516)
node alloc_way_chunks_130 = bits(alloc_way_r_metas, 523, 520)
node alloc_way_chunks_131 = bits(alloc_way_r_metas, 527, 524)
node alloc_way_chunks_132 = bits(alloc_way_r_metas, 531, 528)
node alloc_way_chunks_133 = bits(alloc_way_r_metas, 535, 532)
node alloc_way_chunks_134 = bits(alloc_way_r_metas, 539, 536)
node alloc_way_chunks_135 = bits(alloc_way_r_metas, 543, 540)
node alloc_way_chunks_136 = bits(alloc_way_r_metas, 547, 544)
node alloc_way_chunks_137 = bits(alloc_way_r_metas, 551, 548)
node alloc_way_chunks_138 = bits(alloc_way_r_metas, 555, 552)
node alloc_way_chunks_139 = bits(alloc_way_r_metas, 559, 556)
node alloc_way_chunks_140 = bits(alloc_way_r_metas, 563, 560)
node alloc_way_chunks_141 = bits(alloc_way_r_metas, 567, 564)
node alloc_way_chunks_142 = bits(alloc_way_r_metas, 571, 568)
node alloc_way_chunks_143 = bits(alloc_way_r_metas, 575, 572)
node alloc_way_chunks_144 = bits(alloc_way_r_metas, 579, 576)
node alloc_way_chunks_145 = bits(alloc_way_r_metas, 583, 580)
node alloc_way_chunks_146 = bits(alloc_way_r_metas, 587, 584)
node alloc_way_chunks_147 = bits(alloc_way_r_metas, 591, 588)
node alloc_way_chunks_148 = bits(alloc_way_r_metas, 595, 592)
node alloc_way_chunks_149 = bits(alloc_way_r_metas, 599, 596)
node alloc_way_chunks_150 = bits(alloc_way_r_metas, 603, 600)
node alloc_way_chunks_151 = bits(alloc_way_r_metas, 607, 604)
node alloc_way_chunks_152 = bits(alloc_way_r_metas, 611, 608)
node alloc_way_chunks_153 = bits(alloc_way_r_metas, 615, 612)
node alloc_way_chunks_154 = bits(alloc_way_r_metas, 619, 616)
node alloc_way_chunks_155 = bits(alloc_way_r_metas, 623, 620)
node alloc_way_chunks_156 = bits(alloc_way_r_metas, 627, 624)
node alloc_way_chunks_157 = bits(alloc_way_r_metas, 631, 628)
node alloc_way_chunks_158 = bits(alloc_way_r_metas, 635, 632)
node alloc_way_chunks_159 = bits(alloc_way_r_metas, 639, 636)
node alloc_way_chunks_160 = bits(alloc_way_r_metas, 643, 640)
node alloc_way_chunks_161 = bits(alloc_way_r_metas, 647, 644)
node alloc_way_chunks_162 = bits(alloc_way_r_metas, 651, 648)
node alloc_way_chunks_163 = bits(alloc_way_r_metas, 655, 652)
node alloc_way_chunks_164 = bits(alloc_way_r_metas, 659, 656)
node alloc_way_chunks_165 = bits(alloc_way_r_metas, 663, 660)
node alloc_way_chunks_166 = bits(alloc_way_r_metas, 667, 664)
node alloc_way_chunks_167 = bits(alloc_way_r_metas, 671, 668)
node alloc_way_chunks_168 = bits(alloc_way_r_metas, 675, 672)
node alloc_way_chunks_169 = bits(alloc_way_r_metas, 679, 676)
node alloc_way_chunks_170 = bits(alloc_way_r_metas, 683, 680)
node alloc_way_chunks_171 = bits(alloc_way_r_metas, 687, 684)
node alloc_way_chunks_172 = bits(alloc_way_r_metas, 691, 688)
node alloc_way_chunks_173 = bits(alloc_way_r_metas, 695, 692)
node alloc_way_chunks_174 = bits(alloc_way_r_metas, 699, 696)
node alloc_way_chunks_175 = bits(alloc_way_r_metas, 703, 700)
node alloc_way_chunks_176 = bits(alloc_way_r_metas, 707, 704)
node alloc_way_chunks_177 = bits(alloc_way_r_metas, 711, 708)
node alloc_way_chunks_178 = bits(alloc_way_r_metas, 715, 712)
node alloc_way_chunks_179 = bits(alloc_way_r_metas, 719, 716)
node alloc_way_chunks_180 = bits(alloc_way_r_metas, 723, 720)
node alloc_way_chunks_181 = bits(alloc_way_r_metas, 727, 724)
node alloc_way_chunks_182 = bits(alloc_way_r_metas, 731, 728)
node alloc_way_chunks_183 = bits(alloc_way_r_metas, 735, 732)
node alloc_way_chunks_184 = bits(alloc_way_r_metas, 739, 736)
node alloc_way_chunks_185 = bits(alloc_way_r_metas, 743, 740)
node alloc_way_chunks_186 = bits(alloc_way_r_metas, 747, 744)
node alloc_way_chunks_187 = bits(alloc_way_r_metas, 751, 748)
node alloc_way_chunks_188 = bits(alloc_way_r_metas, 755, 752)
node alloc_way_chunks_189 = bits(alloc_way_r_metas, 759, 756)
node alloc_way_chunks_190 = bits(alloc_way_r_metas, 763, 760)
node alloc_way_chunks_191 = bits(alloc_way_r_metas, 767, 764)
node alloc_way_chunks_192 = bits(alloc_way_r_metas, 771, 768)
node alloc_way_chunks_193 = bits(alloc_way_r_metas, 775, 772)
node alloc_way_chunks_194 = bits(alloc_way_r_metas, 779, 776)
node alloc_way_chunks_195 = bits(alloc_way_r_metas, 783, 780)
node alloc_way_chunks_196 = bits(alloc_way_r_metas, 787, 784)
node alloc_way_chunks_197 = bits(alloc_way_r_metas, 791, 788)
node alloc_way_chunks_198 = bits(alloc_way_r_metas, 795, 792)
node alloc_way_chunks_199 = bits(alloc_way_r_metas, 799, 796)
node alloc_way_chunks_200 = bits(alloc_way_r_metas, 803, 800)
node alloc_way_chunks_201 = bits(alloc_way_r_metas, 807, 804)
node alloc_way_chunks_202 = bits(alloc_way_r_metas, 811, 808)
node alloc_way_chunks_203 = bits(alloc_way_r_metas, 815, 812)
node alloc_way_chunks_204 = bits(alloc_way_r_metas, 819, 816)
node alloc_way_chunks_205 = bits(alloc_way_r_metas, 823, 820)
node alloc_way_chunks_206 = bits(alloc_way_r_metas, 827, 824)
node alloc_way_chunks_207 = bits(alloc_way_r_metas, 831, 828)
node alloc_way_chunks_208 = bits(alloc_way_r_metas, 835, 832)
node alloc_way_chunks_209 = bits(alloc_way_r_metas, 839, 836)
node alloc_way_chunks_210 = bits(alloc_way_r_metas, 843, 840)
node alloc_way_chunks_211 = bits(alloc_way_r_metas, 847, 844)
node alloc_way_chunks_212 = bits(alloc_way_r_metas, 851, 848)
node alloc_way_chunks_213 = bits(alloc_way_r_metas, 855, 852)
node alloc_way_chunks_214 = bits(alloc_way_r_metas, 859, 856)
node alloc_way_chunks_215 = bits(alloc_way_r_metas, 863, 860)
node alloc_way_chunks_216 = bits(alloc_way_r_metas, 867, 864)
node alloc_way_chunks_217 = bits(alloc_way_r_metas, 871, 868)
node alloc_way_chunks_218 = bits(alloc_way_r_metas, 875, 872)
node alloc_way_chunks_219 = bits(alloc_way_r_metas, 879, 876)
node alloc_way_chunks_220 = bits(alloc_way_r_metas, 883, 880)
node alloc_way_chunks_221 = bits(alloc_way_r_metas, 887, 884)
node alloc_way_chunks_222 = bits(alloc_way_r_metas, 891, 888)
node alloc_way_chunks_223 = bits(alloc_way_r_metas, 895, 892)
node alloc_way_chunks_224 = bits(alloc_way_r_metas, 899, 896)
node alloc_way_chunks_225 = bits(alloc_way_r_metas, 903, 900)
node alloc_way_chunks_226 = bits(alloc_way_r_metas, 907, 904)
node alloc_way_chunks_227 = bits(alloc_way_r_metas, 911, 908)
node alloc_way_chunks_228 = bits(alloc_way_r_metas, 915, 912)
node alloc_way_chunks_229 = bits(alloc_way_r_metas, 919, 916)
node alloc_way_chunks_230 = bits(alloc_way_r_metas, 923, 920)
node alloc_way_chunks_231 = bits(alloc_way_r_metas, 927, 924)
node alloc_way_chunks_232 = bits(alloc_way_r_metas, 931, 928)
node alloc_way_chunks_233 = bits(alloc_way_r_metas, 935, 932)
node alloc_way_chunks_234 = bits(alloc_way_r_metas, 939, 936)
node alloc_way_chunks_235 = bits(alloc_way_r_metas, 943, 940)
node alloc_way_chunks_236 = bits(alloc_way_r_metas, 947, 944)
node alloc_way_chunks_237 = bits(alloc_way_r_metas, 951, 948)
node alloc_way_chunks_238 = bits(alloc_way_r_metas, 955, 952)
node alloc_way_chunks_239 = bits(alloc_way_r_metas, 959, 956)
node alloc_way_chunks_240 = bits(alloc_way_r_metas, 963, 960)
node alloc_way_chunks_241 = bits(alloc_way_r_metas, 967, 964)
node alloc_way_chunks_242 = bits(alloc_way_r_metas, 971, 968)
node alloc_way_chunks_243 = bits(alloc_way_r_metas, 975, 972)
node alloc_way_chunks_244 = bits(alloc_way_r_metas, 979, 976)
node alloc_way_chunks_245 = bits(alloc_way_r_metas, 983, 980)
node alloc_way_chunks_246 = bits(alloc_way_r_metas, 987, 984)
node alloc_way_chunks_247 = bits(alloc_way_r_metas, 991, 988)
node alloc_way_chunks_248 = bits(alloc_way_r_metas, 995, 992)
node alloc_way_chunks_249 = bits(alloc_way_r_metas, 999, 996)
node alloc_way_chunks_250 = bits(alloc_way_r_metas, 1003, 1000)
node alloc_way_chunks_251 = bits(alloc_way_r_metas, 1007, 1004)
node alloc_way_chunks_252 = bits(alloc_way_r_metas, 1011, 1008)
node alloc_way_chunks_253 = bits(alloc_way_r_metas, 1015, 1012)
node alloc_way_chunks_254 = bits(alloc_way_r_metas, 1019, 1016)
node alloc_way_chunks_255 = bits(alloc_way_r_metas, 1023, 1020)
node alloc_way_chunks_256 = bits(alloc_way_r_metas, 1027, 1024)
node alloc_way_chunks_257 = bits(alloc_way_r_metas, 1031, 1028)
node alloc_way_chunks_258 = bits(alloc_way_r_metas, 1035, 1032)
node alloc_way_chunks_259 = bits(alloc_way_r_metas, 1039, 1036)
node alloc_way_chunks_260 = bits(alloc_way_r_metas, 1043, 1040)
node alloc_way_chunks_261 = bits(alloc_way_r_metas, 1047, 1044)
node alloc_way_chunks_262 = bits(alloc_way_r_metas, 1051, 1048)
node alloc_way_chunks_263 = bits(alloc_way_r_metas, 1055, 1052)
node alloc_way_chunks_264 = bits(alloc_way_r_metas, 1059, 1056)
node alloc_way_chunks_265 = bits(alloc_way_r_metas, 1063, 1060)
node alloc_way_chunks_266 = bits(alloc_way_r_metas, 1067, 1064)
node alloc_way_chunks_267 = bits(alloc_way_r_metas, 1071, 1068)
node alloc_way_chunks_268 = bits(alloc_way_r_metas, 1075, 1072)
node alloc_way_chunks_269 = bits(alloc_way_r_metas, 1079, 1076)
node alloc_way_chunks_270 = bits(alloc_way_r_metas, 1083, 1080)
node alloc_way_chunks_271 = bits(alloc_way_r_metas, 1087, 1084)
node alloc_way_chunks_272 = bits(alloc_way_r_metas, 1091, 1088)
node alloc_way_chunks_273 = bits(alloc_way_r_metas, 1095, 1092)
node alloc_way_chunks_274 = bits(alloc_way_r_metas, 1099, 1096)
node alloc_way_chunks_275 = bits(alloc_way_r_metas, 1103, 1100)
node alloc_way_chunks_276 = bits(alloc_way_r_metas, 1107, 1104)
node alloc_way_chunks_277 = bits(alloc_way_r_metas, 1111, 1108)
node alloc_way_chunks_278 = bits(alloc_way_r_metas, 1115, 1112)
node alloc_way_chunks_279 = bits(alloc_way_r_metas, 1119, 1116)
node alloc_way_chunks_280 = bits(alloc_way_r_metas, 1123, 1120)
node alloc_way_chunks_281 = bits(alloc_way_r_metas, 1127, 1124)
node alloc_way_chunks_282 = bits(alloc_way_r_metas, 1131, 1128)
node alloc_way_chunks_283 = bits(alloc_way_r_metas, 1135, 1132)
node alloc_way_chunks_284 = bits(alloc_way_r_metas, 1139, 1136)
node alloc_way_chunks_285 = bits(alloc_way_r_metas, 1143, 1140)
node alloc_way_chunks_286 = bits(alloc_way_r_metas, 1147, 1144)
node alloc_way_chunks_287 = bits(alloc_way_r_metas, 1151, 1148)
node alloc_way_chunks_288 = bits(alloc_way_r_metas, 1155, 1152)
node alloc_way_chunks_289 = bits(alloc_way_r_metas, 1159, 1156)
node alloc_way_chunks_290 = bits(alloc_way_r_metas, 1163, 1160)
node alloc_way_chunks_291 = bits(alloc_way_r_metas, 1167, 1164)
node alloc_way_chunks_292 = bits(alloc_way_r_metas, 1171, 1168)
node alloc_way_chunks_293 = bits(alloc_way_r_metas, 1175, 1172)
node alloc_way_chunks_294 = bits(alloc_way_r_metas, 1179, 1176)
node alloc_way_chunks_295 = bits(alloc_way_r_metas, 1183, 1180)
node alloc_way_chunks_296 = bits(alloc_way_r_metas, 1187, 1184)
node alloc_way_chunks_297 = bits(alloc_way_r_metas, 1191, 1188)
node alloc_way_chunks_298 = bits(alloc_way_r_metas, 1195, 1192)
node alloc_way_chunks_299 = bits(alloc_way_r_metas, 1199, 1196)
node alloc_way_chunks_300 = bits(alloc_way_r_metas, 1203, 1200)
node alloc_way_chunks_301 = bits(alloc_way_r_metas, 1207, 1204)
node alloc_way_chunks_302 = bits(alloc_way_r_metas, 1211, 1208)
node alloc_way_chunks_303 = bits(alloc_way_r_metas, 1215, 1212)
node alloc_way_chunks_304 = bits(alloc_way_r_metas, 1219, 1216)
node alloc_way_chunks_305 = bits(alloc_way_r_metas, 1223, 1220)
node alloc_way_chunks_306 = bits(alloc_way_r_metas, 1227, 1224)
node alloc_way_chunks_307 = bits(alloc_way_r_metas, 1231, 1228)
node alloc_way_chunks_308 = bits(alloc_way_r_metas, 1235, 1232)
node alloc_way_chunks_309 = bits(alloc_way_r_metas, 1239, 1236)
node alloc_way_chunks_310 = bits(alloc_way_r_metas, 1243, 1240)
node alloc_way_chunks_311 = bits(alloc_way_r_metas, 1247, 1244)
node alloc_way_chunks_312 = bits(alloc_way_r_metas, 1251, 1248)
node alloc_way_chunks_313 = bits(alloc_way_r_metas, 1255, 1252)
node alloc_way_chunks_314 = bits(alloc_way_r_metas, 1259, 1256)
node alloc_way_chunks_315 = bits(alloc_way_r_metas, 1263, 1260)
node alloc_way_chunks_316 = bits(alloc_way_r_metas, 1267, 1264)
node alloc_way_chunks_317 = bits(alloc_way_r_metas, 1271, 1268)
node alloc_way_chunks_318 = bits(alloc_way_r_metas, 1275, 1272)
node alloc_way_chunks_319 = bits(alloc_way_r_metas, 1279, 1276)
node alloc_way_chunks_320 = bits(alloc_way_r_metas, 1283, 1280)
node alloc_way_chunks_321 = bits(alloc_way_r_metas, 1287, 1284)
node alloc_way_chunks_322 = bits(alloc_way_r_metas, 1291, 1288)
node alloc_way_chunks_323 = bits(alloc_way_r_metas, 1295, 1292)
node alloc_way_chunks_324 = bits(alloc_way_r_metas, 1299, 1296)
node alloc_way_chunks_325 = bits(alloc_way_r_metas, 1303, 1300)
node alloc_way_chunks_326 = bits(alloc_way_r_metas, 1307, 1304)
node alloc_way_chunks_327 = bits(alloc_way_r_metas, 1311, 1308)
node alloc_way_chunks_328 = bits(alloc_way_r_metas, 1315, 1312)
node alloc_way_chunks_329 = bits(alloc_way_r_metas, 1319, 1316)
node alloc_way_chunks_330 = bits(alloc_way_r_metas, 1323, 1320)
node alloc_way_chunks_331 = bits(alloc_way_r_metas, 1327, 1324)
node alloc_way_chunks_332 = bits(alloc_way_r_metas, 1331, 1328)
node alloc_way_chunks_333 = bits(alloc_way_r_metas, 1335, 1332)
node alloc_way_chunks_334 = bits(alloc_way_r_metas, 1339, 1336)
node alloc_way_chunks_335 = bits(alloc_way_r_metas, 1343, 1340)
node alloc_way_chunks_336 = bits(alloc_way_r_metas, 1347, 1344)
node alloc_way_chunks_337 = bits(alloc_way_r_metas, 1351, 1348)
node alloc_way_chunks_338 = bits(alloc_way_r_metas, 1355, 1352)
node alloc_way_chunks_339 = bits(alloc_way_r_metas, 1359, 1356)
node alloc_way_chunks_340 = bits(alloc_way_r_metas, 1363, 1360)
node alloc_way_chunks_341 = bits(alloc_way_r_metas, 1367, 1364)
node alloc_way_chunks_342 = bits(alloc_way_r_metas, 1371, 1368)
node alloc_way_chunks_343 = bits(alloc_way_r_metas, 1375, 1372)
node alloc_way_chunks_344 = bits(alloc_way_r_metas, 1379, 1376)
node alloc_way_chunks_345 = bits(alloc_way_r_metas, 1383, 1380)
node alloc_way_chunks_346 = bits(alloc_way_r_metas, 1387, 1384)
node alloc_way_chunks_347 = bits(alloc_way_r_metas, 1391, 1388)
node alloc_way_chunks_348 = bits(alloc_way_r_metas, 1395, 1392)
node alloc_way_chunks_349 = bits(alloc_way_r_metas, 1399, 1396)
node alloc_way_chunks_350 = bits(alloc_way_r_metas, 1403, 1400)
node alloc_way_chunks_351 = bits(alloc_way_r_metas, 1407, 1404)
node alloc_way_chunks_352 = bits(alloc_way_r_metas, 1411, 1408)
node alloc_way_chunks_353 = bits(alloc_way_r_metas, 1415, 1412)
node alloc_way_chunks_354 = bits(alloc_way_r_metas, 1419, 1416)
node alloc_way_chunks_355 = bits(alloc_way_r_metas, 1423, 1420)
node alloc_way_chunks_356 = bits(alloc_way_r_metas, 1427, 1424)
node alloc_way_chunks_357 = bits(alloc_way_r_metas, 1431, 1428)
node alloc_way_chunks_358 = bits(alloc_way_r_metas, 1435, 1432)
node alloc_way_chunks_359 = bits(alloc_way_r_metas, 1439, 1436)
node alloc_way_chunks_360 = bits(alloc_way_r_metas, 1443, 1440)
node alloc_way_chunks_361 = bits(alloc_way_r_metas, 1447, 1444)
node alloc_way_chunks_362 = bits(alloc_way_r_metas, 1451, 1448)
node alloc_way_chunks_363 = bits(alloc_way_r_metas, 1455, 1452)
node alloc_way_chunks_364 = bits(alloc_way_r_metas, 1459, 1456)
node alloc_way_chunks_365 = bits(alloc_way_r_metas, 1463, 1460)
node alloc_way_chunks_366 = bits(alloc_way_r_metas, 1467, 1464)
node alloc_way_chunks_367 = bits(alloc_way_r_metas, 1471, 1468)
node alloc_way_chunks_368 = bits(alloc_way_r_metas, 1475, 1472)
node alloc_way_chunks_369 = bits(alloc_way_r_metas, 1479, 1476)
node alloc_way_chunks_370 = bits(alloc_way_r_metas, 1483, 1480)
node alloc_way_chunks_371 = bits(alloc_way_r_metas, 1487, 1484)
node alloc_way_chunks_372 = bits(alloc_way_r_metas, 1491, 1488)
node alloc_way_chunks_373 = bits(alloc_way_r_metas, 1495, 1492)
node alloc_way_chunks_374 = bits(alloc_way_r_metas, 1499, 1496)
node alloc_way_chunks_375 = bits(alloc_way_r_metas, 1503, 1500)
node alloc_way_chunks_376 = bits(alloc_way_r_metas, 1507, 1504)
node alloc_way_chunks_377 = bits(alloc_way_r_metas, 1511, 1508)
node alloc_way_chunks_378 = bits(alloc_way_r_metas, 1515, 1512)
node alloc_way_chunks_379 = bits(alloc_way_r_metas, 1519, 1516)
node alloc_way_chunks_380 = bits(alloc_way_r_metas, 1523, 1520)
node alloc_way_chunks_381 = bits(alloc_way_r_metas, 1527, 1524)
node alloc_way_chunks_382 = bits(alloc_way_r_metas, 1531, 1528)
node alloc_way_chunks_383 = bits(alloc_way_r_metas, 1535, 1532)
node alloc_way_chunks_384 = bits(alloc_way_r_metas, 1539, 1536)
node alloc_way_chunks_385 = bits(alloc_way_r_metas, 1543, 1540)
node alloc_way_chunks_386 = bits(alloc_way_r_metas, 1547, 1544)
node alloc_way_chunks_387 = bits(alloc_way_r_metas, 1551, 1548)
node alloc_way_chunks_388 = bits(alloc_way_r_metas, 1555, 1552)
node alloc_way_chunks_389 = bits(alloc_way_r_metas, 1559, 1556)
node alloc_way_chunks_390 = bits(alloc_way_r_metas, 1563, 1560)
node alloc_way_chunks_391 = bits(alloc_way_r_metas, 1567, 1564)
node alloc_way_chunks_392 = bits(alloc_way_r_metas, 1571, 1568)
node alloc_way_chunks_393 = bits(alloc_way_r_metas, 1575, 1572)
node alloc_way_chunks_394 = bits(alloc_way_r_metas, 1579, 1576)
node alloc_way_chunks_395 = bits(alloc_way_r_metas, 1583, 1580)
node alloc_way_chunks_396 = bits(alloc_way_r_metas, 1587, 1584)
node alloc_way_chunks_397 = bits(alloc_way_r_metas, 1591, 1588)
node alloc_way_chunks_398 = bits(alloc_way_r_metas, 1595, 1592)
node alloc_way_chunks_399 = bits(alloc_way_r_metas, 1599, 1596)
node alloc_way_chunks_400 = bits(alloc_way_r_metas, 1603, 1600)
node alloc_way_chunks_401 = bits(alloc_way_r_metas, 1607, 1604)
node alloc_way_chunks_402 = bits(alloc_way_r_metas, 1611, 1608)
node alloc_way_chunks_403 = bits(alloc_way_r_metas, 1615, 1612)
node alloc_way_chunks_404 = bits(alloc_way_r_metas, 1619, 1616)
node alloc_way_chunks_405 = bits(alloc_way_r_metas, 1623, 1620)
node alloc_way_chunks_406 = bits(alloc_way_r_metas, 1627, 1624)
node alloc_way_chunks_407 = bits(alloc_way_r_metas, 1631, 1628)
node alloc_way_chunks_408 = bits(alloc_way_r_metas, 1635, 1632)
node alloc_way_chunks_409 = bits(alloc_way_r_metas, 1639, 1636)
node alloc_way_chunks_410 = bits(alloc_way_r_metas, 1643, 1640)
node alloc_way_chunks_411 = bits(alloc_way_r_metas, 1647, 1644)
node alloc_way_chunks_412 = bits(alloc_way_r_metas, 1651, 1648)
node alloc_way_chunks_413 = bits(alloc_way_r_metas, 1655, 1652)
node alloc_way_chunks_414 = bits(alloc_way_r_metas, 1659, 1656)
node alloc_way_chunks_415 = bits(alloc_way_r_metas, 1663, 1660)
node alloc_way_chunks_416 = bits(alloc_way_r_metas, 1667, 1664)
node alloc_way_chunks_417 = bits(alloc_way_r_metas, 1671, 1668)
node alloc_way_chunks_418 = bits(alloc_way_r_metas, 1675, 1672)
node alloc_way_chunks_419 = bits(alloc_way_r_metas, 1679, 1676)
node alloc_way_chunks_420 = bits(alloc_way_r_metas, 1683, 1680)
node alloc_way_chunks_421 = bits(alloc_way_r_metas, 1687, 1684)
node alloc_way_chunks_422 = bits(alloc_way_r_metas, 1691, 1688)
node alloc_way_chunks_423 = bits(alloc_way_r_metas, 1695, 1692)
node alloc_way_chunks_424 = bits(alloc_way_r_metas, 1699, 1696)
node alloc_way_chunks_425 = bits(alloc_way_r_metas, 1703, 1700)
node alloc_way_chunks_426 = bits(alloc_way_r_metas, 1707, 1704)
node alloc_way_chunks_427 = bits(alloc_way_r_metas, 1711, 1708)
node alloc_way_chunks_428 = bits(alloc_way_r_metas, 1715, 1712)
node alloc_way_chunks_429 = bits(alloc_way_r_metas, 1719, 1716)
node alloc_way_chunks_430 = bits(alloc_way_r_metas, 1723, 1720)
node alloc_way_chunks_431 = bits(alloc_way_r_metas, 1727, 1724)
node alloc_way_chunks_432 = bits(alloc_way_r_metas, 1731, 1728)
node alloc_way_chunks_433 = bits(alloc_way_r_metas, 1735, 1732)
node alloc_way_chunks_434 = bits(alloc_way_r_metas, 1739, 1736)
node alloc_way_chunks_435 = bits(alloc_way_r_metas, 1743, 1740)
node alloc_way_chunks_436 = bits(alloc_way_r_metas, 1747, 1744)
node alloc_way_chunks_437 = bits(alloc_way_r_metas, 1751, 1748)
node alloc_way_chunks_438 = bits(alloc_way_r_metas, 1755, 1752)
node alloc_way_chunks_439 = bits(alloc_way_r_metas, 1759, 1756)
node alloc_way_chunks_440 = bits(alloc_way_r_metas, 1763, 1760)
node alloc_way_chunks_441 = bits(alloc_way_r_metas, 1767, 1764)
node alloc_way_chunks_442 = bits(alloc_way_r_metas, 1771, 1768)
node alloc_way_chunks_443 = bits(alloc_way_r_metas, 1775, 1772)
node alloc_way_chunks_444 = bits(alloc_way_r_metas, 1779, 1776)
node alloc_way_chunks_445 = bits(alloc_way_r_metas, 1783, 1780)
node alloc_way_chunks_446 = bits(alloc_way_r_metas, 1787, 1784)
node alloc_way_chunks_447 = bits(alloc_way_r_metas, 1791, 1788)
node alloc_way_chunks_448 = bits(alloc_way_r_metas, 1795, 1792)
node alloc_way_chunks_449 = bits(alloc_way_r_metas, 1799, 1796)
node alloc_way_chunks_450 = bits(alloc_way_r_metas, 1803, 1800)
node alloc_way_chunks_451 = bits(alloc_way_r_metas, 1807, 1804)
node alloc_way_chunks_452 = bits(alloc_way_r_metas, 1811, 1808)
node alloc_way_chunks_453 = bits(alloc_way_r_metas, 1815, 1812)
node alloc_way_chunks_454 = bits(alloc_way_r_metas, 1819, 1816)
node alloc_way_chunks_455 = bits(alloc_way_r_metas, 1823, 1820)
node alloc_way_chunks_456 = bits(alloc_way_r_metas, 1827, 1824)
node alloc_way_chunks_457 = bits(alloc_way_r_metas, 1831, 1828)
node alloc_way_chunks_458 = bits(alloc_way_r_metas, 1835, 1832)
node alloc_way_chunks_459 = bits(alloc_way_r_metas, 1839, 1836)
node alloc_way_chunks_460 = bits(alloc_way_r_metas, 1843, 1840)
node alloc_way_chunks_461 = bits(alloc_way_r_metas, 1847, 1844)
node alloc_way_chunks_462 = bits(alloc_way_r_metas, 1851, 1848)
node alloc_way_chunks_463 = bits(alloc_way_r_metas, 1855, 1852)
node alloc_way_chunks_464 = bits(alloc_way_r_metas, 1859, 1856)
node alloc_way_chunks_465 = bits(alloc_way_r_metas, 1863, 1860)
node alloc_way_chunks_466 = bits(alloc_way_r_metas, 1867, 1864)
node alloc_way_chunks_467 = bits(alloc_way_r_metas, 1871, 1868)
node alloc_way_chunks_468 = bits(alloc_way_r_metas, 1875, 1872)
node alloc_way_chunks_469 = bits(alloc_way_r_metas, 1879, 1876)
node alloc_way_chunks_470 = bits(alloc_way_r_metas, 1883, 1880)
node alloc_way_chunks_471 = bits(alloc_way_r_metas, 1887, 1884)
node alloc_way_chunks_472 = bits(alloc_way_r_metas, 1891, 1888)
node alloc_way_chunks_473 = bits(alloc_way_r_metas, 1895, 1892)
node alloc_way_chunks_474 = bits(alloc_way_r_metas, 1899, 1896)
node alloc_way_chunks_475 = bits(alloc_way_r_metas, 1903, 1900)
node alloc_way_chunks_476 = bits(alloc_way_r_metas, 1907, 1904)
node alloc_way_chunks_477 = bits(alloc_way_r_metas, 1911, 1908)
node alloc_way_chunks_478 = bits(alloc_way_r_metas, 1915, 1912)
node alloc_way_chunks_479 = bits(alloc_way_r_metas, 1919, 1916)
node alloc_way_chunks_480 = bits(alloc_way_r_metas, 1923, 1920)
node alloc_way_chunks_481 = bits(alloc_way_r_metas, 1927, 1924)
node alloc_way_chunks_482 = bits(alloc_way_r_metas, 1931, 1928)
node alloc_way_chunks_483 = bits(alloc_way_r_metas, 1935, 1932)
node alloc_way_chunks_484 = bits(alloc_way_r_metas, 1939, 1936)
node alloc_way_chunks_485 = bits(alloc_way_r_metas, 1943, 1940)
node alloc_way_chunks_486 = bits(alloc_way_r_metas, 1947, 1944)
node alloc_way_chunks_487 = bits(alloc_way_r_metas, 1951, 1948)
node alloc_way_chunks_488 = bits(alloc_way_r_metas, 1955, 1952)
node alloc_way_chunks_489 = bits(alloc_way_r_metas, 1959, 1956)
node alloc_way_chunks_490 = bits(alloc_way_r_metas, 1963, 1960)
node alloc_way_chunks_491 = bits(alloc_way_r_metas, 1967, 1964)
node alloc_way_chunks_492 = bits(alloc_way_r_metas, 1971, 1968)
node alloc_way_chunks_493 = bits(alloc_way_r_metas, 1975, 1972)
node alloc_way_chunks_494 = bits(alloc_way_r_metas, 1979, 1976)
node alloc_way_chunks_495 = bits(alloc_way_r_metas, 1983, 1980)
node alloc_way_chunks_496 = bits(alloc_way_r_metas, 1987, 1984)
node alloc_way_chunks_497 = bits(alloc_way_r_metas, 1991, 1988)
node alloc_way_chunks_498 = bits(alloc_way_r_metas, 1995, 1992)
node alloc_way_chunks_499 = bits(alloc_way_r_metas, 1999, 1996)
node alloc_way_chunks_500 = bits(alloc_way_r_metas, 2003, 2000)
node alloc_way_chunks_501 = bits(alloc_way_r_metas, 2007, 2004)
node alloc_way_chunks_502 = bits(alloc_way_r_metas, 2011, 2008)
node alloc_way_chunks_503 = bits(alloc_way_r_metas, 2015, 2012)
node alloc_way_chunks_504 = bits(alloc_way_r_metas, 2019, 2016)
node alloc_way_chunks_505 = bits(alloc_way_r_metas, 2023, 2020)
node alloc_way_chunks_506 = bits(alloc_way_r_metas, 2027, 2024)
node alloc_way_chunks_507 = bits(alloc_way_r_metas, 2031, 2028)
node alloc_way_chunks_508 = bits(alloc_way_r_metas, 2035, 2032)
node alloc_way_chunks_509 = bits(alloc_way_r_metas, 2039, 2036)
node alloc_way_chunks_510 = bits(alloc_way_r_metas, 2043, 2040)
node alloc_way_chunks_511 = bits(alloc_way_r_metas, 2047, 2044)
node alloc_way_chunks_512 = bits(alloc_way_r_metas, 2051, 2048)
node alloc_way_chunks_513 = bits(alloc_way_r_metas, 2055, 2052)
node alloc_way_chunks_514 = bits(alloc_way_r_metas, 2059, 2056)
node alloc_way_chunks_515 = bits(alloc_way_r_metas, 2063, 2060)
node alloc_way_chunks_516 = bits(alloc_way_r_metas, 2067, 2064)
node alloc_way_chunks_517 = bits(alloc_way_r_metas, 2071, 2068)
node alloc_way_chunks_518 = bits(alloc_way_r_metas, 2075, 2072)
node alloc_way_chunks_519 = bits(alloc_way_r_metas, 2079, 2076)
node alloc_way_chunks_520 = bits(alloc_way_r_metas, 2083, 2080)
node alloc_way_chunks_521 = bits(alloc_way_r_metas, 2087, 2084)
node alloc_way_chunks_522 = bits(alloc_way_r_metas, 2091, 2088)
node alloc_way_chunks_523 = bits(alloc_way_r_metas, 2095, 2092)
node alloc_way_chunks_524 = bits(alloc_way_r_metas, 2099, 2096)
node alloc_way_chunks_525 = bits(alloc_way_r_metas, 2103, 2100)
node alloc_way_chunks_526 = bits(alloc_way_r_metas, 2107, 2104)
node alloc_way_chunks_527 = bits(alloc_way_r_metas, 2111, 2108)
node alloc_way_chunks_528 = bits(alloc_way_r_metas, 2115, 2112)
node alloc_way_chunks_529 = bits(alloc_way_r_metas, 2119, 2116)
node alloc_way_chunks_530 = bits(alloc_way_r_metas, 2123, 2120)
node alloc_way_chunks_531 = bits(alloc_way_r_metas, 2127, 2124)
node alloc_way_chunks_532 = bits(alloc_way_r_metas, 2131, 2128)
node alloc_way_chunks_533 = bits(alloc_way_r_metas, 2135, 2132)
node alloc_way_chunks_534 = bits(alloc_way_r_metas, 2139, 2136)
node alloc_way_chunks_535 = bits(alloc_way_r_metas, 2143, 2140)
node alloc_way_chunks_536 = bits(alloc_way_r_metas, 2147, 2144)
node alloc_way_chunks_537 = bits(alloc_way_r_metas, 2151, 2148)
node alloc_way_chunks_538 = bits(alloc_way_r_metas, 2155, 2152)
node alloc_way_chunks_539 = bits(alloc_way_r_metas, 2159, 2156)
node alloc_way_chunks_540 = bits(alloc_way_r_metas, 2163, 2160)
node alloc_way_chunks_541 = bits(alloc_way_r_metas, 2167, 2164)
node alloc_way_chunks_542 = bits(alloc_way_r_metas, 2171, 2168)
node alloc_way_chunks_543 = bits(alloc_way_r_metas, 2175, 2172)
node alloc_way_chunks_544 = bits(alloc_way_r_metas, 2179, 2176)
node alloc_way_chunks_545 = bits(alloc_way_r_metas, 2183, 2180)
node alloc_way_chunks_546 = bits(alloc_way_r_metas, 2187, 2184)
node alloc_way_chunks_547 = bits(alloc_way_r_metas, 2191, 2188)
node alloc_way_chunks_548 = bits(alloc_way_r_metas, 2195, 2192)
node alloc_way_chunks_549 = bits(alloc_way_r_metas, 2199, 2196)
node alloc_way_chunks_550 = bits(alloc_way_r_metas, 2203, 2200)
node alloc_way_chunks_551 = bits(alloc_way_r_metas, 2207, 2204)
node alloc_way_chunks_552 = bits(alloc_way_r_metas, 2211, 2208)
node alloc_way_chunks_553 = bits(alloc_way_r_metas, 2215, 2212)
node alloc_way_chunks_554 = bits(alloc_way_r_metas, 2219, 2216)
node alloc_way_chunks_555 = bits(alloc_way_r_metas, 2223, 2220)
node alloc_way_chunks_556 = bits(alloc_way_r_metas, 2227, 2224)
node alloc_way_chunks_557 = bits(alloc_way_r_metas, 2231, 2228)
node alloc_way_chunks_558 = bits(alloc_way_r_metas, 2235, 2232)
node alloc_way_chunks_559 = bits(alloc_way_r_metas, 2239, 2236)
node alloc_way_chunks_560 = bits(alloc_way_r_metas, 2243, 2240)
node alloc_way_chunks_561 = bits(alloc_way_r_metas, 2247, 2244)
node alloc_way_chunks_562 = bits(alloc_way_r_metas, 2251, 2248)
node alloc_way_chunks_563 = bits(alloc_way_r_metas, 2255, 2252)
node alloc_way_chunks_564 = bits(alloc_way_r_metas, 2259, 2256)
node alloc_way_chunks_565 = bits(alloc_way_r_metas, 2263, 2260)
node alloc_way_chunks_566 = bits(alloc_way_r_metas, 2267, 2264)
node alloc_way_chunks_567 = bits(alloc_way_r_metas, 2271, 2268)
node alloc_way_chunks_568 = bits(alloc_way_r_metas, 2275, 2272)
node alloc_way_chunks_569 = bits(alloc_way_r_metas, 2279, 2276)
node alloc_way_chunks_570 = bits(alloc_way_r_metas, 2283, 2280)
node alloc_way_chunks_571 = bits(alloc_way_r_metas, 2287, 2284)
node alloc_way_chunks_572 = bits(alloc_way_r_metas, 2291, 2288)
node alloc_way_chunks_573 = bits(alloc_way_r_metas, 2295, 2292)
node alloc_way_chunks_574 = bits(alloc_way_r_metas, 2299, 2296)
node alloc_way_chunks_575 = bits(alloc_way_r_metas, 2303, 2300)
node alloc_way_chunks_576 = bits(alloc_way_r_metas, 2307, 2304)
node alloc_way_chunks_577 = bits(alloc_way_r_metas, 2311, 2308)
node alloc_way_chunks_578 = bits(alloc_way_r_metas, 2315, 2312)
node alloc_way_chunks_579 = bits(alloc_way_r_metas, 2319, 2316)
node alloc_way_chunks_580 = bits(alloc_way_r_metas, 2323, 2320)
node alloc_way_chunks_581 = bits(alloc_way_r_metas, 2327, 2324)
node alloc_way_chunks_582 = bits(alloc_way_r_metas, 2331, 2328)
node alloc_way_chunks_583 = bits(alloc_way_r_metas, 2335, 2332)
node alloc_way_chunks_584 = bits(alloc_way_r_metas, 2339, 2336)
node alloc_way_chunks_585 = bits(alloc_way_r_metas, 2343, 2340)
node alloc_way_chunks_586 = bits(alloc_way_r_metas, 2347, 2344)
node alloc_way_chunks_587 = bits(alloc_way_r_metas, 2351, 2348)
node alloc_way_chunks_588 = bits(alloc_way_r_metas, 2355, 2352)
node alloc_way_chunks_589 = bits(alloc_way_r_metas, 2359, 2356)
node alloc_way_chunks_590 = bits(alloc_way_r_metas, 2363, 2360)
node alloc_way_chunks_591 = bits(alloc_way_r_metas, 2367, 2364)
node alloc_way_chunks_592 = bits(alloc_way_r_metas, 2371, 2368)
node alloc_way_chunks_593 = bits(alloc_way_r_metas, 2375, 2372)
node alloc_way_chunks_594 = bits(alloc_way_r_metas, 2379, 2376)
node alloc_way_chunks_595 = bits(alloc_way_r_metas, 2383, 2380)
node alloc_way_chunks_596 = bits(alloc_way_r_metas, 2387, 2384)
node alloc_way_chunks_597 = bits(alloc_way_r_metas, 2391, 2388)
node alloc_way_chunks_598 = bits(alloc_way_r_metas, 2395, 2392)
node alloc_way_chunks_599 = bits(alloc_way_r_metas, 2399, 2396)
node alloc_way_chunks_600 = bits(alloc_way_r_metas, 2403, 2400)
node alloc_way_chunks_601 = bits(alloc_way_r_metas, 2404, 2404)
node _alloc_way_T = xor(alloc_way_chunks_0, alloc_way_chunks_1)
node _alloc_way_T_1 = xor(_alloc_way_T, alloc_way_chunks_2)
node _alloc_way_T_2 = xor(_alloc_way_T_1, alloc_way_chunks_3)
node _alloc_way_T_3 = xor(_alloc_way_T_2, alloc_way_chunks_4)
node _alloc_way_T_4 = xor(_alloc_way_T_3, alloc_way_chunks_5)
node _alloc_way_T_5 = xor(_alloc_way_T_4, alloc_way_chunks_6)
node _alloc_way_T_6 = xor(_alloc_way_T_5, alloc_way_chunks_7)
node _alloc_way_T_7 = xor(_alloc_way_T_6, alloc_way_chunks_8)
node _alloc_way_T_8 = xor(_alloc_way_T_7, alloc_way_chunks_9)
node _alloc_way_T_9 = xor(_alloc_way_T_8, alloc_way_chunks_10)
node _alloc_way_T_10 = xor(_alloc_way_T_9, alloc_way_chunks_11)
node _alloc_way_T_11 = xor(_alloc_way_T_10, alloc_way_chunks_12)
node _alloc_way_T_12 = xor(_alloc_way_T_11, alloc_way_chunks_13)
node _alloc_way_T_13 = xor(_alloc_way_T_12, alloc_way_chunks_14)
node _alloc_way_T_14 = xor(_alloc_way_T_13, alloc_way_chunks_15)
node _alloc_way_T_15 = xor(_alloc_way_T_14, alloc_way_chunks_16)
node _alloc_way_T_16 = xor(_alloc_way_T_15, alloc_way_chunks_17)
node _alloc_way_T_17 = xor(_alloc_way_T_16, alloc_way_chunks_18)
node _alloc_way_T_18 = xor(_alloc_way_T_17, alloc_way_chunks_19)
node _alloc_way_T_19 = xor(_alloc_way_T_18, alloc_way_chunks_20)
node _alloc_way_T_20 = xor(_alloc_way_T_19, alloc_way_chunks_21)
node _alloc_way_T_21 = xor(_alloc_way_T_20, alloc_way_chunks_22)
node _alloc_way_T_22 = xor(_alloc_way_T_21, alloc_way_chunks_23)
node _alloc_way_T_23 = xor(_alloc_way_T_22, alloc_way_chunks_24)
node _alloc_way_T_24 = xor(_alloc_way_T_23, alloc_way_chunks_25)
node _alloc_way_T_25 = xor(_alloc_way_T_24, alloc_way_chunks_26)
node _alloc_way_T_26 = xor(_alloc_way_T_25, alloc_way_chunks_27)
node _alloc_way_T_27 = xor(_alloc_way_T_26, alloc_way_chunks_28)
node _alloc_way_T_28 = xor(_alloc_way_T_27, alloc_way_chunks_29)
node _alloc_way_T_29 = xor(_alloc_way_T_28, alloc_way_chunks_30)
node _alloc_way_T_30 = xor(_alloc_way_T_29, alloc_way_chunks_31)
node _alloc_way_T_31 = xor(_alloc_way_T_30, alloc_way_chunks_32)
node _alloc_way_T_32 = xor(_alloc_way_T_31, alloc_way_chunks_33)
node _alloc_way_T_33 = xor(_alloc_way_T_32, alloc_way_chunks_34)
node _alloc_way_T_34 = xor(_alloc_way_T_33, alloc_way_chunks_35)
node _alloc_way_T_35 = xor(_alloc_way_T_34, alloc_way_chunks_36)
node _alloc_way_T_36 = xor(_alloc_way_T_35, alloc_way_chunks_37)
node _alloc_way_T_37 = xor(_alloc_way_T_36, alloc_way_chunks_38)
node _alloc_way_T_38 = xor(_alloc_way_T_37, alloc_way_chunks_39)
node _alloc_way_T_39 = xor(_alloc_way_T_38, alloc_way_chunks_40)
node _alloc_way_T_40 = xor(_alloc_way_T_39, alloc_way_chunks_41)
node _alloc_way_T_41 = xor(_alloc_way_T_40, alloc_way_chunks_42)
node _alloc_way_T_42 = xor(_alloc_way_T_41, alloc_way_chunks_43)
node _alloc_way_T_43 = xor(_alloc_way_T_42, alloc_way_chunks_44)
node _alloc_way_T_44 = xor(_alloc_way_T_43, alloc_way_chunks_45)
node _alloc_way_T_45 = xor(_alloc_way_T_44, alloc_way_chunks_46)
node _alloc_way_T_46 = xor(_alloc_way_T_45, alloc_way_chunks_47)
node _alloc_way_T_47 = xor(_alloc_way_T_46, alloc_way_chunks_48)
node _alloc_way_T_48 = xor(_alloc_way_T_47, alloc_way_chunks_49)
node _alloc_way_T_49 = xor(_alloc_way_T_48, alloc_way_chunks_50)
node _alloc_way_T_50 = xor(_alloc_way_T_49, alloc_way_chunks_51)
node _alloc_way_T_51 = xor(_alloc_way_T_50, alloc_way_chunks_52)
node _alloc_way_T_52 = xor(_alloc_way_T_51, alloc_way_chunks_53)
node _alloc_way_T_53 = xor(_alloc_way_T_52, alloc_way_chunks_54)
node _alloc_way_T_54 = xor(_alloc_way_T_53, alloc_way_chunks_55)
node _alloc_way_T_55 = xor(_alloc_way_T_54, alloc_way_chunks_56)
node _alloc_way_T_56 = xor(_alloc_way_T_55, alloc_way_chunks_57)
node _alloc_way_T_57 = xor(_alloc_way_T_56, alloc_way_chunks_58)
node _alloc_way_T_58 = xor(_alloc_way_T_57, alloc_way_chunks_59)
node _alloc_way_T_59 = xor(_alloc_way_T_58, alloc_way_chunks_60)
node _alloc_way_T_60 = xor(_alloc_way_T_59, alloc_way_chunks_61)
node _alloc_way_T_61 = xor(_alloc_way_T_60, alloc_way_chunks_62)
node _alloc_way_T_62 = xor(_alloc_way_T_61, alloc_way_chunks_63)
node _alloc_way_T_63 = xor(_alloc_way_T_62, alloc_way_chunks_64)
node _alloc_way_T_64 = xor(_alloc_way_T_63, alloc_way_chunks_65)
node _alloc_way_T_65 = xor(_alloc_way_T_64, alloc_way_chunks_66)
node _alloc_way_T_66 = xor(_alloc_way_T_65, alloc_way_chunks_67)
node _alloc_way_T_67 = xor(_alloc_way_T_66, alloc_way_chunks_68)
node _alloc_way_T_68 = xor(_alloc_way_T_67, alloc_way_chunks_69)
node _alloc_way_T_69 = xor(_alloc_way_T_68, alloc_way_chunks_70)
node _alloc_way_T_70 = xor(_alloc_way_T_69, alloc_way_chunks_71)
node _alloc_way_T_71 = xor(_alloc_way_T_70, alloc_way_chunks_72)
node _alloc_way_T_72 = xor(_alloc_way_T_71, alloc_way_chunks_73)
node _alloc_way_T_73 = xor(_alloc_way_T_72, alloc_way_chunks_74)
node _alloc_way_T_74 = xor(_alloc_way_T_73, alloc_way_chunks_75)
node _alloc_way_T_75 = xor(_alloc_way_T_74, alloc_way_chunks_76)
node _alloc_way_T_76 = xor(_alloc_way_T_75, alloc_way_chunks_77)
node _alloc_way_T_77 = xor(_alloc_way_T_76, alloc_way_chunks_78)
node _alloc_way_T_78 = xor(_alloc_way_T_77, alloc_way_chunks_79)
node _alloc_way_T_79 = xor(_alloc_way_T_78, alloc_way_chunks_80)
node _alloc_way_T_80 = xor(_alloc_way_T_79, alloc_way_chunks_81)
node _alloc_way_T_81 = xor(_alloc_way_T_80, alloc_way_chunks_82)
node _alloc_way_T_82 = xor(_alloc_way_T_81, alloc_way_chunks_83)
node _alloc_way_T_83 = xor(_alloc_way_T_82, alloc_way_chunks_84)
node _alloc_way_T_84 = xor(_alloc_way_T_83, alloc_way_chunks_85)
node _alloc_way_T_85 = xor(_alloc_way_T_84, alloc_way_chunks_86)
node _alloc_way_T_86 = xor(_alloc_way_T_85, alloc_way_chunks_87)
node _alloc_way_T_87 = xor(_alloc_way_T_86, alloc_way_chunks_88)
node _alloc_way_T_88 = xor(_alloc_way_T_87, alloc_way_chunks_89)
node _alloc_way_T_89 = xor(_alloc_way_T_88, alloc_way_chunks_90)
node _alloc_way_T_90 = xor(_alloc_way_T_89, alloc_way_chunks_91)
node _alloc_way_T_91 = xor(_alloc_way_T_90, alloc_way_chunks_92)
node _alloc_way_T_92 = xor(_alloc_way_T_91, alloc_way_chunks_93)
node _alloc_way_T_93 = xor(_alloc_way_T_92, alloc_way_chunks_94)
node _alloc_way_T_94 = xor(_alloc_way_T_93, alloc_way_chunks_95)
node _alloc_way_T_95 = xor(_alloc_way_T_94, alloc_way_chunks_96)
node _alloc_way_T_96 = xor(_alloc_way_T_95, alloc_way_chunks_97)
node _alloc_way_T_97 = xor(_alloc_way_T_96, alloc_way_chunks_98)
node _alloc_way_T_98 = xor(_alloc_way_T_97, alloc_way_chunks_99)
node _alloc_way_T_99 = xor(_alloc_way_T_98, alloc_way_chunks_100)
node _alloc_way_T_100 = xor(_alloc_way_T_99, alloc_way_chunks_101)
node _alloc_way_T_101 = xor(_alloc_way_T_100, alloc_way_chunks_102)
node _alloc_way_T_102 = xor(_alloc_way_T_101, alloc_way_chunks_103)
node _alloc_way_T_103 = xor(_alloc_way_T_102, alloc_way_chunks_104)
node _alloc_way_T_104 = xor(_alloc_way_T_103, alloc_way_chunks_105)
node _alloc_way_T_105 = xor(_alloc_way_T_104, alloc_way_chunks_106)
node _alloc_way_T_106 = xor(_alloc_way_T_105, alloc_way_chunks_107)
node _alloc_way_T_107 = xor(_alloc_way_T_106, alloc_way_chunks_108)
node _alloc_way_T_108 = xor(_alloc_way_T_107, alloc_way_chunks_109)
node _alloc_way_T_109 = xor(_alloc_way_T_108, alloc_way_chunks_110)
node _alloc_way_T_110 = xor(_alloc_way_T_109, alloc_way_chunks_111)
node _alloc_way_T_111 = xor(_alloc_way_T_110, alloc_way_chunks_112)
node _alloc_way_T_112 = xor(_alloc_way_T_111, alloc_way_chunks_113)
node _alloc_way_T_113 = xor(_alloc_way_T_112, alloc_way_chunks_114)
node _alloc_way_T_114 = xor(_alloc_way_T_113, alloc_way_chunks_115)
node _alloc_way_T_115 = xor(_alloc_way_T_114, alloc_way_chunks_116)
node _alloc_way_T_116 = xor(_alloc_way_T_115, alloc_way_chunks_117)
node _alloc_way_T_117 = xor(_alloc_way_T_116, alloc_way_chunks_118)
node _alloc_way_T_118 = xor(_alloc_way_T_117, alloc_way_chunks_119)
node _alloc_way_T_119 = xor(_alloc_way_T_118, alloc_way_chunks_120)
node _alloc_way_T_120 = xor(_alloc_way_T_119, alloc_way_chunks_121)
node _alloc_way_T_121 = xor(_alloc_way_T_120, alloc_way_chunks_122)
node _alloc_way_T_122 = xor(_alloc_way_T_121, alloc_way_chunks_123)
node _alloc_way_T_123 = xor(_alloc_way_T_122, alloc_way_chunks_124)
node _alloc_way_T_124 = xor(_alloc_way_T_123, alloc_way_chunks_125)
node _alloc_way_T_125 = xor(_alloc_way_T_124, alloc_way_chunks_126)
node _alloc_way_T_126 = xor(_alloc_way_T_125, alloc_way_chunks_127)
node _alloc_way_T_127 = xor(_alloc_way_T_126, alloc_way_chunks_128)
node _alloc_way_T_128 = xor(_alloc_way_T_127, alloc_way_chunks_129)
node _alloc_way_T_129 = xor(_alloc_way_T_128, alloc_way_chunks_130)
node _alloc_way_T_130 = xor(_alloc_way_T_129, alloc_way_chunks_131)
node _alloc_way_T_131 = xor(_alloc_way_T_130, alloc_way_chunks_132)
node _alloc_way_T_132 = xor(_alloc_way_T_131, alloc_way_chunks_133)
node _alloc_way_T_133 = xor(_alloc_way_T_132, alloc_way_chunks_134)
node _alloc_way_T_134 = xor(_alloc_way_T_133, alloc_way_chunks_135)
node _alloc_way_T_135 = xor(_alloc_way_T_134, alloc_way_chunks_136)
node _alloc_way_T_136 = xor(_alloc_way_T_135, alloc_way_chunks_137)
node _alloc_way_T_137 = xor(_alloc_way_T_136, alloc_way_chunks_138)
node _alloc_way_T_138 = xor(_alloc_way_T_137, alloc_way_chunks_139)
node _alloc_way_T_139 = xor(_alloc_way_T_138, alloc_way_chunks_140)
node _alloc_way_T_140 = xor(_alloc_way_T_139, alloc_way_chunks_141)
node _alloc_way_T_141 = xor(_alloc_way_T_140, alloc_way_chunks_142)
node _alloc_way_T_142 = xor(_alloc_way_T_141, alloc_way_chunks_143)
node _alloc_way_T_143 = xor(_alloc_way_T_142, alloc_way_chunks_144)
node _alloc_way_T_144 = xor(_alloc_way_T_143, alloc_way_chunks_145)
node _alloc_way_T_145 = xor(_alloc_way_T_144, alloc_way_chunks_146)
node _alloc_way_T_146 = xor(_alloc_way_T_145, alloc_way_chunks_147)
node _alloc_way_T_147 = xor(_alloc_way_T_146, alloc_way_chunks_148)
node _alloc_way_T_148 = xor(_alloc_way_T_147, alloc_way_chunks_149)
node _alloc_way_T_149 = xor(_alloc_way_T_148, alloc_way_chunks_150)
node _alloc_way_T_150 = xor(_alloc_way_T_149, alloc_way_chunks_151)
node _alloc_way_T_151 = xor(_alloc_way_T_150, alloc_way_chunks_152)
node _alloc_way_T_152 = xor(_alloc_way_T_151, alloc_way_chunks_153)
node _alloc_way_T_153 = xor(_alloc_way_T_152, alloc_way_chunks_154)
node _alloc_way_T_154 = xor(_alloc_way_T_153, alloc_way_chunks_155)
node _alloc_way_T_155 = xor(_alloc_way_T_154, alloc_way_chunks_156)
node _alloc_way_T_156 = xor(_alloc_way_T_155, alloc_way_chunks_157)
node _alloc_way_T_157 = xor(_alloc_way_T_156, alloc_way_chunks_158)
node _alloc_way_T_158 = xor(_alloc_way_T_157, alloc_way_chunks_159)
node _alloc_way_T_159 = xor(_alloc_way_T_158, alloc_way_chunks_160)
node _alloc_way_T_160 = xor(_alloc_way_T_159, alloc_way_chunks_161)
node _alloc_way_T_161 = xor(_alloc_way_T_160, alloc_way_chunks_162)
node _alloc_way_T_162 = xor(_alloc_way_T_161, alloc_way_chunks_163)
node _alloc_way_T_163 = xor(_alloc_way_T_162, alloc_way_chunks_164)
node _alloc_way_T_164 = xor(_alloc_way_T_163, alloc_way_chunks_165)
node _alloc_way_T_165 = xor(_alloc_way_T_164, alloc_way_chunks_166)
node _alloc_way_T_166 = xor(_alloc_way_T_165, alloc_way_chunks_167)
node _alloc_way_T_167 = xor(_alloc_way_T_166, alloc_way_chunks_168)
node _alloc_way_T_168 = xor(_alloc_way_T_167, alloc_way_chunks_169)
node _alloc_way_T_169 = xor(_alloc_way_T_168, alloc_way_chunks_170)
node _alloc_way_T_170 = xor(_alloc_way_T_169, alloc_way_chunks_171)
node _alloc_way_T_171 = xor(_alloc_way_T_170, alloc_way_chunks_172)
node _alloc_way_T_172 = xor(_alloc_way_T_171, alloc_way_chunks_173)
node _alloc_way_T_173 = xor(_alloc_way_T_172, alloc_way_chunks_174)
node _alloc_way_T_174 = xor(_alloc_way_T_173, alloc_way_chunks_175)
node _alloc_way_T_175 = xor(_alloc_way_T_174, alloc_way_chunks_176)
node _alloc_way_T_176 = xor(_alloc_way_T_175, alloc_way_chunks_177)
node _alloc_way_T_177 = xor(_alloc_way_T_176, alloc_way_chunks_178)
node _alloc_way_T_178 = xor(_alloc_way_T_177, alloc_way_chunks_179)
node _alloc_way_T_179 = xor(_alloc_way_T_178, alloc_way_chunks_180)
node _alloc_way_T_180 = xor(_alloc_way_T_179, alloc_way_chunks_181)
node _alloc_way_T_181 = xor(_alloc_way_T_180, alloc_way_chunks_182)
node _alloc_way_T_182 = xor(_alloc_way_T_181, alloc_way_chunks_183)
node _alloc_way_T_183 = xor(_alloc_way_T_182, alloc_way_chunks_184)
node _alloc_way_T_184 = xor(_alloc_way_T_183, alloc_way_chunks_185)
node _alloc_way_T_185 = xor(_alloc_way_T_184, alloc_way_chunks_186)
node _alloc_way_T_186 = xor(_alloc_way_T_185, alloc_way_chunks_187)
node _alloc_way_T_187 = xor(_alloc_way_T_186, alloc_way_chunks_188)
node _alloc_way_T_188 = xor(_alloc_way_T_187, alloc_way_chunks_189)
node _alloc_way_T_189 = xor(_alloc_way_T_188, alloc_way_chunks_190)
node _alloc_way_T_190 = xor(_alloc_way_T_189, alloc_way_chunks_191)
node _alloc_way_T_191 = xor(_alloc_way_T_190, alloc_way_chunks_192)
node _alloc_way_T_192 = xor(_alloc_way_T_191, alloc_way_chunks_193)
node _alloc_way_T_193 = xor(_alloc_way_T_192, alloc_way_chunks_194)
node _alloc_way_T_194 = xor(_alloc_way_T_193, alloc_way_chunks_195)
node _alloc_way_T_195 = xor(_alloc_way_T_194, alloc_way_chunks_196)
node _alloc_way_T_196 = xor(_alloc_way_T_195, alloc_way_chunks_197)
node _alloc_way_T_197 = xor(_alloc_way_T_196, alloc_way_chunks_198)
node _alloc_way_T_198 = xor(_alloc_way_T_197, alloc_way_chunks_199)
node _alloc_way_T_199 = xor(_alloc_way_T_198, alloc_way_chunks_200)
node _alloc_way_T_200 = xor(_alloc_way_T_199, alloc_way_chunks_201)
node _alloc_way_T_201 = xor(_alloc_way_T_200, alloc_way_chunks_202)
node _alloc_way_T_202 = xor(_alloc_way_T_201, alloc_way_chunks_203)
node _alloc_way_T_203 = xor(_alloc_way_T_202, alloc_way_chunks_204)
node _alloc_way_T_204 = xor(_alloc_way_T_203, alloc_way_chunks_205)
node _alloc_way_T_205 = xor(_alloc_way_T_204, alloc_way_chunks_206)
node _alloc_way_T_206 = xor(_alloc_way_T_205, alloc_way_chunks_207)
node _alloc_way_T_207 = xor(_alloc_way_T_206, alloc_way_chunks_208)
node _alloc_way_T_208 = xor(_alloc_way_T_207, alloc_way_chunks_209)
node _alloc_way_T_209 = xor(_alloc_way_T_208, alloc_way_chunks_210)
node _alloc_way_T_210 = xor(_alloc_way_T_209, alloc_way_chunks_211)
node _alloc_way_T_211 = xor(_alloc_way_T_210, alloc_way_chunks_212)
node _alloc_way_T_212 = xor(_alloc_way_T_211, alloc_way_chunks_213)
node _alloc_way_T_213 = xor(_alloc_way_T_212, alloc_way_chunks_214)
node _alloc_way_T_214 = xor(_alloc_way_T_213, alloc_way_chunks_215)
node _alloc_way_T_215 = xor(_alloc_way_T_214, alloc_way_chunks_216)
node _alloc_way_T_216 = xor(_alloc_way_T_215, alloc_way_chunks_217)
node _alloc_way_T_217 = xor(_alloc_way_T_216, alloc_way_chunks_218)
node _alloc_way_T_218 = xor(_alloc_way_T_217, alloc_way_chunks_219)
node _alloc_way_T_219 = xor(_alloc_way_T_218, alloc_way_chunks_220)
node _alloc_way_T_220 = xor(_alloc_way_T_219, alloc_way_chunks_221)
node _alloc_way_T_221 = xor(_alloc_way_T_220, alloc_way_chunks_222)
node _alloc_way_T_222 = xor(_alloc_way_T_221, alloc_way_chunks_223)
node _alloc_way_T_223 = xor(_alloc_way_T_222, alloc_way_chunks_224)
node _alloc_way_T_224 = xor(_alloc_way_T_223, alloc_way_chunks_225)
node _alloc_way_T_225 = xor(_alloc_way_T_224, alloc_way_chunks_226)
node _alloc_way_T_226 = xor(_alloc_way_T_225, alloc_way_chunks_227)
node _alloc_way_T_227 = xor(_alloc_way_T_226, alloc_way_chunks_228)
node _alloc_way_T_228 = xor(_alloc_way_T_227, alloc_way_chunks_229)
node _alloc_way_T_229 = xor(_alloc_way_T_228, alloc_way_chunks_230)
node _alloc_way_T_230 = xor(_alloc_way_T_229, alloc_way_chunks_231)
node _alloc_way_T_231 = xor(_alloc_way_T_230, alloc_way_chunks_232)
node _alloc_way_T_232 = xor(_alloc_way_T_231, alloc_way_chunks_233)
node _alloc_way_T_233 = xor(_alloc_way_T_232, alloc_way_chunks_234)
node _alloc_way_T_234 = xor(_alloc_way_T_233, alloc_way_chunks_235)
node _alloc_way_T_235 = xor(_alloc_way_T_234, alloc_way_chunks_236)
node _alloc_way_T_236 = xor(_alloc_way_T_235, alloc_way_chunks_237)
node _alloc_way_T_237 = xor(_alloc_way_T_236, alloc_way_chunks_238)
node _alloc_way_T_238 = xor(_alloc_way_T_237, alloc_way_chunks_239)
node _alloc_way_T_239 = xor(_alloc_way_T_238, alloc_way_chunks_240)
node _alloc_way_T_240 = xor(_alloc_way_T_239, alloc_way_chunks_241)
node _alloc_way_T_241 = xor(_alloc_way_T_240, alloc_way_chunks_242)
node _alloc_way_T_242 = xor(_alloc_way_T_241, alloc_way_chunks_243)
node _alloc_way_T_243 = xor(_alloc_way_T_242, alloc_way_chunks_244)
node _alloc_way_T_244 = xor(_alloc_way_T_243, alloc_way_chunks_245)
node _alloc_way_T_245 = xor(_alloc_way_T_244, alloc_way_chunks_246)
node _alloc_way_T_246 = xor(_alloc_way_T_245, alloc_way_chunks_247)
node _alloc_way_T_247 = xor(_alloc_way_T_246, alloc_way_chunks_248)
node _alloc_way_T_248 = xor(_alloc_way_T_247, alloc_way_chunks_249)
node _alloc_way_T_249 = xor(_alloc_way_T_248, alloc_way_chunks_250)
node _alloc_way_T_250 = xor(_alloc_way_T_249, alloc_way_chunks_251)
node _alloc_way_T_251 = xor(_alloc_way_T_250, alloc_way_chunks_252)
node _alloc_way_T_252 = xor(_alloc_way_T_251, alloc_way_chunks_253)
node _alloc_way_T_253 = xor(_alloc_way_T_252, alloc_way_chunks_254)
node _alloc_way_T_254 = xor(_alloc_way_T_253, alloc_way_chunks_255)
node _alloc_way_T_255 = xor(_alloc_way_T_254, alloc_way_chunks_256)
node _alloc_way_T_256 = xor(_alloc_way_T_255, alloc_way_chunks_257)
node _alloc_way_T_257 = xor(_alloc_way_T_256, alloc_way_chunks_258)
node _alloc_way_T_258 = xor(_alloc_way_T_257, alloc_way_chunks_259)
node _alloc_way_T_259 = xor(_alloc_way_T_258, alloc_way_chunks_260)
node _alloc_way_T_260 = xor(_alloc_way_T_259, alloc_way_chunks_261)
node _alloc_way_T_261 = xor(_alloc_way_T_260, alloc_way_chunks_262)
node _alloc_way_T_262 = xor(_alloc_way_T_261, alloc_way_chunks_263)
node _alloc_way_T_263 = xor(_alloc_way_T_262, alloc_way_chunks_264)
node _alloc_way_T_264 = xor(_alloc_way_T_263, alloc_way_chunks_265)
node _alloc_way_T_265 = xor(_alloc_way_T_264, alloc_way_chunks_266)
node _alloc_way_T_266 = xor(_alloc_way_T_265, alloc_way_chunks_267)
node _alloc_way_T_267 = xor(_alloc_way_T_266, alloc_way_chunks_268)
node _alloc_way_T_268 = xor(_alloc_way_T_267, alloc_way_chunks_269)
node _alloc_way_T_269 = xor(_alloc_way_T_268, alloc_way_chunks_270)
node _alloc_way_T_270 = xor(_alloc_way_T_269, alloc_way_chunks_271)
node _alloc_way_T_271 = xor(_alloc_way_T_270, alloc_way_chunks_272)
node _alloc_way_T_272 = xor(_alloc_way_T_271, alloc_way_chunks_273)
node _alloc_way_T_273 = xor(_alloc_way_T_272, alloc_way_chunks_274)
node _alloc_way_T_274 = xor(_alloc_way_T_273, alloc_way_chunks_275)
node _alloc_way_T_275 = xor(_alloc_way_T_274, alloc_way_chunks_276)
node _alloc_way_T_276 = xor(_alloc_way_T_275, alloc_way_chunks_277)
node _alloc_way_T_277 = xor(_alloc_way_T_276, alloc_way_chunks_278)
node _alloc_way_T_278 = xor(_alloc_way_T_277, alloc_way_chunks_279)
node _alloc_way_T_279 = xor(_alloc_way_T_278, alloc_way_chunks_280)
node _alloc_way_T_280 = xor(_alloc_way_T_279, alloc_way_chunks_281)
node _alloc_way_T_281 = xor(_alloc_way_T_280, alloc_way_chunks_282)
node _alloc_way_T_282 = xor(_alloc_way_T_281, alloc_way_chunks_283)
node _alloc_way_T_283 = xor(_alloc_way_T_282, alloc_way_chunks_284)
node _alloc_way_T_284 = xor(_alloc_way_T_283, alloc_way_chunks_285)
node _alloc_way_T_285 = xor(_alloc_way_T_284, alloc_way_chunks_286)
node _alloc_way_T_286 = xor(_alloc_way_T_285, alloc_way_chunks_287)
node _alloc_way_T_287 = xor(_alloc_way_T_286, alloc_way_chunks_288)
node _alloc_way_T_288 = xor(_alloc_way_T_287, alloc_way_chunks_289)
node _alloc_way_T_289 = xor(_alloc_way_T_288, alloc_way_chunks_290)
node _alloc_way_T_290 = xor(_alloc_way_T_289, alloc_way_chunks_291)
node _alloc_way_T_291 = xor(_alloc_way_T_290, alloc_way_chunks_292)
node _alloc_way_T_292 = xor(_alloc_way_T_291, alloc_way_chunks_293)
node _alloc_way_T_293 = xor(_alloc_way_T_292, alloc_way_chunks_294)
node _alloc_way_T_294 = xor(_alloc_way_T_293, alloc_way_chunks_295)
node _alloc_way_T_295 = xor(_alloc_way_T_294, alloc_way_chunks_296)
node _alloc_way_T_296 = xor(_alloc_way_T_295, alloc_way_chunks_297)
node _alloc_way_T_297 = xor(_alloc_way_T_296, alloc_way_chunks_298)
node _alloc_way_T_298 = xor(_alloc_way_T_297, alloc_way_chunks_299)
node _alloc_way_T_299 = xor(_alloc_way_T_298, alloc_way_chunks_300)
node _alloc_way_T_300 = xor(_alloc_way_T_299, alloc_way_chunks_301)
node _alloc_way_T_301 = xor(_alloc_way_T_300, alloc_way_chunks_302)
node _alloc_way_T_302 = xor(_alloc_way_T_301, alloc_way_chunks_303)
node _alloc_way_T_303 = xor(_alloc_way_T_302, alloc_way_chunks_304)
node _alloc_way_T_304 = xor(_alloc_way_T_303, alloc_way_chunks_305)
node _alloc_way_T_305 = xor(_alloc_way_T_304, alloc_way_chunks_306)
node _alloc_way_T_306 = xor(_alloc_way_T_305, alloc_way_chunks_307)
node _alloc_way_T_307 = xor(_alloc_way_T_306, alloc_way_chunks_308)
node _alloc_way_T_308 = xor(_alloc_way_T_307, alloc_way_chunks_309)
node _alloc_way_T_309 = xor(_alloc_way_T_308, alloc_way_chunks_310)
node _alloc_way_T_310 = xor(_alloc_way_T_309, alloc_way_chunks_311)
node _alloc_way_T_311 = xor(_alloc_way_T_310, alloc_way_chunks_312)
node _alloc_way_T_312 = xor(_alloc_way_T_311, alloc_way_chunks_313)
node _alloc_way_T_313 = xor(_alloc_way_T_312, alloc_way_chunks_314)
node _alloc_way_T_314 = xor(_alloc_way_T_313, alloc_way_chunks_315)
node _alloc_way_T_315 = xor(_alloc_way_T_314, alloc_way_chunks_316)
node _alloc_way_T_316 = xor(_alloc_way_T_315, alloc_way_chunks_317)
node _alloc_way_T_317 = xor(_alloc_way_T_316, alloc_way_chunks_318)
node _alloc_way_T_318 = xor(_alloc_way_T_317, alloc_way_chunks_319)
node _alloc_way_T_319 = xor(_alloc_way_T_318, alloc_way_chunks_320)
node _alloc_way_T_320 = xor(_alloc_way_T_319, alloc_way_chunks_321)
node _alloc_way_T_321 = xor(_alloc_way_T_320, alloc_way_chunks_322)
node _alloc_way_T_322 = xor(_alloc_way_T_321, alloc_way_chunks_323)
node _alloc_way_T_323 = xor(_alloc_way_T_322, alloc_way_chunks_324)
node _alloc_way_T_324 = xor(_alloc_way_T_323, alloc_way_chunks_325)
node _alloc_way_T_325 = xor(_alloc_way_T_324, alloc_way_chunks_326)
node _alloc_way_T_326 = xor(_alloc_way_T_325, alloc_way_chunks_327)
node _alloc_way_T_327 = xor(_alloc_way_T_326, alloc_way_chunks_328)
node _alloc_way_T_328 = xor(_alloc_way_T_327, alloc_way_chunks_329)
node _alloc_way_T_329 = xor(_alloc_way_T_328, alloc_way_chunks_330)
node _alloc_way_T_330 = xor(_alloc_way_T_329, alloc_way_chunks_331)
node _alloc_way_T_331 = xor(_alloc_way_T_330, alloc_way_chunks_332)
node _alloc_way_T_332 = xor(_alloc_way_T_331, alloc_way_chunks_333)
node _alloc_way_T_333 = xor(_alloc_way_T_332, alloc_way_chunks_334)
node _alloc_way_T_334 = xor(_alloc_way_T_333, alloc_way_chunks_335)
node _alloc_way_T_335 = xor(_alloc_way_T_334, alloc_way_chunks_336)
node _alloc_way_T_336 = xor(_alloc_way_T_335, alloc_way_chunks_337)
node _alloc_way_T_337 = xor(_alloc_way_T_336, alloc_way_chunks_338)
node _alloc_way_T_338 = xor(_alloc_way_T_337, alloc_way_chunks_339)
node _alloc_way_T_339 = xor(_alloc_way_T_338, alloc_way_chunks_340)
node _alloc_way_T_340 = xor(_alloc_way_T_339, alloc_way_chunks_341)
node _alloc_way_T_341 = xor(_alloc_way_T_340, alloc_way_chunks_342)
node _alloc_way_T_342 = xor(_alloc_way_T_341, alloc_way_chunks_343)
node _alloc_way_T_343 = xor(_alloc_way_T_342, alloc_way_chunks_344)
node _alloc_way_T_344 = xor(_alloc_way_T_343, alloc_way_chunks_345)
node _alloc_way_T_345 = xor(_alloc_way_T_344, alloc_way_chunks_346)
node _alloc_way_T_346 = xor(_alloc_way_T_345, alloc_way_chunks_347)
node _alloc_way_T_347 = xor(_alloc_way_T_346, alloc_way_chunks_348)
node _alloc_way_T_348 = xor(_alloc_way_T_347, alloc_way_chunks_349)
node _alloc_way_T_349 = xor(_alloc_way_T_348, alloc_way_chunks_350)
node _alloc_way_T_350 = xor(_alloc_way_T_349, alloc_way_chunks_351)
node _alloc_way_T_351 = xor(_alloc_way_T_350, alloc_way_chunks_352)
node _alloc_way_T_352 = xor(_alloc_way_T_351, alloc_way_chunks_353)
node _alloc_way_T_353 = xor(_alloc_way_T_352, alloc_way_chunks_354)
node _alloc_way_T_354 = xor(_alloc_way_T_353, alloc_way_chunks_355)
node _alloc_way_T_355 = xor(_alloc_way_T_354, alloc_way_chunks_356)
node _alloc_way_T_356 = xor(_alloc_way_T_355, alloc_way_chunks_357)
node _alloc_way_T_357 = xor(_alloc_way_T_356, alloc_way_chunks_358)
node _alloc_way_T_358 = xor(_alloc_way_T_357, alloc_way_chunks_359)
node _alloc_way_T_359 = xor(_alloc_way_T_358, alloc_way_chunks_360)
node _alloc_way_T_360 = xor(_alloc_way_T_359, alloc_way_chunks_361)
node _alloc_way_T_361 = xor(_alloc_way_T_360, alloc_way_chunks_362)
node _alloc_way_T_362 = xor(_alloc_way_T_361, alloc_way_chunks_363)
node _alloc_way_T_363 = xor(_alloc_way_T_362, alloc_way_chunks_364)
node _alloc_way_T_364 = xor(_alloc_way_T_363, alloc_way_chunks_365)
node _alloc_way_T_365 = xor(_alloc_way_T_364, alloc_way_chunks_366)
node _alloc_way_T_366 = xor(_alloc_way_T_365, alloc_way_chunks_367)
node _alloc_way_T_367 = xor(_alloc_way_T_366, alloc_way_chunks_368)
node _alloc_way_T_368 = xor(_alloc_way_T_367, alloc_way_chunks_369)
node _alloc_way_T_369 = xor(_alloc_way_T_368, alloc_way_chunks_370)
node _alloc_way_T_370 = xor(_alloc_way_T_369, alloc_way_chunks_371)
node _alloc_way_T_371 = xor(_alloc_way_T_370, alloc_way_chunks_372)
node _alloc_way_T_372 = xor(_alloc_way_T_371, alloc_way_chunks_373)
node _alloc_way_T_373 = xor(_alloc_way_T_372, alloc_way_chunks_374)
node _alloc_way_T_374 = xor(_alloc_way_T_373, alloc_way_chunks_375)
node _alloc_way_T_375 = xor(_alloc_way_T_374, alloc_way_chunks_376)
node _alloc_way_T_376 = xor(_alloc_way_T_375, alloc_way_chunks_377)
node _alloc_way_T_377 = xor(_alloc_way_T_376, alloc_way_chunks_378)
node _alloc_way_T_378 = xor(_alloc_way_T_377, alloc_way_chunks_379)
node _alloc_way_T_379 = xor(_alloc_way_T_378, alloc_way_chunks_380)
node _alloc_way_T_380 = xor(_alloc_way_T_379, alloc_way_chunks_381)
node _alloc_way_T_381 = xor(_alloc_way_T_380, alloc_way_chunks_382)
node _alloc_way_T_382 = xor(_alloc_way_T_381, alloc_way_chunks_383)
node _alloc_way_T_383 = xor(_alloc_way_T_382, alloc_way_chunks_384)
node _alloc_way_T_384 = xor(_alloc_way_T_383, alloc_way_chunks_385)
node _alloc_way_T_385 = xor(_alloc_way_T_384, alloc_way_chunks_386)
node _alloc_way_T_386 = xor(_alloc_way_T_385, alloc_way_chunks_387)
node _alloc_way_T_387 = xor(_alloc_way_T_386, alloc_way_chunks_388)
node _alloc_way_T_388 = xor(_alloc_way_T_387, alloc_way_chunks_389)
node _alloc_way_T_389 = xor(_alloc_way_T_388, alloc_way_chunks_390)
node _alloc_way_T_390 = xor(_alloc_way_T_389, alloc_way_chunks_391)
node _alloc_way_T_391 = xor(_alloc_way_T_390, alloc_way_chunks_392)
node _alloc_way_T_392 = xor(_alloc_way_T_391, alloc_way_chunks_393)
node _alloc_way_T_393 = xor(_alloc_way_T_392, alloc_way_chunks_394)
node _alloc_way_T_394 = xor(_alloc_way_T_393, alloc_way_chunks_395)
node _alloc_way_T_395 = xor(_alloc_way_T_394, alloc_way_chunks_396)
node _alloc_way_T_396 = xor(_alloc_way_T_395, alloc_way_chunks_397)
node _alloc_way_T_397 = xor(_alloc_way_T_396, alloc_way_chunks_398)
node _alloc_way_T_398 = xor(_alloc_way_T_397, alloc_way_chunks_399)
node _alloc_way_T_399 = xor(_alloc_way_T_398, alloc_way_chunks_400)
node _alloc_way_T_400 = xor(_alloc_way_T_399, alloc_way_chunks_401)
node _alloc_way_T_401 = xor(_alloc_way_T_400, alloc_way_chunks_402)
node _alloc_way_T_402 = xor(_alloc_way_T_401, alloc_way_chunks_403)
node _alloc_way_T_403 = xor(_alloc_way_T_402, alloc_way_chunks_404)
node _alloc_way_T_404 = xor(_alloc_way_T_403, alloc_way_chunks_405)
node _alloc_way_T_405 = xor(_alloc_way_T_404, alloc_way_chunks_406)
node _alloc_way_T_406 = xor(_alloc_way_T_405, alloc_way_chunks_407)
node _alloc_way_T_407 = xor(_alloc_way_T_406, alloc_way_chunks_408)
node _alloc_way_T_408 = xor(_alloc_way_T_407, alloc_way_chunks_409)
node _alloc_way_T_409 = xor(_alloc_way_T_408, alloc_way_chunks_410)
node _alloc_way_T_410 = xor(_alloc_way_T_409, alloc_way_chunks_411)
node _alloc_way_T_411 = xor(_alloc_way_T_410, alloc_way_chunks_412)
node _alloc_way_T_412 = xor(_alloc_way_T_411, alloc_way_chunks_413)
node _alloc_way_T_413 = xor(_alloc_way_T_412, alloc_way_chunks_414)
node _alloc_way_T_414 = xor(_alloc_way_T_413, alloc_way_chunks_415)
node _alloc_way_T_415 = xor(_alloc_way_T_414, alloc_way_chunks_416)
node _alloc_way_T_416 = xor(_alloc_way_T_415, alloc_way_chunks_417)
node _alloc_way_T_417 = xor(_alloc_way_T_416, alloc_way_chunks_418)
node _alloc_way_T_418 = xor(_alloc_way_T_417, alloc_way_chunks_419)
node _alloc_way_T_419 = xor(_alloc_way_T_418, alloc_way_chunks_420)
node _alloc_way_T_420 = xor(_alloc_way_T_419, alloc_way_chunks_421)
node _alloc_way_T_421 = xor(_alloc_way_T_420, alloc_way_chunks_422)
node _alloc_way_T_422 = xor(_alloc_way_T_421, alloc_way_chunks_423)
node _alloc_way_T_423 = xor(_alloc_way_T_422, alloc_way_chunks_424)
node _alloc_way_T_424 = xor(_alloc_way_T_423, alloc_way_chunks_425)
node _alloc_way_T_425 = xor(_alloc_way_T_424, alloc_way_chunks_426)
node _alloc_way_T_426 = xor(_alloc_way_T_425, alloc_way_chunks_427)
node _alloc_way_T_427 = xor(_alloc_way_T_426, alloc_way_chunks_428)
node _alloc_way_T_428 = xor(_alloc_way_T_427, alloc_way_chunks_429)
node _alloc_way_T_429 = xor(_alloc_way_T_428, alloc_way_chunks_430)
node _alloc_way_T_430 = xor(_alloc_way_T_429, alloc_way_chunks_431)
node _alloc_way_T_431 = xor(_alloc_way_T_430, alloc_way_chunks_432)
node _alloc_way_T_432 = xor(_alloc_way_T_431, alloc_way_chunks_433)
node _alloc_way_T_433 = xor(_alloc_way_T_432, alloc_way_chunks_434)
node _alloc_way_T_434 = xor(_alloc_way_T_433, alloc_way_chunks_435)
node _alloc_way_T_435 = xor(_alloc_way_T_434, alloc_way_chunks_436)
node _alloc_way_T_436 = xor(_alloc_way_T_435, alloc_way_chunks_437)
node _alloc_way_T_437 = xor(_alloc_way_T_436, alloc_way_chunks_438)
node _alloc_way_T_438 = xor(_alloc_way_T_437, alloc_way_chunks_439)
node _alloc_way_T_439 = xor(_alloc_way_T_438, alloc_way_chunks_440)
node _alloc_way_T_440 = xor(_alloc_way_T_439, alloc_way_chunks_441)
node _alloc_way_T_441 = xor(_alloc_way_T_440, alloc_way_chunks_442)
node _alloc_way_T_442 = xor(_alloc_way_T_441, alloc_way_chunks_443)
node _alloc_way_T_443 = xor(_alloc_way_T_442, alloc_way_chunks_444)
node _alloc_way_T_444 = xor(_alloc_way_T_443, alloc_way_chunks_445)
node _alloc_way_T_445 = xor(_alloc_way_T_444, alloc_way_chunks_446)
node _alloc_way_T_446 = xor(_alloc_way_T_445, alloc_way_chunks_447)
node _alloc_way_T_447 = xor(_alloc_way_T_446, alloc_way_chunks_448)
node _alloc_way_T_448 = xor(_alloc_way_T_447, alloc_way_chunks_449)
node _alloc_way_T_449 = xor(_alloc_way_T_448, alloc_way_chunks_450)
node _alloc_way_T_450 = xor(_alloc_way_T_449, alloc_way_chunks_451)
node _alloc_way_T_451 = xor(_alloc_way_T_450, alloc_way_chunks_452)
node _alloc_way_T_452 = xor(_alloc_way_T_451, alloc_way_chunks_453)
node _alloc_way_T_453 = xor(_alloc_way_T_452, alloc_way_chunks_454)
node _alloc_way_T_454 = xor(_alloc_way_T_453, alloc_way_chunks_455)
node _alloc_way_T_455 = xor(_alloc_way_T_454, alloc_way_chunks_456)
node _alloc_way_T_456 = xor(_alloc_way_T_455, alloc_way_chunks_457)
node _alloc_way_T_457 = xor(_alloc_way_T_456, alloc_way_chunks_458)
node _alloc_way_T_458 = xor(_alloc_way_T_457, alloc_way_chunks_459)
node _alloc_way_T_459 = xor(_alloc_way_T_458, alloc_way_chunks_460)
node _alloc_way_T_460 = xor(_alloc_way_T_459, alloc_way_chunks_461)
node _alloc_way_T_461 = xor(_alloc_way_T_460, alloc_way_chunks_462)
node _alloc_way_T_462 = xor(_alloc_way_T_461, alloc_way_chunks_463)
node _alloc_way_T_463 = xor(_alloc_way_T_462, alloc_way_chunks_464)
node _alloc_way_T_464 = xor(_alloc_way_T_463, alloc_way_chunks_465)
node _alloc_way_T_465 = xor(_alloc_way_T_464, alloc_way_chunks_466)
node _alloc_way_T_466 = xor(_alloc_way_T_465, alloc_way_chunks_467)
node _alloc_way_T_467 = xor(_alloc_way_T_466, alloc_way_chunks_468)
node _alloc_way_T_468 = xor(_alloc_way_T_467, alloc_way_chunks_469)
node _alloc_way_T_469 = xor(_alloc_way_T_468, alloc_way_chunks_470)
node _alloc_way_T_470 = xor(_alloc_way_T_469, alloc_way_chunks_471)
node _alloc_way_T_471 = xor(_alloc_way_T_470, alloc_way_chunks_472)
node _alloc_way_T_472 = xor(_alloc_way_T_471, alloc_way_chunks_473)
node _alloc_way_T_473 = xor(_alloc_way_T_472, alloc_way_chunks_474)
node _alloc_way_T_474 = xor(_alloc_way_T_473, alloc_way_chunks_475)
node _alloc_way_T_475 = xor(_alloc_way_T_474, alloc_way_chunks_476)
node _alloc_way_T_476 = xor(_alloc_way_T_475, alloc_way_chunks_477)
node _alloc_way_T_477 = xor(_alloc_way_T_476, alloc_way_chunks_478)
node _alloc_way_T_478 = xor(_alloc_way_T_477, alloc_way_chunks_479)
node _alloc_way_T_479 = xor(_alloc_way_T_478, alloc_way_chunks_480)
node _alloc_way_T_480 = xor(_alloc_way_T_479, alloc_way_chunks_481)
node _alloc_way_T_481 = xor(_alloc_way_T_480, alloc_way_chunks_482)
node _alloc_way_T_482 = xor(_alloc_way_T_481, alloc_way_chunks_483)
node _alloc_way_T_483 = xor(_alloc_way_T_482, alloc_way_chunks_484)
node _alloc_way_T_484 = xor(_alloc_way_T_483, alloc_way_chunks_485)
node _alloc_way_T_485 = xor(_alloc_way_T_484, alloc_way_chunks_486)
node _alloc_way_T_486 = xor(_alloc_way_T_485, alloc_way_chunks_487)
node _alloc_way_T_487 = xor(_alloc_way_T_486, alloc_way_chunks_488)
node _alloc_way_T_488 = xor(_alloc_way_T_487, alloc_way_chunks_489)
node _alloc_way_T_489 = xor(_alloc_way_T_488, alloc_way_chunks_490)
node _alloc_way_T_490 = xor(_alloc_way_T_489, alloc_way_chunks_491)
node _alloc_way_T_491 = xor(_alloc_way_T_490, alloc_way_chunks_492)
node _alloc_way_T_492 = xor(_alloc_way_T_491, alloc_way_chunks_493)
node _alloc_way_T_493 = xor(_alloc_way_T_492, alloc_way_chunks_494)
node _alloc_way_T_494 = xor(_alloc_way_T_493, alloc_way_chunks_495)
node _alloc_way_T_495 = xor(_alloc_way_T_494, alloc_way_chunks_496)
node _alloc_way_T_496 = xor(_alloc_way_T_495, alloc_way_chunks_497)
node _alloc_way_T_497 = xor(_alloc_way_T_496, alloc_way_chunks_498)
node _alloc_way_T_498 = xor(_alloc_way_T_497, alloc_way_chunks_499)
node _alloc_way_T_499 = xor(_alloc_way_T_498, alloc_way_chunks_500)
node _alloc_way_T_500 = xor(_alloc_way_T_499, alloc_way_chunks_501)
node _alloc_way_T_501 = xor(_alloc_way_T_500, alloc_way_chunks_502)
node _alloc_way_T_502 = xor(_alloc_way_T_501, alloc_way_chunks_503)
node _alloc_way_T_503 = xor(_alloc_way_T_502, alloc_way_chunks_504)
node _alloc_way_T_504 = xor(_alloc_way_T_503, alloc_way_chunks_505)
node _alloc_way_T_505 = xor(_alloc_way_T_504, alloc_way_chunks_506)
node _alloc_way_T_506 = xor(_alloc_way_T_505, alloc_way_chunks_507)
node _alloc_way_T_507 = xor(_alloc_way_T_506, alloc_way_chunks_508)
node _alloc_way_T_508 = xor(_alloc_way_T_507, alloc_way_chunks_509)
node _alloc_way_T_509 = xor(_alloc_way_T_508, alloc_way_chunks_510)
node _alloc_way_T_510 = xor(_alloc_way_T_509, alloc_way_chunks_511)
node _alloc_way_T_511 = xor(_alloc_way_T_510, alloc_way_chunks_512)
node _alloc_way_T_512 = xor(_alloc_way_T_511, alloc_way_chunks_513)
node _alloc_way_T_513 = xor(_alloc_way_T_512, alloc_way_chunks_514)
node _alloc_way_T_514 = xor(_alloc_way_T_513, alloc_way_chunks_515)
node _alloc_way_T_515 = xor(_alloc_way_T_514, alloc_way_chunks_516)
node _alloc_way_T_516 = xor(_alloc_way_T_515, alloc_way_chunks_517)
node _alloc_way_T_517 = xor(_alloc_way_T_516, alloc_way_chunks_518)
node _alloc_way_T_518 = xor(_alloc_way_T_517, alloc_way_chunks_519)
node _alloc_way_T_519 = xor(_alloc_way_T_518, alloc_way_chunks_520)
node _alloc_way_T_520 = xor(_alloc_way_T_519, alloc_way_chunks_521)
node _alloc_way_T_521 = xor(_alloc_way_T_520, alloc_way_chunks_522)
node _alloc_way_T_522 = xor(_alloc_way_T_521, alloc_way_chunks_523)
node _alloc_way_T_523 = xor(_alloc_way_T_522, alloc_way_chunks_524)
node _alloc_way_T_524 = xor(_alloc_way_T_523, alloc_way_chunks_525)
node _alloc_way_T_525 = xor(_alloc_way_T_524, alloc_way_chunks_526)
node _alloc_way_T_526 = xor(_alloc_way_T_525, alloc_way_chunks_527)
node _alloc_way_T_527 = xor(_alloc_way_T_526, alloc_way_chunks_528)
node _alloc_way_T_528 = xor(_alloc_way_T_527, alloc_way_chunks_529)
node _alloc_way_T_529 = xor(_alloc_way_T_528, alloc_way_chunks_530)
node _alloc_way_T_530 = xor(_alloc_way_T_529, alloc_way_chunks_531)
node _alloc_way_T_531 = xor(_alloc_way_T_530, alloc_way_chunks_532)
node _alloc_way_T_532 = xor(_alloc_way_T_531, alloc_way_chunks_533)
node _alloc_way_T_533 = xor(_alloc_way_T_532, alloc_way_chunks_534)
node _alloc_way_T_534 = xor(_alloc_way_T_533, alloc_way_chunks_535)
node _alloc_way_T_535 = xor(_alloc_way_T_534, alloc_way_chunks_536)
node _alloc_way_T_536 = xor(_alloc_way_T_535, alloc_way_chunks_537)
node _alloc_way_T_537 = xor(_alloc_way_T_536, alloc_way_chunks_538)
node _alloc_way_T_538 = xor(_alloc_way_T_537, alloc_way_chunks_539)
node _alloc_way_T_539 = xor(_alloc_way_T_538, alloc_way_chunks_540)
node _alloc_way_T_540 = xor(_alloc_way_T_539, alloc_way_chunks_541)
node _alloc_way_T_541 = xor(_alloc_way_T_540, alloc_way_chunks_542)
node _alloc_way_T_542 = xor(_alloc_way_T_541, alloc_way_chunks_543)
node _alloc_way_T_543 = xor(_alloc_way_T_542, alloc_way_chunks_544)
node _alloc_way_T_544 = xor(_alloc_way_T_543, alloc_way_chunks_545)
node _alloc_way_T_545 = xor(_alloc_way_T_544, alloc_way_chunks_546)
node _alloc_way_T_546 = xor(_alloc_way_T_545, alloc_way_chunks_547)
node _alloc_way_T_547 = xor(_alloc_way_T_546, alloc_way_chunks_548)
node _alloc_way_T_548 = xor(_alloc_way_T_547, alloc_way_chunks_549)
node _alloc_way_T_549 = xor(_alloc_way_T_548, alloc_way_chunks_550)
node _alloc_way_T_550 = xor(_alloc_way_T_549, alloc_way_chunks_551)
node _alloc_way_T_551 = xor(_alloc_way_T_550, alloc_way_chunks_552)
node _alloc_way_T_552 = xor(_alloc_way_T_551, alloc_way_chunks_553)
node _alloc_way_T_553 = xor(_alloc_way_T_552, alloc_way_chunks_554)
node _alloc_way_T_554 = xor(_alloc_way_T_553, alloc_way_chunks_555)
node _alloc_way_T_555 = xor(_alloc_way_T_554, alloc_way_chunks_556)
node _alloc_way_T_556 = xor(_alloc_way_T_555, alloc_way_chunks_557)
node _alloc_way_T_557 = xor(_alloc_way_T_556, alloc_way_chunks_558)
node _alloc_way_T_558 = xor(_alloc_way_T_557, alloc_way_chunks_559)
node _alloc_way_T_559 = xor(_alloc_way_T_558, alloc_way_chunks_560)
node _alloc_way_T_560 = xor(_alloc_way_T_559, alloc_way_chunks_561)
node _alloc_way_T_561 = xor(_alloc_way_T_560, alloc_way_chunks_562)
node _alloc_way_T_562 = xor(_alloc_way_T_561, alloc_way_chunks_563)
node _alloc_way_T_563 = xor(_alloc_way_T_562, alloc_way_chunks_564)
node _alloc_way_T_564 = xor(_alloc_way_T_563, alloc_way_chunks_565)
node _alloc_way_T_565 = xor(_alloc_way_T_564, alloc_way_chunks_566)
node _alloc_way_T_566 = xor(_alloc_way_T_565, alloc_way_chunks_567)
node _alloc_way_T_567 = xor(_alloc_way_T_566, alloc_way_chunks_568)
node _alloc_way_T_568 = xor(_alloc_way_T_567, alloc_way_chunks_569)
node _alloc_way_T_569 = xor(_alloc_way_T_568, alloc_way_chunks_570)
node _alloc_way_T_570 = xor(_alloc_way_T_569, alloc_way_chunks_571)
node _alloc_way_T_571 = xor(_alloc_way_T_570, alloc_way_chunks_572)
node _alloc_way_T_572 = xor(_alloc_way_T_571, alloc_way_chunks_573)
node _alloc_way_T_573 = xor(_alloc_way_T_572, alloc_way_chunks_574)
node _alloc_way_T_574 = xor(_alloc_way_T_573, alloc_way_chunks_575)
node _alloc_way_T_575 = xor(_alloc_way_T_574, alloc_way_chunks_576)
node _alloc_way_T_576 = xor(_alloc_way_T_575, alloc_way_chunks_577)
node _alloc_way_T_577 = xor(_alloc_way_T_576, alloc_way_chunks_578)
node _alloc_way_T_578 = xor(_alloc_way_T_577, alloc_way_chunks_579)
node _alloc_way_T_579 = xor(_alloc_way_T_578, alloc_way_chunks_580)
node _alloc_way_T_580 = xor(_alloc_way_T_579, alloc_way_chunks_581)
node _alloc_way_T_581 = xor(_alloc_way_T_580, alloc_way_chunks_582)
node _alloc_way_T_582 = xor(_alloc_way_T_581, alloc_way_chunks_583)
node _alloc_way_T_583 = xor(_alloc_way_T_582, alloc_way_chunks_584)
node _alloc_way_T_584 = xor(_alloc_way_T_583, alloc_way_chunks_585)
node _alloc_way_T_585 = xor(_alloc_way_T_584, alloc_way_chunks_586)
node _alloc_way_T_586 = xor(_alloc_way_T_585, alloc_way_chunks_587)
node _alloc_way_T_587 = xor(_alloc_way_T_586, alloc_way_chunks_588)
node _alloc_way_T_588 = xor(_alloc_way_T_587, alloc_way_chunks_589)
node _alloc_way_T_589 = xor(_alloc_way_T_588, alloc_way_chunks_590)
node _alloc_way_T_590 = xor(_alloc_way_T_589, alloc_way_chunks_591)
node _alloc_way_T_591 = xor(_alloc_way_T_590, alloc_way_chunks_592)
node _alloc_way_T_592 = xor(_alloc_way_T_591, alloc_way_chunks_593)
node _alloc_way_T_593 = xor(_alloc_way_T_592, alloc_way_chunks_594)
node _alloc_way_T_594 = xor(_alloc_way_T_593, alloc_way_chunks_595)
node _alloc_way_T_595 = xor(_alloc_way_T_594, alloc_way_chunks_596)
node _alloc_way_T_596 = xor(_alloc_way_T_595, alloc_way_chunks_597)
node _alloc_way_T_597 = xor(_alloc_way_T_596, alloc_way_chunks_598)
node _alloc_way_T_598 = xor(_alloc_way_T_597, alloc_way_chunks_599)
node _alloc_way_T_599 = xor(_alloc_way_T_598, alloc_way_chunks_600)
node alloc_way = xor(_alloc_way_T_599, alloc_way_chunks_601)
node _s1_meta_write_way_T = or(s1_hits_0, s1_hits_1)
node _s1_meta_write_way_T_1 = or(_s1_meta_write_way_T, s1_hits_2)
node _s1_meta_write_way_T_2 = or(_s1_meta_write_way_T_1, s1_hits_3)
node s1_meta_write_way_lo_lo_lo = cat(s1_hit_ohs[0][1], s1_hit_ohs[0][0])
node s1_meta_write_way_lo_lo_hi = cat(s1_hit_ohs[0][3], s1_hit_ohs[0][2])
node s1_meta_write_way_lo_lo = cat(s1_meta_write_way_lo_lo_hi, s1_meta_write_way_lo_lo_lo)
node s1_meta_write_way_lo_hi_lo = cat(s1_hit_ohs[0][5], s1_hit_ohs[0][4])
node s1_meta_write_way_lo_hi_hi = cat(s1_hit_ohs[0][7], s1_hit_ohs[0][6])
node s1_meta_write_way_lo_hi = cat(s1_meta_write_way_lo_hi_hi, s1_meta_write_way_lo_hi_lo)
node s1_meta_write_way_lo = cat(s1_meta_write_way_lo_hi, s1_meta_write_way_lo_lo)
node s1_meta_write_way_hi_lo_lo = cat(s1_hit_ohs[0][9], s1_hit_ohs[0][8])
node s1_meta_write_way_hi_lo_hi = cat(s1_hit_ohs[0][11], s1_hit_ohs[0][10])
node s1_meta_write_way_hi_lo = cat(s1_meta_write_way_hi_lo_hi, s1_meta_write_way_hi_lo_lo)
node s1_meta_write_way_hi_hi_lo = cat(s1_hit_ohs[0][13], s1_hit_ohs[0][12])
node s1_meta_write_way_hi_hi_hi = cat(s1_hit_ohs[0][15], s1_hit_ohs[0][14])
node s1_meta_write_way_hi_hi = cat(s1_meta_write_way_hi_hi_hi, s1_meta_write_way_hi_hi_lo)
node s1_meta_write_way_hi = cat(s1_meta_write_way_hi_hi, s1_meta_write_way_hi_lo)
node _s1_meta_write_way_T_3 = cat(s1_meta_write_way_hi, s1_meta_write_way_lo)
node s1_meta_write_way_lo_lo_lo_1 = cat(s1_hit_ohs[1][1], s1_hit_ohs[1][0])
node s1_meta_write_way_lo_lo_hi_1 = cat(s1_hit_ohs[1][3], s1_hit_ohs[1][2])
node s1_meta_write_way_lo_lo_1 = cat(s1_meta_write_way_lo_lo_hi_1, s1_meta_write_way_lo_lo_lo_1)
node s1_meta_write_way_lo_hi_lo_1 = cat(s1_hit_ohs[1][5], s1_hit_ohs[1][4])
node s1_meta_write_way_lo_hi_hi_1 = cat(s1_hit_ohs[1][7], s1_hit_ohs[1][6])
node s1_meta_write_way_lo_hi_1 = cat(s1_meta_write_way_lo_hi_hi_1, s1_meta_write_way_lo_hi_lo_1)
node s1_meta_write_way_lo_1 = cat(s1_meta_write_way_lo_hi_1, s1_meta_write_way_lo_lo_1)
node s1_meta_write_way_hi_lo_lo_1 = cat(s1_hit_ohs[1][9], s1_hit_ohs[1][8])
node s1_meta_write_way_hi_lo_hi_1 = cat(s1_hit_ohs[1][11], s1_hit_ohs[1][10])
node s1_meta_write_way_hi_lo_1 = cat(s1_meta_write_way_hi_lo_hi_1, s1_meta_write_way_hi_lo_lo_1)
node s1_meta_write_way_hi_hi_lo_1 = cat(s1_hit_ohs[1][13], s1_hit_ohs[1][12])
node s1_meta_write_way_hi_hi_hi_1 = cat(s1_hit_ohs[1][15], s1_hit_ohs[1][14])
node s1_meta_write_way_hi_hi_1 = cat(s1_meta_write_way_hi_hi_hi_1, s1_meta_write_way_hi_hi_lo_1)
node s1_meta_write_way_hi_1 = cat(s1_meta_write_way_hi_hi_1, s1_meta_write_way_hi_lo_1)
node _s1_meta_write_way_T_4 = cat(s1_meta_write_way_hi_1, s1_meta_write_way_lo_1)
node s1_meta_write_way_lo_lo_lo_2 = cat(s1_hit_ohs[2][1], s1_hit_ohs[2][0])
node s1_meta_write_way_lo_lo_hi_2 = cat(s1_hit_ohs[2][3], s1_hit_ohs[2][2])
node s1_meta_write_way_lo_lo_2 = cat(s1_meta_write_way_lo_lo_hi_2, s1_meta_write_way_lo_lo_lo_2)
node s1_meta_write_way_lo_hi_lo_2 = cat(s1_hit_ohs[2][5], s1_hit_ohs[2][4])
node s1_meta_write_way_lo_hi_hi_2 = cat(s1_hit_ohs[2][7], s1_hit_ohs[2][6])
node s1_meta_write_way_lo_hi_2 = cat(s1_meta_write_way_lo_hi_hi_2, s1_meta_write_way_lo_hi_lo_2)
node s1_meta_write_way_lo_2 = cat(s1_meta_write_way_lo_hi_2, s1_meta_write_way_lo_lo_2)
node s1_meta_write_way_hi_lo_lo_2 = cat(s1_hit_ohs[2][9], s1_hit_ohs[2][8])
node s1_meta_write_way_hi_lo_hi_2 = cat(s1_hit_ohs[2][11], s1_hit_ohs[2][10])
node s1_meta_write_way_hi_lo_2 = cat(s1_meta_write_way_hi_lo_hi_2, s1_meta_write_way_hi_lo_lo_2)
node s1_meta_write_way_hi_hi_lo_2 = cat(s1_hit_ohs[2][13], s1_hit_ohs[2][12])
node s1_meta_write_way_hi_hi_hi_2 = cat(s1_hit_ohs[2][15], s1_hit_ohs[2][14])
node s1_meta_write_way_hi_hi_2 = cat(s1_meta_write_way_hi_hi_hi_2, s1_meta_write_way_hi_hi_lo_2)
node s1_meta_write_way_hi_2 = cat(s1_meta_write_way_hi_hi_2, s1_meta_write_way_hi_lo_2)
node _s1_meta_write_way_T_5 = cat(s1_meta_write_way_hi_2, s1_meta_write_way_lo_2)
node s1_meta_write_way_lo_lo_lo_3 = cat(s1_hit_ohs[3][1], s1_hit_ohs[3][0])
node s1_meta_write_way_lo_lo_hi_3 = cat(s1_hit_ohs[3][3], s1_hit_ohs[3][2])
node s1_meta_write_way_lo_lo_3 = cat(s1_meta_write_way_lo_lo_hi_3, s1_meta_write_way_lo_lo_lo_3)
node s1_meta_write_way_lo_hi_lo_3 = cat(s1_hit_ohs[3][5], s1_hit_ohs[3][4])
node s1_meta_write_way_lo_hi_hi_3 = cat(s1_hit_ohs[3][7], s1_hit_ohs[3][6])
node s1_meta_write_way_lo_hi_3 = cat(s1_meta_write_way_lo_hi_hi_3, s1_meta_write_way_lo_hi_lo_3)
node s1_meta_write_way_lo_3 = cat(s1_meta_write_way_lo_hi_3, s1_meta_write_way_lo_lo_3)
node s1_meta_write_way_hi_lo_lo_3 = cat(s1_hit_ohs[3][9], s1_hit_ohs[3][8])
node s1_meta_write_way_hi_lo_hi_3 = cat(s1_hit_ohs[3][11], s1_hit_ohs[3][10])
node s1_meta_write_way_hi_lo_3 = cat(s1_meta_write_way_hi_lo_hi_3, s1_meta_write_way_hi_lo_lo_3)
node s1_meta_write_way_hi_hi_lo_3 = cat(s1_hit_ohs[3][13], s1_hit_ohs[3][12])
node s1_meta_write_way_hi_hi_hi_3 = cat(s1_hit_ohs[3][15], s1_hit_ohs[3][14])
node s1_meta_write_way_hi_hi_3 = cat(s1_meta_write_way_hi_hi_hi_3, s1_meta_write_way_hi_hi_lo_3)
node s1_meta_write_way_hi_3 = cat(s1_meta_write_way_hi_hi_3, s1_meta_write_way_hi_lo_3)
node _s1_meta_write_way_T_6 = cat(s1_meta_write_way_hi_3, s1_meta_write_way_lo_3)
node _s1_meta_write_way_T_7 = or(_s1_meta_write_way_T_3, _s1_meta_write_way_T_4)
node _s1_meta_write_way_T_8 = or(_s1_meta_write_way_T_7, _s1_meta_write_way_T_5)
node _s1_meta_write_way_T_9 = or(_s1_meta_write_way_T_8, _s1_meta_write_way_T_6)
node _s1_meta_write_way_T_10 = bits(_s1_meta_write_way_T_9, 0, 0)
node _s1_meta_write_way_T_11 = bits(_s1_meta_write_way_T_9, 1, 1)
node _s1_meta_write_way_T_12 = bits(_s1_meta_write_way_T_9, 2, 2)
node _s1_meta_write_way_T_13 = bits(_s1_meta_write_way_T_9, 3, 3)
node _s1_meta_write_way_T_14 = bits(_s1_meta_write_way_T_9, 4, 4)
node _s1_meta_write_way_T_15 = bits(_s1_meta_write_way_T_9, 5, 5)
node _s1_meta_write_way_T_16 = bits(_s1_meta_write_way_T_9, 6, 6)
node _s1_meta_write_way_T_17 = bits(_s1_meta_write_way_T_9, 7, 7)
node _s1_meta_write_way_T_18 = bits(_s1_meta_write_way_T_9, 8, 8)
node _s1_meta_write_way_T_19 = bits(_s1_meta_write_way_T_9, 9, 9)
node _s1_meta_write_way_T_20 = bits(_s1_meta_write_way_T_9, 10, 10)
node _s1_meta_write_way_T_21 = bits(_s1_meta_write_way_T_9, 11, 11)
node _s1_meta_write_way_T_22 = bits(_s1_meta_write_way_T_9, 12, 12)
node _s1_meta_write_way_T_23 = bits(_s1_meta_write_way_T_9, 13, 13)
node _s1_meta_write_way_T_24 = bits(_s1_meta_write_way_T_9, 14, 14)
node _s1_meta_write_way_T_25 = bits(_s1_meta_write_way_T_9, 15, 15)
node _s1_meta_write_way_T_26 = mux(_s1_meta_write_way_T_24, UInt<4>(0he), UInt<4>(0hf))
node _s1_meta_write_way_T_27 = mux(_s1_meta_write_way_T_23, UInt<4>(0hd), _s1_meta_write_way_T_26)
node _s1_meta_write_way_T_28 = mux(_s1_meta_write_way_T_22, UInt<4>(0hc), _s1_meta_write_way_T_27)
node _s1_meta_write_way_T_29 = mux(_s1_meta_write_way_T_21, UInt<4>(0hb), _s1_meta_write_way_T_28)
node _s1_meta_write_way_T_30 = mux(_s1_meta_write_way_T_20, UInt<4>(0ha), _s1_meta_write_way_T_29)
node _s1_meta_write_way_T_31 = mux(_s1_meta_write_way_T_19, UInt<4>(0h9), _s1_meta_write_way_T_30)
node _s1_meta_write_way_T_32 = mux(_s1_meta_write_way_T_18, UInt<4>(0h8), _s1_meta_write_way_T_31)
node _s1_meta_write_way_T_33 = mux(_s1_meta_write_way_T_17, UInt<3>(0h7), _s1_meta_write_way_T_32)
node _s1_meta_write_way_T_34 = mux(_s1_meta_write_way_T_16, UInt<3>(0h6), _s1_meta_write_way_T_33)
node _s1_meta_write_way_T_35 = mux(_s1_meta_write_way_T_15, UInt<3>(0h5), _s1_meta_write_way_T_34)
node _s1_meta_write_way_T_36 = mux(_s1_meta_write_way_T_14, UInt<3>(0h4), _s1_meta_write_way_T_35)
node _s1_meta_write_way_T_37 = mux(_s1_meta_write_way_T_13, UInt<2>(0h3), _s1_meta_write_way_T_36)
node _s1_meta_write_way_T_38 = mux(_s1_meta_write_way_T_12, UInt<2>(0h2), _s1_meta_write_way_T_37)
node _s1_meta_write_way_T_39 = mux(_s1_meta_write_way_T_11, UInt<1>(0h1), _s1_meta_write_way_T_38)
node _s1_meta_write_way_T_40 = mux(_s1_meta_write_way_T_10, UInt<1>(0h0), _s1_meta_write_way_T_39)
node _s1_meta_write_way_T_41 = mux(_s1_meta_write_way_T_2, _s1_meta_write_way_T_40, alloc_way)
connect s1_meta.write_way, _s1_meta_write_way_T_41
connect io.resp.f1[0].predicted_pc, s1_resp[0]
connect io.resp.f1[0].is_br, s1_is_br[0]
connect io.resp.f1[0].is_jal, s1_is_jal[0]
connect io.resp.f1[0].taken, s1_taken[0]
reg io_resp_f2_0_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f2_0_REG.predicted_pc.bits, io.resp.f1[0].predicted_pc.bits
connect io_resp_f2_0_REG.predicted_pc.valid, io.resp.f1[0].predicted_pc.valid
connect io_resp_f2_0_REG.is_jal, io.resp.f1[0].is_jal
connect io_resp_f2_0_REG.is_br, io.resp.f1[0].is_br
connect io_resp_f2_0_REG.taken, io.resp.f1[0].taken
connect io.resp.f2[0], io_resp_f2_0_REG
reg io_resp_f3_0_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f3_0_REG.predicted_pc.bits, io.resp.f2[0].predicted_pc.bits
connect io_resp_f3_0_REG.predicted_pc.valid, io.resp.f2[0].predicted_pc.valid
connect io_resp_f3_0_REG.is_jal, io.resp.f2[0].is_jal
connect io_resp_f3_0_REG.is_br, io.resp.f2[0].is_br
connect io_resp_f3_0_REG.taken, io.resp.f2[0].taken
connect io.resp.f3[0], io_resp_f3_0_REG
connect io.resp.f1[1].predicted_pc, s1_resp[1]
connect io.resp.f1[1].is_br, s1_is_br[1]
connect io.resp.f1[1].is_jal, s1_is_jal[1]
connect io.resp.f1[1].taken, s1_taken[1]
reg io_resp_f2_1_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f2_1_REG.predicted_pc.bits, io.resp.f1[1].predicted_pc.bits
connect io_resp_f2_1_REG.predicted_pc.valid, io.resp.f1[1].predicted_pc.valid
connect io_resp_f2_1_REG.is_jal, io.resp.f1[1].is_jal
connect io_resp_f2_1_REG.is_br, io.resp.f1[1].is_br
connect io_resp_f2_1_REG.taken, io.resp.f1[1].taken
connect io.resp.f2[1], io_resp_f2_1_REG
reg io_resp_f3_1_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f3_1_REG.predicted_pc.bits, io.resp.f2[1].predicted_pc.bits
connect io_resp_f3_1_REG.predicted_pc.valid, io.resp.f2[1].predicted_pc.valid
connect io_resp_f3_1_REG.is_jal, io.resp.f2[1].is_jal
connect io_resp_f3_1_REG.is_br, io.resp.f2[1].is_br
connect io_resp_f3_1_REG.taken, io.resp.f2[1].taken
connect io.resp.f3[1], io_resp_f3_1_REG
connect io.resp.f1[2].predicted_pc, s1_resp[2]
connect io.resp.f1[2].is_br, s1_is_br[2]
connect io.resp.f1[2].is_jal, s1_is_jal[2]
connect io.resp.f1[2].taken, s1_taken[2]
reg io_resp_f2_2_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f2_2_REG.predicted_pc.bits, io.resp.f1[2].predicted_pc.bits
connect io_resp_f2_2_REG.predicted_pc.valid, io.resp.f1[2].predicted_pc.valid
connect io_resp_f2_2_REG.is_jal, io.resp.f1[2].is_jal
connect io_resp_f2_2_REG.is_br, io.resp.f1[2].is_br
connect io_resp_f2_2_REG.taken, io.resp.f1[2].taken
connect io.resp.f2[2], io_resp_f2_2_REG
reg io_resp_f3_2_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f3_2_REG.predicted_pc.bits, io.resp.f2[2].predicted_pc.bits
connect io_resp_f3_2_REG.predicted_pc.valid, io.resp.f2[2].predicted_pc.valid
connect io_resp_f3_2_REG.is_jal, io.resp.f2[2].is_jal
connect io_resp_f3_2_REG.is_br, io.resp.f2[2].is_br
connect io_resp_f3_2_REG.taken, io.resp.f2[2].taken
connect io.resp.f3[2], io_resp_f3_2_REG
connect io.resp.f1[3].predicted_pc, s1_resp[3]
connect io.resp.f1[3].is_br, s1_is_br[3]
connect io.resp.f1[3].is_jal, s1_is_jal[3]
connect io.resp.f1[3].taken, s1_taken[3]
reg io_resp_f2_3_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f2_3_REG.predicted_pc.bits, io.resp.f1[3].predicted_pc.bits
connect io_resp_f2_3_REG.predicted_pc.valid, io.resp.f1[3].predicted_pc.valid
connect io_resp_f2_3_REG.is_jal, io.resp.f1[3].is_jal
connect io_resp_f2_3_REG.is_br, io.resp.f1[3].is_br
connect io_resp_f2_3_REG.taken, io.resp.f1[3].taken
connect io.resp.f2[3], io_resp_f2_3_REG
reg io_resp_f3_3_REG : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}, clock
connect io_resp_f3_3_REG.predicted_pc.bits, io.resp.f2[3].predicted_pc.bits
connect io_resp_f3_3_REG.predicted_pc.valid, io.resp.f2[3].predicted_pc.valid
connect io_resp_f3_3_REG.is_jal, io.resp.f2[3].is_jal
connect io_resp_f3_3_REG.is_br, io.resp.f2[3].is_br
connect io_resp_f3_3_REG.taken, io.resp.f2[3].taken
connect io.resp.f3[3], io_resp_f3_3_REG
node io_f3_meta_lo = cat(s1_meta.hits[1], s1_meta.hits[0])
node io_f3_meta_hi = cat(s1_meta.hits[3], s1_meta.hits[2])
node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo)
node _io_f3_meta_T_1 = cat(_io_f3_meta_T, s1_meta.write_way)
reg io_f3_meta_REG : UInt, clock
connect io_f3_meta_REG, _io_f3_meta_T_1
reg io_f3_meta_REG_1 : UInt, clock
connect io_f3_meta_REG_1, io_f3_meta_REG
connect io.f3_meta, io_f3_meta_REG_1
wire s1_update_meta : { hits : UInt<1>[4], write_way : UInt<4>}
wire _s1_update_meta_WIRE : UInt<8>
connect _s1_update_meta_WIRE, s1_update.bits.meta
node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 3, 0)
connect s1_update_meta.write_way, _s1_update_meta_T
node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 4, 4)
connect s1_update_meta.hits[0], _s1_update_meta_T_1
node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 5, 5)
connect s1_update_meta.hits[1], _s1_update_meta_T_2
node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 6, 6)
connect s1_update_meta.hits[2], _s1_update_meta_T_3
node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 7, 7)
connect s1_update_meta.hits[3], _s1_update_meta_T_4
node _max_offset_value_T = not(UInt<12>(0h0))
node max_offset_value = asSInt(_max_offset_value_T)
node _min_offset_value_T = cat(UInt<1>(0h1), UInt<12>(0h0))
node min_offset_value = asSInt(_min_offset_value_T)
node _new_offset_value_T = asSInt(s1_update.bits.target)
node _new_offset_value_T_1 = shl(s1_update.bits.cfi_idx.bits, 1)
node _new_offset_value_T_2 = add(s1_update.bits.pc, _new_offset_value_T_1)
node _new_offset_value_T_3 = tail(_new_offset_value_T_2, 1)
node _new_offset_value_T_4 = asSInt(_new_offset_value_T_3)
node _new_offset_value_T_5 = sub(_new_offset_value_T, _new_offset_value_T_4)
node _new_offset_value_T_6 = tail(_new_offset_value_T_5, 1)
node new_offset_value = asSInt(_new_offset_value_T_6)
wire s1_update_wbtb_data : { offset : SInt<13>}
connect s1_update_wbtb_data.offset, new_offset_value
node _s1_update_wbtb_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits)
node _s1_update_wbtb_mask_T_1 = and(s1_update.bits.cfi_idx.valid, s1_update.valid)
node _s1_update_wbtb_mask_T_2 = and(_s1_update_wbtb_mask_T_1, s1_update.bits.cfi_taken)
node _s1_update_wbtb_mask_T_3 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wbtb_mask_T_4 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_5 = or(_s1_update_wbtb_mask_T_3, _s1_update_wbtb_mask_T_4)
node _s1_update_wbtb_mask_T_6 = eq(_s1_update_wbtb_mask_T_5, UInt<1>(0h0))
node _s1_update_wbtb_mask_T_7 = and(_s1_update_wbtb_mask_T_2, _s1_update_wbtb_mask_T_6)
node _s1_update_wbtb_mask_T_8 = mux(_s1_update_wbtb_mask_T_7, UInt<4>(0hf), UInt<4>(0h0))
node s1_update_wbtb_mask = and(_s1_update_wbtb_mask_T, _s1_update_wbtb_mask_T_8)
node _s1_update_wmeta_mask_T = or(s1_update_wbtb_mask, s1_update.bits.br_mask)
node _s1_update_wmeta_mask_T_1 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _s1_update_wmeta_mask_T_2 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_3 = or(_s1_update_wmeta_mask_T_1, _s1_update_wmeta_mask_T_2)
node _s1_update_wmeta_mask_T_4 = eq(_s1_update_wmeta_mask_T_3, UInt<1>(0h0))
node _s1_update_wmeta_mask_T_5 = and(s1_update.valid, _s1_update_wmeta_mask_T_4)
node _s1_update_wmeta_mask_T_6 = mux(_s1_update_wmeta_mask_T_5, UInt<4>(0hf), UInt<4>(0h0))
node s1_update_wmeta_mask = and(_s1_update_wmeta_mask_T, _s1_update_wmeta_mask_T_6)
node _T_2 = and(s1_update.valid, s1_update.bits.cfi_taken)
node _T_3 = and(_T_2, s1_update.bits.cfi_idx.valid)
node _T_4 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_5 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_6 = or(_T_4, _T_5)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(_T_3, _T_7)
when _T_8 :
connect btb[s1_update_meta.write_way][s1_update.bits.cfi_idx.bits].offset, new_offset_value
node _T_9 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_10 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = eq(_T_11, UInt<1>(0h0))
node _T_13 = and(s1_update.valid, _T_12)
node _T_14 = bits(s1_update.bits.br_mask, 0, 0)
node _T_15 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0))
node _T_16 = and(_T_15, s1_update.bits.cfi_taken)
node _T_17 = and(_T_16, s1_update.bits.cfi_idx.valid)
node _T_18 = or(_T_14, _T_17)
node _T_19 = and(_T_13, _T_18)
when _T_19 :
node _was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0))
node _was_taken_T_1 = and(_was_taken_T, s1_update.bits.cfi_idx.valid)
node _was_taken_T_2 = or(s1_update.bits.cfi_taken, s1_update.bits.cfi_is_jal)
node was_taken = and(_was_taken_T_1, _was_taken_T_2)
node _meta_0_is_br_T = bits(s1_update.bits.br_mask, 0, 0)
connect meta[s1_update_meta.write_way][0].is_br, _meta_0_is_br_T
connect meta[s1_update_meta.write_way][0].tag, s1_update_idx
node _meta_0_ctr_T = eq(s1_update_meta.hits[0], UInt<1>(0h0))
node _meta_0_ctr_T_1 = mux(was_taken, UInt<2>(0h3), UInt<1>(0h0))
node meta_0_ctr_old_bim_sat_taken = eq(meta[s1_update_meta.write_way][0].ctr, UInt<2>(0h3))
node meta_0_ctr_old_bim_sat_ntaken = eq(meta[s1_update_meta.write_way][0].ctr, UInt<1>(0h0))
node _meta_0_ctr_T_2 = and(meta_0_ctr_old_bim_sat_taken, was_taken)
node _meta_0_ctr_T_3 = eq(was_taken, UInt<1>(0h0))
node _meta_0_ctr_T_4 = and(meta_0_ctr_old_bim_sat_ntaken, _meta_0_ctr_T_3)
node _meta_0_ctr_T_5 = add(meta[s1_update_meta.write_way][0].ctr, UInt<1>(0h1))
node _meta_0_ctr_T_6 = tail(_meta_0_ctr_T_5, 1)
node _meta_0_ctr_T_7 = sub(meta[s1_update_meta.write_way][0].ctr, UInt<1>(0h1))
node _meta_0_ctr_T_8 = tail(_meta_0_ctr_T_7, 1)
node _meta_0_ctr_T_9 = mux(was_taken, _meta_0_ctr_T_6, _meta_0_ctr_T_8)
node _meta_0_ctr_T_10 = mux(_meta_0_ctr_T_4, UInt<1>(0h0), _meta_0_ctr_T_9)
node _meta_0_ctr_T_11 = mux(_meta_0_ctr_T_2, UInt<2>(0h3), _meta_0_ctr_T_10)
node _meta_0_ctr_T_12 = mux(_meta_0_ctr_T, _meta_0_ctr_T_1, _meta_0_ctr_T_11)
connect meta[s1_update_meta.write_way][0].ctr, _meta_0_ctr_T_12
node _T_20 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_21 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_22 = or(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = and(s1_update.valid, _T_23)
node _T_25 = bits(s1_update.bits.br_mask, 1, 1)
node _T_26 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1))
node _T_27 = and(_T_26, s1_update.bits.cfi_taken)
node _T_28 = and(_T_27, s1_update.bits.cfi_idx.valid)
node _T_29 = or(_T_25, _T_28)
node _T_30 = and(_T_24, _T_29)
when _T_30 :
node _was_taken_T_3 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1))
node _was_taken_T_4 = and(_was_taken_T_3, s1_update.bits.cfi_idx.valid)
node _was_taken_T_5 = or(s1_update.bits.cfi_taken, s1_update.bits.cfi_is_jal)
node was_taken_1 = and(_was_taken_T_4, _was_taken_T_5)
node _meta_1_is_br_T = bits(s1_update.bits.br_mask, 1, 1)
connect meta[s1_update_meta.write_way][1].is_br, _meta_1_is_br_T
connect meta[s1_update_meta.write_way][1].tag, s1_update_idx
node _meta_1_ctr_T = eq(s1_update_meta.hits[1], UInt<1>(0h0))
node _meta_1_ctr_T_1 = mux(was_taken_1, UInt<2>(0h3), UInt<1>(0h0))
node meta_1_ctr_old_bim_sat_taken = eq(meta[s1_update_meta.write_way][1].ctr, UInt<2>(0h3))
node meta_1_ctr_old_bim_sat_ntaken = eq(meta[s1_update_meta.write_way][1].ctr, UInt<1>(0h0))
node _meta_1_ctr_T_2 = and(meta_1_ctr_old_bim_sat_taken, was_taken_1)
node _meta_1_ctr_T_3 = eq(was_taken_1, UInt<1>(0h0))
node _meta_1_ctr_T_4 = and(meta_1_ctr_old_bim_sat_ntaken, _meta_1_ctr_T_3)
node _meta_1_ctr_T_5 = add(meta[s1_update_meta.write_way][1].ctr, UInt<1>(0h1))
node _meta_1_ctr_T_6 = tail(_meta_1_ctr_T_5, 1)
node _meta_1_ctr_T_7 = sub(meta[s1_update_meta.write_way][1].ctr, UInt<1>(0h1))
node _meta_1_ctr_T_8 = tail(_meta_1_ctr_T_7, 1)
node _meta_1_ctr_T_9 = mux(was_taken_1, _meta_1_ctr_T_6, _meta_1_ctr_T_8)
node _meta_1_ctr_T_10 = mux(_meta_1_ctr_T_4, UInt<1>(0h0), _meta_1_ctr_T_9)
node _meta_1_ctr_T_11 = mux(_meta_1_ctr_T_2, UInt<2>(0h3), _meta_1_ctr_T_10)
node _meta_1_ctr_T_12 = mux(_meta_1_ctr_T, _meta_1_ctr_T_1, _meta_1_ctr_T_11)
connect meta[s1_update_meta.write_way][1].ctr, _meta_1_ctr_T_12
node _T_31 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_32 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_33 = or(_T_31, _T_32)
node _T_34 = eq(_T_33, UInt<1>(0h0))
node _T_35 = and(s1_update.valid, _T_34)
node _T_36 = bits(s1_update.bits.br_mask, 2, 2)
node _T_37 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2))
node _T_38 = and(_T_37, s1_update.bits.cfi_taken)
node _T_39 = and(_T_38, s1_update.bits.cfi_idx.valid)
node _T_40 = or(_T_36, _T_39)
node _T_41 = and(_T_35, _T_40)
when _T_41 :
node _was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2))
node _was_taken_T_7 = and(_was_taken_T_6, s1_update.bits.cfi_idx.valid)
node _was_taken_T_8 = or(s1_update.bits.cfi_taken, s1_update.bits.cfi_is_jal)
node was_taken_2 = and(_was_taken_T_7, _was_taken_T_8)
node _meta_2_is_br_T = bits(s1_update.bits.br_mask, 2, 2)
connect meta[s1_update_meta.write_way][2].is_br, _meta_2_is_br_T
connect meta[s1_update_meta.write_way][2].tag, s1_update_idx
node _meta_2_ctr_T = eq(s1_update_meta.hits[2], UInt<1>(0h0))
node _meta_2_ctr_T_1 = mux(was_taken_2, UInt<2>(0h3), UInt<1>(0h0))
node meta_2_ctr_old_bim_sat_taken = eq(meta[s1_update_meta.write_way][2].ctr, UInt<2>(0h3))
node meta_2_ctr_old_bim_sat_ntaken = eq(meta[s1_update_meta.write_way][2].ctr, UInt<1>(0h0))
node _meta_2_ctr_T_2 = and(meta_2_ctr_old_bim_sat_taken, was_taken_2)
node _meta_2_ctr_T_3 = eq(was_taken_2, UInt<1>(0h0))
node _meta_2_ctr_T_4 = and(meta_2_ctr_old_bim_sat_ntaken, _meta_2_ctr_T_3)
node _meta_2_ctr_T_5 = add(meta[s1_update_meta.write_way][2].ctr, UInt<1>(0h1))
node _meta_2_ctr_T_6 = tail(_meta_2_ctr_T_5, 1)
node _meta_2_ctr_T_7 = sub(meta[s1_update_meta.write_way][2].ctr, UInt<1>(0h1))
node _meta_2_ctr_T_8 = tail(_meta_2_ctr_T_7, 1)
node _meta_2_ctr_T_9 = mux(was_taken_2, _meta_2_ctr_T_6, _meta_2_ctr_T_8)
node _meta_2_ctr_T_10 = mux(_meta_2_ctr_T_4, UInt<1>(0h0), _meta_2_ctr_T_9)
node _meta_2_ctr_T_11 = mux(_meta_2_ctr_T_2, UInt<2>(0h3), _meta_2_ctr_T_10)
node _meta_2_ctr_T_12 = mux(_meta_2_ctr_T, _meta_2_ctr_T_1, _meta_2_ctr_T_11)
connect meta[s1_update_meta.write_way][2].ctr, _meta_2_ctr_T_12
node _T_42 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update)
node _T_43 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0))
node _T_44 = or(_T_42, _T_43)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = and(s1_update.valid, _T_45)
node _T_47 = bits(s1_update.bits.br_mask, 3, 3)
node _T_48 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3))
node _T_49 = and(_T_48, s1_update.bits.cfi_taken)
node _T_50 = and(_T_49, s1_update.bits.cfi_idx.valid)
node _T_51 = or(_T_47, _T_50)
node _T_52 = and(_T_46, _T_51)
when _T_52 :
node _was_taken_T_9 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3))
node _was_taken_T_10 = and(_was_taken_T_9, s1_update.bits.cfi_idx.valid)
node _was_taken_T_11 = or(s1_update.bits.cfi_taken, s1_update.bits.cfi_is_jal)
node was_taken_3 = and(_was_taken_T_10, _was_taken_T_11)
node _meta_3_is_br_T = bits(s1_update.bits.br_mask, 3, 3)
connect meta[s1_update_meta.write_way][3].is_br, _meta_3_is_br_T
connect meta[s1_update_meta.write_way][3].tag, s1_update_idx
node _meta_3_ctr_T = eq(s1_update_meta.hits[3], UInt<1>(0h0))
node _meta_3_ctr_T_1 = mux(was_taken_3, UInt<2>(0h3), UInt<1>(0h0))
node meta_3_ctr_old_bim_sat_taken = eq(meta[s1_update_meta.write_way][3].ctr, UInt<2>(0h3))
node meta_3_ctr_old_bim_sat_ntaken = eq(meta[s1_update_meta.write_way][3].ctr, UInt<1>(0h0))
node _meta_3_ctr_T_2 = and(meta_3_ctr_old_bim_sat_taken, was_taken_3)
node _meta_3_ctr_T_3 = eq(was_taken_3, UInt<1>(0h0))
node _meta_3_ctr_T_4 = and(meta_3_ctr_old_bim_sat_ntaken, _meta_3_ctr_T_3)
node _meta_3_ctr_T_5 = add(meta[s1_update_meta.write_way][3].ctr, UInt<1>(0h1))
node _meta_3_ctr_T_6 = tail(_meta_3_ctr_T_5, 1)
node _meta_3_ctr_T_7 = sub(meta[s1_update_meta.write_way][3].ctr, UInt<1>(0h1))
node _meta_3_ctr_T_8 = tail(_meta_3_ctr_T_7, 1)
node _meta_3_ctr_T_9 = mux(was_taken_3, _meta_3_ctr_T_6, _meta_3_ctr_T_8)
node _meta_3_ctr_T_10 = mux(_meta_3_ctr_T_4, UInt<1>(0h0), _meta_3_ctr_T_9)
node _meta_3_ctr_T_11 = mux(_meta_3_ctr_T_2, UInt<2>(0h3), _meta_3_ctr_T_10)
node _meta_3_ctr_T_12 = mux(_meta_3_ctr_T, _meta_3_ctr_T_1, _meta_3_ctr_T_11)
connect meta[s1_update_meta.write_way][3].ctr, _meta_3_ctr_T_12 | module FAMicroBTBBranchPredictorBank( // @[faubtb.scala:21:7]
input clock, // @[faubtb.scala:21:7]
input reset, // @[faubtb.scala:21:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire io_f0_valid_0 = io_f0_valid; // @[faubtb.scala:21:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[faubtb.scala:21:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[faubtb.scala:21:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[faubtb.scala:21:7]
wire io_f3_fire_0 = io_f3_fire; // @[faubtb.scala:21:7]
wire io_update_valid_0 = io_update_valid; // @[faubtb.scala:21:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[faubtb.scala:21:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[faubtb.scala:21:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[faubtb.scala:21:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[faubtb.scala:21:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[faubtb.scala:21:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[faubtb.scala:21:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[faubtb.scala:21:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[faubtb.scala:21:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[faubtb.scala:21:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[faubtb.scala:21:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[faubtb.scala:21:7]
wire [36:0] _meta_WIRE_0_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_0_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_0_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_0_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_1_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_1_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_1_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_1_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_2_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_2_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_2_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_2_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_3_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_3_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_3_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_3_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_4_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_4_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_4_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_4_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_5_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_5_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_5_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_5_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_6_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_6_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_6_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_6_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_7_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_7_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_7_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_7_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_8_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_8_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_8_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_8_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_9_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_9_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_9_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_9_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_10_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_10_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_10_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_10_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_11_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_11_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_11_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_11_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_12_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_12_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_12_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_12_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_13_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_13_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_13_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_13_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_14_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_14_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_14_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_14_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_15_0_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_15_1_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_15_2_tag = 37'h0; // @[faubtb.scala:57:40]
wire [36:0] _meta_WIRE_15_3_tag = 37'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_0_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_0_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_0_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_0_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_1_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_1_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_1_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_1_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_2_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_2_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_2_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_2_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_3_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_3_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_3_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_3_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_4_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_4_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_4_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_4_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_5_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_5_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_5_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_5_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_6_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_6_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_6_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_6_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_7_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_7_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_7_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_7_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_8_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_8_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_8_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_8_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_9_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_9_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_9_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_9_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_10_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_10_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_10_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_10_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_11_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_11_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_11_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_11_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_12_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_12_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_12_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_12_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_13_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_13_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_13_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_13_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_14_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_14_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_14_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_14_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_15_0_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_15_1_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_15_2_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [1:0] _meta_WIRE_15_3_ctr = 2'h0; // @[faubtb.scala:57:40]
wire [11:0] _max_offset_value_T = 12'hFFF; // @[faubtb.scala:116:{27,51}]
wire [11:0] max_offset_value = 12'hFFF; // @[faubtb.scala:116:51]
wire [12:0] _min_offset_value_T = 13'h1000; // @[faubtb.scala:117:{29,58}]
wire [12:0] min_offset_value = 13'h1000; // @[faubtb.scala:117:58]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire io_f1_lhist = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_0_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_0_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_1_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_1_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_2_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_2_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_3_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_3_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_0_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_0_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_1_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_1_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_2_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_2_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_3_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_3_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_0_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_0_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_1_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_1_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_2_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_2_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_3_taken = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_3_is_br = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[faubtb.scala:21:7]
wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[faubtb.scala:21:7]
wire _meta_WIRE_0_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_0_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_0_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_0_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_1_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_1_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_1_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_1_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_2_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_2_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_2_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_2_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_3_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_3_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_3_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_3_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_4_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_4_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_4_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_4_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_5_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_5_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_5_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_5_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_6_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_6_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_6_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_6_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_7_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_7_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_7_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_7_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_8_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_8_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_8_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_8_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_9_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_9_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_9_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_9_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_10_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_10_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_10_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_10_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_11_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_11_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_11_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_11_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_12_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_12_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_12_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_12_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_13_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_13_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_13_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_13_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_14_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_14_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_14_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_14_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_15_0_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_15_1_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_15_2_is_br = 1'h0; // @[faubtb.scala:57:40]
wire _meta_WIRE_15_3_is_br = 1'h0; // @[faubtb.scala:57:40]
wire s1_taken_0; // @[faubtb.scala:66:23]
wire s1_is_br_0; // @[faubtb.scala:67:23]
wire s1_is_jal_0; // @[faubtb.scala:68:23]
wire s1_resp_0_valid; // @[faubtb.scala:65:23]
wire [39:0] s1_resp_0_bits; // @[faubtb.scala:65:23]
wire s1_taken_1; // @[faubtb.scala:66:23]
wire s1_is_br_1; // @[faubtb.scala:67:23]
wire s1_is_jal_1; // @[faubtb.scala:68:23]
wire s1_resp_1_valid; // @[faubtb.scala:65:23]
wire [39:0] s1_resp_1_bits; // @[faubtb.scala:65:23]
wire s1_taken_2; // @[faubtb.scala:66:23]
wire s1_is_br_2; // @[faubtb.scala:67:23]
wire s1_is_jal_2; // @[faubtb.scala:68:23]
wire s1_resp_2_valid; // @[faubtb.scala:65:23]
wire [39:0] s1_resp_2_bits; // @[faubtb.scala:65:23]
wire s1_taken_3; // @[faubtb.scala:66:23]
wire s1_is_br_3; // @[faubtb.scala:67:23]
wire s1_is_jal_3; // @[faubtb.scala:68:23]
wire s1_resp_3_valid; // @[faubtb.scala:65:23]
wire [39:0] s1_resp_3_bits; // @[faubtb.scala:65:23]
wire io_resp_f1_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f1_0_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f1_0_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f1_0_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f1_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f1_1_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f1_1_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f1_1_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f1_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f1_2_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f1_2_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f1_2_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f1_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f1_3_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f1_3_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f1_3_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f2_0_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f2_0_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f2_0_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f2_1_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f2_1_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f2_1_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f2_2_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f2_2_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f2_2_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f2_3_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f2_3_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f2_3_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f3_0_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f3_0_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f3_0_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f3_1_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f3_1_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f3_1_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f3_2_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f3_2_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f3_2_is_jal_0; // @[faubtb.scala:21:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
wire io_resp_f3_3_taken_0; // @[faubtb.scala:21:7]
wire io_resp_f3_3_is_br_0; // @[faubtb.scala:21:7]
wire io_resp_f3_3_is_jal_0; // @[faubtb.scala:21:7]
wire [119:0] io_f3_meta_0; // @[faubtb.scala:21:7]
wire [36:0] s0_idx = io_f0_pc_0[39:3]; // @[frontend.scala:162:35]
reg [36:0] s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_2 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_4 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_6 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_8 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_10 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_12 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_14 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_16 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_18 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_20 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_22 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_24 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_26 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_28 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_30 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_32 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_34 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_36 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_38 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_40 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_42 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_44 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_46 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_48 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_50 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_52 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_54 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_56 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_58 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_60 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_62 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_64 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_66 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_68 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_70 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_72 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_74 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_76 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_78 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_80 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_82 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_84 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_86 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_88 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_90 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_92 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_94 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_96 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_98 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_100 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_102 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_104 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_106 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_108 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_110 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_112 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_114 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_116 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_118 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_120 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_122 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_124 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _s1_hit_ohs_T_126 = s1_idx; // @[predictor.scala:163:29]
wire [36:0] _alloc_way_r_metas_T_17 = s1_idx; // @[predictor.scala:163:29]
reg [36:0] s2_idx; // @[predictor.scala:164:29]
reg [36:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_0_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_1_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_2_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [39:0] _s1_resp_3_bits_T = s1_pc; // @[predictor.scala:178:22]
wire [36:0] s0_update_idx = io_update_bits_pc_0[39:3]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T = s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [36:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire s1_hits_0; // @[faubtb.scala:75:55]
wire s1_hits_1; // @[faubtb.scala:75:55]
wire s1_hits_2; // @[faubtb.scala:75:55]
wire s1_hits_3; // @[faubtb.scala:75:55]
wire [3:0] _s1_meta_write_way_T_41; // @[faubtb.scala:97:27]
wire s1_meta_hits_0; // @[faubtb.scala:53:21]
wire s1_meta_hits_1; // @[faubtb.scala:53:21]
wire s1_meta_hits_2; // @[faubtb.scala:53:21]
wire s1_meta_hits_3; // @[faubtb.scala:53:21]
wire [3:0] s1_meta_write_way; // @[faubtb.scala:53:21]
wire [1:0] _GEN = {s1_meta_hits_1, s1_meta_hits_0}; // @[faubtb.scala:53:21, :54:33]
wire [1:0] lo; // @[faubtb.scala:54:33]
assign lo = _GEN; // @[faubtb.scala:54:33]
wire [1:0] io_f3_meta_lo; // @[faubtb.scala:110:41]
assign io_f3_meta_lo = _GEN; // @[faubtb.scala:54:33, :110:41]
wire [1:0] _GEN_0 = {s1_meta_hits_3, s1_meta_hits_2}; // @[faubtb.scala:53:21, :54:33]
wire [1:0] hi; // @[faubtb.scala:54:33]
assign hi = _GEN_0; // @[faubtb.scala:54:33]
wire [1:0] io_f3_meta_hi; // @[faubtb.scala:110:41]
assign io_f3_meta_hi = _GEN_0; // @[faubtb.scala:54:33, :110:41]
reg meta_0_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_0_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_0 = meta_0_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_0_0_ctr; // @[faubtb.scala:57:25]
reg meta_0_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_0_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_1 = meta_0_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_0_1_ctr; // @[faubtb.scala:57:25]
reg meta_0_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_0_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_2 = meta_0_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_0_2_ctr; // @[faubtb.scala:57:25]
reg meta_0_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_0_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_3 = meta_0_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_0_3_ctr; // @[faubtb.scala:57:25]
reg meta_1_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_1_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_1_0 = meta_1_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_1_0_ctr; // @[faubtb.scala:57:25]
reg meta_1_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_1_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_1_1 = meta_1_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_1_1_ctr; // @[faubtb.scala:57:25]
reg meta_1_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_1_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_1_2 = meta_1_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_1_2_ctr; // @[faubtb.scala:57:25]
reg meta_1_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_1_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_1_3 = meta_1_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_1_3_ctr; // @[faubtb.scala:57:25]
reg meta_2_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_2_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_2_0 = meta_2_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_2_0_ctr; // @[faubtb.scala:57:25]
reg meta_2_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_2_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_2_1 = meta_2_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_2_1_ctr; // @[faubtb.scala:57:25]
reg meta_2_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_2_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_2_2 = meta_2_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_2_2_ctr; // @[faubtb.scala:57:25]
reg meta_2_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_2_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_2_3 = meta_2_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_2_3_ctr; // @[faubtb.scala:57:25]
reg meta_3_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_3_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_3_0 = meta_3_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_3_0_ctr; // @[faubtb.scala:57:25]
reg meta_3_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_3_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_3_1 = meta_3_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_3_1_ctr; // @[faubtb.scala:57:25]
reg meta_3_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_3_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_3_2 = meta_3_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_3_2_ctr; // @[faubtb.scala:57:25]
reg meta_3_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_3_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_3_3 = meta_3_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_3_3_ctr; // @[faubtb.scala:57:25]
reg meta_4_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_4_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_4_0 = meta_4_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_4_0_ctr; // @[faubtb.scala:57:25]
reg meta_4_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_4_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_4_1 = meta_4_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_4_1_ctr; // @[faubtb.scala:57:25]
reg meta_4_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_4_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_4_2 = meta_4_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_4_2_ctr; // @[faubtb.scala:57:25]
reg meta_4_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_4_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_4_3 = meta_4_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_4_3_ctr; // @[faubtb.scala:57:25]
reg meta_5_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_5_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_5_0 = meta_5_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_5_0_ctr; // @[faubtb.scala:57:25]
reg meta_5_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_5_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_5_1 = meta_5_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_5_1_ctr; // @[faubtb.scala:57:25]
reg meta_5_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_5_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_5_2 = meta_5_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_5_2_ctr; // @[faubtb.scala:57:25]
reg meta_5_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_5_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_5_3 = meta_5_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_5_3_ctr; // @[faubtb.scala:57:25]
reg meta_6_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_6_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_6_0 = meta_6_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_6_0_ctr; // @[faubtb.scala:57:25]
reg meta_6_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_6_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_6_1 = meta_6_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_6_1_ctr; // @[faubtb.scala:57:25]
reg meta_6_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_6_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_6_2 = meta_6_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_6_2_ctr; // @[faubtb.scala:57:25]
reg meta_6_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_6_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_6_3 = meta_6_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_6_3_ctr; // @[faubtb.scala:57:25]
reg meta_7_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_7_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_7_0 = meta_7_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_7_0_ctr; // @[faubtb.scala:57:25]
reg meta_7_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_7_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_7_1 = meta_7_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_7_1_ctr; // @[faubtb.scala:57:25]
reg meta_7_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_7_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_7_2 = meta_7_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_7_2_ctr; // @[faubtb.scala:57:25]
reg meta_7_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_7_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_7_3 = meta_7_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_7_3_ctr; // @[faubtb.scala:57:25]
reg meta_8_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_8_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_8_0 = meta_8_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_8_0_ctr; // @[faubtb.scala:57:25]
reg meta_8_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_8_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_8_1 = meta_8_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_8_1_ctr; // @[faubtb.scala:57:25]
reg meta_8_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_8_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_8_2 = meta_8_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_8_2_ctr; // @[faubtb.scala:57:25]
reg meta_8_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_8_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_8_3 = meta_8_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_8_3_ctr; // @[faubtb.scala:57:25]
reg meta_9_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_9_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_9_0 = meta_9_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_9_0_ctr; // @[faubtb.scala:57:25]
reg meta_9_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_9_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_9_1 = meta_9_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_9_1_ctr; // @[faubtb.scala:57:25]
reg meta_9_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_9_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_9_2 = meta_9_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_9_2_ctr; // @[faubtb.scala:57:25]
reg meta_9_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_9_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_9_3 = meta_9_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_9_3_ctr; // @[faubtb.scala:57:25]
reg meta_10_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_10_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_10_0 = meta_10_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_10_0_ctr; // @[faubtb.scala:57:25]
reg meta_10_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_10_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_10_1 = meta_10_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_10_1_ctr; // @[faubtb.scala:57:25]
reg meta_10_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_10_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_10_2 = meta_10_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_10_2_ctr; // @[faubtb.scala:57:25]
reg meta_10_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_10_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_10_3 = meta_10_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_10_3_ctr; // @[faubtb.scala:57:25]
reg meta_11_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_11_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_11_0 = meta_11_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_11_0_ctr; // @[faubtb.scala:57:25]
reg meta_11_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_11_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_11_1 = meta_11_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_11_1_ctr; // @[faubtb.scala:57:25]
reg meta_11_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_11_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_11_2 = meta_11_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_11_2_ctr; // @[faubtb.scala:57:25]
reg meta_11_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_11_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_11_3 = meta_11_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_11_3_ctr; // @[faubtb.scala:57:25]
reg meta_12_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_12_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_12_0 = meta_12_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_12_0_ctr; // @[faubtb.scala:57:25]
reg meta_12_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_12_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_12_1 = meta_12_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_12_1_ctr; // @[faubtb.scala:57:25]
reg meta_12_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_12_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_12_2 = meta_12_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_12_2_ctr; // @[faubtb.scala:57:25]
reg meta_12_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_12_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_12_3 = meta_12_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_12_3_ctr; // @[faubtb.scala:57:25]
reg meta_13_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_13_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_13_0 = meta_13_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_13_0_ctr; // @[faubtb.scala:57:25]
reg meta_13_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_13_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_13_1 = meta_13_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_13_1_ctr; // @[faubtb.scala:57:25]
reg meta_13_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_13_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_13_2 = meta_13_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_13_2_ctr; // @[faubtb.scala:57:25]
reg meta_13_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_13_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_13_3 = meta_13_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_13_3_ctr; // @[faubtb.scala:57:25]
reg meta_14_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_14_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_14_0 = meta_14_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_14_0_ctr; // @[faubtb.scala:57:25]
reg meta_14_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_14_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_14_1 = meta_14_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_14_1_ctr; // @[faubtb.scala:57:25]
reg meta_14_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_14_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_14_2 = meta_14_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_14_2_ctr; // @[faubtb.scala:57:25]
reg meta_14_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_14_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_14_3 = meta_14_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_14_3_ctr; // @[faubtb.scala:57:25]
reg meta_15_0_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_15_0_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_15_0 = meta_15_0_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_15_0_ctr; // @[faubtb.scala:57:25]
reg meta_15_1_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_15_1_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_15_1 = meta_15_1_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_15_1_ctr; // @[faubtb.scala:57:25]
reg meta_15_2_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_15_2_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_15_2 = meta_15_2_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_15_2_ctr; // @[faubtb.scala:57:25]
reg meta_15_3_is_br; // @[faubtb.scala:57:25]
reg [36:0] meta_15_3_tag; // @[faubtb.scala:57:25]
wire [36:0] _alloc_way_r_metas_WIRE_15_3 = meta_15_3_tag; // @[faubtb.scala:57:25, :89:52]
reg [1:0] meta_15_3_ctr; // @[faubtb.scala:57:25]
reg [12:0] btb_0_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_0_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_0_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_0_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_1_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_1_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_1_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_1_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_2_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_2_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_2_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_2_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_3_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_3_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_3_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_3_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_4_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_4_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_4_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_4_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_5_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_5_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_5_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_5_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_6_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_6_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_6_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_6_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_7_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_7_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_7_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_7_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_8_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_8_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_8_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_8_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_9_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_9_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_9_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_9_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_10_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_10_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_10_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_10_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_11_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_11_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_11_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_11_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_12_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_12_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_12_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_12_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_13_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_13_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_13_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_13_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_14_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_14_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_14_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_14_3_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_15_0_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_15_1_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_15_2_offset; // @[faubtb.scala:58:21]
reg [12:0] btb_15_3_offset; // @[faubtb.scala:58:21]
wire _s1_resp_0_valid_T; // @[faubtb.scala:80:34]
assign io_resp_f1_0_predicted_pc_valid_0 = s1_resp_0_valid; // @[faubtb.scala:21:7, :65:23]
wire [39:0] _s1_resp_0_bits_T_7; // @[faubtb.scala:81:85]
assign io_resp_f1_0_predicted_pc_bits_0 = s1_resp_0_bits; // @[faubtb.scala:21:7, :65:23]
wire _s1_resp_1_valid_T; // @[faubtb.scala:80:34]
assign io_resp_f1_1_predicted_pc_valid_0 = s1_resp_1_valid; // @[faubtb.scala:21:7, :65:23]
wire [39:0] _s1_resp_1_bits_T_7; // @[faubtb.scala:81:85]
assign io_resp_f1_1_predicted_pc_bits_0 = s1_resp_1_bits; // @[faubtb.scala:21:7, :65:23]
wire _s1_resp_2_valid_T; // @[faubtb.scala:80:34]
assign io_resp_f1_2_predicted_pc_valid_0 = s1_resp_2_valid; // @[faubtb.scala:21:7, :65:23]
wire [39:0] _s1_resp_2_bits_T_7; // @[faubtb.scala:81:85]
assign io_resp_f1_2_predicted_pc_bits_0 = s1_resp_2_bits; // @[faubtb.scala:21:7, :65:23]
wire _s1_resp_3_valid_T; // @[faubtb.scala:80:34]
assign io_resp_f1_3_predicted_pc_valid_0 = s1_resp_3_valid; // @[faubtb.scala:21:7, :65:23]
wire [39:0] _s1_resp_3_bits_T_7; // @[faubtb.scala:81:85]
assign io_resp_f1_3_predicted_pc_bits_0 = s1_resp_3_bits; // @[faubtb.scala:21:7, :65:23]
wire _s1_taken_0_T_2; // @[faubtb.scala:84:43]
assign io_resp_f1_0_taken_0 = s1_taken_0; // @[faubtb.scala:21:7, :66:23]
wire _s1_taken_1_T_2; // @[faubtb.scala:84:43]
assign io_resp_f1_1_taken_0 = s1_taken_1; // @[faubtb.scala:21:7, :66:23]
wire _s1_taken_2_T_2; // @[faubtb.scala:84:43]
assign io_resp_f1_2_taken_0 = s1_taken_2; // @[faubtb.scala:21:7, :66:23]
wire _s1_taken_3_T_2; // @[faubtb.scala:84:43]
assign io_resp_f1_3_taken_0 = s1_taken_3; // @[faubtb.scala:21:7, :66:23]
wire _s1_is_br_0_T; // @[faubtb.scala:82:42]
assign io_resp_f1_0_is_br_0 = s1_is_br_0; // @[faubtb.scala:21:7, :67:23]
wire _s1_is_br_1_T; // @[faubtb.scala:82:42]
assign io_resp_f1_1_is_br_0 = s1_is_br_1; // @[faubtb.scala:21:7, :67:23]
wire _s1_is_br_2_T; // @[faubtb.scala:82:42]
assign io_resp_f1_2_is_br_0 = s1_is_br_2; // @[faubtb.scala:21:7, :67:23]
wire _s1_is_br_3_T; // @[faubtb.scala:82:42]
assign io_resp_f1_3_is_br_0 = s1_is_br_3; // @[faubtb.scala:21:7, :67:23]
wire _s1_is_jal_0_T_1; // @[faubtb.scala:83:42]
assign io_resp_f1_0_is_jal_0 = s1_is_jal_0; // @[faubtb.scala:21:7, :68:23]
wire _s1_is_jal_1_T_1; // @[faubtb.scala:83:42]
assign io_resp_f1_1_is_jal_0 = s1_is_jal_1; // @[faubtb.scala:21:7, :68:23]
wire _s1_is_jal_2_T_1; // @[faubtb.scala:83:42]
assign io_resp_f1_2_is_jal_0 = s1_is_jal_2; // @[faubtb.scala:21:7, :68:23]
wire _s1_is_jal_3_T_1; // @[faubtb.scala:83:42]
assign io_resp_f1_3_is_jal_0 = s1_is_jal_3; // @[faubtb.scala:21:7, :68:23]
wire _s1_hit_ohs_T_1 = meta_0_0_tag == _s1_hit_ohs_T; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_0 = _s1_hit_ohs_T_1; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_3 = meta_1_0_tag == _s1_hit_ohs_T_2; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1 = _s1_hit_ohs_T_3; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_5 = meta_2_0_tag == _s1_hit_ohs_T_4; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2 = _s1_hit_ohs_T_5; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_7 = meta_3_0_tag == _s1_hit_ohs_T_6; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3 = _s1_hit_ohs_T_7; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_9 = meta_4_0_tag == _s1_hit_ohs_T_8; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_4 = _s1_hit_ohs_T_9; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_11 = meta_5_0_tag == _s1_hit_ohs_T_10; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_5 = _s1_hit_ohs_T_11; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_13 = meta_6_0_tag == _s1_hit_ohs_T_12; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_6 = _s1_hit_ohs_T_13; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_15 = meta_7_0_tag == _s1_hit_ohs_T_14; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_7 = _s1_hit_ohs_T_15; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_17 = meta_8_0_tag == _s1_hit_ohs_T_16; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_8 = _s1_hit_ohs_T_17; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_19 = meta_9_0_tag == _s1_hit_ohs_T_18; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_9 = _s1_hit_ohs_T_19; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_21 = meta_10_0_tag == _s1_hit_ohs_T_20; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_10 = _s1_hit_ohs_T_21; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_23 = meta_11_0_tag == _s1_hit_ohs_T_22; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_11 = _s1_hit_ohs_T_23; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_25 = meta_12_0_tag == _s1_hit_ohs_T_24; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_12 = _s1_hit_ohs_T_25; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_27 = meta_13_0_tag == _s1_hit_ohs_T_26; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_13 = _s1_hit_ohs_T_27; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_29 = meta_14_0_tag == _s1_hit_ohs_T_28; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_14 = _s1_hit_ohs_T_29; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_31 = meta_15_0_tag == _s1_hit_ohs_T_30; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_15 = _s1_hit_ohs_T_31; // @[faubtb.scala:71:12, :72:22]
wire s1_hit_ohs_0_0 = _s1_hit_ohs_WIRE_0; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_1 = _s1_hit_ohs_WIRE_1; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_2 = _s1_hit_ohs_WIRE_2; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_3 = _s1_hit_ohs_WIRE_3; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_4 = _s1_hit_ohs_WIRE_4; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_5 = _s1_hit_ohs_WIRE_5; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_6 = _s1_hit_ohs_WIRE_6; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_7 = _s1_hit_ohs_WIRE_7; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_8 = _s1_hit_ohs_WIRE_8; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_9 = _s1_hit_ohs_WIRE_9; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_10 = _s1_hit_ohs_WIRE_10; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_11 = _s1_hit_ohs_WIRE_11; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_12 = _s1_hit_ohs_WIRE_12; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_13 = _s1_hit_ohs_WIRE_13; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_14 = _s1_hit_ohs_WIRE_14; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_0_15 = _s1_hit_ohs_WIRE_15; // @[faubtb.scala:70:27, :71:12]
wire _s1_hit_ohs_T_33 = meta_0_1_tag == _s1_hit_ohs_T_32; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_0 = _s1_hit_ohs_T_33; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_35 = meta_1_1_tag == _s1_hit_ohs_T_34; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_1 = _s1_hit_ohs_T_35; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_37 = meta_2_1_tag == _s1_hit_ohs_T_36; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_2 = _s1_hit_ohs_T_37; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_39 = meta_3_1_tag == _s1_hit_ohs_T_38; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_3 = _s1_hit_ohs_T_39; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_41 = meta_4_1_tag == _s1_hit_ohs_T_40; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_4 = _s1_hit_ohs_T_41; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_43 = meta_5_1_tag == _s1_hit_ohs_T_42; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_5 = _s1_hit_ohs_T_43; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_45 = meta_6_1_tag == _s1_hit_ohs_T_44; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_6 = _s1_hit_ohs_T_45; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_47 = meta_7_1_tag == _s1_hit_ohs_T_46; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_7 = _s1_hit_ohs_T_47; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_49 = meta_8_1_tag == _s1_hit_ohs_T_48; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_8 = _s1_hit_ohs_T_49; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_51 = meta_9_1_tag == _s1_hit_ohs_T_50; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_9 = _s1_hit_ohs_T_51; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_53 = meta_10_1_tag == _s1_hit_ohs_T_52; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_10 = _s1_hit_ohs_T_53; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_55 = meta_11_1_tag == _s1_hit_ohs_T_54; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_11 = _s1_hit_ohs_T_55; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_57 = meta_12_1_tag == _s1_hit_ohs_T_56; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_12 = _s1_hit_ohs_T_57; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_59 = meta_13_1_tag == _s1_hit_ohs_T_58; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_13 = _s1_hit_ohs_T_59; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_61 = meta_14_1_tag == _s1_hit_ohs_T_60; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_14 = _s1_hit_ohs_T_61; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_63 = meta_15_1_tag == _s1_hit_ohs_T_62; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_1_15 = _s1_hit_ohs_T_63; // @[faubtb.scala:71:12, :72:22]
wire s1_hit_ohs_1_0 = _s1_hit_ohs_WIRE_1_0; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_1 = _s1_hit_ohs_WIRE_1_1; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_2 = _s1_hit_ohs_WIRE_1_2; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_3 = _s1_hit_ohs_WIRE_1_3; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_4 = _s1_hit_ohs_WIRE_1_4; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_5 = _s1_hit_ohs_WIRE_1_5; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_6 = _s1_hit_ohs_WIRE_1_6; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_7 = _s1_hit_ohs_WIRE_1_7; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_8 = _s1_hit_ohs_WIRE_1_8; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_9 = _s1_hit_ohs_WIRE_1_9; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_10 = _s1_hit_ohs_WIRE_1_10; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_11 = _s1_hit_ohs_WIRE_1_11; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_12 = _s1_hit_ohs_WIRE_1_12; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_13 = _s1_hit_ohs_WIRE_1_13; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_14 = _s1_hit_ohs_WIRE_1_14; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_1_15 = _s1_hit_ohs_WIRE_1_15; // @[faubtb.scala:70:27, :71:12]
wire _s1_hit_ohs_T_65 = meta_0_2_tag == _s1_hit_ohs_T_64; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_0 = _s1_hit_ohs_T_65; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_67 = meta_1_2_tag == _s1_hit_ohs_T_66; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_1 = _s1_hit_ohs_T_67; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_69 = meta_2_2_tag == _s1_hit_ohs_T_68; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_2 = _s1_hit_ohs_T_69; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_71 = meta_3_2_tag == _s1_hit_ohs_T_70; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_3 = _s1_hit_ohs_T_71; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_73 = meta_4_2_tag == _s1_hit_ohs_T_72; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_4 = _s1_hit_ohs_T_73; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_75 = meta_5_2_tag == _s1_hit_ohs_T_74; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_5 = _s1_hit_ohs_T_75; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_77 = meta_6_2_tag == _s1_hit_ohs_T_76; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_6 = _s1_hit_ohs_T_77; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_79 = meta_7_2_tag == _s1_hit_ohs_T_78; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_7 = _s1_hit_ohs_T_79; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_81 = meta_8_2_tag == _s1_hit_ohs_T_80; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_8 = _s1_hit_ohs_T_81; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_83 = meta_9_2_tag == _s1_hit_ohs_T_82; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_9 = _s1_hit_ohs_T_83; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_85 = meta_10_2_tag == _s1_hit_ohs_T_84; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_10 = _s1_hit_ohs_T_85; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_87 = meta_11_2_tag == _s1_hit_ohs_T_86; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_11 = _s1_hit_ohs_T_87; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_89 = meta_12_2_tag == _s1_hit_ohs_T_88; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_12 = _s1_hit_ohs_T_89; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_91 = meta_13_2_tag == _s1_hit_ohs_T_90; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_13 = _s1_hit_ohs_T_91; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_93 = meta_14_2_tag == _s1_hit_ohs_T_92; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_14 = _s1_hit_ohs_T_93; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_95 = meta_15_2_tag == _s1_hit_ohs_T_94; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_2_15 = _s1_hit_ohs_T_95; // @[faubtb.scala:71:12, :72:22]
wire s1_hit_ohs_2_0 = _s1_hit_ohs_WIRE_2_0; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_1 = _s1_hit_ohs_WIRE_2_1; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_2 = _s1_hit_ohs_WIRE_2_2; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_3 = _s1_hit_ohs_WIRE_2_3; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_4 = _s1_hit_ohs_WIRE_2_4; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_5 = _s1_hit_ohs_WIRE_2_5; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_6 = _s1_hit_ohs_WIRE_2_6; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_7 = _s1_hit_ohs_WIRE_2_7; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_8 = _s1_hit_ohs_WIRE_2_8; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_9 = _s1_hit_ohs_WIRE_2_9; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_10 = _s1_hit_ohs_WIRE_2_10; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_11 = _s1_hit_ohs_WIRE_2_11; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_12 = _s1_hit_ohs_WIRE_2_12; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_13 = _s1_hit_ohs_WIRE_2_13; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_14 = _s1_hit_ohs_WIRE_2_14; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_2_15 = _s1_hit_ohs_WIRE_2_15; // @[faubtb.scala:70:27, :71:12]
wire _s1_hit_ohs_T_97 = meta_0_3_tag == _s1_hit_ohs_T_96; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_0 = _s1_hit_ohs_T_97; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_99 = meta_1_3_tag == _s1_hit_ohs_T_98; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_1 = _s1_hit_ohs_T_99; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_101 = meta_2_3_tag == _s1_hit_ohs_T_100; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_2 = _s1_hit_ohs_T_101; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_103 = meta_3_3_tag == _s1_hit_ohs_T_102; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_3 = _s1_hit_ohs_T_103; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_105 = meta_4_3_tag == _s1_hit_ohs_T_104; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_4 = _s1_hit_ohs_T_105; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_107 = meta_5_3_tag == _s1_hit_ohs_T_106; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_5 = _s1_hit_ohs_T_107; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_109 = meta_6_3_tag == _s1_hit_ohs_T_108; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_6 = _s1_hit_ohs_T_109; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_111 = meta_7_3_tag == _s1_hit_ohs_T_110; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_7 = _s1_hit_ohs_T_111; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_113 = meta_8_3_tag == _s1_hit_ohs_T_112; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_8 = _s1_hit_ohs_T_113; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_115 = meta_9_3_tag == _s1_hit_ohs_T_114; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_9 = _s1_hit_ohs_T_115; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_117 = meta_10_3_tag == _s1_hit_ohs_T_116; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_10 = _s1_hit_ohs_T_117; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_119 = meta_11_3_tag == _s1_hit_ohs_T_118; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_11 = _s1_hit_ohs_T_119; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_121 = meta_12_3_tag == _s1_hit_ohs_T_120; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_12 = _s1_hit_ohs_T_121; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_123 = meta_13_3_tag == _s1_hit_ohs_T_122; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_13 = _s1_hit_ohs_T_123; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_125 = meta_14_3_tag == _s1_hit_ohs_T_124; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_14 = _s1_hit_ohs_T_125; // @[faubtb.scala:71:12, :72:22]
wire _s1_hit_ohs_T_127 = meta_15_3_tag == _s1_hit_ohs_T_126; // @[faubtb.scala:57:25, :72:{22,36}]
wire _s1_hit_ohs_WIRE_3_15 = _s1_hit_ohs_T_127; // @[faubtb.scala:71:12, :72:22]
wire s1_hit_ohs_3_0 = _s1_hit_ohs_WIRE_3_0; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_1 = _s1_hit_ohs_WIRE_3_1; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_2 = _s1_hit_ohs_WIRE_3_2; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_3 = _s1_hit_ohs_WIRE_3_3; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_4 = _s1_hit_ohs_WIRE_3_4; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_5 = _s1_hit_ohs_WIRE_3_5; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_6 = _s1_hit_ohs_WIRE_3_6; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_7 = _s1_hit_ohs_WIRE_3_7; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_8 = _s1_hit_ohs_WIRE_3_8; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_9 = _s1_hit_ohs_WIRE_3_9; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_10 = _s1_hit_ohs_WIRE_3_10; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_11 = _s1_hit_ohs_WIRE_3_11; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_12 = _s1_hit_ohs_WIRE_3_12; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_13 = _s1_hit_ohs_WIRE_3_13; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_14 = _s1_hit_ohs_WIRE_3_14; // @[faubtb.scala:70:27, :71:12]
wire s1_hit_ohs_3_15 = _s1_hit_ohs_WIRE_3_15; // @[faubtb.scala:70:27, :71:12]
wire _s1_hits_T = s1_hit_ohs_0_0 | s1_hit_ohs_0_1; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_1 = _s1_hits_T | s1_hit_ohs_0_2; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_2 = _s1_hits_T_1 | s1_hit_ohs_0_3; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_3 = _s1_hits_T_2 | s1_hit_ohs_0_4; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_4 = _s1_hits_T_3 | s1_hit_ohs_0_5; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_5 = _s1_hits_T_4 | s1_hit_ohs_0_6; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_6 = _s1_hits_T_5 | s1_hit_ohs_0_7; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_7 = _s1_hits_T_6 | s1_hit_ohs_0_8; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_8 = _s1_hits_T_7 | s1_hit_ohs_0_9; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_9 = _s1_hits_T_8 | s1_hit_ohs_0_10; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_10 = _s1_hits_T_9 | s1_hit_ohs_0_11; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_11 = _s1_hits_T_10 | s1_hit_ohs_0_12; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_12 = _s1_hits_T_11 | s1_hit_ohs_0_13; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_13 = _s1_hits_T_12 | s1_hit_ohs_0_14; // @[faubtb.scala:70:27, :75:55]
assign s1_hits_0 = _s1_hits_T_13 | s1_hit_ohs_0_15; // @[faubtb.scala:70:27, :75:55]
assign s1_meta_hits_0 = s1_hits_0; // @[faubtb.scala:53:21, :75:55]
wire _s1_hits_T_14 = s1_hit_ohs_1_0 | s1_hit_ohs_1_1; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_15 = _s1_hits_T_14 | s1_hit_ohs_1_2; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_16 = _s1_hits_T_15 | s1_hit_ohs_1_3; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_17 = _s1_hits_T_16 | s1_hit_ohs_1_4; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_18 = _s1_hits_T_17 | s1_hit_ohs_1_5; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_19 = _s1_hits_T_18 | s1_hit_ohs_1_6; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_20 = _s1_hits_T_19 | s1_hit_ohs_1_7; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_21 = _s1_hits_T_20 | s1_hit_ohs_1_8; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_22 = _s1_hits_T_21 | s1_hit_ohs_1_9; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_23 = _s1_hits_T_22 | s1_hit_ohs_1_10; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_24 = _s1_hits_T_23 | s1_hit_ohs_1_11; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_25 = _s1_hits_T_24 | s1_hit_ohs_1_12; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_26 = _s1_hits_T_25 | s1_hit_ohs_1_13; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_27 = _s1_hits_T_26 | s1_hit_ohs_1_14; // @[faubtb.scala:70:27, :75:55]
assign s1_hits_1 = _s1_hits_T_27 | s1_hit_ohs_1_15; // @[faubtb.scala:70:27, :75:55]
assign s1_meta_hits_1 = s1_hits_1; // @[faubtb.scala:53:21, :75:55]
wire _s1_hits_T_28 = s1_hit_ohs_2_0 | s1_hit_ohs_2_1; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_29 = _s1_hits_T_28 | s1_hit_ohs_2_2; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_30 = _s1_hits_T_29 | s1_hit_ohs_2_3; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_31 = _s1_hits_T_30 | s1_hit_ohs_2_4; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_32 = _s1_hits_T_31 | s1_hit_ohs_2_5; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_33 = _s1_hits_T_32 | s1_hit_ohs_2_6; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_34 = _s1_hits_T_33 | s1_hit_ohs_2_7; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_35 = _s1_hits_T_34 | s1_hit_ohs_2_8; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_36 = _s1_hits_T_35 | s1_hit_ohs_2_9; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_37 = _s1_hits_T_36 | s1_hit_ohs_2_10; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_38 = _s1_hits_T_37 | s1_hit_ohs_2_11; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_39 = _s1_hits_T_38 | s1_hit_ohs_2_12; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_40 = _s1_hits_T_39 | s1_hit_ohs_2_13; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_41 = _s1_hits_T_40 | s1_hit_ohs_2_14; // @[faubtb.scala:70:27, :75:55]
assign s1_hits_2 = _s1_hits_T_41 | s1_hit_ohs_2_15; // @[faubtb.scala:70:27, :75:55]
assign s1_meta_hits_2 = s1_hits_2; // @[faubtb.scala:53:21, :75:55]
wire _s1_hits_T_42 = s1_hit_ohs_3_0 | s1_hit_ohs_3_1; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_43 = _s1_hits_T_42 | s1_hit_ohs_3_2; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_44 = _s1_hits_T_43 | s1_hit_ohs_3_3; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_45 = _s1_hits_T_44 | s1_hit_ohs_3_4; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_46 = _s1_hits_T_45 | s1_hit_ohs_3_5; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_47 = _s1_hits_T_46 | s1_hit_ohs_3_6; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_48 = _s1_hits_T_47 | s1_hit_ohs_3_7; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_49 = _s1_hits_T_48 | s1_hit_ohs_3_8; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_50 = _s1_hits_T_49 | s1_hit_ohs_3_9; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_51 = _s1_hits_T_50 | s1_hit_ohs_3_10; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_52 = _s1_hits_T_51 | s1_hit_ohs_3_11; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_53 = _s1_hits_T_52 | s1_hit_ohs_3_12; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_54 = _s1_hits_T_53 | s1_hit_ohs_3_13; // @[faubtb.scala:70:27, :75:55]
wire _s1_hits_T_55 = _s1_hits_T_54 | s1_hit_ohs_3_14; // @[faubtb.scala:70:27, :75:55]
assign s1_hits_3 = _s1_hits_T_55 | s1_hit_ohs_3_15; // @[faubtb.scala:70:27, :75:55]
assign s1_meta_hits_3 = s1_hits_3; // @[faubtb.scala:53:21, :75:55]
wire [3:0] _s1_hit_ways_T = {3'h7, ~s1_hit_ohs_0_14}; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_1 = s1_hit_ohs_0_13 ? 4'hD : _s1_hit_ways_T; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_2 = s1_hit_ohs_0_12 ? 4'hC : _s1_hit_ways_T_1; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_3 = s1_hit_ohs_0_11 ? 4'hB : _s1_hit_ways_T_2; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_4 = s1_hit_ohs_0_10 ? 4'hA : _s1_hit_ways_T_3; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_5 = s1_hit_ohs_0_9 ? 4'h9 : _s1_hit_ways_T_4; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_6 = s1_hit_ohs_0_8 ? 4'h8 : _s1_hit_ways_T_5; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_7 = s1_hit_ohs_0_7 ? 4'h7 : _s1_hit_ways_T_6; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_8 = s1_hit_ohs_0_6 ? 4'h6 : _s1_hit_ways_T_7; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_9 = s1_hit_ohs_0_5 ? 4'h5 : _s1_hit_ways_T_8; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_10 = s1_hit_ohs_0_4 ? 4'h4 : _s1_hit_ways_T_9; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_11 = s1_hit_ohs_0_3 ? 4'h3 : _s1_hit_ways_T_10; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_12 = s1_hit_ohs_0_2 ? 4'h2 : _s1_hit_ways_T_11; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_13 = s1_hit_ohs_0_1 ? 4'h1 : _s1_hit_ways_T_12; // @[OneHot.scala:58:35]
wire [3:0] s1_hit_ways_0 = s1_hit_ohs_0_0 ? 4'h0 : _s1_hit_ways_T_13; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_14 = {3'h7, ~s1_hit_ohs_1_14}; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_15 = s1_hit_ohs_1_13 ? 4'hD : _s1_hit_ways_T_14; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_16 = s1_hit_ohs_1_12 ? 4'hC : _s1_hit_ways_T_15; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_17 = s1_hit_ohs_1_11 ? 4'hB : _s1_hit_ways_T_16; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_18 = s1_hit_ohs_1_10 ? 4'hA : _s1_hit_ways_T_17; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_19 = s1_hit_ohs_1_9 ? 4'h9 : _s1_hit_ways_T_18; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_20 = s1_hit_ohs_1_8 ? 4'h8 : _s1_hit_ways_T_19; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_21 = s1_hit_ohs_1_7 ? 4'h7 : _s1_hit_ways_T_20; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_22 = s1_hit_ohs_1_6 ? 4'h6 : _s1_hit_ways_T_21; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_23 = s1_hit_ohs_1_5 ? 4'h5 : _s1_hit_ways_T_22; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_24 = s1_hit_ohs_1_4 ? 4'h4 : _s1_hit_ways_T_23; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_25 = s1_hit_ohs_1_3 ? 4'h3 : _s1_hit_ways_T_24; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_26 = s1_hit_ohs_1_2 ? 4'h2 : _s1_hit_ways_T_25; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_27 = s1_hit_ohs_1_1 ? 4'h1 : _s1_hit_ways_T_26; // @[OneHot.scala:58:35]
wire [3:0] s1_hit_ways_1 = s1_hit_ohs_1_0 ? 4'h0 : _s1_hit_ways_T_27; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_28 = {3'h7, ~s1_hit_ohs_2_14}; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_29 = s1_hit_ohs_2_13 ? 4'hD : _s1_hit_ways_T_28; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_30 = s1_hit_ohs_2_12 ? 4'hC : _s1_hit_ways_T_29; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_31 = s1_hit_ohs_2_11 ? 4'hB : _s1_hit_ways_T_30; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_32 = s1_hit_ohs_2_10 ? 4'hA : _s1_hit_ways_T_31; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_33 = s1_hit_ohs_2_9 ? 4'h9 : _s1_hit_ways_T_32; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_34 = s1_hit_ohs_2_8 ? 4'h8 : _s1_hit_ways_T_33; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_35 = s1_hit_ohs_2_7 ? 4'h7 : _s1_hit_ways_T_34; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_36 = s1_hit_ohs_2_6 ? 4'h6 : _s1_hit_ways_T_35; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_37 = s1_hit_ohs_2_5 ? 4'h5 : _s1_hit_ways_T_36; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_38 = s1_hit_ohs_2_4 ? 4'h4 : _s1_hit_ways_T_37; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_39 = s1_hit_ohs_2_3 ? 4'h3 : _s1_hit_ways_T_38; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_40 = s1_hit_ohs_2_2 ? 4'h2 : _s1_hit_ways_T_39; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_41 = s1_hit_ohs_2_1 ? 4'h1 : _s1_hit_ways_T_40; // @[OneHot.scala:58:35]
wire [3:0] s1_hit_ways_2 = s1_hit_ohs_2_0 ? 4'h0 : _s1_hit_ways_T_41; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_42 = {3'h7, ~s1_hit_ohs_3_14}; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_43 = s1_hit_ohs_3_13 ? 4'hD : _s1_hit_ways_T_42; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_44 = s1_hit_ohs_3_12 ? 4'hC : _s1_hit_ways_T_43; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_45 = s1_hit_ohs_3_11 ? 4'hB : _s1_hit_ways_T_44; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_46 = s1_hit_ohs_3_10 ? 4'hA : _s1_hit_ways_T_45; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_47 = s1_hit_ohs_3_9 ? 4'h9 : _s1_hit_ways_T_46; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_48 = s1_hit_ohs_3_8 ? 4'h8 : _s1_hit_ways_T_47; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_49 = s1_hit_ohs_3_7 ? 4'h7 : _s1_hit_ways_T_48; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_50 = s1_hit_ohs_3_6 ? 4'h6 : _s1_hit_ways_T_49; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_51 = s1_hit_ohs_3_5 ? 4'h5 : _s1_hit_ways_T_50; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_52 = s1_hit_ohs_3_4 ? 4'h4 : _s1_hit_ways_T_51; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_53 = s1_hit_ohs_3_3 ? 4'h3 : _s1_hit_ways_T_52; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_54 = s1_hit_ohs_3_2 ? 4'h2 : _s1_hit_ways_T_53; // @[Mux.scala:50:70]
wire [3:0] _s1_hit_ways_T_55 = s1_hit_ohs_3_1 ? 4'h1 : _s1_hit_ways_T_54; // @[OneHot.scala:58:35]
wire [3:0] s1_hit_ways_3 = s1_hit_ohs_3_0 ? 4'h0 : _s1_hit_ways_T_55; // @[Mux.scala:50:70]
assign _s1_resp_0_valid_T = s1_valid & s1_hits_0; // @[predictor.scala:168:25]
assign s1_resp_0_valid = _s1_resp_0_valid_T; // @[faubtb.scala:65:23, :80:34]
wire [40:0] _s1_resp_0_bits_T_1 = {_s1_resp_0_bits_T[39], _s1_resp_0_bits_T}; // @[faubtb.scala:81:{32,39}]
wire [39:0] _s1_resp_0_bits_T_2 = _s1_resp_0_bits_T_1[39:0]; // @[faubtb.scala:81:39]
wire [39:0] _s1_resp_0_bits_T_3 = _s1_resp_0_bits_T_2; // @[faubtb.scala:81:39]
wire [15:0][12:0] _GEN_1 = {{btb_15_0_offset}, {btb_14_0_offset}, {btb_13_0_offset}, {btb_12_0_offset}, {btb_11_0_offset}, {btb_10_0_offset}, {btb_9_0_offset}, {btb_8_0_offset}, {btb_7_0_offset}, {btb_6_0_offset}, {btb_5_0_offset}, {btb_4_0_offset}, {btb_3_0_offset}, {btb_2_0_offset}, {btb_1_0_offset}, {btb_0_0_offset}}; // @[faubtb.scala:58:21, :81:52]
wire [40:0] _s1_resp_0_bits_T_4 = {_s1_resp_0_bits_T_3[39], _s1_resp_0_bits_T_3} + {{28{_GEN_1[s1_hit_ways_0][12]}}, _GEN_1[s1_hit_ways_0]}; // @[Mux.scala:50:70]
wire [39:0] _s1_resp_0_bits_T_5 = _s1_resp_0_bits_T_4[39:0]; // @[faubtb.scala:81:52]
wire [39:0] _s1_resp_0_bits_T_6 = _s1_resp_0_bits_T_5; // @[faubtb.scala:81:52]
assign _s1_resp_0_bits_T_7 = _s1_resp_0_bits_T_6; // @[faubtb.scala:81:{52,85}]
assign s1_resp_0_bits = _s1_resp_0_bits_T_7; // @[faubtb.scala:65:23, :81:85]
wire [15:0] _GEN_2 = {{meta_15_0_is_br}, {meta_14_0_is_br}, {meta_13_0_is_br}, {meta_12_0_is_br}, {meta_11_0_is_br}, {meta_10_0_is_br}, {meta_9_0_is_br}, {meta_8_0_is_br}, {meta_7_0_is_br}, {meta_6_0_is_br}, {meta_5_0_is_br}, {meta_4_0_is_br}, {meta_3_0_is_br}, {meta_2_0_is_br}, {meta_1_0_is_br}, {meta_0_0_is_br}}; // @[faubtb.scala:57:25, :82:42]
wire [15:0][1:0] _GEN_3 = {{meta_15_0_ctr}, {meta_14_0_ctr}, {meta_13_0_ctr}, {meta_12_0_ctr}, {meta_11_0_ctr}, {meta_10_0_ctr}, {meta_9_0_ctr}, {meta_8_0_ctr}, {meta_7_0_ctr}, {meta_6_0_ctr}, {meta_5_0_ctr}, {meta_4_0_ctr}, {meta_3_0_ctr}, {meta_2_0_ctr}, {meta_1_0_ctr}, {meta_0_0_ctr}}; // @[faubtb.scala:57:25, :82:42]
assign _s1_is_br_0_T = s1_resp_0_valid & _GEN_2[s1_hit_ways_0]; // @[Mux.scala:50:70]
assign s1_is_br_0 = _s1_is_br_0_T; // @[faubtb.scala:67:23, :82:42]
wire _s1_is_jal_0_T = ~_GEN_2[s1_hit_ways_0]; // @[Mux.scala:50:70]
assign _s1_is_jal_0_T_1 = s1_resp_0_valid & _s1_is_jal_0_T; // @[faubtb.scala:65:23, :83:{42,45}]
assign s1_is_jal_0 = _s1_is_jal_0_T_1; // @[faubtb.scala:68:23, :83:42]
wire _s1_taken_0_T = ~_GEN_2[s1_hit_ways_0]; // @[Mux.scala:50:70]
wire _s1_taken_0_T_1 = _GEN_3[s1_hit_ways_0][1]; // @[Mux.scala:50:70]
assign _s1_taken_0_T_2 = _s1_taken_0_T | _s1_taken_0_T_1; // @[faubtb.scala:84:{25,43,60}]
assign s1_taken_0 = _s1_taken_0_T_2; // @[faubtb.scala:66:23, :84:43]
assign _s1_resp_1_valid_T = s1_valid & s1_hits_1; // @[predictor.scala:168:25]
assign s1_resp_1_valid = _s1_resp_1_valid_T; // @[faubtb.scala:65:23, :80:34]
wire [40:0] _s1_resp_1_bits_T_1 = {_s1_resp_1_bits_T[39], _s1_resp_1_bits_T} + 41'h2; // @[faubtb.scala:81:{32,39}]
wire [39:0] _s1_resp_1_bits_T_2 = _s1_resp_1_bits_T_1[39:0]; // @[faubtb.scala:81:39]
wire [39:0] _s1_resp_1_bits_T_3 = _s1_resp_1_bits_T_2; // @[faubtb.scala:81:39]
wire [15:0][12:0] _GEN_4 = {{btb_15_1_offset}, {btb_14_1_offset}, {btb_13_1_offset}, {btb_12_1_offset}, {btb_11_1_offset}, {btb_10_1_offset}, {btb_9_1_offset}, {btb_8_1_offset}, {btb_7_1_offset}, {btb_6_1_offset}, {btb_5_1_offset}, {btb_4_1_offset}, {btb_3_1_offset}, {btb_2_1_offset}, {btb_1_1_offset}, {btb_0_1_offset}}; // @[faubtb.scala:58:21, :81:52]
wire [40:0] _s1_resp_1_bits_T_4 = {_s1_resp_1_bits_T_3[39], _s1_resp_1_bits_T_3} + {{28{_GEN_4[s1_hit_ways_1][12]}}, _GEN_4[s1_hit_ways_1]}; // @[Mux.scala:50:70]
wire [39:0] _s1_resp_1_bits_T_5 = _s1_resp_1_bits_T_4[39:0]; // @[faubtb.scala:81:52]
wire [39:0] _s1_resp_1_bits_T_6 = _s1_resp_1_bits_T_5; // @[faubtb.scala:81:52]
assign _s1_resp_1_bits_T_7 = _s1_resp_1_bits_T_6; // @[faubtb.scala:81:{52,85}]
assign s1_resp_1_bits = _s1_resp_1_bits_T_7; // @[faubtb.scala:65:23, :81:85]
wire [15:0] _GEN_5 = {{meta_15_1_is_br}, {meta_14_1_is_br}, {meta_13_1_is_br}, {meta_12_1_is_br}, {meta_11_1_is_br}, {meta_10_1_is_br}, {meta_9_1_is_br}, {meta_8_1_is_br}, {meta_7_1_is_br}, {meta_6_1_is_br}, {meta_5_1_is_br}, {meta_4_1_is_br}, {meta_3_1_is_br}, {meta_2_1_is_br}, {meta_1_1_is_br}, {meta_0_1_is_br}}; // @[faubtb.scala:57:25, :82:42]
wire [15:0][1:0] _GEN_6 = {{meta_15_1_ctr}, {meta_14_1_ctr}, {meta_13_1_ctr}, {meta_12_1_ctr}, {meta_11_1_ctr}, {meta_10_1_ctr}, {meta_9_1_ctr}, {meta_8_1_ctr}, {meta_7_1_ctr}, {meta_6_1_ctr}, {meta_5_1_ctr}, {meta_4_1_ctr}, {meta_3_1_ctr}, {meta_2_1_ctr}, {meta_1_1_ctr}, {meta_0_1_ctr}}; // @[faubtb.scala:57:25, :82:42]
assign _s1_is_br_1_T = s1_resp_1_valid & _GEN_5[s1_hit_ways_1]; // @[Mux.scala:50:70]
assign s1_is_br_1 = _s1_is_br_1_T; // @[faubtb.scala:67:23, :82:42]
wire _s1_is_jal_1_T = ~_GEN_5[s1_hit_ways_1]; // @[Mux.scala:50:70]
assign _s1_is_jal_1_T_1 = s1_resp_1_valid & _s1_is_jal_1_T; // @[faubtb.scala:65:23, :83:{42,45}]
assign s1_is_jal_1 = _s1_is_jal_1_T_1; // @[faubtb.scala:68:23, :83:42]
wire _s1_taken_1_T = ~_GEN_5[s1_hit_ways_1]; // @[Mux.scala:50:70]
wire _s1_taken_1_T_1 = _GEN_6[s1_hit_ways_1][1]; // @[Mux.scala:50:70]
assign _s1_taken_1_T_2 = _s1_taken_1_T | _s1_taken_1_T_1; // @[faubtb.scala:84:{25,43,60}]
assign s1_taken_1 = _s1_taken_1_T_2; // @[faubtb.scala:66:23, :84:43]
assign _s1_resp_2_valid_T = s1_valid & s1_hits_2; // @[predictor.scala:168:25]
assign s1_resp_2_valid = _s1_resp_2_valid_T; // @[faubtb.scala:65:23, :80:34]
wire [40:0] _s1_resp_2_bits_T_1 = {_s1_resp_2_bits_T[39], _s1_resp_2_bits_T} + 41'h4; // @[faubtb.scala:81:{32,39}]
wire [39:0] _s1_resp_2_bits_T_2 = _s1_resp_2_bits_T_1[39:0]; // @[faubtb.scala:81:39]
wire [39:0] _s1_resp_2_bits_T_3 = _s1_resp_2_bits_T_2; // @[faubtb.scala:81:39]
wire [15:0][12:0] _GEN_7 = {{btb_15_2_offset}, {btb_14_2_offset}, {btb_13_2_offset}, {btb_12_2_offset}, {btb_11_2_offset}, {btb_10_2_offset}, {btb_9_2_offset}, {btb_8_2_offset}, {btb_7_2_offset}, {btb_6_2_offset}, {btb_5_2_offset}, {btb_4_2_offset}, {btb_3_2_offset}, {btb_2_2_offset}, {btb_1_2_offset}, {btb_0_2_offset}}; // @[faubtb.scala:58:21, :81:52]
wire [40:0] _s1_resp_2_bits_T_4 = {_s1_resp_2_bits_T_3[39], _s1_resp_2_bits_T_3} + {{28{_GEN_7[s1_hit_ways_2][12]}}, _GEN_7[s1_hit_ways_2]}; // @[Mux.scala:50:70]
wire [39:0] _s1_resp_2_bits_T_5 = _s1_resp_2_bits_T_4[39:0]; // @[faubtb.scala:81:52]
wire [39:0] _s1_resp_2_bits_T_6 = _s1_resp_2_bits_T_5; // @[faubtb.scala:81:52]
assign _s1_resp_2_bits_T_7 = _s1_resp_2_bits_T_6; // @[faubtb.scala:81:{52,85}]
assign s1_resp_2_bits = _s1_resp_2_bits_T_7; // @[faubtb.scala:65:23, :81:85]
wire [15:0] _GEN_8 = {{meta_15_2_is_br}, {meta_14_2_is_br}, {meta_13_2_is_br}, {meta_12_2_is_br}, {meta_11_2_is_br}, {meta_10_2_is_br}, {meta_9_2_is_br}, {meta_8_2_is_br}, {meta_7_2_is_br}, {meta_6_2_is_br}, {meta_5_2_is_br}, {meta_4_2_is_br}, {meta_3_2_is_br}, {meta_2_2_is_br}, {meta_1_2_is_br}, {meta_0_2_is_br}}; // @[faubtb.scala:57:25, :82:42]
wire [15:0][1:0] _GEN_9 = {{meta_15_2_ctr}, {meta_14_2_ctr}, {meta_13_2_ctr}, {meta_12_2_ctr}, {meta_11_2_ctr}, {meta_10_2_ctr}, {meta_9_2_ctr}, {meta_8_2_ctr}, {meta_7_2_ctr}, {meta_6_2_ctr}, {meta_5_2_ctr}, {meta_4_2_ctr}, {meta_3_2_ctr}, {meta_2_2_ctr}, {meta_1_2_ctr}, {meta_0_2_ctr}}; // @[faubtb.scala:57:25, :82:42]
assign _s1_is_br_2_T = s1_resp_2_valid & _GEN_8[s1_hit_ways_2]; // @[Mux.scala:50:70]
assign s1_is_br_2 = _s1_is_br_2_T; // @[faubtb.scala:67:23, :82:42]
wire _s1_is_jal_2_T = ~_GEN_8[s1_hit_ways_2]; // @[Mux.scala:50:70]
assign _s1_is_jal_2_T_1 = s1_resp_2_valid & _s1_is_jal_2_T; // @[faubtb.scala:65:23, :83:{42,45}]
assign s1_is_jal_2 = _s1_is_jal_2_T_1; // @[faubtb.scala:68:23, :83:42]
wire _s1_taken_2_T = ~_GEN_8[s1_hit_ways_2]; // @[Mux.scala:50:70]
wire _s1_taken_2_T_1 = _GEN_9[s1_hit_ways_2][1]; // @[Mux.scala:50:70]
assign _s1_taken_2_T_2 = _s1_taken_2_T | _s1_taken_2_T_1; // @[faubtb.scala:84:{25,43,60}]
assign s1_taken_2 = _s1_taken_2_T_2; // @[faubtb.scala:66:23, :84:43]
assign _s1_resp_3_valid_T = s1_valid & s1_hits_3; // @[predictor.scala:168:25]
assign s1_resp_3_valid = _s1_resp_3_valid_T; // @[faubtb.scala:65:23, :80:34]
wire [40:0] _s1_resp_3_bits_T_1 = {_s1_resp_3_bits_T[39], _s1_resp_3_bits_T} + 41'h6; // @[faubtb.scala:81:{32,39}]
wire [39:0] _s1_resp_3_bits_T_2 = _s1_resp_3_bits_T_1[39:0]; // @[faubtb.scala:81:39]
wire [39:0] _s1_resp_3_bits_T_3 = _s1_resp_3_bits_T_2; // @[faubtb.scala:81:39]
wire [15:0][12:0] _GEN_10 = {{btb_15_3_offset}, {btb_14_3_offset}, {btb_13_3_offset}, {btb_12_3_offset}, {btb_11_3_offset}, {btb_10_3_offset}, {btb_9_3_offset}, {btb_8_3_offset}, {btb_7_3_offset}, {btb_6_3_offset}, {btb_5_3_offset}, {btb_4_3_offset}, {btb_3_3_offset}, {btb_2_3_offset}, {btb_1_3_offset}, {btb_0_3_offset}}; // @[faubtb.scala:58:21, :81:52]
wire [40:0] _s1_resp_3_bits_T_4 = {_s1_resp_3_bits_T_3[39], _s1_resp_3_bits_T_3} + {{28{_GEN_10[s1_hit_ways_3][12]}}, _GEN_10[s1_hit_ways_3]}; // @[Mux.scala:50:70]
wire [39:0] _s1_resp_3_bits_T_5 = _s1_resp_3_bits_T_4[39:0]; // @[faubtb.scala:81:52]
wire [39:0] _s1_resp_3_bits_T_6 = _s1_resp_3_bits_T_5; // @[faubtb.scala:81:52]
assign _s1_resp_3_bits_T_7 = _s1_resp_3_bits_T_6; // @[faubtb.scala:81:{52,85}]
assign s1_resp_3_bits = _s1_resp_3_bits_T_7; // @[faubtb.scala:65:23, :81:85]
wire [15:0] _GEN_11 = {{meta_15_3_is_br}, {meta_14_3_is_br}, {meta_13_3_is_br}, {meta_12_3_is_br}, {meta_11_3_is_br}, {meta_10_3_is_br}, {meta_9_3_is_br}, {meta_8_3_is_br}, {meta_7_3_is_br}, {meta_6_3_is_br}, {meta_5_3_is_br}, {meta_4_3_is_br}, {meta_3_3_is_br}, {meta_2_3_is_br}, {meta_1_3_is_br}, {meta_0_3_is_br}}; // @[faubtb.scala:57:25, :82:42]
wire [15:0][1:0] _GEN_12 = {{meta_15_3_ctr}, {meta_14_3_ctr}, {meta_13_3_ctr}, {meta_12_3_ctr}, {meta_11_3_ctr}, {meta_10_3_ctr}, {meta_9_3_ctr}, {meta_8_3_ctr}, {meta_7_3_ctr}, {meta_6_3_ctr}, {meta_5_3_ctr}, {meta_4_3_ctr}, {meta_3_3_ctr}, {meta_2_3_ctr}, {meta_1_3_ctr}, {meta_0_3_ctr}}; // @[faubtb.scala:57:25, :82:42]
assign _s1_is_br_3_T = s1_resp_3_valid & _GEN_11[s1_hit_ways_3]; // @[Mux.scala:50:70]
assign s1_is_br_3 = _s1_is_br_3_T; // @[faubtb.scala:67:23, :82:42]
wire _s1_is_jal_3_T = ~_GEN_11[s1_hit_ways_3]; // @[Mux.scala:50:70]
assign _s1_is_jal_3_T_1 = s1_resp_3_valid & _s1_is_jal_3_T; // @[faubtb.scala:65:23, :83:{42,45}]
assign s1_is_jal_3 = _s1_is_jal_3_T_1; // @[faubtb.scala:68:23, :83:42]
wire _s1_taken_3_T = ~_GEN_11[s1_hit_ways_3]; // @[Mux.scala:50:70]
wire _s1_taken_3_T_1 = _GEN_12[s1_hit_ways_3][1]; // @[Mux.scala:50:70]
assign _s1_taken_3_T_2 = _s1_taken_3_T | _s1_taken_3_T_1; // @[faubtb.scala:84:{25,43,60}]
assign s1_taken_3 = _s1_taken_3_T_2; // @[faubtb.scala:66:23, :84:43]
wire [36:0] _alloc_way_r_metas_WIRE_16_0_0 = _alloc_way_r_metas_WIRE_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_0_1 = _alloc_way_r_metas_WIRE_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_0_2 = _alloc_way_r_metas_WIRE_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_0_3 = _alloc_way_r_metas_WIRE_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_1_0 = _alloc_way_r_metas_WIRE_1_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_1_1 = _alloc_way_r_metas_WIRE_1_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_1_2 = _alloc_way_r_metas_WIRE_1_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_1_3 = _alloc_way_r_metas_WIRE_1_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_2_0 = _alloc_way_r_metas_WIRE_2_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_2_1 = _alloc_way_r_metas_WIRE_2_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_2_2 = _alloc_way_r_metas_WIRE_2_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_2_3 = _alloc_way_r_metas_WIRE_2_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_3_0 = _alloc_way_r_metas_WIRE_3_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_3_1 = _alloc_way_r_metas_WIRE_3_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_3_2 = _alloc_way_r_metas_WIRE_3_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_3_3 = _alloc_way_r_metas_WIRE_3_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_4_0 = _alloc_way_r_metas_WIRE_4_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_4_1 = _alloc_way_r_metas_WIRE_4_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_4_2 = _alloc_way_r_metas_WIRE_4_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_4_3 = _alloc_way_r_metas_WIRE_4_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_5_0 = _alloc_way_r_metas_WIRE_5_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_5_1 = _alloc_way_r_metas_WIRE_5_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_5_2 = _alloc_way_r_metas_WIRE_5_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_5_3 = _alloc_way_r_metas_WIRE_5_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_6_0 = _alloc_way_r_metas_WIRE_6_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_6_1 = _alloc_way_r_metas_WIRE_6_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_6_2 = _alloc_way_r_metas_WIRE_6_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_6_3 = _alloc_way_r_metas_WIRE_6_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_7_0 = _alloc_way_r_metas_WIRE_7_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_7_1 = _alloc_way_r_metas_WIRE_7_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_7_2 = _alloc_way_r_metas_WIRE_7_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_7_3 = _alloc_way_r_metas_WIRE_7_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_8_0 = _alloc_way_r_metas_WIRE_8_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_8_1 = _alloc_way_r_metas_WIRE_8_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_8_2 = _alloc_way_r_metas_WIRE_8_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_8_3 = _alloc_way_r_metas_WIRE_8_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_9_0 = _alloc_way_r_metas_WIRE_9_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_9_1 = _alloc_way_r_metas_WIRE_9_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_9_2 = _alloc_way_r_metas_WIRE_9_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_9_3 = _alloc_way_r_metas_WIRE_9_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_10_0 = _alloc_way_r_metas_WIRE_10_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_10_1 = _alloc_way_r_metas_WIRE_10_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_10_2 = _alloc_way_r_metas_WIRE_10_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_10_3 = _alloc_way_r_metas_WIRE_10_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_11_0 = _alloc_way_r_metas_WIRE_11_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_11_1 = _alloc_way_r_metas_WIRE_11_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_11_2 = _alloc_way_r_metas_WIRE_11_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_11_3 = _alloc_way_r_metas_WIRE_11_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_12_0 = _alloc_way_r_metas_WIRE_12_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_12_1 = _alloc_way_r_metas_WIRE_12_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_12_2 = _alloc_way_r_metas_WIRE_12_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_12_3 = _alloc_way_r_metas_WIRE_12_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_13_0 = _alloc_way_r_metas_WIRE_13_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_13_1 = _alloc_way_r_metas_WIRE_13_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_13_2 = _alloc_way_r_metas_WIRE_13_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_13_3 = _alloc_way_r_metas_WIRE_13_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_14_0 = _alloc_way_r_metas_WIRE_14_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_14_1 = _alloc_way_r_metas_WIRE_14_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_14_2 = _alloc_way_r_metas_WIRE_14_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_14_3 = _alloc_way_r_metas_WIRE_14_3; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_15_0 = _alloc_way_r_metas_WIRE_15_0; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_15_1 = _alloc_way_r_metas_WIRE_15_1; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_15_2 = _alloc_way_r_metas_WIRE_15_2; // @[faubtb.scala:89:{30,52}]
wire [36:0] _alloc_way_r_metas_WIRE_16_15_3 = _alloc_way_r_metas_WIRE_15_3; // @[faubtb.scala:89:{30,52}]
wire [73:0] alloc_way_r_metas_lo = {_alloc_way_r_metas_WIRE_16_0_1, _alloc_way_r_metas_WIRE_16_0_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi = {_alloc_way_r_metas_WIRE_16_0_3, _alloc_way_r_metas_WIRE_16_0_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T = {alloc_way_r_metas_hi, alloc_way_r_metas_lo}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_1 = {_alloc_way_r_metas_WIRE_16_1_1, _alloc_way_r_metas_WIRE_16_1_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_1 = {_alloc_way_r_metas_WIRE_16_1_3, _alloc_way_r_metas_WIRE_16_1_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_1 = {alloc_way_r_metas_hi_1, alloc_way_r_metas_lo_1}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_2 = {_alloc_way_r_metas_WIRE_16_2_1, _alloc_way_r_metas_WIRE_16_2_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_2 = {_alloc_way_r_metas_WIRE_16_2_3, _alloc_way_r_metas_WIRE_16_2_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_2 = {alloc_way_r_metas_hi_2, alloc_way_r_metas_lo_2}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_3 = {_alloc_way_r_metas_WIRE_16_3_1, _alloc_way_r_metas_WIRE_16_3_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_3 = {_alloc_way_r_metas_WIRE_16_3_3, _alloc_way_r_metas_WIRE_16_3_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_3 = {alloc_way_r_metas_hi_3, alloc_way_r_metas_lo_3}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_4 = {_alloc_way_r_metas_WIRE_16_4_1, _alloc_way_r_metas_WIRE_16_4_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_4 = {_alloc_way_r_metas_WIRE_16_4_3, _alloc_way_r_metas_WIRE_16_4_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_4 = {alloc_way_r_metas_hi_4, alloc_way_r_metas_lo_4}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_5 = {_alloc_way_r_metas_WIRE_16_5_1, _alloc_way_r_metas_WIRE_16_5_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_5 = {_alloc_way_r_metas_WIRE_16_5_3, _alloc_way_r_metas_WIRE_16_5_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_5 = {alloc_way_r_metas_hi_5, alloc_way_r_metas_lo_5}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_6 = {_alloc_way_r_metas_WIRE_16_6_1, _alloc_way_r_metas_WIRE_16_6_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_6 = {_alloc_way_r_metas_WIRE_16_6_3, _alloc_way_r_metas_WIRE_16_6_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_6 = {alloc_way_r_metas_hi_6, alloc_way_r_metas_lo_6}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_7 = {_alloc_way_r_metas_WIRE_16_7_1, _alloc_way_r_metas_WIRE_16_7_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_7 = {_alloc_way_r_metas_WIRE_16_7_3, _alloc_way_r_metas_WIRE_16_7_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_7 = {alloc_way_r_metas_hi_7, alloc_way_r_metas_lo_7}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_8 = {_alloc_way_r_metas_WIRE_16_8_1, _alloc_way_r_metas_WIRE_16_8_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_8 = {_alloc_way_r_metas_WIRE_16_8_3, _alloc_way_r_metas_WIRE_16_8_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_8 = {alloc_way_r_metas_hi_8, alloc_way_r_metas_lo_8}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_9 = {_alloc_way_r_metas_WIRE_16_9_1, _alloc_way_r_metas_WIRE_16_9_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_9 = {_alloc_way_r_metas_WIRE_16_9_3, _alloc_way_r_metas_WIRE_16_9_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_9 = {alloc_way_r_metas_hi_9, alloc_way_r_metas_lo_9}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_10 = {_alloc_way_r_metas_WIRE_16_10_1, _alloc_way_r_metas_WIRE_16_10_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_10 = {_alloc_way_r_metas_WIRE_16_10_3, _alloc_way_r_metas_WIRE_16_10_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_10 = {alloc_way_r_metas_hi_10, alloc_way_r_metas_lo_10}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_11 = {_alloc_way_r_metas_WIRE_16_11_1, _alloc_way_r_metas_WIRE_16_11_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_11 = {_alloc_way_r_metas_WIRE_16_11_3, _alloc_way_r_metas_WIRE_16_11_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_11 = {alloc_way_r_metas_hi_11, alloc_way_r_metas_lo_11}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_12 = {_alloc_way_r_metas_WIRE_16_12_1, _alloc_way_r_metas_WIRE_16_12_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_12 = {_alloc_way_r_metas_WIRE_16_12_3, _alloc_way_r_metas_WIRE_16_12_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_12 = {alloc_way_r_metas_hi_12, alloc_way_r_metas_lo_12}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_13 = {_alloc_way_r_metas_WIRE_16_13_1, _alloc_way_r_metas_WIRE_16_13_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_13 = {_alloc_way_r_metas_WIRE_16_13_3, _alloc_way_r_metas_WIRE_16_13_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_13 = {alloc_way_r_metas_hi_13, alloc_way_r_metas_lo_13}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_14 = {_alloc_way_r_metas_WIRE_16_14_1, _alloc_way_r_metas_WIRE_16_14_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_14 = {_alloc_way_r_metas_WIRE_16_14_3, _alloc_way_r_metas_WIRE_16_14_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_14 = {alloc_way_r_metas_hi_14, alloc_way_r_metas_lo_14}; // @[faubtb.scala:89:69]
wire [73:0] alloc_way_r_metas_lo_15 = {_alloc_way_r_metas_WIRE_16_15_1, _alloc_way_r_metas_WIRE_16_15_0}; // @[faubtb.scala:89:{30,69}]
wire [73:0] alloc_way_r_metas_hi_15 = {_alloc_way_r_metas_WIRE_16_15_3, _alloc_way_r_metas_WIRE_16_15_2}; // @[faubtb.scala:89:{30,69}]
wire [147:0] _alloc_way_r_metas_T_15 = {alloc_way_r_metas_hi_15, alloc_way_r_metas_lo_15}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_lo_lo_lo = {_alloc_way_r_metas_T_1, _alloc_way_r_metas_T}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_lo_lo_hi = {_alloc_way_r_metas_T_3, _alloc_way_r_metas_T_2}; // @[faubtb.scala:89:69]
wire [591:0] alloc_way_r_metas_lo_lo = {alloc_way_r_metas_lo_lo_hi, alloc_way_r_metas_lo_lo_lo}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_lo_hi_lo = {_alloc_way_r_metas_T_5, _alloc_way_r_metas_T_4}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_lo_hi_hi = {_alloc_way_r_metas_T_7, _alloc_way_r_metas_T_6}; // @[faubtb.scala:89:69]
wire [591:0] alloc_way_r_metas_lo_hi = {alloc_way_r_metas_lo_hi_hi, alloc_way_r_metas_lo_hi_lo}; // @[faubtb.scala:89:69]
wire [1183:0] alloc_way_r_metas_lo_16 = {alloc_way_r_metas_lo_hi, alloc_way_r_metas_lo_lo}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_hi_lo_lo = {_alloc_way_r_metas_T_9, _alloc_way_r_metas_T_8}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_hi_lo_hi = {_alloc_way_r_metas_T_11, _alloc_way_r_metas_T_10}; // @[faubtb.scala:89:69]
wire [591:0] alloc_way_r_metas_hi_lo = {alloc_way_r_metas_hi_lo_hi, alloc_way_r_metas_hi_lo_lo}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_hi_hi_lo = {_alloc_way_r_metas_T_13, _alloc_way_r_metas_T_12}; // @[faubtb.scala:89:69]
wire [295:0] alloc_way_r_metas_hi_hi_hi = {_alloc_way_r_metas_T_15, _alloc_way_r_metas_T_14}; // @[faubtb.scala:89:69]
wire [591:0] alloc_way_r_metas_hi_hi = {alloc_way_r_metas_hi_hi_hi, alloc_way_r_metas_hi_hi_lo}; // @[faubtb.scala:89:69]
wire [1183:0] alloc_way_r_metas_hi_16 = {alloc_way_r_metas_hi_hi, alloc_way_r_metas_hi_lo}; // @[faubtb.scala:89:69]
wire [2367:0] _alloc_way_r_metas_T_16 = {alloc_way_r_metas_hi_16, alloc_way_r_metas_lo_16}; // @[faubtb.scala:89:69]
wire [2404:0] alloc_way_r_metas = {_alloc_way_r_metas_T_16, _alloc_way_r_metas_T_17}; // @[faubtb.scala:89:{22,69,83}]
wire [3:0] alloc_way_chunks_0 = alloc_way_r_metas[3:0]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_1 = alloc_way_r_metas[7:4]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_2 = alloc_way_r_metas[11:8]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_3 = alloc_way_r_metas[15:12]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_4 = alloc_way_r_metas[19:16]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_5 = alloc_way_r_metas[23:20]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_6 = alloc_way_r_metas[27:24]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_7 = alloc_way_r_metas[31:28]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_8 = alloc_way_r_metas[35:32]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_9 = alloc_way_r_metas[39:36]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_10 = alloc_way_r_metas[43:40]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_11 = alloc_way_r_metas[47:44]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_12 = alloc_way_r_metas[51:48]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_13 = alloc_way_r_metas[55:52]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_14 = alloc_way_r_metas[59:56]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_15 = alloc_way_r_metas[63:60]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_16 = alloc_way_r_metas[67:64]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_17 = alloc_way_r_metas[71:68]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_18 = alloc_way_r_metas[75:72]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_19 = alloc_way_r_metas[79:76]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_20 = alloc_way_r_metas[83:80]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_21 = alloc_way_r_metas[87:84]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_22 = alloc_way_r_metas[91:88]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_23 = alloc_way_r_metas[95:92]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_24 = alloc_way_r_metas[99:96]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_25 = alloc_way_r_metas[103:100]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_26 = alloc_way_r_metas[107:104]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_27 = alloc_way_r_metas[111:108]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_28 = alloc_way_r_metas[115:112]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_29 = alloc_way_r_metas[119:116]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_30 = alloc_way_r_metas[123:120]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_31 = alloc_way_r_metas[127:124]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_32 = alloc_way_r_metas[131:128]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_33 = alloc_way_r_metas[135:132]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_34 = alloc_way_r_metas[139:136]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_35 = alloc_way_r_metas[143:140]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_36 = alloc_way_r_metas[147:144]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_37 = alloc_way_r_metas[151:148]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_38 = alloc_way_r_metas[155:152]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_39 = alloc_way_r_metas[159:156]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_40 = alloc_way_r_metas[163:160]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_41 = alloc_way_r_metas[167:164]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_42 = alloc_way_r_metas[171:168]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_43 = alloc_way_r_metas[175:172]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_44 = alloc_way_r_metas[179:176]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_45 = alloc_way_r_metas[183:180]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_46 = alloc_way_r_metas[187:184]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_47 = alloc_way_r_metas[191:188]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_48 = alloc_way_r_metas[195:192]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_49 = alloc_way_r_metas[199:196]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_50 = alloc_way_r_metas[203:200]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_51 = alloc_way_r_metas[207:204]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_52 = alloc_way_r_metas[211:208]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_53 = alloc_way_r_metas[215:212]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_54 = alloc_way_r_metas[219:216]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_55 = alloc_way_r_metas[223:220]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_56 = alloc_way_r_metas[227:224]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_57 = alloc_way_r_metas[231:228]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_58 = alloc_way_r_metas[235:232]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_59 = alloc_way_r_metas[239:236]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_60 = alloc_way_r_metas[243:240]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_61 = alloc_way_r_metas[247:244]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_62 = alloc_way_r_metas[251:248]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_63 = alloc_way_r_metas[255:252]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_64 = alloc_way_r_metas[259:256]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_65 = alloc_way_r_metas[263:260]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_66 = alloc_way_r_metas[267:264]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_67 = alloc_way_r_metas[271:268]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_68 = alloc_way_r_metas[275:272]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_69 = alloc_way_r_metas[279:276]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_70 = alloc_way_r_metas[283:280]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_71 = alloc_way_r_metas[287:284]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_72 = alloc_way_r_metas[291:288]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_73 = alloc_way_r_metas[295:292]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_74 = alloc_way_r_metas[299:296]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_75 = alloc_way_r_metas[303:300]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_76 = alloc_way_r_metas[307:304]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_77 = alloc_way_r_metas[311:308]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_78 = alloc_way_r_metas[315:312]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_79 = alloc_way_r_metas[319:316]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_80 = alloc_way_r_metas[323:320]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_81 = alloc_way_r_metas[327:324]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_82 = alloc_way_r_metas[331:328]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_83 = alloc_way_r_metas[335:332]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_84 = alloc_way_r_metas[339:336]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_85 = alloc_way_r_metas[343:340]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_86 = alloc_way_r_metas[347:344]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_87 = alloc_way_r_metas[351:348]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_88 = alloc_way_r_metas[355:352]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_89 = alloc_way_r_metas[359:356]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_90 = alloc_way_r_metas[363:360]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_91 = alloc_way_r_metas[367:364]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_92 = alloc_way_r_metas[371:368]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_93 = alloc_way_r_metas[375:372]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_94 = alloc_way_r_metas[379:376]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_95 = alloc_way_r_metas[383:380]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_96 = alloc_way_r_metas[387:384]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_97 = alloc_way_r_metas[391:388]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_98 = alloc_way_r_metas[395:392]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_99 = alloc_way_r_metas[399:396]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_100 = alloc_way_r_metas[403:400]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_101 = alloc_way_r_metas[407:404]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_102 = alloc_way_r_metas[411:408]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_103 = alloc_way_r_metas[415:412]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_104 = alloc_way_r_metas[419:416]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_105 = alloc_way_r_metas[423:420]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_106 = alloc_way_r_metas[427:424]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_107 = alloc_way_r_metas[431:428]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_108 = alloc_way_r_metas[435:432]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_109 = alloc_way_r_metas[439:436]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_110 = alloc_way_r_metas[443:440]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_111 = alloc_way_r_metas[447:444]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_112 = alloc_way_r_metas[451:448]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_113 = alloc_way_r_metas[455:452]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_114 = alloc_way_r_metas[459:456]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_115 = alloc_way_r_metas[463:460]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_116 = alloc_way_r_metas[467:464]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_117 = alloc_way_r_metas[471:468]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_118 = alloc_way_r_metas[475:472]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_119 = alloc_way_r_metas[479:476]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_120 = alloc_way_r_metas[483:480]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_121 = alloc_way_r_metas[487:484]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_122 = alloc_way_r_metas[491:488]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_123 = alloc_way_r_metas[495:492]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_124 = alloc_way_r_metas[499:496]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_125 = alloc_way_r_metas[503:500]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_126 = alloc_way_r_metas[507:504]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_127 = alloc_way_r_metas[511:508]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_128 = alloc_way_r_metas[515:512]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_129 = alloc_way_r_metas[519:516]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_130 = alloc_way_r_metas[523:520]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_131 = alloc_way_r_metas[527:524]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_132 = alloc_way_r_metas[531:528]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_133 = alloc_way_r_metas[535:532]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_134 = alloc_way_r_metas[539:536]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_135 = alloc_way_r_metas[543:540]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_136 = alloc_way_r_metas[547:544]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_137 = alloc_way_r_metas[551:548]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_138 = alloc_way_r_metas[555:552]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_139 = alloc_way_r_metas[559:556]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_140 = alloc_way_r_metas[563:560]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_141 = alloc_way_r_metas[567:564]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_142 = alloc_way_r_metas[571:568]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_143 = alloc_way_r_metas[575:572]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_144 = alloc_way_r_metas[579:576]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_145 = alloc_way_r_metas[583:580]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_146 = alloc_way_r_metas[587:584]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_147 = alloc_way_r_metas[591:588]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_148 = alloc_way_r_metas[595:592]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_149 = alloc_way_r_metas[599:596]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_150 = alloc_way_r_metas[603:600]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_151 = alloc_way_r_metas[607:604]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_152 = alloc_way_r_metas[611:608]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_153 = alloc_way_r_metas[615:612]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_154 = alloc_way_r_metas[619:616]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_155 = alloc_way_r_metas[623:620]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_156 = alloc_way_r_metas[627:624]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_157 = alloc_way_r_metas[631:628]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_158 = alloc_way_r_metas[635:632]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_159 = alloc_way_r_metas[639:636]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_160 = alloc_way_r_metas[643:640]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_161 = alloc_way_r_metas[647:644]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_162 = alloc_way_r_metas[651:648]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_163 = alloc_way_r_metas[655:652]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_164 = alloc_way_r_metas[659:656]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_165 = alloc_way_r_metas[663:660]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_166 = alloc_way_r_metas[667:664]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_167 = alloc_way_r_metas[671:668]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_168 = alloc_way_r_metas[675:672]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_169 = alloc_way_r_metas[679:676]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_170 = alloc_way_r_metas[683:680]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_171 = alloc_way_r_metas[687:684]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_172 = alloc_way_r_metas[691:688]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_173 = alloc_way_r_metas[695:692]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_174 = alloc_way_r_metas[699:696]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_175 = alloc_way_r_metas[703:700]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_176 = alloc_way_r_metas[707:704]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_177 = alloc_way_r_metas[711:708]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_178 = alloc_way_r_metas[715:712]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_179 = alloc_way_r_metas[719:716]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_180 = alloc_way_r_metas[723:720]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_181 = alloc_way_r_metas[727:724]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_182 = alloc_way_r_metas[731:728]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_183 = alloc_way_r_metas[735:732]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_184 = alloc_way_r_metas[739:736]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_185 = alloc_way_r_metas[743:740]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_186 = alloc_way_r_metas[747:744]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_187 = alloc_way_r_metas[751:748]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_188 = alloc_way_r_metas[755:752]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_189 = alloc_way_r_metas[759:756]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_190 = alloc_way_r_metas[763:760]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_191 = alloc_way_r_metas[767:764]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_192 = alloc_way_r_metas[771:768]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_193 = alloc_way_r_metas[775:772]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_194 = alloc_way_r_metas[779:776]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_195 = alloc_way_r_metas[783:780]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_196 = alloc_way_r_metas[787:784]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_197 = alloc_way_r_metas[791:788]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_198 = alloc_way_r_metas[795:792]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_199 = alloc_way_r_metas[799:796]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_200 = alloc_way_r_metas[803:800]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_201 = alloc_way_r_metas[807:804]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_202 = alloc_way_r_metas[811:808]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_203 = alloc_way_r_metas[815:812]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_204 = alloc_way_r_metas[819:816]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_205 = alloc_way_r_metas[823:820]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_206 = alloc_way_r_metas[827:824]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_207 = alloc_way_r_metas[831:828]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_208 = alloc_way_r_metas[835:832]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_209 = alloc_way_r_metas[839:836]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_210 = alloc_way_r_metas[843:840]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_211 = alloc_way_r_metas[847:844]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_212 = alloc_way_r_metas[851:848]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_213 = alloc_way_r_metas[855:852]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_214 = alloc_way_r_metas[859:856]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_215 = alloc_way_r_metas[863:860]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_216 = alloc_way_r_metas[867:864]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_217 = alloc_way_r_metas[871:868]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_218 = alloc_way_r_metas[875:872]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_219 = alloc_way_r_metas[879:876]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_220 = alloc_way_r_metas[883:880]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_221 = alloc_way_r_metas[887:884]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_222 = alloc_way_r_metas[891:888]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_223 = alloc_way_r_metas[895:892]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_224 = alloc_way_r_metas[899:896]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_225 = alloc_way_r_metas[903:900]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_226 = alloc_way_r_metas[907:904]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_227 = alloc_way_r_metas[911:908]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_228 = alloc_way_r_metas[915:912]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_229 = alloc_way_r_metas[919:916]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_230 = alloc_way_r_metas[923:920]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_231 = alloc_way_r_metas[927:924]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_232 = alloc_way_r_metas[931:928]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_233 = alloc_way_r_metas[935:932]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_234 = alloc_way_r_metas[939:936]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_235 = alloc_way_r_metas[943:940]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_236 = alloc_way_r_metas[947:944]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_237 = alloc_way_r_metas[951:948]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_238 = alloc_way_r_metas[955:952]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_239 = alloc_way_r_metas[959:956]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_240 = alloc_way_r_metas[963:960]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_241 = alloc_way_r_metas[967:964]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_242 = alloc_way_r_metas[971:968]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_243 = alloc_way_r_metas[975:972]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_244 = alloc_way_r_metas[979:976]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_245 = alloc_way_r_metas[983:980]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_246 = alloc_way_r_metas[987:984]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_247 = alloc_way_r_metas[991:988]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_248 = alloc_way_r_metas[995:992]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_249 = alloc_way_r_metas[999:996]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_250 = alloc_way_r_metas[1003:1000]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_251 = alloc_way_r_metas[1007:1004]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_252 = alloc_way_r_metas[1011:1008]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_253 = alloc_way_r_metas[1015:1012]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_254 = alloc_way_r_metas[1019:1016]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_255 = alloc_way_r_metas[1023:1020]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_256 = alloc_way_r_metas[1027:1024]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_257 = alloc_way_r_metas[1031:1028]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_258 = alloc_way_r_metas[1035:1032]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_259 = alloc_way_r_metas[1039:1036]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_260 = alloc_way_r_metas[1043:1040]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_261 = alloc_way_r_metas[1047:1044]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_262 = alloc_way_r_metas[1051:1048]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_263 = alloc_way_r_metas[1055:1052]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_264 = alloc_way_r_metas[1059:1056]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_265 = alloc_way_r_metas[1063:1060]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_266 = alloc_way_r_metas[1067:1064]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_267 = alloc_way_r_metas[1071:1068]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_268 = alloc_way_r_metas[1075:1072]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_269 = alloc_way_r_metas[1079:1076]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_270 = alloc_way_r_metas[1083:1080]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_271 = alloc_way_r_metas[1087:1084]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_272 = alloc_way_r_metas[1091:1088]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_273 = alloc_way_r_metas[1095:1092]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_274 = alloc_way_r_metas[1099:1096]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_275 = alloc_way_r_metas[1103:1100]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_276 = alloc_way_r_metas[1107:1104]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_277 = alloc_way_r_metas[1111:1108]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_278 = alloc_way_r_metas[1115:1112]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_279 = alloc_way_r_metas[1119:1116]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_280 = alloc_way_r_metas[1123:1120]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_281 = alloc_way_r_metas[1127:1124]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_282 = alloc_way_r_metas[1131:1128]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_283 = alloc_way_r_metas[1135:1132]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_284 = alloc_way_r_metas[1139:1136]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_285 = alloc_way_r_metas[1143:1140]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_286 = alloc_way_r_metas[1147:1144]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_287 = alloc_way_r_metas[1151:1148]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_288 = alloc_way_r_metas[1155:1152]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_289 = alloc_way_r_metas[1159:1156]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_290 = alloc_way_r_metas[1163:1160]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_291 = alloc_way_r_metas[1167:1164]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_292 = alloc_way_r_metas[1171:1168]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_293 = alloc_way_r_metas[1175:1172]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_294 = alloc_way_r_metas[1179:1176]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_295 = alloc_way_r_metas[1183:1180]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_296 = alloc_way_r_metas[1187:1184]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_297 = alloc_way_r_metas[1191:1188]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_298 = alloc_way_r_metas[1195:1192]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_299 = alloc_way_r_metas[1199:1196]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_300 = alloc_way_r_metas[1203:1200]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_301 = alloc_way_r_metas[1207:1204]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_302 = alloc_way_r_metas[1211:1208]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_303 = alloc_way_r_metas[1215:1212]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_304 = alloc_way_r_metas[1219:1216]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_305 = alloc_way_r_metas[1223:1220]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_306 = alloc_way_r_metas[1227:1224]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_307 = alloc_way_r_metas[1231:1228]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_308 = alloc_way_r_metas[1235:1232]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_309 = alloc_way_r_metas[1239:1236]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_310 = alloc_way_r_metas[1243:1240]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_311 = alloc_way_r_metas[1247:1244]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_312 = alloc_way_r_metas[1251:1248]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_313 = alloc_way_r_metas[1255:1252]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_314 = alloc_way_r_metas[1259:1256]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_315 = alloc_way_r_metas[1263:1260]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_316 = alloc_way_r_metas[1267:1264]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_317 = alloc_way_r_metas[1271:1268]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_318 = alloc_way_r_metas[1275:1272]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_319 = alloc_way_r_metas[1279:1276]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_320 = alloc_way_r_metas[1283:1280]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_321 = alloc_way_r_metas[1287:1284]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_322 = alloc_way_r_metas[1291:1288]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_323 = alloc_way_r_metas[1295:1292]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_324 = alloc_way_r_metas[1299:1296]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_325 = alloc_way_r_metas[1303:1300]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_326 = alloc_way_r_metas[1307:1304]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_327 = alloc_way_r_metas[1311:1308]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_328 = alloc_way_r_metas[1315:1312]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_329 = alloc_way_r_metas[1319:1316]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_330 = alloc_way_r_metas[1323:1320]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_331 = alloc_way_r_metas[1327:1324]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_332 = alloc_way_r_metas[1331:1328]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_333 = alloc_way_r_metas[1335:1332]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_334 = alloc_way_r_metas[1339:1336]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_335 = alloc_way_r_metas[1343:1340]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_336 = alloc_way_r_metas[1347:1344]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_337 = alloc_way_r_metas[1351:1348]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_338 = alloc_way_r_metas[1355:1352]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_339 = alloc_way_r_metas[1359:1356]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_340 = alloc_way_r_metas[1363:1360]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_341 = alloc_way_r_metas[1367:1364]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_342 = alloc_way_r_metas[1371:1368]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_343 = alloc_way_r_metas[1375:1372]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_344 = alloc_way_r_metas[1379:1376]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_345 = alloc_way_r_metas[1383:1380]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_346 = alloc_way_r_metas[1387:1384]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_347 = alloc_way_r_metas[1391:1388]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_348 = alloc_way_r_metas[1395:1392]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_349 = alloc_way_r_metas[1399:1396]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_350 = alloc_way_r_metas[1403:1400]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_351 = alloc_way_r_metas[1407:1404]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_352 = alloc_way_r_metas[1411:1408]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_353 = alloc_way_r_metas[1415:1412]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_354 = alloc_way_r_metas[1419:1416]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_355 = alloc_way_r_metas[1423:1420]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_356 = alloc_way_r_metas[1427:1424]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_357 = alloc_way_r_metas[1431:1428]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_358 = alloc_way_r_metas[1435:1432]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_359 = alloc_way_r_metas[1439:1436]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_360 = alloc_way_r_metas[1443:1440]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_361 = alloc_way_r_metas[1447:1444]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_362 = alloc_way_r_metas[1451:1448]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_363 = alloc_way_r_metas[1455:1452]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_364 = alloc_way_r_metas[1459:1456]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_365 = alloc_way_r_metas[1463:1460]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_366 = alloc_way_r_metas[1467:1464]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_367 = alloc_way_r_metas[1471:1468]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_368 = alloc_way_r_metas[1475:1472]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_369 = alloc_way_r_metas[1479:1476]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_370 = alloc_way_r_metas[1483:1480]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_371 = alloc_way_r_metas[1487:1484]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_372 = alloc_way_r_metas[1491:1488]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_373 = alloc_way_r_metas[1495:1492]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_374 = alloc_way_r_metas[1499:1496]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_375 = alloc_way_r_metas[1503:1500]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_376 = alloc_way_r_metas[1507:1504]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_377 = alloc_way_r_metas[1511:1508]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_378 = alloc_way_r_metas[1515:1512]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_379 = alloc_way_r_metas[1519:1516]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_380 = alloc_way_r_metas[1523:1520]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_381 = alloc_way_r_metas[1527:1524]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_382 = alloc_way_r_metas[1531:1528]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_383 = alloc_way_r_metas[1535:1532]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_384 = alloc_way_r_metas[1539:1536]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_385 = alloc_way_r_metas[1543:1540]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_386 = alloc_way_r_metas[1547:1544]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_387 = alloc_way_r_metas[1551:1548]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_388 = alloc_way_r_metas[1555:1552]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_389 = alloc_way_r_metas[1559:1556]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_390 = alloc_way_r_metas[1563:1560]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_391 = alloc_way_r_metas[1567:1564]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_392 = alloc_way_r_metas[1571:1568]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_393 = alloc_way_r_metas[1575:1572]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_394 = alloc_way_r_metas[1579:1576]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_395 = alloc_way_r_metas[1583:1580]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_396 = alloc_way_r_metas[1587:1584]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_397 = alloc_way_r_metas[1591:1588]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_398 = alloc_way_r_metas[1595:1592]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_399 = alloc_way_r_metas[1599:1596]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_400 = alloc_way_r_metas[1603:1600]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_401 = alloc_way_r_metas[1607:1604]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_402 = alloc_way_r_metas[1611:1608]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_403 = alloc_way_r_metas[1615:1612]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_404 = alloc_way_r_metas[1619:1616]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_405 = alloc_way_r_metas[1623:1620]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_406 = alloc_way_r_metas[1627:1624]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_407 = alloc_way_r_metas[1631:1628]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_408 = alloc_way_r_metas[1635:1632]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_409 = alloc_way_r_metas[1639:1636]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_410 = alloc_way_r_metas[1643:1640]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_411 = alloc_way_r_metas[1647:1644]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_412 = alloc_way_r_metas[1651:1648]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_413 = alloc_way_r_metas[1655:1652]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_414 = alloc_way_r_metas[1659:1656]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_415 = alloc_way_r_metas[1663:1660]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_416 = alloc_way_r_metas[1667:1664]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_417 = alloc_way_r_metas[1671:1668]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_418 = alloc_way_r_metas[1675:1672]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_419 = alloc_way_r_metas[1679:1676]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_420 = alloc_way_r_metas[1683:1680]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_421 = alloc_way_r_metas[1687:1684]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_422 = alloc_way_r_metas[1691:1688]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_423 = alloc_way_r_metas[1695:1692]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_424 = alloc_way_r_metas[1699:1696]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_425 = alloc_way_r_metas[1703:1700]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_426 = alloc_way_r_metas[1707:1704]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_427 = alloc_way_r_metas[1711:1708]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_428 = alloc_way_r_metas[1715:1712]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_429 = alloc_way_r_metas[1719:1716]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_430 = alloc_way_r_metas[1723:1720]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_431 = alloc_way_r_metas[1727:1724]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_432 = alloc_way_r_metas[1731:1728]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_433 = alloc_way_r_metas[1735:1732]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_434 = alloc_way_r_metas[1739:1736]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_435 = alloc_way_r_metas[1743:1740]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_436 = alloc_way_r_metas[1747:1744]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_437 = alloc_way_r_metas[1751:1748]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_438 = alloc_way_r_metas[1755:1752]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_439 = alloc_way_r_metas[1759:1756]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_440 = alloc_way_r_metas[1763:1760]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_441 = alloc_way_r_metas[1767:1764]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_442 = alloc_way_r_metas[1771:1768]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_443 = alloc_way_r_metas[1775:1772]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_444 = alloc_way_r_metas[1779:1776]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_445 = alloc_way_r_metas[1783:1780]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_446 = alloc_way_r_metas[1787:1784]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_447 = alloc_way_r_metas[1791:1788]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_448 = alloc_way_r_metas[1795:1792]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_449 = alloc_way_r_metas[1799:1796]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_450 = alloc_way_r_metas[1803:1800]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_451 = alloc_way_r_metas[1807:1804]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_452 = alloc_way_r_metas[1811:1808]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_453 = alloc_way_r_metas[1815:1812]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_454 = alloc_way_r_metas[1819:1816]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_455 = alloc_way_r_metas[1823:1820]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_456 = alloc_way_r_metas[1827:1824]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_457 = alloc_way_r_metas[1831:1828]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_458 = alloc_way_r_metas[1835:1832]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_459 = alloc_way_r_metas[1839:1836]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_460 = alloc_way_r_metas[1843:1840]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_461 = alloc_way_r_metas[1847:1844]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_462 = alloc_way_r_metas[1851:1848]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_463 = alloc_way_r_metas[1855:1852]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_464 = alloc_way_r_metas[1859:1856]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_465 = alloc_way_r_metas[1863:1860]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_466 = alloc_way_r_metas[1867:1864]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_467 = alloc_way_r_metas[1871:1868]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_468 = alloc_way_r_metas[1875:1872]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_469 = alloc_way_r_metas[1879:1876]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_470 = alloc_way_r_metas[1883:1880]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_471 = alloc_way_r_metas[1887:1884]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_472 = alloc_way_r_metas[1891:1888]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_473 = alloc_way_r_metas[1895:1892]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_474 = alloc_way_r_metas[1899:1896]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_475 = alloc_way_r_metas[1903:1900]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_476 = alloc_way_r_metas[1907:1904]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_477 = alloc_way_r_metas[1911:1908]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_478 = alloc_way_r_metas[1915:1912]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_479 = alloc_way_r_metas[1919:1916]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_480 = alloc_way_r_metas[1923:1920]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_481 = alloc_way_r_metas[1927:1924]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_482 = alloc_way_r_metas[1931:1928]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_483 = alloc_way_r_metas[1935:1932]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_484 = alloc_way_r_metas[1939:1936]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_485 = alloc_way_r_metas[1943:1940]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_486 = alloc_way_r_metas[1947:1944]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_487 = alloc_way_r_metas[1951:1948]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_488 = alloc_way_r_metas[1955:1952]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_489 = alloc_way_r_metas[1959:1956]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_490 = alloc_way_r_metas[1963:1960]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_491 = alloc_way_r_metas[1967:1964]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_492 = alloc_way_r_metas[1971:1968]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_493 = alloc_way_r_metas[1975:1972]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_494 = alloc_way_r_metas[1979:1976]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_495 = alloc_way_r_metas[1983:1980]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_496 = alloc_way_r_metas[1987:1984]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_497 = alloc_way_r_metas[1991:1988]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_498 = alloc_way_r_metas[1995:1992]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_499 = alloc_way_r_metas[1999:1996]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_500 = alloc_way_r_metas[2003:2000]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_501 = alloc_way_r_metas[2007:2004]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_502 = alloc_way_r_metas[2011:2008]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_503 = alloc_way_r_metas[2015:2012]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_504 = alloc_way_r_metas[2019:2016]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_505 = alloc_way_r_metas[2023:2020]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_506 = alloc_way_r_metas[2027:2024]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_507 = alloc_way_r_metas[2031:2028]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_508 = alloc_way_r_metas[2035:2032]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_509 = alloc_way_r_metas[2039:2036]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_510 = alloc_way_r_metas[2043:2040]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_511 = alloc_way_r_metas[2047:2044]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_512 = alloc_way_r_metas[2051:2048]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_513 = alloc_way_r_metas[2055:2052]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_514 = alloc_way_r_metas[2059:2056]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_515 = alloc_way_r_metas[2063:2060]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_516 = alloc_way_r_metas[2067:2064]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_517 = alloc_way_r_metas[2071:2068]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_518 = alloc_way_r_metas[2075:2072]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_519 = alloc_way_r_metas[2079:2076]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_520 = alloc_way_r_metas[2083:2080]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_521 = alloc_way_r_metas[2087:2084]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_522 = alloc_way_r_metas[2091:2088]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_523 = alloc_way_r_metas[2095:2092]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_524 = alloc_way_r_metas[2099:2096]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_525 = alloc_way_r_metas[2103:2100]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_526 = alloc_way_r_metas[2107:2104]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_527 = alloc_way_r_metas[2111:2108]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_528 = alloc_way_r_metas[2115:2112]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_529 = alloc_way_r_metas[2119:2116]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_530 = alloc_way_r_metas[2123:2120]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_531 = alloc_way_r_metas[2127:2124]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_532 = alloc_way_r_metas[2131:2128]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_533 = alloc_way_r_metas[2135:2132]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_534 = alloc_way_r_metas[2139:2136]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_535 = alloc_way_r_metas[2143:2140]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_536 = alloc_way_r_metas[2147:2144]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_537 = alloc_way_r_metas[2151:2148]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_538 = alloc_way_r_metas[2155:2152]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_539 = alloc_way_r_metas[2159:2156]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_540 = alloc_way_r_metas[2163:2160]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_541 = alloc_way_r_metas[2167:2164]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_542 = alloc_way_r_metas[2171:2168]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_543 = alloc_way_r_metas[2175:2172]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_544 = alloc_way_r_metas[2179:2176]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_545 = alloc_way_r_metas[2183:2180]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_546 = alloc_way_r_metas[2187:2184]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_547 = alloc_way_r_metas[2191:2188]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_548 = alloc_way_r_metas[2195:2192]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_549 = alloc_way_r_metas[2199:2196]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_550 = alloc_way_r_metas[2203:2200]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_551 = alloc_way_r_metas[2207:2204]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_552 = alloc_way_r_metas[2211:2208]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_553 = alloc_way_r_metas[2215:2212]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_554 = alloc_way_r_metas[2219:2216]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_555 = alloc_way_r_metas[2223:2220]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_556 = alloc_way_r_metas[2227:2224]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_557 = alloc_way_r_metas[2231:2228]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_558 = alloc_way_r_metas[2235:2232]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_559 = alloc_way_r_metas[2239:2236]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_560 = alloc_way_r_metas[2243:2240]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_561 = alloc_way_r_metas[2247:2244]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_562 = alloc_way_r_metas[2251:2248]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_563 = alloc_way_r_metas[2255:2252]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_564 = alloc_way_r_metas[2259:2256]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_565 = alloc_way_r_metas[2263:2260]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_566 = alloc_way_r_metas[2267:2264]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_567 = alloc_way_r_metas[2271:2268]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_568 = alloc_way_r_metas[2275:2272]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_569 = alloc_way_r_metas[2279:2276]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_570 = alloc_way_r_metas[2283:2280]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_571 = alloc_way_r_metas[2287:2284]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_572 = alloc_way_r_metas[2291:2288]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_573 = alloc_way_r_metas[2295:2292]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_574 = alloc_way_r_metas[2299:2296]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_575 = alloc_way_r_metas[2303:2300]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_576 = alloc_way_r_metas[2307:2304]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_577 = alloc_way_r_metas[2311:2308]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_578 = alloc_way_r_metas[2315:2312]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_579 = alloc_way_r_metas[2319:2316]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_580 = alloc_way_r_metas[2323:2320]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_581 = alloc_way_r_metas[2327:2324]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_582 = alloc_way_r_metas[2331:2328]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_583 = alloc_way_r_metas[2335:2332]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_584 = alloc_way_r_metas[2339:2336]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_585 = alloc_way_r_metas[2343:2340]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_586 = alloc_way_r_metas[2347:2344]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_587 = alloc_way_r_metas[2351:2348]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_588 = alloc_way_r_metas[2355:2352]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_589 = alloc_way_r_metas[2359:2356]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_590 = alloc_way_r_metas[2363:2360]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_591 = alloc_way_r_metas[2367:2364]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_592 = alloc_way_r_metas[2371:2368]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_593 = alloc_way_r_metas[2375:2372]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_594 = alloc_way_r_metas[2379:2376]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_595 = alloc_way_r_metas[2383:2380]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_596 = alloc_way_r_metas[2387:2384]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_597 = alloc_way_r_metas[2391:2388]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_598 = alloc_way_r_metas[2395:2392]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_599 = alloc_way_r_metas[2399:2396]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] alloc_way_chunks_600 = alloc_way_r_metas[2403:2400]; // @[faubtb.scala:89:22, :93:14]
wire alloc_way_chunks_601 = alloc_way_r_metas[2404]; // @[faubtb.scala:89:22, :93:14]
wire [3:0] _alloc_way_T = alloc_way_chunks_0 ^ alloc_way_chunks_1; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_1 = _alloc_way_T ^ alloc_way_chunks_2; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_2 = _alloc_way_T_1 ^ alloc_way_chunks_3; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_3 = _alloc_way_T_2 ^ alloc_way_chunks_4; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_4 = _alloc_way_T_3 ^ alloc_way_chunks_5; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_5 = _alloc_way_T_4 ^ alloc_way_chunks_6; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_6 = _alloc_way_T_5 ^ alloc_way_chunks_7; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_7 = _alloc_way_T_6 ^ alloc_way_chunks_8; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_8 = _alloc_way_T_7 ^ alloc_way_chunks_9; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_9 = _alloc_way_T_8 ^ alloc_way_chunks_10; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_10 = _alloc_way_T_9 ^ alloc_way_chunks_11; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_11 = _alloc_way_T_10 ^ alloc_way_chunks_12; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_12 = _alloc_way_T_11 ^ alloc_way_chunks_13; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_13 = _alloc_way_T_12 ^ alloc_way_chunks_14; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_14 = _alloc_way_T_13 ^ alloc_way_chunks_15; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_15 = _alloc_way_T_14 ^ alloc_way_chunks_16; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_16 = _alloc_way_T_15 ^ alloc_way_chunks_17; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_17 = _alloc_way_T_16 ^ alloc_way_chunks_18; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_18 = _alloc_way_T_17 ^ alloc_way_chunks_19; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_19 = _alloc_way_T_18 ^ alloc_way_chunks_20; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_20 = _alloc_way_T_19 ^ alloc_way_chunks_21; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_21 = _alloc_way_T_20 ^ alloc_way_chunks_22; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_22 = _alloc_way_T_21 ^ alloc_way_chunks_23; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_23 = _alloc_way_T_22 ^ alloc_way_chunks_24; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_24 = _alloc_way_T_23 ^ alloc_way_chunks_25; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_25 = _alloc_way_T_24 ^ alloc_way_chunks_26; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_26 = _alloc_way_T_25 ^ alloc_way_chunks_27; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_27 = _alloc_way_T_26 ^ alloc_way_chunks_28; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_28 = _alloc_way_T_27 ^ alloc_way_chunks_29; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_29 = _alloc_way_T_28 ^ alloc_way_chunks_30; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_30 = _alloc_way_T_29 ^ alloc_way_chunks_31; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_31 = _alloc_way_T_30 ^ alloc_way_chunks_32; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_32 = _alloc_way_T_31 ^ alloc_way_chunks_33; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_33 = _alloc_way_T_32 ^ alloc_way_chunks_34; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_34 = _alloc_way_T_33 ^ alloc_way_chunks_35; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_35 = _alloc_way_T_34 ^ alloc_way_chunks_36; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_36 = _alloc_way_T_35 ^ alloc_way_chunks_37; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_37 = _alloc_way_T_36 ^ alloc_way_chunks_38; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_38 = _alloc_way_T_37 ^ alloc_way_chunks_39; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_39 = _alloc_way_T_38 ^ alloc_way_chunks_40; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_40 = _alloc_way_T_39 ^ alloc_way_chunks_41; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_41 = _alloc_way_T_40 ^ alloc_way_chunks_42; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_42 = _alloc_way_T_41 ^ alloc_way_chunks_43; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_43 = _alloc_way_T_42 ^ alloc_way_chunks_44; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_44 = _alloc_way_T_43 ^ alloc_way_chunks_45; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_45 = _alloc_way_T_44 ^ alloc_way_chunks_46; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_46 = _alloc_way_T_45 ^ alloc_way_chunks_47; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_47 = _alloc_way_T_46 ^ alloc_way_chunks_48; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_48 = _alloc_way_T_47 ^ alloc_way_chunks_49; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_49 = _alloc_way_T_48 ^ alloc_way_chunks_50; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_50 = _alloc_way_T_49 ^ alloc_way_chunks_51; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_51 = _alloc_way_T_50 ^ alloc_way_chunks_52; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_52 = _alloc_way_T_51 ^ alloc_way_chunks_53; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_53 = _alloc_way_T_52 ^ alloc_way_chunks_54; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_54 = _alloc_way_T_53 ^ alloc_way_chunks_55; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_55 = _alloc_way_T_54 ^ alloc_way_chunks_56; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_56 = _alloc_way_T_55 ^ alloc_way_chunks_57; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_57 = _alloc_way_T_56 ^ alloc_way_chunks_58; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_58 = _alloc_way_T_57 ^ alloc_way_chunks_59; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_59 = _alloc_way_T_58 ^ alloc_way_chunks_60; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_60 = _alloc_way_T_59 ^ alloc_way_chunks_61; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_61 = _alloc_way_T_60 ^ alloc_way_chunks_62; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_62 = _alloc_way_T_61 ^ alloc_way_chunks_63; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_63 = _alloc_way_T_62 ^ alloc_way_chunks_64; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_64 = _alloc_way_T_63 ^ alloc_way_chunks_65; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_65 = _alloc_way_T_64 ^ alloc_way_chunks_66; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_66 = _alloc_way_T_65 ^ alloc_way_chunks_67; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_67 = _alloc_way_T_66 ^ alloc_way_chunks_68; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_68 = _alloc_way_T_67 ^ alloc_way_chunks_69; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_69 = _alloc_way_T_68 ^ alloc_way_chunks_70; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_70 = _alloc_way_T_69 ^ alloc_way_chunks_71; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_71 = _alloc_way_T_70 ^ alloc_way_chunks_72; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_72 = _alloc_way_T_71 ^ alloc_way_chunks_73; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_73 = _alloc_way_T_72 ^ alloc_way_chunks_74; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_74 = _alloc_way_T_73 ^ alloc_way_chunks_75; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_75 = _alloc_way_T_74 ^ alloc_way_chunks_76; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_76 = _alloc_way_T_75 ^ alloc_way_chunks_77; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_77 = _alloc_way_T_76 ^ alloc_way_chunks_78; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_78 = _alloc_way_T_77 ^ alloc_way_chunks_79; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_79 = _alloc_way_T_78 ^ alloc_way_chunks_80; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_80 = _alloc_way_T_79 ^ alloc_way_chunks_81; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_81 = _alloc_way_T_80 ^ alloc_way_chunks_82; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_82 = _alloc_way_T_81 ^ alloc_way_chunks_83; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_83 = _alloc_way_T_82 ^ alloc_way_chunks_84; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_84 = _alloc_way_T_83 ^ alloc_way_chunks_85; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_85 = _alloc_way_T_84 ^ alloc_way_chunks_86; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_86 = _alloc_way_T_85 ^ alloc_way_chunks_87; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_87 = _alloc_way_T_86 ^ alloc_way_chunks_88; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_88 = _alloc_way_T_87 ^ alloc_way_chunks_89; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_89 = _alloc_way_T_88 ^ alloc_way_chunks_90; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_90 = _alloc_way_T_89 ^ alloc_way_chunks_91; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_91 = _alloc_way_T_90 ^ alloc_way_chunks_92; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_92 = _alloc_way_T_91 ^ alloc_way_chunks_93; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_93 = _alloc_way_T_92 ^ alloc_way_chunks_94; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_94 = _alloc_way_T_93 ^ alloc_way_chunks_95; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_95 = _alloc_way_T_94 ^ alloc_way_chunks_96; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_96 = _alloc_way_T_95 ^ alloc_way_chunks_97; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_97 = _alloc_way_T_96 ^ alloc_way_chunks_98; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_98 = _alloc_way_T_97 ^ alloc_way_chunks_99; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_99 = _alloc_way_T_98 ^ alloc_way_chunks_100; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_100 = _alloc_way_T_99 ^ alloc_way_chunks_101; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_101 = _alloc_way_T_100 ^ alloc_way_chunks_102; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_102 = _alloc_way_T_101 ^ alloc_way_chunks_103; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_103 = _alloc_way_T_102 ^ alloc_way_chunks_104; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_104 = _alloc_way_T_103 ^ alloc_way_chunks_105; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_105 = _alloc_way_T_104 ^ alloc_way_chunks_106; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_106 = _alloc_way_T_105 ^ alloc_way_chunks_107; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_107 = _alloc_way_T_106 ^ alloc_way_chunks_108; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_108 = _alloc_way_T_107 ^ alloc_way_chunks_109; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_109 = _alloc_way_T_108 ^ alloc_way_chunks_110; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_110 = _alloc_way_T_109 ^ alloc_way_chunks_111; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_111 = _alloc_way_T_110 ^ alloc_way_chunks_112; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_112 = _alloc_way_T_111 ^ alloc_way_chunks_113; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_113 = _alloc_way_T_112 ^ alloc_way_chunks_114; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_114 = _alloc_way_T_113 ^ alloc_way_chunks_115; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_115 = _alloc_way_T_114 ^ alloc_way_chunks_116; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_116 = _alloc_way_T_115 ^ alloc_way_chunks_117; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_117 = _alloc_way_T_116 ^ alloc_way_chunks_118; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_118 = _alloc_way_T_117 ^ alloc_way_chunks_119; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_119 = _alloc_way_T_118 ^ alloc_way_chunks_120; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_120 = _alloc_way_T_119 ^ alloc_way_chunks_121; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_121 = _alloc_way_T_120 ^ alloc_way_chunks_122; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_122 = _alloc_way_T_121 ^ alloc_way_chunks_123; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_123 = _alloc_way_T_122 ^ alloc_way_chunks_124; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_124 = _alloc_way_T_123 ^ alloc_way_chunks_125; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_125 = _alloc_way_T_124 ^ alloc_way_chunks_126; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_126 = _alloc_way_T_125 ^ alloc_way_chunks_127; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_127 = _alloc_way_T_126 ^ alloc_way_chunks_128; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_128 = _alloc_way_T_127 ^ alloc_way_chunks_129; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_129 = _alloc_way_T_128 ^ alloc_way_chunks_130; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_130 = _alloc_way_T_129 ^ alloc_way_chunks_131; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_131 = _alloc_way_T_130 ^ alloc_way_chunks_132; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_132 = _alloc_way_T_131 ^ alloc_way_chunks_133; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_133 = _alloc_way_T_132 ^ alloc_way_chunks_134; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_134 = _alloc_way_T_133 ^ alloc_way_chunks_135; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_135 = _alloc_way_T_134 ^ alloc_way_chunks_136; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_136 = _alloc_way_T_135 ^ alloc_way_chunks_137; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_137 = _alloc_way_T_136 ^ alloc_way_chunks_138; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_138 = _alloc_way_T_137 ^ alloc_way_chunks_139; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_139 = _alloc_way_T_138 ^ alloc_way_chunks_140; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_140 = _alloc_way_T_139 ^ alloc_way_chunks_141; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_141 = _alloc_way_T_140 ^ alloc_way_chunks_142; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_142 = _alloc_way_T_141 ^ alloc_way_chunks_143; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_143 = _alloc_way_T_142 ^ alloc_way_chunks_144; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_144 = _alloc_way_T_143 ^ alloc_way_chunks_145; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_145 = _alloc_way_T_144 ^ alloc_way_chunks_146; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_146 = _alloc_way_T_145 ^ alloc_way_chunks_147; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_147 = _alloc_way_T_146 ^ alloc_way_chunks_148; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_148 = _alloc_way_T_147 ^ alloc_way_chunks_149; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_149 = _alloc_way_T_148 ^ alloc_way_chunks_150; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_150 = _alloc_way_T_149 ^ alloc_way_chunks_151; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_151 = _alloc_way_T_150 ^ alloc_way_chunks_152; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_152 = _alloc_way_T_151 ^ alloc_way_chunks_153; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_153 = _alloc_way_T_152 ^ alloc_way_chunks_154; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_154 = _alloc_way_T_153 ^ alloc_way_chunks_155; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_155 = _alloc_way_T_154 ^ alloc_way_chunks_156; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_156 = _alloc_way_T_155 ^ alloc_way_chunks_157; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_157 = _alloc_way_T_156 ^ alloc_way_chunks_158; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_158 = _alloc_way_T_157 ^ alloc_way_chunks_159; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_159 = _alloc_way_T_158 ^ alloc_way_chunks_160; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_160 = _alloc_way_T_159 ^ alloc_way_chunks_161; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_161 = _alloc_way_T_160 ^ alloc_way_chunks_162; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_162 = _alloc_way_T_161 ^ alloc_way_chunks_163; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_163 = _alloc_way_T_162 ^ alloc_way_chunks_164; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_164 = _alloc_way_T_163 ^ alloc_way_chunks_165; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_165 = _alloc_way_T_164 ^ alloc_way_chunks_166; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_166 = _alloc_way_T_165 ^ alloc_way_chunks_167; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_167 = _alloc_way_T_166 ^ alloc_way_chunks_168; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_168 = _alloc_way_T_167 ^ alloc_way_chunks_169; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_169 = _alloc_way_T_168 ^ alloc_way_chunks_170; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_170 = _alloc_way_T_169 ^ alloc_way_chunks_171; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_171 = _alloc_way_T_170 ^ alloc_way_chunks_172; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_172 = _alloc_way_T_171 ^ alloc_way_chunks_173; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_173 = _alloc_way_T_172 ^ alloc_way_chunks_174; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_174 = _alloc_way_T_173 ^ alloc_way_chunks_175; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_175 = _alloc_way_T_174 ^ alloc_way_chunks_176; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_176 = _alloc_way_T_175 ^ alloc_way_chunks_177; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_177 = _alloc_way_T_176 ^ alloc_way_chunks_178; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_178 = _alloc_way_T_177 ^ alloc_way_chunks_179; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_179 = _alloc_way_T_178 ^ alloc_way_chunks_180; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_180 = _alloc_way_T_179 ^ alloc_way_chunks_181; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_181 = _alloc_way_T_180 ^ alloc_way_chunks_182; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_182 = _alloc_way_T_181 ^ alloc_way_chunks_183; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_183 = _alloc_way_T_182 ^ alloc_way_chunks_184; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_184 = _alloc_way_T_183 ^ alloc_way_chunks_185; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_185 = _alloc_way_T_184 ^ alloc_way_chunks_186; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_186 = _alloc_way_T_185 ^ alloc_way_chunks_187; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_187 = _alloc_way_T_186 ^ alloc_way_chunks_188; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_188 = _alloc_way_T_187 ^ alloc_way_chunks_189; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_189 = _alloc_way_T_188 ^ alloc_way_chunks_190; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_190 = _alloc_way_T_189 ^ alloc_way_chunks_191; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_191 = _alloc_way_T_190 ^ alloc_way_chunks_192; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_192 = _alloc_way_T_191 ^ alloc_way_chunks_193; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_193 = _alloc_way_T_192 ^ alloc_way_chunks_194; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_194 = _alloc_way_T_193 ^ alloc_way_chunks_195; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_195 = _alloc_way_T_194 ^ alloc_way_chunks_196; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_196 = _alloc_way_T_195 ^ alloc_way_chunks_197; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_197 = _alloc_way_T_196 ^ alloc_way_chunks_198; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_198 = _alloc_way_T_197 ^ alloc_way_chunks_199; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_199 = _alloc_way_T_198 ^ alloc_way_chunks_200; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_200 = _alloc_way_T_199 ^ alloc_way_chunks_201; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_201 = _alloc_way_T_200 ^ alloc_way_chunks_202; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_202 = _alloc_way_T_201 ^ alloc_way_chunks_203; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_203 = _alloc_way_T_202 ^ alloc_way_chunks_204; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_204 = _alloc_way_T_203 ^ alloc_way_chunks_205; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_205 = _alloc_way_T_204 ^ alloc_way_chunks_206; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_206 = _alloc_way_T_205 ^ alloc_way_chunks_207; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_207 = _alloc_way_T_206 ^ alloc_way_chunks_208; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_208 = _alloc_way_T_207 ^ alloc_way_chunks_209; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_209 = _alloc_way_T_208 ^ alloc_way_chunks_210; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_210 = _alloc_way_T_209 ^ alloc_way_chunks_211; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_211 = _alloc_way_T_210 ^ alloc_way_chunks_212; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_212 = _alloc_way_T_211 ^ alloc_way_chunks_213; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_213 = _alloc_way_T_212 ^ alloc_way_chunks_214; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_214 = _alloc_way_T_213 ^ alloc_way_chunks_215; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_215 = _alloc_way_T_214 ^ alloc_way_chunks_216; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_216 = _alloc_way_T_215 ^ alloc_way_chunks_217; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_217 = _alloc_way_T_216 ^ alloc_way_chunks_218; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_218 = _alloc_way_T_217 ^ alloc_way_chunks_219; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_219 = _alloc_way_T_218 ^ alloc_way_chunks_220; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_220 = _alloc_way_T_219 ^ alloc_way_chunks_221; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_221 = _alloc_way_T_220 ^ alloc_way_chunks_222; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_222 = _alloc_way_T_221 ^ alloc_way_chunks_223; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_223 = _alloc_way_T_222 ^ alloc_way_chunks_224; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_224 = _alloc_way_T_223 ^ alloc_way_chunks_225; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_225 = _alloc_way_T_224 ^ alloc_way_chunks_226; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_226 = _alloc_way_T_225 ^ alloc_way_chunks_227; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_227 = _alloc_way_T_226 ^ alloc_way_chunks_228; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_228 = _alloc_way_T_227 ^ alloc_way_chunks_229; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_229 = _alloc_way_T_228 ^ alloc_way_chunks_230; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_230 = _alloc_way_T_229 ^ alloc_way_chunks_231; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_231 = _alloc_way_T_230 ^ alloc_way_chunks_232; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_232 = _alloc_way_T_231 ^ alloc_way_chunks_233; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_233 = _alloc_way_T_232 ^ alloc_way_chunks_234; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_234 = _alloc_way_T_233 ^ alloc_way_chunks_235; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_235 = _alloc_way_T_234 ^ alloc_way_chunks_236; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_236 = _alloc_way_T_235 ^ alloc_way_chunks_237; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_237 = _alloc_way_T_236 ^ alloc_way_chunks_238; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_238 = _alloc_way_T_237 ^ alloc_way_chunks_239; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_239 = _alloc_way_T_238 ^ alloc_way_chunks_240; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_240 = _alloc_way_T_239 ^ alloc_way_chunks_241; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_241 = _alloc_way_T_240 ^ alloc_way_chunks_242; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_242 = _alloc_way_T_241 ^ alloc_way_chunks_243; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_243 = _alloc_way_T_242 ^ alloc_way_chunks_244; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_244 = _alloc_way_T_243 ^ alloc_way_chunks_245; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_245 = _alloc_way_T_244 ^ alloc_way_chunks_246; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_246 = _alloc_way_T_245 ^ alloc_way_chunks_247; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_247 = _alloc_way_T_246 ^ alloc_way_chunks_248; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_248 = _alloc_way_T_247 ^ alloc_way_chunks_249; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_249 = _alloc_way_T_248 ^ alloc_way_chunks_250; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_250 = _alloc_way_T_249 ^ alloc_way_chunks_251; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_251 = _alloc_way_T_250 ^ alloc_way_chunks_252; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_252 = _alloc_way_T_251 ^ alloc_way_chunks_253; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_253 = _alloc_way_T_252 ^ alloc_way_chunks_254; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_254 = _alloc_way_T_253 ^ alloc_way_chunks_255; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_255 = _alloc_way_T_254 ^ alloc_way_chunks_256; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_256 = _alloc_way_T_255 ^ alloc_way_chunks_257; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_257 = _alloc_way_T_256 ^ alloc_way_chunks_258; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_258 = _alloc_way_T_257 ^ alloc_way_chunks_259; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_259 = _alloc_way_T_258 ^ alloc_way_chunks_260; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_260 = _alloc_way_T_259 ^ alloc_way_chunks_261; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_261 = _alloc_way_T_260 ^ alloc_way_chunks_262; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_262 = _alloc_way_T_261 ^ alloc_way_chunks_263; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_263 = _alloc_way_T_262 ^ alloc_way_chunks_264; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_264 = _alloc_way_T_263 ^ alloc_way_chunks_265; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_265 = _alloc_way_T_264 ^ alloc_way_chunks_266; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_266 = _alloc_way_T_265 ^ alloc_way_chunks_267; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_267 = _alloc_way_T_266 ^ alloc_way_chunks_268; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_268 = _alloc_way_T_267 ^ alloc_way_chunks_269; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_269 = _alloc_way_T_268 ^ alloc_way_chunks_270; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_270 = _alloc_way_T_269 ^ alloc_way_chunks_271; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_271 = _alloc_way_T_270 ^ alloc_way_chunks_272; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_272 = _alloc_way_T_271 ^ alloc_way_chunks_273; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_273 = _alloc_way_T_272 ^ alloc_way_chunks_274; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_274 = _alloc_way_T_273 ^ alloc_way_chunks_275; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_275 = _alloc_way_T_274 ^ alloc_way_chunks_276; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_276 = _alloc_way_T_275 ^ alloc_way_chunks_277; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_277 = _alloc_way_T_276 ^ alloc_way_chunks_278; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_278 = _alloc_way_T_277 ^ alloc_way_chunks_279; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_279 = _alloc_way_T_278 ^ alloc_way_chunks_280; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_280 = _alloc_way_T_279 ^ alloc_way_chunks_281; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_281 = _alloc_way_T_280 ^ alloc_way_chunks_282; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_282 = _alloc_way_T_281 ^ alloc_way_chunks_283; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_283 = _alloc_way_T_282 ^ alloc_way_chunks_284; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_284 = _alloc_way_T_283 ^ alloc_way_chunks_285; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_285 = _alloc_way_T_284 ^ alloc_way_chunks_286; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_286 = _alloc_way_T_285 ^ alloc_way_chunks_287; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_287 = _alloc_way_T_286 ^ alloc_way_chunks_288; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_288 = _alloc_way_T_287 ^ alloc_way_chunks_289; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_289 = _alloc_way_T_288 ^ alloc_way_chunks_290; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_290 = _alloc_way_T_289 ^ alloc_way_chunks_291; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_291 = _alloc_way_T_290 ^ alloc_way_chunks_292; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_292 = _alloc_way_T_291 ^ alloc_way_chunks_293; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_293 = _alloc_way_T_292 ^ alloc_way_chunks_294; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_294 = _alloc_way_T_293 ^ alloc_way_chunks_295; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_295 = _alloc_way_T_294 ^ alloc_way_chunks_296; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_296 = _alloc_way_T_295 ^ alloc_way_chunks_297; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_297 = _alloc_way_T_296 ^ alloc_way_chunks_298; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_298 = _alloc_way_T_297 ^ alloc_way_chunks_299; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_299 = _alloc_way_T_298 ^ alloc_way_chunks_300; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_300 = _alloc_way_T_299 ^ alloc_way_chunks_301; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_301 = _alloc_way_T_300 ^ alloc_way_chunks_302; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_302 = _alloc_way_T_301 ^ alloc_way_chunks_303; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_303 = _alloc_way_T_302 ^ alloc_way_chunks_304; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_304 = _alloc_way_T_303 ^ alloc_way_chunks_305; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_305 = _alloc_way_T_304 ^ alloc_way_chunks_306; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_306 = _alloc_way_T_305 ^ alloc_way_chunks_307; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_307 = _alloc_way_T_306 ^ alloc_way_chunks_308; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_308 = _alloc_way_T_307 ^ alloc_way_chunks_309; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_309 = _alloc_way_T_308 ^ alloc_way_chunks_310; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_310 = _alloc_way_T_309 ^ alloc_way_chunks_311; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_311 = _alloc_way_T_310 ^ alloc_way_chunks_312; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_312 = _alloc_way_T_311 ^ alloc_way_chunks_313; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_313 = _alloc_way_T_312 ^ alloc_way_chunks_314; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_314 = _alloc_way_T_313 ^ alloc_way_chunks_315; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_315 = _alloc_way_T_314 ^ alloc_way_chunks_316; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_316 = _alloc_way_T_315 ^ alloc_way_chunks_317; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_317 = _alloc_way_T_316 ^ alloc_way_chunks_318; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_318 = _alloc_way_T_317 ^ alloc_way_chunks_319; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_319 = _alloc_way_T_318 ^ alloc_way_chunks_320; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_320 = _alloc_way_T_319 ^ alloc_way_chunks_321; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_321 = _alloc_way_T_320 ^ alloc_way_chunks_322; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_322 = _alloc_way_T_321 ^ alloc_way_chunks_323; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_323 = _alloc_way_T_322 ^ alloc_way_chunks_324; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_324 = _alloc_way_T_323 ^ alloc_way_chunks_325; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_325 = _alloc_way_T_324 ^ alloc_way_chunks_326; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_326 = _alloc_way_T_325 ^ alloc_way_chunks_327; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_327 = _alloc_way_T_326 ^ alloc_way_chunks_328; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_328 = _alloc_way_T_327 ^ alloc_way_chunks_329; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_329 = _alloc_way_T_328 ^ alloc_way_chunks_330; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_330 = _alloc_way_T_329 ^ alloc_way_chunks_331; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_331 = _alloc_way_T_330 ^ alloc_way_chunks_332; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_332 = _alloc_way_T_331 ^ alloc_way_chunks_333; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_333 = _alloc_way_T_332 ^ alloc_way_chunks_334; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_334 = _alloc_way_T_333 ^ alloc_way_chunks_335; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_335 = _alloc_way_T_334 ^ alloc_way_chunks_336; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_336 = _alloc_way_T_335 ^ alloc_way_chunks_337; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_337 = _alloc_way_T_336 ^ alloc_way_chunks_338; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_338 = _alloc_way_T_337 ^ alloc_way_chunks_339; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_339 = _alloc_way_T_338 ^ alloc_way_chunks_340; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_340 = _alloc_way_T_339 ^ alloc_way_chunks_341; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_341 = _alloc_way_T_340 ^ alloc_way_chunks_342; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_342 = _alloc_way_T_341 ^ alloc_way_chunks_343; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_343 = _alloc_way_T_342 ^ alloc_way_chunks_344; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_344 = _alloc_way_T_343 ^ alloc_way_chunks_345; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_345 = _alloc_way_T_344 ^ alloc_way_chunks_346; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_346 = _alloc_way_T_345 ^ alloc_way_chunks_347; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_347 = _alloc_way_T_346 ^ alloc_way_chunks_348; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_348 = _alloc_way_T_347 ^ alloc_way_chunks_349; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_349 = _alloc_way_T_348 ^ alloc_way_chunks_350; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_350 = _alloc_way_T_349 ^ alloc_way_chunks_351; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_351 = _alloc_way_T_350 ^ alloc_way_chunks_352; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_352 = _alloc_way_T_351 ^ alloc_way_chunks_353; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_353 = _alloc_way_T_352 ^ alloc_way_chunks_354; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_354 = _alloc_way_T_353 ^ alloc_way_chunks_355; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_355 = _alloc_way_T_354 ^ alloc_way_chunks_356; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_356 = _alloc_way_T_355 ^ alloc_way_chunks_357; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_357 = _alloc_way_T_356 ^ alloc_way_chunks_358; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_358 = _alloc_way_T_357 ^ alloc_way_chunks_359; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_359 = _alloc_way_T_358 ^ alloc_way_chunks_360; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_360 = _alloc_way_T_359 ^ alloc_way_chunks_361; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_361 = _alloc_way_T_360 ^ alloc_way_chunks_362; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_362 = _alloc_way_T_361 ^ alloc_way_chunks_363; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_363 = _alloc_way_T_362 ^ alloc_way_chunks_364; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_364 = _alloc_way_T_363 ^ alloc_way_chunks_365; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_365 = _alloc_way_T_364 ^ alloc_way_chunks_366; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_366 = _alloc_way_T_365 ^ alloc_way_chunks_367; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_367 = _alloc_way_T_366 ^ alloc_way_chunks_368; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_368 = _alloc_way_T_367 ^ alloc_way_chunks_369; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_369 = _alloc_way_T_368 ^ alloc_way_chunks_370; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_370 = _alloc_way_T_369 ^ alloc_way_chunks_371; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_371 = _alloc_way_T_370 ^ alloc_way_chunks_372; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_372 = _alloc_way_T_371 ^ alloc_way_chunks_373; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_373 = _alloc_way_T_372 ^ alloc_way_chunks_374; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_374 = _alloc_way_T_373 ^ alloc_way_chunks_375; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_375 = _alloc_way_T_374 ^ alloc_way_chunks_376; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_376 = _alloc_way_T_375 ^ alloc_way_chunks_377; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_377 = _alloc_way_T_376 ^ alloc_way_chunks_378; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_378 = _alloc_way_T_377 ^ alloc_way_chunks_379; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_379 = _alloc_way_T_378 ^ alloc_way_chunks_380; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_380 = _alloc_way_T_379 ^ alloc_way_chunks_381; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_381 = _alloc_way_T_380 ^ alloc_way_chunks_382; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_382 = _alloc_way_T_381 ^ alloc_way_chunks_383; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_383 = _alloc_way_T_382 ^ alloc_way_chunks_384; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_384 = _alloc_way_T_383 ^ alloc_way_chunks_385; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_385 = _alloc_way_T_384 ^ alloc_way_chunks_386; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_386 = _alloc_way_T_385 ^ alloc_way_chunks_387; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_387 = _alloc_way_T_386 ^ alloc_way_chunks_388; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_388 = _alloc_way_T_387 ^ alloc_way_chunks_389; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_389 = _alloc_way_T_388 ^ alloc_way_chunks_390; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_390 = _alloc_way_T_389 ^ alloc_way_chunks_391; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_391 = _alloc_way_T_390 ^ alloc_way_chunks_392; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_392 = _alloc_way_T_391 ^ alloc_way_chunks_393; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_393 = _alloc_way_T_392 ^ alloc_way_chunks_394; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_394 = _alloc_way_T_393 ^ alloc_way_chunks_395; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_395 = _alloc_way_T_394 ^ alloc_way_chunks_396; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_396 = _alloc_way_T_395 ^ alloc_way_chunks_397; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_397 = _alloc_way_T_396 ^ alloc_way_chunks_398; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_398 = _alloc_way_T_397 ^ alloc_way_chunks_399; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_399 = _alloc_way_T_398 ^ alloc_way_chunks_400; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_400 = _alloc_way_T_399 ^ alloc_way_chunks_401; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_401 = _alloc_way_T_400 ^ alloc_way_chunks_402; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_402 = _alloc_way_T_401 ^ alloc_way_chunks_403; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_403 = _alloc_way_T_402 ^ alloc_way_chunks_404; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_404 = _alloc_way_T_403 ^ alloc_way_chunks_405; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_405 = _alloc_way_T_404 ^ alloc_way_chunks_406; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_406 = _alloc_way_T_405 ^ alloc_way_chunks_407; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_407 = _alloc_way_T_406 ^ alloc_way_chunks_408; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_408 = _alloc_way_T_407 ^ alloc_way_chunks_409; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_409 = _alloc_way_T_408 ^ alloc_way_chunks_410; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_410 = _alloc_way_T_409 ^ alloc_way_chunks_411; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_411 = _alloc_way_T_410 ^ alloc_way_chunks_412; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_412 = _alloc_way_T_411 ^ alloc_way_chunks_413; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_413 = _alloc_way_T_412 ^ alloc_way_chunks_414; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_414 = _alloc_way_T_413 ^ alloc_way_chunks_415; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_415 = _alloc_way_T_414 ^ alloc_way_chunks_416; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_416 = _alloc_way_T_415 ^ alloc_way_chunks_417; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_417 = _alloc_way_T_416 ^ alloc_way_chunks_418; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_418 = _alloc_way_T_417 ^ alloc_way_chunks_419; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_419 = _alloc_way_T_418 ^ alloc_way_chunks_420; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_420 = _alloc_way_T_419 ^ alloc_way_chunks_421; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_421 = _alloc_way_T_420 ^ alloc_way_chunks_422; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_422 = _alloc_way_T_421 ^ alloc_way_chunks_423; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_423 = _alloc_way_T_422 ^ alloc_way_chunks_424; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_424 = _alloc_way_T_423 ^ alloc_way_chunks_425; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_425 = _alloc_way_T_424 ^ alloc_way_chunks_426; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_426 = _alloc_way_T_425 ^ alloc_way_chunks_427; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_427 = _alloc_way_T_426 ^ alloc_way_chunks_428; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_428 = _alloc_way_T_427 ^ alloc_way_chunks_429; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_429 = _alloc_way_T_428 ^ alloc_way_chunks_430; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_430 = _alloc_way_T_429 ^ alloc_way_chunks_431; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_431 = _alloc_way_T_430 ^ alloc_way_chunks_432; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_432 = _alloc_way_T_431 ^ alloc_way_chunks_433; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_433 = _alloc_way_T_432 ^ alloc_way_chunks_434; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_434 = _alloc_way_T_433 ^ alloc_way_chunks_435; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_435 = _alloc_way_T_434 ^ alloc_way_chunks_436; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_436 = _alloc_way_T_435 ^ alloc_way_chunks_437; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_437 = _alloc_way_T_436 ^ alloc_way_chunks_438; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_438 = _alloc_way_T_437 ^ alloc_way_chunks_439; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_439 = _alloc_way_T_438 ^ alloc_way_chunks_440; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_440 = _alloc_way_T_439 ^ alloc_way_chunks_441; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_441 = _alloc_way_T_440 ^ alloc_way_chunks_442; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_442 = _alloc_way_T_441 ^ alloc_way_chunks_443; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_443 = _alloc_way_T_442 ^ alloc_way_chunks_444; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_444 = _alloc_way_T_443 ^ alloc_way_chunks_445; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_445 = _alloc_way_T_444 ^ alloc_way_chunks_446; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_446 = _alloc_way_T_445 ^ alloc_way_chunks_447; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_447 = _alloc_way_T_446 ^ alloc_way_chunks_448; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_448 = _alloc_way_T_447 ^ alloc_way_chunks_449; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_449 = _alloc_way_T_448 ^ alloc_way_chunks_450; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_450 = _alloc_way_T_449 ^ alloc_way_chunks_451; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_451 = _alloc_way_T_450 ^ alloc_way_chunks_452; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_452 = _alloc_way_T_451 ^ alloc_way_chunks_453; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_453 = _alloc_way_T_452 ^ alloc_way_chunks_454; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_454 = _alloc_way_T_453 ^ alloc_way_chunks_455; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_455 = _alloc_way_T_454 ^ alloc_way_chunks_456; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_456 = _alloc_way_T_455 ^ alloc_way_chunks_457; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_457 = _alloc_way_T_456 ^ alloc_way_chunks_458; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_458 = _alloc_way_T_457 ^ alloc_way_chunks_459; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_459 = _alloc_way_T_458 ^ alloc_way_chunks_460; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_460 = _alloc_way_T_459 ^ alloc_way_chunks_461; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_461 = _alloc_way_T_460 ^ alloc_way_chunks_462; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_462 = _alloc_way_T_461 ^ alloc_way_chunks_463; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_463 = _alloc_way_T_462 ^ alloc_way_chunks_464; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_464 = _alloc_way_T_463 ^ alloc_way_chunks_465; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_465 = _alloc_way_T_464 ^ alloc_way_chunks_466; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_466 = _alloc_way_T_465 ^ alloc_way_chunks_467; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_467 = _alloc_way_T_466 ^ alloc_way_chunks_468; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_468 = _alloc_way_T_467 ^ alloc_way_chunks_469; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_469 = _alloc_way_T_468 ^ alloc_way_chunks_470; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_470 = _alloc_way_T_469 ^ alloc_way_chunks_471; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_471 = _alloc_way_T_470 ^ alloc_way_chunks_472; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_472 = _alloc_way_T_471 ^ alloc_way_chunks_473; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_473 = _alloc_way_T_472 ^ alloc_way_chunks_474; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_474 = _alloc_way_T_473 ^ alloc_way_chunks_475; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_475 = _alloc_way_T_474 ^ alloc_way_chunks_476; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_476 = _alloc_way_T_475 ^ alloc_way_chunks_477; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_477 = _alloc_way_T_476 ^ alloc_way_chunks_478; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_478 = _alloc_way_T_477 ^ alloc_way_chunks_479; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_479 = _alloc_way_T_478 ^ alloc_way_chunks_480; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_480 = _alloc_way_T_479 ^ alloc_way_chunks_481; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_481 = _alloc_way_T_480 ^ alloc_way_chunks_482; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_482 = _alloc_way_T_481 ^ alloc_way_chunks_483; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_483 = _alloc_way_T_482 ^ alloc_way_chunks_484; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_484 = _alloc_way_T_483 ^ alloc_way_chunks_485; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_485 = _alloc_way_T_484 ^ alloc_way_chunks_486; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_486 = _alloc_way_T_485 ^ alloc_way_chunks_487; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_487 = _alloc_way_T_486 ^ alloc_way_chunks_488; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_488 = _alloc_way_T_487 ^ alloc_way_chunks_489; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_489 = _alloc_way_T_488 ^ alloc_way_chunks_490; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_490 = _alloc_way_T_489 ^ alloc_way_chunks_491; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_491 = _alloc_way_T_490 ^ alloc_way_chunks_492; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_492 = _alloc_way_T_491 ^ alloc_way_chunks_493; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_493 = _alloc_way_T_492 ^ alloc_way_chunks_494; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_494 = _alloc_way_T_493 ^ alloc_way_chunks_495; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_495 = _alloc_way_T_494 ^ alloc_way_chunks_496; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_496 = _alloc_way_T_495 ^ alloc_way_chunks_497; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_497 = _alloc_way_T_496 ^ alloc_way_chunks_498; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_498 = _alloc_way_T_497 ^ alloc_way_chunks_499; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_499 = _alloc_way_T_498 ^ alloc_way_chunks_500; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_500 = _alloc_way_T_499 ^ alloc_way_chunks_501; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_501 = _alloc_way_T_500 ^ alloc_way_chunks_502; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_502 = _alloc_way_T_501 ^ alloc_way_chunks_503; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_503 = _alloc_way_T_502 ^ alloc_way_chunks_504; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_504 = _alloc_way_T_503 ^ alloc_way_chunks_505; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_505 = _alloc_way_T_504 ^ alloc_way_chunks_506; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_506 = _alloc_way_T_505 ^ alloc_way_chunks_507; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_507 = _alloc_way_T_506 ^ alloc_way_chunks_508; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_508 = _alloc_way_T_507 ^ alloc_way_chunks_509; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_509 = _alloc_way_T_508 ^ alloc_way_chunks_510; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_510 = _alloc_way_T_509 ^ alloc_way_chunks_511; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_511 = _alloc_way_T_510 ^ alloc_way_chunks_512; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_512 = _alloc_way_T_511 ^ alloc_way_chunks_513; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_513 = _alloc_way_T_512 ^ alloc_way_chunks_514; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_514 = _alloc_way_T_513 ^ alloc_way_chunks_515; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_515 = _alloc_way_T_514 ^ alloc_way_chunks_516; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_516 = _alloc_way_T_515 ^ alloc_way_chunks_517; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_517 = _alloc_way_T_516 ^ alloc_way_chunks_518; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_518 = _alloc_way_T_517 ^ alloc_way_chunks_519; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_519 = _alloc_way_T_518 ^ alloc_way_chunks_520; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_520 = _alloc_way_T_519 ^ alloc_way_chunks_521; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_521 = _alloc_way_T_520 ^ alloc_way_chunks_522; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_522 = _alloc_way_T_521 ^ alloc_way_chunks_523; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_523 = _alloc_way_T_522 ^ alloc_way_chunks_524; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_524 = _alloc_way_T_523 ^ alloc_way_chunks_525; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_525 = _alloc_way_T_524 ^ alloc_way_chunks_526; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_526 = _alloc_way_T_525 ^ alloc_way_chunks_527; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_527 = _alloc_way_T_526 ^ alloc_way_chunks_528; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_528 = _alloc_way_T_527 ^ alloc_way_chunks_529; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_529 = _alloc_way_T_528 ^ alloc_way_chunks_530; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_530 = _alloc_way_T_529 ^ alloc_way_chunks_531; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_531 = _alloc_way_T_530 ^ alloc_way_chunks_532; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_532 = _alloc_way_T_531 ^ alloc_way_chunks_533; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_533 = _alloc_way_T_532 ^ alloc_way_chunks_534; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_534 = _alloc_way_T_533 ^ alloc_way_chunks_535; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_535 = _alloc_way_T_534 ^ alloc_way_chunks_536; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_536 = _alloc_way_T_535 ^ alloc_way_chunks_537; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_537 = _alloc_way_T_536 ^ alloc_way_chunks_538; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_538 = _alloc_way_T_537 ^ alloc_way_chunks_539; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_539 = _alloc_way_T_538 ^ alloc_way_chunks_540; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_540 = _alloc_way_T_539 ^ alloc_way_chunks_541; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_541 = _alloc_way_T_540 ^ alloc_way_chunks_542; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_542 = _alloc_way_T_541 ^ alloc_way_chunks_543; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_543 = _alloc_way_T_542 ^ alloc_way_chunks_544; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_544 = _alloc_way_T_543 ^ alloc_way_chunks_545; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_545 = _alloc_way_T_544 ^ alloc_way_chunks_546; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_546 = _alloc_way_T_545 ^ alloc_way_chunks_547; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_547 = _alloc_way_T_546 ^ alloc_way_chunks_548; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_548 = _alloc_way_T_547 ^ alloc_way_chunks_549; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_549 = _alloc_way_T_548 ^ alloc_way_chunks_550; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_550 = _alloc_way_T_549 ^ alloc_way_chunks_551; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_551 = _alloc_way_T_550 ^ alloc_way_chunks_552; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_552 = _alloc_way_T_551 ^ alloc_way_chunks_553; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_553 = _alloc_way_T_552 ^ alloc_way_chunks_554; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_554 = _alloc_way_T_553 ^ alloc_way_chunks_555; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_555 = _alloc_way_T_554 ^ alloc_way_chunks_556; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_556 = _alloc_way_T_555 ^ alloc_way_chunks_557; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_557 = _alloc_way_T_556 ^ alloc_way_chunks_558; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_558 = _alloc_way_T_557 ^ alloc_way_chunks_559; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_559 = _alloc_way_T_558 ^ alloc_way_chunks_560; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_560 = _alloc_way_T_559 ^ alloc_way_chunks_561; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_561 = _alloc_way_T_560 ^ alloc_way_chunks_562; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_562 = _alloc_way_T_561 ^ alloc_way_chunks_563; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_563 = _alloc_way_T_562 ^ alloc_way_chunks_564; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_564 = _alloc_way_T_563 ^ alloc_way_chunks_565; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_565 = _alloc_way_T_564 ^ alloc_way_chunks_566; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_566 = _alloc_way_T_565 ^ alloc_way_chunks_567; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_567 = _alloc_way_T_566 ^ alloc_way_chunks_568; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_568 = _alloc_way_T_567 ^ alloc_way_chunks_569; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_569 = _alloc_way_T_568 ^ alloc_way_chunks_570; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_570 = _alloc_way_T_569 ^ alloc_way_chunks_571; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_571 = _alloc_way_T_570 ^ alloc_way_chunks_572; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_572 = _alloc_way_T_571 ^ alloc_way_chunks_573; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_573 = _alloc_way_T_572 ^ alloc_way_chunks_574; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_574 = _alloc_way_T_573 ^ alloc_way_chunks_575; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_575 = _alloc_way_T_574 ^ alloc_way_chunks_576; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_576 = _alloc_way_T_575 ^ alloc_way_chunks_577; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_577 = _alloc_way_T_576 ^ alloc_way_chunks_578; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_578 = _alloc_way_T_577 ^ alloc_way_chunks_579; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_579 = _alloc_way_T_578 ^ alloc_way_chunks_580; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_580 = _alloc_way_T_579 ^ alloc_way_chunks_581; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_581 = _alloc_way_T_580 ^ alloc_way_chunks_582; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_582 = _alloc_way_T_581 ^ alloc_way_chunks_583; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_583 = _alloc_way_T_582 ^ alloc_way_chunks_584; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_584 = _alloc_way_T_583 ^ alloc_way_chunks_585; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_585 = _alloc_way_T_584 ^ alloc_way_chunks_586; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_586 = _alloc_way_T_585 ^ alloc_way_chunks_587; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_587 = _alloc_way_T_586 ^ alloc_way_chunks_588; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_588 = _alloc_way_T_587 ^ alloc_way_chunks_589; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_589 = _alloc_way_T_588 ^ alloc_way_chunks_590; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_590 = _alloc_way_T_589 ^ alloc_way_chunks_591; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_591 = _alloc_way_T_590 ^ alloc_way_chunks_592; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_592 = _alloc_way_T_591 ^ alloc_way_chunks_593; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_593 = _alloc_way_T_592 ^ alloc_way_chunks_594; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_594 = _alloc_way_T_593 ^ alloc_way_chunks_595; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_595 = _alloc_way_T_594 ^ alloc_way_chunks_596; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_596 = _alloc_way_T_595 ^ alloc_way_chunks_597; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_597 = _alloc_way_T_596 ^ alloc_way_chunks_598; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_598 = _alloc_way_T_597 ^ alloc_way_chunks_599; // @[faubtb.scala:93:14, :95:20]
wire [3:0] _alloc_way_T_599 = _alloc_way_T_598 ^ alloc_way_chunks_600; // @[faubtb.scala:93:14, :95:20]
wire [3:0] alloc_way = {_alloc_way_T_599[3:1], _alloc_way_T_599[0] ^ alloc_way_chunks_601}; // @[faubtb.scala:93:14, :95:20]
wire _s1_meta_write_way_T = s1_hits_0 | s1_hits_1; // @[faubtb.scala:75:55, :97:44]
wire _s1_meta_write_way_T_1 = _s1_meta_write_way_T | s1_hits_2; // @[faubtb.scala:75:55, :97:44]
wire _s1_meta_write_way_T_2 = _s1_meta_write_way_T_1 | s1_hits_3; // @[faubtb.scala:75:55, :97:44]
wire [1:0] s1_meta_write_way_lo_lo_lo = {s1_hit_ohs_0_1, s1_hit_ohs_0_0}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_lo_hi = {s1_hit_ohs_0_3, s1_hit_ohs_0_2}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_lo = {s1_meta_write_way_lo_lo_hi, s1_meta_write_way_lo_lo_lo}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_hi_lo = {s1_hit_ohs_0_5, s1_hit_ohs_0_4}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_hi_hi = {s1_hit_ohs_0_7, s1_hit_ohs_0_6}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_hi = {s1_meta_write_way_lo_hi_hi, s1_meta_write_way_lo_hi_lo}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_lo = {s1_meta_write_way_lo_hi, s1_meta_write_way_lo_lo}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_lo_lo = {s1_hit_ohs_0_9, s1_hit_ohs_0_8}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_lo_hi = {s1_hit_ohs_0_11, s1_hit_ohs_0_10}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_lo = {s1_meta_write_way_hi_lo_hi, s1_meta_write_way_hi_lo_lo}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_hi_lo = {s1_hit_ohs_0_13, s1_hit_ohs_0_12}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_hi_hi = {s1_hit_ohs_0_15, s1_hit_ohs_0_14}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_hi = {s1_meta_write_way_hi_hi_hi, s1_meta_write_way_hi_hi_lo}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_hi = {s1_meta_write_way_hi_hi, s1_meta_write_way_hi_lo}; // @[faubtb.scala:98:38]
wire [15:0] _s1_meta_write_way_T_3 = {s1_meta_write_way_hi, s1_meta_write_way_lo}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_lo_lo_1 = {s1_hit_ohs_1_1, s1_hit_ohs_1_0}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_lo_hi_1 = {s1_hit_ohs_1_3, s1_hit_ohs_1_2}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_lo_1 = {s1_meta_write_way_lo_lo_hi_1, s1_meta_write_way_lo_lo_lo_1}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_hi_lo_1 = {s1_hit_ohs_1_5, s1_hit_ohs_1_4}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_hi_hi_1 = {s1_hit_ohs_1_7, s1_hit_ohs_1_6}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_hi_1 = {s1_meta_write_way_lo_hi_hi_1, s1_meta_write_way_lo_hi_lo_1}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_lo_1 = {s1_meta_write_way_lo_hi_1, s1_meta_write_way_lo_lo_1}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_lo_lo_1 = {s1_hit_ohs_1_9, s1_hit_ohs_1_8}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_lo_hi_1 = {s1_hit_ohs_1_11, s1_hit_ohs_1_10}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_lo_1 = {s1_meta_write_way_hi_lo_hi_1, s1_meta_write_way_hi_lo_lo_1}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_hi_lo_1 = {s1_hit_ohs_1_13, s1_hit_ohs_1_12}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_hi_hi_1 = {s1_hit_ohs_1_15, s1_hit_ohs_1_14}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_hi_1 = {s1_meta_write_way_hi_hi_hi_1, s1_meta_write_way_hi_hi_lo_1}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_hi_1 = {s1_meta_write_way_hi_hi_1, s1_meta_write_way_hi_lo_1}; // @[faubtb.scala:98:38]
wire [15:0] _s1_meta_write_way_T_4 = {s1_meta_write_way_hi_1, s1_meta_write_way_lo_1}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_lo_lo_2 = {s1_hit_ohs_2_1, s1_hit_ohs_2_0}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_lo_hi_2 = {s1_hit_ohs_2_3, s1_hit_ohs_2_2}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_lo_2 = {s1_meta_write_way_lo_lo_hi_2, s1_meta_write_way_lo_lo_lo_2}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_hi_lo_2 = {s1_hit_ohs_2_5, s1_hit_ohs_2_4}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_hi_hi_2 = {s1_hit_ohs_2_7, s1_hit_ohs_2_6}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_hi_2 = {s1_meta_write_way_lo_hi_hi_2, s1_meta_write_way_lo_hi_lo_2}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_lo_2 = {s1_meta_write_way_lo_hi_2, s1_meta_write_way_lo_lo_2}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_lo_lo_2 = {s1_hit_ohs_2_9, s1_hit_ohs_2_8}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_lo_hi_2 = {s1_hit_ohs_2_11, s1_hit_ohs_2_10}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_lo_2 = {s1_meta_write_way_hi_lo_hi_2, s1_meta_write_way_hi_lo_lo_2}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_hi_lo_2 = {s1_hit_ohs_2_13, s1_hit_ohs_2_12}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_hi_hi_2 = {s1_hit_ohs_2_15, s1_hit_ohs_2_14}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_hi_2 = {s1_meta_write_way_hi_hi_hi_2, s1_meta_write_way_hi_hi_lo_2}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_hi_2 = {s1_meta_write_way_hi_hi_2, s1_meta_write_way_hi_lo_2}; // @[faubtb.scala:98:38]
wire [15:0] _s1_meta_write_way_T_5 = {s1_meta_write_way_hi_2, s1_meta_write_way_lo_2}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_lo_lo_3 = {s1_hit_ohs_3_1, s1_hit_ohs_3_0}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_lo_hi_3 = {s1_hit_ohs_3_3, s1_hit_ohs_3_2}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_lo_3 = {s1_meta_write_way_lo_lo_hi_3, s1_meta_write_way_lo_lo_lo_3}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_lo_hi_lo_3 = {s1_hit_ohs_3_5, s1_hit_ohs_3_4}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_lo_hi_hi_3 = {s1_hit_ohs_3_7, s1_hit_ohs_3_6}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_lo_hi_3 = {s1_meta_write_way_lo_hi_hi_3, s1_meta_write_way_lo_hi_lo_3}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_lo_3 = {s1_meta_write_way_lo_hi_3, s1_meta_write_way_lo_lo_3}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_lo_lo_3 = {s1_hit_ohs_3_9, s1_hit_ohs_3_8}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_lo_hi_3 = {s1_hit_ohs_3_11, s1_hit_ohs_3_10}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_lo_3 = {s1_meta_write_way_hi_lo_hi_3, s1_meta_write_way_hi_lo_lo_3}; // @[faubtb.scala:98:38]
wire [1:0] s1_meta_write_way_hi_hi_lo_3 = {s1_hit_ohs_3_13, s1_hit_ohs_3_12}; // @[faubtb.scala:70:27, :98:38]
wire [1:0] s1_meta_write_way_hi_hi_hi_3 = {s1_hit_ohs_3_15, s1_hit_ohs_3_14}; // @[faubtb.scala:70:27, :98:38]
wire [3:0] s1_meta_write_way_hi_hi_3 = {s1_meta_write_way_hi_hi_hi_3, s1_meta_write_way_hi_hi_lo_3}; // @[faubtb.scala:98:38]
wire [7:0] s1_meta_write_way_hi_3 = {s1_meta_write_way_hi_hi_3, s1_meta_write_way_hi_lo_3}; // @[faubtb.scala:98:38]
wire [15:0] _s1_meta_write_way_T_6 = {s1_meta_write_way_hi_3, s1_meta_write_way_lo_3}; // @[faubtb.scala:98:38]
wire [15:0] _s1_meta_write_way_T_7 = _s1_meta_write_way_T_3 | _s1_meta_write_way_T_4; // @[faubtb.scala:98:{38,54}]
wire [15:0] _s1_meta_write_way_T_8 = _s1_meta_write_way_T_7 | _s1_meta_write_way_T_5; // @[faubtb.scala:98:{38,54}]
wire [15:0] _s1_meta_write_way_T_9 = _s1_meta_write_way_T_8 | _s1_meta_write_way_T_6; // @[faubtb.scala:98:{38,54}]
wire _s1_meta_write_way_T_10 = _s1_meta_write_way_T_9[0]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_11 = _s1_meta_write_way_T_9[1]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_12 = _s1_meta_write_way_T_9[2]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_13 = _s1_meta_write_way_T_9[3]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_14 = _s1_meta_write_way_T_9[4]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_15 = _s1_meta_write_way_T_9[5]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_16 = _s1_meta_write_way_T_9[6]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_17 = _s1_meta_write_way_T_9[7]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_18 = _s1_meta_write_way_T_9[8]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_19 = _s1_meta_write_way_T_9[9]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_20 = _s1_meta_write_way_T_9[10]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_21 = _s1_meta_write_way_T_9[11]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_22 = _s1_meta_write_way_T_9[12]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_23 = _s1_meta_write_way_T_9[13]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_24 = _s1_meta_write_way_T_9[14]; // @[OneHot.scala:48:45]
wire _s1_meta_write_way_T_25 = _s1_meta_write_way_T_9[15]; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_26 = {3'h7, ~_s1_meta_write_way_T_24}; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_27 = _s1_meta_write_way_T_23 ? 4'hD : _s1_meta_write_way_T_26; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_28 = _s1_meta_write_way_T_22 ? 4'hC : _s1_meta_write_way_T_27; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_29 = _s1_meta_write_way_T_21 ? 4'hB : _s1_meta_write_way_T_28; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_30 = _s1_meta_write_way_T_20 ? 4'hA : _s1_meta_write_way_T_29; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_31 = _s1_meta_write_way_T_19 ? 4'h9 : _s1_meta_write_way_T_30; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_32 = _s1_meta_write_way_T_18 ? 4'h8 : _s1_meta_write_way_T_31; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_33 = _s1_meta_write_way_T_17 ? 4'h7 : _s1_meta_write_way_T_32; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_34 = _s1_meta_write_way_T_16 ? 4'h6 : _s1_meta_write_way_T_33; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_35 = _s1_meta_write_way_T_15 ? 4'h5 : _s1_meta_write_way_T_34; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_36 = _s1_meta_write_way_T_14 ? 4'h4 : _s1_meta_write_way_T_35; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_37 = _s1_meta_write_way_T_13 ? 4'h3 : _s1_meta_write_way_T_36; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_38 = _s1_meta_write_way_T_12 ? 4'h2 : _s1_meta_write_way_T_37; // @[OneHot.scala:48:45]
wire [3:0] _s1_meta_write_way_T_39 = _s1_meta_write_way_T_11 ? 4'h1 : _s1_meta_write_way_T_38; // @[OneHot.scala:48:45, :58:35]
wire [3:0] _s1_meta_write_way_T_40 = _s1_meta_write_way_T_10 ? 4'h0 : _s1_meta_write_way_T_39; // @[OneHot.scala:48:45]
assign _s1_meta_write_way_T_41 = _s1_meta_write_way_T_2 ? _s1_meta_write_way_T_40 : alloc_way; // @[Mux.scala:50:70]
assign s1_meta_write_way = _s1_meta_write_way_T_41; // @[faubtb.scala:53:21, :97:27]
reg io_resp_f2_0_REG_taken; // @[faubtb.scala:107:29]
assign io_resp_f2_0_taken_0 = io_resp_f2_0_REG_taken; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_0_REG_is_br; // @[faubtb.scala:107:29]
assign io_resp_f2_0_is_br_0 = io_resp_f2_0_REG_is_br; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_0_REG_is_jal; // @[faubtb.scala:107:29]
assign io_resp_f2_0_is_jal_0 = io_resp_f2_0_REG_is_jal; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_0_REG_predicted_pc_valid; // @[faubtb.scala:107:29]
assign io_resp_f2_0_predicted_pc_valid_0 = io_resp_f2_0_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :107:29]
reg [39:0] io_resp_f2_0_REG_predicted_pc_bits; // @[faubtb.scala:107:29]
assign io_resp_f2_0_predicted_pc_bits_0 = io_resp_f2_0_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f3_0_REG_taken; // @[faubtb.scala:108:29]
assign io_resp_f3_0_taken_0 = io_resp_f3_0_REG_taken; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_0_REG_is_br; // @[faubtb.scala:108:29]
assign io_resp_f3_0_is_br_0 = io_resp_f3_0_REG_is_br; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_0_REG_is_jal; // @[faubtb.scala:108:29]
assign io_resp_f3_0_is_jal_0 = io_resp_f3_0_REG_is_jal; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_0_REG_predicted_pc_valid; // @[faubtb.scala:108:29]
assign io_resp_f3_0_predicted_pc_valid_0 = io_resp_f3_0_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :108:29]
reg [39:0] io_resp_f3_0_REG_predicted_pc_bits; // @[faubtb.scala:108:29]
assign io_resp_f3_0_predicted_pc_bits_0 = io_resp_f3_0_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f2_1_REG_taken; // @[faubtb.scala:107:29]
assign io_resp_f2_1_taken_0 = io_resp_f2_1_REG_taken; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_1_REG_is_br; // @[faubtb.scala:107:29]
assign io_resp_f2_1_is_br_0 = io_resp_f2_1_REG_is_br; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_1_REG_is_jal; // @[faubtb.scala:107:29]
assign io_resp_f2_1_is_jal_0 = io_resp_f2_1_REG_is_jal; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_1_REG_predicted_pc_valid; // @[faubtb.scala:107:29]
assign io_resp_f2_1_predicted_pc_valid_0 = io_resp_f2_1_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :107:29]
reg [39:0] io_resp_f2_1_REG_predicted_pc_bits; // @[faubtb.scala:107:29]
assign io_resp_f2_1_predicted_pc_bits_0 = io_resp_f2_1_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f3_1_REG_taken; // @[faubtb.scala:108:29]
assign io_resp_f3_1_taken_0 = io_resp_f3_1_REG_taken; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_1_REG_is_br; // @[faubtb.scala:108:29]
assign io_resp_f3_1_is_br_0 = io_resp_f3_1_REG_is_br; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_1_REG_is_jal; // @[faubtb.scala:108:29]
assign io_resp_f3_1_is_jal_0 = io_resp_f3_1_REG_is_jal; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_1_REG_predicted_pc_valid; // @[faubtb.scala:108:29]
assign io_resp_f3_1_predicted_pc_valid_0 = io_resp_f3_1_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :108:29]
reg [39:0] io_resp_f3_1_REG_predicted_pc_bits; // @[faubtb.scala:108:29]
assign io_resp_f3_1_predicted_pc_bits_0 = io_resp_f3_1_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f2_2_REG_taken; // @[faubtb.scala:107:29]
assign io_resp_f2_2_taken_0 = io_resp_f2_2_REG_taken; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_2_REG_is_br; // @[faubtb.scala:107:29]
assign io_resp_f2_2_is_br_0 = io_resp_f2_2_REG_is_br; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_2_REG_is_jal; // @[faubtb.scala:107:29]
assign io_resp_f2_2_is_jal_0 = io_resp_f2_2_REG_is_jal; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_2_REG_predicted_pc_valid; // @[faubtb.scala:107:29]
assign io_resp_f2_2_predicted_pc_valid_0 = io_resp_f2_2_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :107:29]
reg [39:0] io_resp_f2_2_REG_predicted_pc_bits; // @[faubtb.scala:107:29]
assign io_resp_f2_2_predicted_pc_bits_0 = io_resp_f2_2_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f3_2_REG_taken; // @[faubtb.scala:108:29]
assign io_resp_f3_2_taken_0 = io_resp_f3_2_REG_taken; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_2_REG_is_br; // @[faubtb.scala:108:29]
assign io_resp_f3_2_is_br_0 = io_resp_f3_2_REG_is_br; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_2_REG_is_jal; // @[faubtb.scala:108:29]
assign io_resp_f3_2_is_jal_0 = io_resp_f3_2_REG_is_jal; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_2_REG_predicted_pc_valid; // @[faubtb.scala:108:29]
assign io_resp_f3_2_predicted_pc_valid_0 = io_resp_f3_2_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :108:29]
reg [39:0] io_resp_f3_2_REG_predicted_pc_bits; // @[faubtb.scala:108:29]
assign io_resp_f3_2_predicted_pc_bits_0 = io_resp_f3_2_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f2_3_REG_taken; // @[faubtb.scala:107:29]
assign io_resp_f2_3_taken_0 = io_resp_f2_3_REG_taken; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_3_REG_is_br; // @[faubtb.scala:107:29]
assign io_resp_f2_3_is_br_0 = io_resp_f2_3_REG_is_br; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_3_REG_is_jal; // @[faubtb.scala:107:29]
assign io_resp_f2_3_is_jal_0 = io_resp_f2_3_REG_is_jal; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f2_3_REG_predicted_pc_valid; // @[faubtb.scala:107:29]
assign io_resp_f2_3_predicted_pc_valid_0 = io_resp_f2_3_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :107:29]
reg [39:0] io_resp_f2_3_REG_predicted_pc_bits; // @[faubtb.scala:107:29]
assign io_resp_f2_3_predicted_pc_bits_0 = io_resp_f2_3_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :107:29]
reg io_resp_f3_3_REG_taken; // @[faubtb.scala:108:29]
assign io_resp_f3_3_taken_0 = io_resp_f3_3_REG_taken; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_3_REG_is_br; // @[faubtb.scala:108:29]
assign io_resp_f3_3_is_br_0 = io_resp_f3_3_REG_is_br; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_3_REG_is_jal; // @[faubtb.scala:108:29]
assign io_resp_f3_3_is_jal_0 = io_resp_f3_3_REG_is_jal; // @[faubtb.scala:21:7, :108:29]
reg io_resp_f3_3_REG_predicted_pc_valid; // @[faubtb.scala:108:29]
assign io_resp_f3_3_predicted_pc_valid_0 = io_resp_f3_3_REG_predicted_pc_valid; // @[faubtb.scala:21:7, :108:29]
reg [39:0] io_resp_f3_3_REG_predicted_pc_bits; // @[faubtb.scala:108:29]
assign io_resp_f3_3_predicted_pc_bits_0 = io_resp_f3_3_REG_predicted_pc_bits; // @[faubtb.scala:21:7, :108:29]
wire [3:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[faubtb.scala:110:41]
wire [7:0] _io_f3_meta_T_1 = {_io_f3_meta_T, s1_meta_write_way}; // @[faubtb.scala:53:21, :110:41]
reg [7:0] io_f3_meta_REG; // @[faubtb.scala:110:32]
reg [7:0] io_f3_meta_REG_1; // @[faubtb.scala:110:24]
assign io_f3_meta_0 = {112'h0, io_f3_meta_REG_1}; // @[faubtb.scala:21:7, :110:{14,24}]
wire _s1_update_meta_T_1; // @[faubtb.scala:113:55]
wire _s1_update_meta_T_2; // @[faubtb.scala:113:55]
wire _s1_update_meta_T_3; // @[faubtb.scala:113:55]
wire _s1_update_meta_T_4; // @[faubtb.scala:113:55]
wire [3:0] _s1_update_meta_T; // @[faubtb.scala:113:55]
wire s1_update_meta_hits_0; // @[faubtb.scala:113:55]
wire s1_update_meta_hits_1; // @[faubtb.scala:113:55]
wire s1_update_meta_hits_2; // @[faubtb.scala:113:55]
wire s1_update_meta_hits_3; // @[faubtb.scala:113:55]
wire [3:0] s1_update_meta_write_way; // @[faubtb.scala:113:55]
wire [7:0] _s1_update_meta_WIRE = s1_update_bits_meta[7:0]; // @[predictor.scala:184:30]
assign _s1_update_meta_T = _s1_update_meta_WIRE[3:0]; // @[faubtb.scala:113:55]
assign s1_update_meta_write_way = _s1_update_meta_T; // @[faubtb.scala:113:55]
assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[4]; // @[faubtb.scala:113:55]
assign s1_update_meta_hits_0 = _s1_update_meta_T_1; // @[faubtb.scala:113:55]
assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[5]; // @[faubtb.scala:113:55]
assign s1_update_meta_hits_1 = _s1_update_meta_T_2; // @[faubtb.scala:113:55]
assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[6]; // @[faubtb.scala:113:55]
assign s1_update_meta_hits_2 = _s1_update_meta_T_3; // @[faubtb.scala:113:55]
assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[7]; // @[faubtb.scala:113:55]
assign s1_update_meta_hits_3 = _s1_update_meta_T_4; // @[faubtb.scala:113:55]
wire [2:0] _new_offset_value_T_1 = {s1_update_bits_cfi_idx_bits, 1'h0}; // @[predictor.scala:184:30]
wire [40:0] _new_offset_value_T_2 = {1'h0, s1_update_bits_pc} + {38'h0, _new_offset_value_T_1}; // @[predictor.scala:184:30]
wire [39:0] _new_offset_value_T_3 = _new_offset_value_T_2[39:0]; // @[faubtb.scala:119:24]
wire [39:0] _new_offset_value_T_4 = _new_offset_value_T_3; // @[faubtb.scala:119:{24,62}]
wire [40:0] _new_offset_value_T_5 = {_new_offset_value_T[39], _new_offset_value_T} - {_new_offset_value_T_4[39], _new_offset_value_T_4}; // @[faubtb.scala:118:{49,56}, :119:62]
wire [39:0] _new_offset_value_T_6 = _new_offset_value_T_5[39:0]; // @[faubtb.scala:118:56]
wire [39:0] new_offset_value = _new_offset_value_T_6; // @[faubtb.scala:118:56]
wire [12:0] s1_update_wbtb_data_offset; // @[faubtb.scala:121:37]
assign s1_update_wbtb_data_offset = new_offset_value[12:0]; // @[faubtb.scala:118:56, :121:37, :122:30]
wire [3:0] _s1_update_wbtb_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35]
wire _s1_update_wbtb_mask_T_1 = s1_update_bits_cfi_idx_valid & s1_update_valid; // @[predictor.scala:184:30]
wire _s1_update_wbtb_mask_T_2 = _s1_update_wbtb_mask_T_1 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
wire _T_42 = s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update; // @[predictor.scala:96:49, :184:30]
wire _s1_update_wbtb_mask_T_3; // @[predictor.scala:96:49]
assign _s1_update_wbtb_mask_T_3 = _T_42; // @[predictor.scala:96:49]
wire _s1_update_wmeta_mask_T_1; // @[predictor.scala:96:49]
assign _s1_update_wmeta_mask_T_1 = _T_42; // @[predictor.scala:96:49]
wire _s1_update_wbtb_mask_T_4 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wbtb_mask_T_5 = _s1_update_wbtb_mask_T_3 | _s1_update_wbtb_mask_T_4; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wbtb_mask_T_6 = ~_s1_update_wbtb_mask_T_5; // @[predictor.scala:96:{26,69}]
wire _s1_update_wbtb_mask_T_7 = _s1_update_wbtb_mask_T_2 & _s1_update_wbtb_mask_T_6; // @[predictor.scala:96:26]
wire [3:0] _s1_update_wbtb_mask_T_8 = {4{_s1_update_wbtb_mask_T_7}}; // @[faubtb.scala:124:{9,97}]
wire [3:0] s1_update_wbtb_mask = _s1_update_wbtb_mask_T & _s1_update_wbtb_mask_T_8; // @[OneHot.scala:58:35]
wire [3:0] _s1_update_wmeta_mask_T = s1_update_wbtb_mask | s1_update_bits_br_mask; // @[predictor.scala:184:30]
wire _s1_update_wmeta_mask_T_2 = |s1_update_bits_btb_mispredicts; // @[predictor.scala:94:50, :184:30]
wire _s1_update_wmeta_mask_T_3 = _s1_update_wmeta_mask_T_1 | _s1_update_wmeta_mask_T_2; // @[predictor.scala:94:50, :96:{49,69}]
wire _s1_update_wmeta_mask_T_4 = ~_s1_update_wmeta_mask_T_3; // @[predictor.scala:96:{26,69}]
wire _s1_update_wmeta_mask_T_5 = s1_update_valid & _s1_update_wmeta_mask_T_4; // @[predictor.scala:96:26, :184:30]
wire [3:0] _s1_update_wmeta_mask_T_6 = {4{_s1_update_wmeta_mask_T_5}}; // @[faubtb.scala:127:{9,37}]
wire [3:0] s1_update_wmeta_mask = _s1_update_wmeta_mask_T & _s1_update_wmeta_mask_T_6; // @[faubtb.scala:126:{52,78}, :127:9]
wire _meta_0_is_br_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
wire _was_taken_T = ~(|s1_update_bits_cfi_idx_bits); // @[predictor.scala:184:30]
wire _was_taken_T_1 = _was_taken_T & s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
wire _GEN_13 = s1_update_bits_cfi_taken | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
wire _was_taken_T_2; // @[faubtb.scala:140:35]
assign _was_taken_T_2 = _GEN_13; // @[faubtb.scala:140:35]
wire _was_taken_T_5; // @[faubtb.scala:140:35]
assign _was_taken_T_5 = _GEN_13; // @[faubtb.scala:140:35]
wire _was_taken_T_8; // @[faubtb.scala:140:35]
assign _was_taken_T_8 = _GEN_13; // @[faubtb.scala:140:35]
wire _was_taken_T_11; // @[faubtb.scala:140:35]
assign _was_taken_T_11 = _GEN_13; // @[faubtb.scala:140:35]
wire was_taken = _was_taken_T_1 & _was_taken_T_2; // @[faubtb.scala:139:{50,82}, :140:35]
wire _meta_0_ctr_T = ~s1_update_meta_hits_0; // @[faubtb.scala:113:55, :144:49]
wire [1:0] _meta_0_ctr_T_1 = {2{was_taken}}; // @[faubtb.scala:139:82, :145:12]
wire meta_0_ctr_old_bim_sat_taken = &_GEN_3[s1_update_meta_write_way]; // @[faubtb.scala:29:32, :82:42, :113:55, :142:42]
wire meta_0_ctr_old_bim_sat_ntaken = _GEN_3[s1_update_meta_write_way] == 2'h0; // @[faubtb.scala:30:32, :82:42, :113:55, :142:42]
wire _meta_0_ctr_T_2 = meta_0_ctr_old_bim_sat_taken & was_taken; // @[faubtb.scala:29:32, :31:28, :139:82]
wire _meta_0_ctr_T_3 = ~was_taken; // @[faubtb.scala:32:33, :139:82]
wire _meta_0_ctr_T_4 = meta_0_ctr_old_bim_sat_ntaken & _meta_0_ctr_T_3; // @[faubtb.scala:30:32, :32:{30,33}]
wire [2:0] _GEN_14 = {1'h0, _GEN_3[s1_update_meta_write_way]}; // @[faubtb.scala:33:20, :82:42, :113:55, :142:42]
wire [2:0] _meta_0_ctr_T_5 = _GEN_14 + 3'h1; // @[faubtb.scala:33:20]
wire [1:0] _meta_0_ctr_T_6 = _meta_0_ctr_T_5[1:0]; // @[faubtb.scala:33:20]
wire [2:0] _meta_0_ctr_T_7 = _GEN_14 - 3'h1; // @[faubtb.scala:33:{20,29}]
wire [1:0] _meta_0_ctr_T_8 = _meta_0_ctr_T_7[1:0]; // @[faubtb.scala:33:29]
wire [1:0] _meta_0_ctr_T_9 = was_taken ? _meta_0_ctr_T_6 : _meta_0_ctr_T_8; // @[faubtb.scala:33:{10,20,29}, :139:82]
wire [1:0] _meta_0_ctr_T_10 = _meta_0_ctr_T_4 ? 2'h0 : _meta_0_ctr_T_9; // @[faubtb.scala:32:{10,30}, :33:10]
wire [1:0] _meta_0_ctr_T_11 = _meta_0_ctr_T_2 ? 2'h3 : _meta_0_ctr_T_10; // @[faubtb.scala:31:{8,28}, :32:10]
wire [1:0] _meta_0_ctr_T_12 = _meta_0_ctr_T ? _meta_0_ctr_T_1 : _meta_0_ctr_T_11; // @[faubtb.scala:31:8, :144:{48,49}, :145:12]
wire _meta_1_is_br_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
wire _was_taken_T_3 = s1_update_bits_cfi_idx_bits == 2'h1; // @[predictor.scala:184:30]
wire _was_taken_T_4 = _was_taken_T_3 & s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
wire was_taken_1 = _was_taken_T_4 & _was_taken_T_5; // @[faubtb.scala:139:{50,82}, :140:35]
wire _meta_1_ctr_T = ~s1_update_meta_hits_1; // @[faubtb.scala:113:55, :144:49]
wire [1:0] _meta_1_ctr_T_1 = {2{was_taken_1}}; // @[faubtb.scala:139:82, :145:12]
wire meta_1_ctr_old_bim_sat_taken = &_GEN_6[s1_update_meta_write_way]; // @[faubtb.scala:29:32, :82:42, :113:55, :142:42]
wire meta_1_ctr_old_bim_sat_ntaken = _GEN_6[s1_update_meta_write_way] == 2'h0; // @[faubtb.scala:30:32, :82:42, :113:55, :142:42]
wire _meta_1_ctr_T_2 = meta_1_ctr_old_bim_sat_taken & was_taken_1; // @[faubtb.scala:29:32, :31:28, :139:82]
wire _meta_1_ctr_T_3 = ~was_taken_1; // @[faubtb.scala:32:33, :139:82]
wire _meta_1_ctr_T_4 = meta_1_ctr_old_bim_sat_ntaken & _meta_1_ctr_T_3; // @[faubtb.scala:30:32, :32:{30,33}]
wire [2:0] _GEN_15 = {1'h0, _GEN_6[s1_update_meta_write_way]}; // @[faubtb.scala:33:20, :82:42, :113:55, :142:42]
wire [2:0] _meta_1_ctr_T_5 = _GEN_15 + 3'h1; // @[faubtb.scala:33:20]
wire [1:0] _meta_1_ctr_T_6 = _meta_1_ctr_T_5[1:0]; // @[faubtb.scala:33:20]
wire [2:0] _meta_1_ctr_T_7 = _GEN_15 - 3'h1; // @[faubtb.scala:33:{20,29}]
wire [1:0] _meta_1_ctr_T_8 = _meta_1_ctr_T_7[1:0]; // @[faubtb.scala:33:29]
wire [1:0] _meta_1_ctr_T_9 = was_taken_1 ? _meta_1_ctr_T_6 : _meta_1_ctr_T_8; // @[faubtb.scala:33:{10,20,29}, :139:82]
wire [1:0] _meta_1_ctr_T_10 = _meta_1_ctr_T_4 ? 2'h0 : _meta_1_ctr_T_9; // @[faubtb.scala:32:{10,30}, :33:10]
wire [1:0] _meta_1_ctr_T_11 = _meta_1_ctr_T_2 ? 2'h3 : _meta_1_ctr_T_10; // @[faubtb.scala:31:{8,28}, :32:10]
wire [1:0] _meta_1_ctr_T_12 = _meta_1_ctr_T ? _meta_1_ctr_T_1 : _meta_1_ctr_T_11; // @[faubtb.scala:31:8, :144:{48,49}, :145:12]
wire _meta_2_is_br_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
wire _was_taken_T_6 = s1_update_bits_cfi_idx_bits == 2'h2; // @[predictor.scala:184:30]
wire _was_taken_T_7 = _was_taken_T_6 & s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
wire was_taken_2 = _was_taken_T_7 & _was_taken_T_8; // @[faubtb.scala:139:{50,82}, :140:35]
wire _meta_2_ctr_T = ~s1_update_meta_hits_2; // @[faubtb.scala:113:55, :144:49]
wire [1:0] _meta_2_ctr_T_1 = {2{was_taken_2}}; // @[faubtb.scala:139:82, :145:12]
wire meta_2_ctr_old_bim_sat_taken = &_GEN_9[s1_update_meta_write_way]; // @[faubtb.scala:29:32, :82:42, :113:55, :142:42]
wire meta_2_ctr_old_bim_sat_ntaken = _GEN_9[s1_update_meta_write_way] == 2'h0; // @[faubtb.scala:30:32, :82:42, :113:55, :142:42]
wire _meta_2_ctr_T_2 = meta_2_ctr_old_bim_sat_taken & was_taken_2; // @[faubtb.scala:29:32, :31:28, :139:82]
wire _meta_2_ctr_T_3 = ~was_taken_2; // @[faubtb.scala:32:33, :139:82]
wire _meta_2_ctr_T_4 = meta_2_ctr_old_bim_sat_ntaken & _meta_2_ctr_T_3; // @[faubtb.scala:30:32, :32:{30,33}]
wire [2:0] _GEN_16 = {1'h0, _GEN_9[s1_update_meta_write_way]}; // @[faubtb.scala:33:20, :82:42, :113:55, :142:42]
wire [2:0] _meta_2_ctr_T_5 = _GEN_16 + 3'h1; // @[faubtb.scala:33:20]
wire [1:0] _meta_2_ctr_T_6 = _meta_2_ctr_T_5[1:0]; // @[faubtb.scala:33:20]
wire [2:0] _meta_2_ctr_T_7 = _GEN_16 - 3'h1; // @[faubtb.scala:33:{20,29}]
wire [1:0] _meta_2_ctr_T_8 = _meta_2_ctr_T_7[1:0]; // @[faubtb.scala:33:29]
wire [1:0] _meta_2_ctr_T_9 = was_taken_2 ? _meta_2_ctr_T_6 : _meta_2_ctr_T_8; // @[faubtb.scala:33:{10,20,29}, :139:82]
wire [1:0] _meta_2_ctr_T_10 = _meta_2_ctr_T_4 ? 2'h0 : _meta_2_ctr_T_9; // @[faubtb.scala:32:{10,30}, :33:10]
wire [1:0] _meta_2_ctr_T_11 = _meta_2_ctr_T_2 ? 2'h3 : _meta_2_ctr_T_10; // @[faubtb.scala:31:{8,28}, :32:10]
wire [1:0] _meta_2_ctr_T_12 = _meta_2_ctr_T ? _meta_2_ctr_T_1 : _meta_2_ctr_T_11; // @[faubtb.scala:31:8, :144:{48,49}, :145:12]
wire _meta_3_is_br_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
wire _was_taken_T_9 = &s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
wire _was_taken_T_10 = _was_taken_T_9 & s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
wire was_taken_3 = _was_taken_T_10 & _was_taken_T_11; // @[faubtb.scala:139:{50,82}, :140:35]
wire _meta_3_ctr_T = ~s1_update_meta_hits_3; // @[faubtb.scala:113:55, :144:49]
wire [1:0] _meta_3_ctr_T_1 = {2{was_taken_3}}; // @[faubtb.scala:139:82, :145:12]
wire meta_3_ctr_old_bim_sat_taken = &_GEN_12[s1_update_meta_write_way]; // @[faubtb.scala:29:32, :82:42, :113:55, :142:42]
wire meta_3_ctr_old_bim_sat_ntaken = _GEN_12[s1_update_meta_write_way] == 2'h0; // @[faubtb.scala:30:32, :82:42, :113:55, :142:42]
wire _meta_3_ctr_T_2 = meta_3_ctr_old_bim_sat_taken & was_taken_3; // @[faubtb.scala:29:32, :31:28, :139:82]
wire _meta_3_ctr_T_3 = ~was_taken_3; // @[faubtb.scala:32:33, :139:82]
wire _meta_3_ctr_T_4 = meta_3_ctr_old_bim_sat_ntaken & _meta_3_ctr_T_3; // @[faubtb.scala:30:32, :32:{30,33}]
wire [2:0] _GEN_17 = {1'h0, _GEN_12[s1_update_meta_write_way]}; // @[faubtb.scala:33:20, :82:42, :113:55, :142:42]
wire [2:0] _meta_3_ctr_T_5 = _GEN_17 + 3'h1; // @[faubtb.scala:33:20]
wire [1:0] _meta_3_ctr_T_6 = _meta_3_ctr_T_5[1:0]; // @[faubtb.scala:33:20]
wire [2:0] _meta_3_ctr_T_7 = _GEN_17 - 3'h1; // @[faubtb.scala:33:{20,29}]
wire [1:0] _meta_3_ctr_T_8 = _meta_3_ctr_T_7[1:0]; // @[faubtb.scala:33:29]
wire [1:0] _meta_3_ctr_T_9 = was_taken_3 ? _meta_3_ctr_T_6 : _meta_3_ctr_T_8; // @[faubtb.scala:33:{10,20,29}, :139:82]
wire [1:0] _meta_3_ctr_T_10 = _meta_3_ctr_T_4 ? 2'h0 : _meta_3_ctr_T_9; // @[faubtb.scala:32:{10,30}, :33:10]
wire [1:0] _meta_3_ctr_T_11 = _meta_3_ctr_T_2 ? 2'h3 : _meta_3_ctr_T_10; // @[faubtb.scala:31:{8,28}, :32:10]
wire [1:0] _meta_3_ctr_T_12 = _meta_3_ctr_T ? _meta_3_ctr_T_1 : _meta_3_ctr_T_11; // @[faubtb.scala:31:8, :144:{48,49}, :145:12]
wire [4:0] _GEN_18 = {_T_42, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30]
wire _T_8 = s1_update_valid & s1_update_bits_cfi_taken & s1_update_bits_cfi_idx_valid & _GEN_18 == 5'h0; // @[predictor.scala:94:50, :96:69, :184:30]
wire _GEN_19 = s1_update_meta_write_way == 4'h0; // @[faubtb.scala:113:55, :131:56]
wire _GEN_20 = s1_update_bits_cfi_idx_bits == 2'h1; // @[predictor.scala:184:30]
wire _GEN_21 = s1_update_bits_cfi_idx_bits == 2'h2; // @[predictor.scala:184:30]
wire _GEN_22 = s1_update_meta_write_way == 4'h1; // @[OneHot.scala:58:35]
wire _GEN_23 = s1_update_meta_write_way == 4'h2; // @[faubtb.scala:113:55, :131:56]
wire _GEN_24 = s1_update_meta_write_way == 4'h3; // @[faubtb.scala:113:55, :131:56]
wire _GEN_25 = s1_update_meta_write_way == 4'h4; // @[faubtb.scala:113:55, :131:56]
wire _GEN_26 = s1_update_meta_write_way == 4'h5; // @[faubtb.scala:113:55, :131:56]
wire _GEN_27 = s1_update_meta_write_way == 4'h6; // @[faubtb.scala:113:55, :131:56]
wire _GEN_28 = s1_update_meta_write_way == 4'h7; // @[faubtb.scala:113:55, :131:56]
wire _GEN_29 = s1_update_meta_write_way == 4'h8; // @[faubtb.scala:113:55, :131:56]
wire _GEN_30 = s1_update_meta_write_way == 4'h9; // @[faubtb.scala:113:55, :131:56]
wire _GEN_31 = s1_update_meta_write_way == 4'hA; // @[faubtb.scala:113:55, :131:56]
wire _GEN_32 = s1_update_meta_write_way == 4'hB; // @[faubtb.scala:113:55, :131:56]
wire _GEN_33 = s1_update_meta_write_way == 4'hC; // @[faubtb.scala:113:55, :131:56]
wire _GEN_34 = s1_update_meta_write_way == 4'hD; // @[faubtb.scala:113:55, :131:56]
wire _GEN_35 = s1_update_meta_write_way == 4'hE; // @[faubtb.scala:113:55, :131:56]
wire _T_19 = s1_update_valid & _GEN_18 == 5'h0 & (_meta_0_is_br_T | ~(|s1_update_bits_cfi_idx_bits) & s1_update_bits_cfi_taken & s1_update_bits_cfi_idx_valid); // @[predictor.scala:94:50, :96:69, :184:30]
wire _T_30 = s1_update_valid & _GEN_18 == 5'h0 & (_meta_1_is_br_T | _was_taken_T_3 & s1_update_bits_cfi_taken & s1_update_bits_cfi_idx_valid); // @[predictor.scala:94:50, :96:69, :184:30]
wire _T_41 = s1_update_valid & _GEN_18 == 5'h0 & (_meta_2_is_br_T | _was_taken_T_6 & s1_update_bits_cfi_taken & s1_update_bits_cfi_idx_valid); // @[predictor.scala:94:50, :96:69, :184:30]
wire _T_52 = s1_update_valid & _GEN_18 == 5'h0 & (_meta_3_is_br_T | (&s1_update_bits_cfi_idx_bits) & s1_update_bits_cfi_taken & s1_update_bits_cfi_idx_valid); // @[predictor.scala:94:50, :96:69, :184:30]
always @(posedge clock) begin // @[faubtb.scala:21:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
if (_T_8 & _GEN_19 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_0_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_19 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_0_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_19 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_0_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_19 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_0_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_22 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_1_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_22 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_1_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_22 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_1_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_22 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_1_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_23 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_2_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_23 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_2_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_23 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_2_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_23 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_2_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_24 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_3_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_24 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_3_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_24 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_3_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_24 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_3_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_25 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_4_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_25 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_4_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_25 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_4_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_25 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_4_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_26 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_5_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_26 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_5_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_26 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_5_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_26 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_5_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_27 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_6_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_27 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_6_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_27 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_6_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_27 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_6_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_28 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_7_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_28 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_7_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_28 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_7_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_28 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_7_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_29 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_8_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_29 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_8_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_29 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_8_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_29 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_8_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_30 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_9_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_30 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_9_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_30 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_9_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_30 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_9_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_31 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_10_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_31 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_10_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_31 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_10_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_31 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_10_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_32 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_11_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_32 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_11_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_32 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_11_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_32 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_11_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_33 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_12_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_33 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_12_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_33 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_12_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_33 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_12_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_34 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_13_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_34 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_13_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_34 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_13_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_34 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_13_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_35 & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_14_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_35 & _GEN_20) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_14_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_35 & _GEN_21) // @[faubtb.scala:58:21, :130:{25,53,85,121}, :131:56]
btb_14_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & _GEN_35 & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_14_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & (&s1_update_meta_write_way) & ~(|s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_15_0_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & (&s1_update_meta_write_way) & _GEN_20) // @[faubtb.scala:58:21, :113:55, :130:{25,53,85,121}, :131:56]
btb_15_1_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & (&s1_update_meta_write_way) & _GEN_21) // @[faubtb.scala:58:21, :113:55, :130:{25,53,85,121}, :131:56]
btb_15_2_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
if (_T_8 & (&s1_update_meta_write_way) & (&s1_update_bits_cfi_idx_bits)) // @[predictor.scala:184:30]
btb_15_3_offset <= s1_update_wbtb_data_offset; // @[faubtb.scala:58:21, :121:37]
io_resp_f2_0_REG_taken <= io_resp_f1_0_taken_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_0_REG_is_br <= io_resp_f1_0_is_br_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_0_REG_is_jal <= io_resp_f1_0_is_jal_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_0_REG_predicted_pc_valid <= io_resp_f1_0_predicted_pc_valid_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_0_REG_predicted_pc_bits <= io_resp_f1_0_predicted_pc_bits_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f3_0_REG_taken <= io_resp_f2_0_taken_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_0_REG_is_br <= io_resp_f2_0_is_br_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_0_REG_is_jal <= io_resp_f2_0_is_jal_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_0_REG_predicted_pc_valid <= io_resp_f2_0_predicted_pc_valid_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_0_REG_predicted_pc_bits <= io_resp_f2_0_predicted_pc_bits_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f2_1_REG_taken <= io_resp_f1_1_taken_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_1_REG_is_br <= io_resp_f1_1_is_br_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_1_REG_is_jal <= io_resp_f1_1_is_jal_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_1_REG_predicted_pc_valid <= io_resp_f1_1_predicted_pc_valid_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_1_REG_predicted_pc_bits <= io_resp_f1_1_predicted_pc_bits_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f3_1_REG_taken <= io_resp_f2_1_taken_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_1_REG_is_br <= io_resp_f2_1_is_br_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_1_REG_is_jal <= io_resp_f2_1_is_jal_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_1_REG_predicted_pc_valid <= io_resp_f2_1_predicted_pc_valid_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_1_REG_predicted_pc_bits <= io_resp_f2_1_predicted_pc_bits_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f2_2_REG_taken <= io_resp_f1_2_taken_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_2_REG_is_br <= io_resp_f1_2_is_br_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_2_REG_is_jal <= io_resp_f1_2_is_jal_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_2_REG_predicted_pc_valid <= io_resp_f1_2_predicted_pc_valid_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_2_REG_predicted_pc_bits <= io_resp_f1_2_predicted_pc_bits_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f3_2_REG_taken <= io_resp_f2_2_taken_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_2_REG_is_br <= io_resp_f2_2_is_br_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_2_REG_is_jal <= io_resp_f2_2_is_jal_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_2_REG_predicted_pc_valid <= io_resp_f2_2_predicted_pc_valid_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_2_REG_predicted_pc_bits <= io_resp_f2_2_predicted_pc_bits_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f2_3_REG_taken <= io_resp_f1_3_taken_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_3_REG_is_br <= io_resp_f1_3_is_br_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_3_REG_is_jal <= io_resp_f1_3_is_jal_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_3_REG_predicted_pc_valid <= io_resp_f1_3_predicted_pc_valid_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f2_3_REG_predicted_pc_bits <= io_resp_f1_3_predicted_pc_bits_0; // @[faubtb.scala:21:7, :107:29]
io_resp_f3_3_REG_taken <= io_resp_f2_3_taken_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_3_REG_is_br <= io_resp_f2_3_is_br_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_3_REG_is_jal <= io_resp_f2_3_is_jal_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_3_REG_predicted_pc_valid <= io_resp_f2_3_predicted_pc_valid_0; // @[faubtb.scala:21:7, :108:29]
io_resp_f3_3_REG_predicted_pc_bits <= io_resp_f2_3_predicted_pc_bits_0; // @[faubtb.scala:21:7, :108:29]
io_f3_meta_REG <= _io_f3_meta_T_1; // @[faubtb.scala:110:{32,41}]
io_f3_meta_REG_1 <= io_f3_meta_REG; // @[faubtb.scala:110:{24,32}]
if (reset) begin // @[faubtb.scala:21:7]
meta_0_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_0_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_0_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_0_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_0_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_0_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_0_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_0_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_0_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_0_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_0_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_0_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_1_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_1_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_1_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_1_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_1_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_1_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_1_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_1_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_1_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_1_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_1_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_1_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_2_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_2_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_2_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_2_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_2_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_2_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_2_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_2_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_2_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_2_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_2_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_2_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_3_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_3_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_3_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_3_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_3_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_3_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_3_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_3_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_3_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_3_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_3_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_3_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_4_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_4_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_4_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_4_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_4_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_4_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_4_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_4_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_4_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_4_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_4_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_4_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_5_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_5_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_5_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_5_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_5_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_5_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_5_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_5_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_5_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_5_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_5_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_5_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_6_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_6_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_6_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_6_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_6_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_6_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_6_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_6_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_6_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_6_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_6_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_6_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_7_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_7_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_7_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_7_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_7_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_7_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_7_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_7_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_7_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_7_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_7_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_7_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_8_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_8_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_8_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_8_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_8_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_8_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_8_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_8_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_8_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_8_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_8_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_8_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_9_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_9_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_9_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_9_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_9_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_9_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_9_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_9_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_9_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_9_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_9_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_9_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_10_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_10_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_10_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_10_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_10_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_10_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_10_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_10_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_10_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_10_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_10_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_10_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_11_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_11_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_11_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_11_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_11_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_11_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_11_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_11_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_11_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_11_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_11_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_11_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_12_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_12_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_12_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_12_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_12_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_12_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_12_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_12_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_12_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_12_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_12_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_12_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_13_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_13_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_13_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_13_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_13_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_13_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_13_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_13_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_13_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_13_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_13_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_13_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_14_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_14_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_14_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_14_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_14_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_14_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_14_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_14_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_14_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_14_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_14_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_14_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_15_0_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_15_0_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_15_0_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_15_1_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_15_1_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_15_1_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_15_2_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_15_2_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_15_2_ctr <= 2'h0; // @[faubtb.scala:57:25]
meta_15_3_is_br <= 1'h0; // @[faubtb.scala:57:25]
meta_15_3_tag <= 37'h0; // @[faubtb.scala:57:25]
meta_15_3_ctr <= 2'h0; // @[faubtb.scala:57:25]
end
else begin // @[faubtb.scala:21:7]
if (_T_19 & _GEN_19) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_0_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_0_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_0_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_19) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_0_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_0_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_0_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_19) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_0_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_0_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_0_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_19) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_0_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_0_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_0_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_22) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_1_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_1_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_1_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_22) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_1_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_1_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_1_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_22) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_1_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_1_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_1_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_22) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_1_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_1_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_1_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_23) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_2_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_2_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_2_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_23) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_2_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_2_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_2_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_23) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_2_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_2_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_2_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_23) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_2_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_2_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_2_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_24) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_3_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_3_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_3_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_24) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_3_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_3_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_3_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_24) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_3_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_3_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_3_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_24) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_3_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_3_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_3_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_25) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_4_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_4_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_4_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_25) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_4_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_4_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_4_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_25) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_4_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_4_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_4_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_25) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_4_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_4_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_4_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_26) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_5_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_5_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_5_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_26) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_5_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_5_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_5_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_26) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_5_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_5_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_5_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_26) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_5_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_5_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_5_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_27) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_6_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_6_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_6_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_27) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_6_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_6_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_6_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_27) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_6_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_6_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_6_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_27) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_6_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_6_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_6_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_28) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_7_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_7_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_7_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_28) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_7_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_7_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_7_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_28) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_7_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_7_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_7_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_28) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_7_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_7_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_7_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_29) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_8_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_8_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_8_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_29) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_8_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_8_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_8_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_29) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_8_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_8_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_8_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_29) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_8_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_8_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_8_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_30) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_9_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_9_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_9_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_30) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_9_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_9_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_9_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_30) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_9_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_9_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_9_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_30) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_9_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_9_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_9_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_31) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_10_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_10_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_10_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_31) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_10_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_10_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_10_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_31) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_10_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_10_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_10_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_31) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_10_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_10_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_10_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_32) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_11_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_11_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_11_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_32) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_11_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_11_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_11_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_32) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_11_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_11_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_11_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_32) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_11_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_11_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_11_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_33) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_12_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_12_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_12_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_33) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_12_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_12_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_12_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_33) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_12_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_12_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_12_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_33) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_12_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_12_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_12_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_34) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_13_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_13_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_13_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_34) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_13_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_13_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_13_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_34) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_13_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_13_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_13_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_34) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_13_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_13_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_13_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & _GEN_35) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_14_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_14_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_14_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & _GEN_35) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_14_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_14_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_14_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & _GEN_35) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_14_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_14_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_14_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & _GEN_35) begin // @[faubtb.scala:57:25, :131:56, :136:{27,62}, :138:99, :142:42]
meta_14_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_14_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_14_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_19 & (&s1_update_meta_write_way)) begin // @[faubtb.scala:57:25, :113:55, :131:56, :136:{27,62}, :138:99, :142:42]
meta_15_0_is_br <= _meta_0_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_15_0_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_15_0_ctr <= _meta_0_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_30 & (&s1_update_meta_write_way)) begin // @[faubtb.scala:57:25, :113:55, :131:56, :136:{27,62}, :138:99, :142:42]
meta_15_1_is_br <= _meta_1_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_15_1_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_15_1_ctr <= _meta_1_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_41 & (&s1_update_meta_write_way)) begin // @[faubtb.scala:57:25, :113:55, :131:56, :136:{27,62}, :138:99, :142:42]
meta_15_2_is_br <= _meta_2_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_15_2_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_15_2_ctr <= _meta_2_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
if (_T_52 & (&s1_update_meta_write_way)) begin // @[faubtb.scala:57:25, :113:55, :131:56, :136:{27,62}, :138:99, :142:42]
meta_15_3_is_br <= _meta_3_is_br_T; // @[faubtb.scala:57:25, :142:67]
meta_15_3_tag <= s1_update_idx; // @[predictor.scala:185:30]
meta_15_3_ctr <= _meta_3_ctr_T_12; // @[faubtb.scala:57:25, :144:48]
end
end
always @(posedge)
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[faubtb.scala:21:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[faubtb.scala:21:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[faubtb.scala:21:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[faubtb.scala:21:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[faubtb.scala:21:7]
assign io_f3_meta = io_f3_meta_0; // @[faubtb.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Tile_253 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_509
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_253( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_509 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_18 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_18( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_78 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = or(_T_25, _T_32)
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_33, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_78( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_7 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_65
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleA_a32d256s5k3z4u_5
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonIn.a
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64)
node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2)
node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0))
node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 3)
regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonOut.a.ready, anonOut.a.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
node repeat_sel = bits(cated.bits.address, 4, 3)
node repeat_index = or(repeat_sel, repeat_count)
connect anonOut.a.bits, cated.bits
connect anonOut.a.valid, cated.valid
connect cated.ready, anonOut.a.ready
node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0)
node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64)
node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128)
node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192)
wire repeat_anonOut_a_bits_data_mux : UInt<64>[4]
connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T
connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1
connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2
connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3
connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index]
node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0)
node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8)
node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16)
node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24)
wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4]
connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T
connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1
connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2
connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3
connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
node hasData = bits(anonOut.d.bits.opcode, 0, 0)
node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size)
node _limit_T_1 = bits(_limit_T, 4, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 3)
regreset count : UInt<2>, clock, reset, UInt<2>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg)
node _T = and(anonOut.d.ready, anonOut.d.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonOut_d_ready_T = eq(last, UInt<1>(0h0))
node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T)
connect anonOut.d.ready, _anonOut_d_ready_T_1
node _anonIn_d_valid_T = and(anonOut.d.valid, last)
connect anonIn.d.valid, _anonIn_d_valid_T
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T)
node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1)
node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2)
node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3)
wire anonIn_d_bits_data_odata_0 : UInt
connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_1 : UInt
connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_2 : UInt
connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_3 : UInt
connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data
reg anonIn_d_bits_data_rdata : UInt<64>[3], clock
node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0])
node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1])
node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2])
node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data)
node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid)
node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1)
when _anonIn_d_bits_data_T_2 :
connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0
connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1
connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2
node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0)
node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2)
node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo)
connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3
connect anonIn.d.bits.corrupt, corrupt_out
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget32_7( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_65 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s5k3z4u_5 repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_122 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_137
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_122( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_137 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_99 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_99( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_10 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_10( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_74 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}}
inst input_buffer of InputBuffer_74
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter2_RouteComputerReq_28
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4`
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2]
wire vcalloc_vals : UInt<1>[2]
node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0))
node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11)
node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_18 = and(io.router_req.ready, io.router_req.valid)
when _T_18 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1])
when _T_19 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = bits(vcalloc_sel, 0, 0)
node _mask_T_6 = bits(vcalloc_sel, 1, 1)
node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0))
node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0))
node _mask_T_9 = or(_mask_T_7, _mask_T_8)
wire _mask_WIRE : UInt<2>
connect _mask_WIRE, _mask_T_9
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2]
node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2]
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16
connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19
connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[2]
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_34
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_40
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_43
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_46
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_20 = bits(vcalloc_sel, 0, 0)
node _T_21 = and(vcalloc_vals[0], _T_20)
node _T_22 = and(_T_21, io.vcalloc_req.ready)
when _T_22 :
connect states[0].g, UInt<3>(0h3)
node _T_23 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_23 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].vc_sel.`3`[1]
invalidate vcalloc_reqs[1].vc_sel.`4`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready)
node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_3
node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_24 :
node _T_25 = bits(vcalloc_sel, 0, 0)
when _T_25 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[0].g, UInt<3>(0h3)
node _T_26 = bits(vcalloc_sel, 1, 1)
when _T_26 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[1].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_182
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node _credit_available_T = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node _credit_available_T_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node _credit_available_T_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node _credit_available_T_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_hi = cat(states[0].vc_sel.`4`[0], _credit_available_T_3)
node credit_available_hi = cat(credit_available_hi_hi, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi, credit_available_lo)
node _credit_available_T_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node _credit_available_T_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node _credit_available_T_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node _credit_available_T_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_1 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_hi_1 = cat(io.out_credit_available.`4`[0], _credit_available_T_8)
node credit_available_hi_1 = cat(credit_available_hi_hi_1, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_27 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_28 = and(_T_27, input_buffer.io.deq[0].bits.tail)
when _T_28 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`4`[0]
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_5
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5
node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_7
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _vc_sel_WIRE : UInt<1>[2]
node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_4
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_7
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_3 : UInt<1>[2]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_10
connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4
node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_13
connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5
connect vc_sel.`1`, _vc_sel_WIRE_3
wire _vc_sel_WIRE_6 : UInt<1>[2]
node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_16
connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7
node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_19
connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8
connect vc_sel.`2`, _vc_sel_WIRE_6
wire _vc_sel_WIRE_9 : UInt<1>[2]
node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_22
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_25 = or(_vc_sel_T_23, _vc_sel_T_24)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_25
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
connect vc_sel.`3`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_26 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_28 = or(_vc_sel_T_26, _vc_sel_T_27)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_28
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`4`, _vc_sel_WIRE_12
node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_3 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1)
node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0))
node _virt_channel_T_9 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0))
node _virt_channel_T_10 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0))
node _virt_channel_T_11 = mux(channel_oh_3, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_12 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_13 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_10)
node _virt_channel_T_15 = or(_virt_channel_T_14, _virt_channel_T_11)
node _virt_channel_T_16 = or(_virt_channel_T_15, _virt_channel_T_12)
wire virt_channel : UInt<1>
connect virt_channel, _virt_channel_T_16
node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_29 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[0], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].vc_sel.`3`[1]
invalidate states[1].vc_sel.`4`[0]
invalidate states[1].g
node _T_30 = asUInt(reset)
when _T_30 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0) | module InputUnit_74( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_1_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_64 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_64( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_132 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_153
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_132( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_153 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_27 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_250
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_251
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_27( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_250 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_251 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_253 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Directory :
input clock : Clock
input reset : Reset
output io : { flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, flip read : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>}}, result : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, ready : UInt<1>}
smem cc_dir : UInt<17>[8] [1024]
inst write_q of Queue1_DirectoryWrite
connect write_q.clock, clock
connect write_q.reset, reset
connect write_q.io.enq.valid, io.write.valid
connect write_q.io.enq.bits.data.tag, io.write.bits.data.tag
connect write_q.io.enq.bits.data.clients, io.write.bits.data.clients
connect write_q.io.enq.bits.data.state, io.write.bits.data.state
connect write_q.io.enq.bits.data.dirty, io.write.bits.data.dirty
connect write_q.io.enq.bits.way, io.write.bits.way
connect write_q.io.enq.bits.set, io.write.bits.set
connect io.write.ready, write_q.io.enq.ready
regreset wipeCount : UInt<11>, clock, reset, UInt<11>(0h0)
regreset wipeOff : UInt<1>, clock, reset, UInt<1>(0h1)
connect wipeOff, UInt<1>(0h0)
node wipeDone = bits(wipeCount, 10, 10)
node wipeSet = bits(wipeCount, 9, 0)
connect io.ready, wipeDone
node _T = eq(wipeDone, UInt<1>(0h0))
node _T_1 = eq(wipeOff, UInt<1>(0h0))
node _T_2 = and(_T, _T_1)
when _T_2 :
node _wipeCount_T = add(wipeCount, UInt<1>(0h1))
node _wipeCount_T_1 = tail(_wipeCount_T, 1)
connect wipeCount, _wipeCount_T_1
node _T_3 = eq(io.read.valid, UInt<1>(0h0))
node _T_4 = or(wipeDone, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:86 assert (wipeDone || !io.read.valid)\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _wen_T = eq(wipeDone, UInt<1>(0h0))
node _wen_T_1 = eq(wipeOff, UInt<1>(0h0))
node _wen_T_2 = and(_wen_T, _wen_T_1)
node wen = or(_wen_T_2, write_q.io.deq.valid)
node _T_8 = eq(io.read.valid, UInt<1>(0h0))
node _T_9 = or(_T_8, wipeDone)
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:91 assert (!io.read.valid || wipeDone)\n") : printf_1
assert(clock, _T_9, UInt<1>(0h1), "") : assert_1
node _q_io_deq_ready_T = eq(io.read.valid, UInt<1>(0h0))
connect write_q.io.deq.ready, _q_io_deq_ready_T
node _T_13 = eq(io.read.valid, UInt<1>(0h0))
node _T_14 = and(_T_13, wen)
when _T_14 :
node _T_15 = mux(wipeDone, write_q.io.deq.bits.set, wipeSet)
node lo = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_16 = cat(hi, lo)
node _T_17 = mux(wipeDone, _T_16, UInt<1>(0h0))
node lo_1 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_1 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_18 = cat(hi_1, lo_1)
node _T_19 = mux(wipeDone, _T_18, UInt<1>(0h0))
node lo_2 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_2 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_20 = cat(hi_2, lo_2)
node _T_21 = mux(wipeDone, _T_20, UInt<1>(0h0))
node lo_3 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_3 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_22 = cat(hi_3, lo_3)
node _T_23 = mux(wipeDone, _T_22, UInt<1>(0h0))
node lo_4 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_4 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_24 = cat(hi_4, lo_4)
node _T_25 = mux(wipeDone, _T_24, UInt<1>(0h0))
node lo_5 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_5 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_26 = cat(hi_5, lo_5)
node _T_27 = mux(wipeDone, _T_26, UInt<1>(0h0))
node lo_6 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_6 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_28 = cat(hi_6, lo_6)
node _T_29 = mux(wipeDone, _T_28, UInt<1>(0h0))
node lo_7 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag)
node hi_7 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state)
node _T_30 = cat(hi_7, lo_7)
node _T_31 = mux(wipeDone, _T_30, UInt<1>(0h0))
wire _WIRE : UInt<17>[8]
connect _WIRE[0], _T_17
connect _WIRE[1], _T_19
connect _WIRE[2], _T_21
connect _WIRE[3], _T_23
connect _WIRE[4], _T_25
connect _WIRE[5], _T_27
connect _WIRE[6], _T_29
connect _WIRE[7], _T_31
node shiftAmount = bits(write_q.io.deq.bits.way, 2, 0)
node _T_32 = dshl(UInt<1>(0h1), shiftAmount)
node _T_33 = bits(_T_32, 7, 0)
node _T_34 = bits(_T_33, 0, 0)
node _T_35 = bits(_T_33, 1, 1)
node _T_36 = bits(_T_33, 2, 2)
node _T_37 = bits(_T_33, 3, 3)
node _T_38 = bits(_T_33, 4, 4)
node _T_39 = bits(_T_33, 5, 5)
node _T_40 = bits(_T_33, 6, 6)
node _T_41 = bits(_T_33, 7, 7)
node _T_42 = eq(wipeDone, UInt<1>(0h0))
node _T_43 = or(_T_34, _T_42)
node _T_44 = eq(wipeDone, UInt<1>(0h0))
node _T_45 = or(_T_35, _T_44)
node _T_46 = eq(wipeDone, UInt<1>(0h0))
node _T_47 = or(_T_36, _T_46)
node _T_48 = eq(wipeDone, UInt<1>(0h0))
node _T_49 = or(_T_37, _T_48)
node _T_50 = eq(wipeDone, UInt<1>(0h0))
node _T_51 = or(_T_38, _T_50)
node _T_52 = eq(wipeDone, UInt<1>(0h0))
node _T_53 = or(_T_39, _T_52)
node _T_54 = eq(wipeDone, UInt<1>(0h0))
node _T_55 = or(_T_40, _T_54)
node _T_56 = eq(wipeDone, UInt<1>(0h0))
node _T_57 = or(_T_41, _T_56)
write mport MPORT = cc_dir[_T_15], clock
when _T_43 :
connect MPORT[0], _WIRE[0]
when _T_45 :
connect MPORT[1], _WIRE[1]
when _T_47 :
connect MPORT[2], _WIRE[2]
when _T_49 :
connect MPORT[3], _WIRE[3]
when _T_51 :
connect MPORT[4], _WIRE[4]
when _T_53 :
connect MPORT[5], _WIRE[5]
when _T_55 :
connect MPORT[6], _WIRE[6]
when _T_57 :
connect MPORT[7], _WIRE[7]
regreset ren1 : UInt<1>, clock, reset, UInt<1>(0h0)
connect ren1, ren1
connect ren1, io.read.valid
node _bypass_T = and(ren1, write_q.io.deq.valid)
wire _regout_WIRE : UInt<10>
invalidate _regout_WIRE
when io.read.valid :
connect _regout_WIRE, io.read.bits.set
read mport regout = cc_dir[_regout_WIRE], clock
reg tag : UInt<12>, clock
when io.read.valid :
connect tag, io.read.bits.tag
reg set : UInt<10>, clock
when io.read.valid :
connect set, io.read.bits.set
inst victimLFSR_prng of MaxPeriodFibonacciLFSR
connect victimLFSR_prng.clock, clock
connect victimLFSR_prng.reset, reset
connect victimLFSR_prng.io.seed.valid, UInt<1>(0h0)
invalidate victimLFSR_prng.io.seed.bits[0]
invalidate victimLFSR_prng.io.seed.bits[1]
invalidate victimLFSR_prng.io.seed.bits[2]
invalidate victimLFSR_prng.io.seed.bits[3]
invalidate victimLFSR_prng.io.seed.bits[4]
invalidate victimLFSR_prng.io.seed.bits[5]
invalidate victimLFSR_prng.io.seed.bits[6]
invalidate victimLFSR_prng.io.seed.bits[7]
invalidate victimLFSR_prng.io.seed.bits[8]
invalidate victimLFSR_prng.io.seed.bits[9]
invalidate victimLFSR_prng.io.seed.bits[10]
invalidate victimLFSR_prng.io.seed.bits[11]
invalidate victimLFSR_prng.io.seed.bits[12]
invalidate victimLFSR_prng.io.seed.bits[13]
invalidate victimLFSR_prng.io.seed.bits[14]
invalidate victimLFSR_prng.io.seed.bits[15]
connect victimLFSR_prng.io.increment, io.read.valid
node victimLFSR_lo_lo_lo = cat(victimLFSR_prng.io.out[1], victimLFSR_prng.io.out[0])
node victimLFSR_lo_lo_hi = cat(victimLFSR_prng.io.out[3], victimLFSR_prng.io.out[2])
node victimLFSR_lo_lo = cat(victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo)
node victimLFSR_lo_hi_lo = cat(victimLFSR_prng.io.out[5], victimLFSR_prng.io.out[4])
node victimLFSR_lo_hi_hi = cat(victimLFSR_prng.io.out[7], victimLFSR_prng.io.out[6])
node victimLFSR_lo_hi = cat(victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo)
node victimLFSR_lo = cat(victimLFSR_lo_hi, victimLFSR_lo_lo)
node victimLFSR_hi_lo_lo = cat(victimLFSR_prng.io.out[9], victimLFSR_prng.io.out[8])
node victimLFSR_hi_lo_hi = cat(victimLFSR_prng.io.out[11], victimLFSR_prng.io.out[10])
node victimLFSR_hi_lo = cat(victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo)
node victimLFSR_hi_hi_lo = cat(victimLFSR_prng.io.out[13], victimLFSR_prng.io.out[12])
node victimLFSR_hi_hi_hi = cat(victimLFSR_prng.io.out[15], victimLFSR_prng.io.out[14])
node victimLFSR_hi_hi = cat(victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo)
node victimLFSR_hi = cat(victimLFSR_hi_hi, victimLFSR_hi_lo)
node _victimLFSR_T = cat(victimLFSR_hi, victimLFSR_lo)
node victimLFSR = bits(_victimLFSR_T, 9, 0)
node _victimLTE_T = leq(UInt<1>(0h0), victimLFSR)
node _victimLTE_T_1 = leq(UInt<8>(0h80), victimLFSR)
node _victimLTE_T_2 = leq(UInt<9>(0h100), victimLFSR)
node _victimLTE_T_3 = leq(UInt<9>(0h180), victimLFSR)
node _victimLTE_T_4 = leq(UInt<10>(0h200), victimLFSR)
node _victimLTE_T_5 = leq(UInt<10>(0h280), victimLFSR)
node _victimLTE_T_6 = leq(UInt<10>(0h300), victimLFSR)
node _victimLTE_T_7 = leq(UInt<10>(0h380), victimLFSR)
node victimLTE_lo_lo = cat(_victimLTE_T_1, _victimLTE_T)
node victimLTE_lo_hi = cat(_victimLTE_T_3, _victimLTE_T_2)
node victimLTE_lo = cat(victimLTE_lo_hi, victimLTE_lo_lo)
node victimLTE_hi_lo = cat(_victimLTE_T_5, _victimLTE_T_4)
node victimLTE_hi_hi = cat(_victimLTE_T_7, _victimLTE_T_6)
node victimLTE_hi = cat(victimLTE_hi_hi, victimLTE_hi_lo)
node victimLTE = cat(victimLTE_hi, victimLTE_lo)
node _victimSimp_T = bits(victimLTE, 7, 1)
node victimSimp_hi = cat(UInt<1>(0h0), _victimSimp_T)
node victimSimp = cat(victimSimp_hi, UInt<1>(0h1))
node _victimWayOH_T = bits(victimSimp, 7, 0)
node _victimWayOH_T_1 = shr(victimSimp, 1)
node _victimWayOH_T_2 = not(_victimWayOH_T_1)
node victimWayOH = and(_victimWayOH_T, _victimWayOH_T_2)
node victimWay_hi = bits(victimWayOH, 7, 4)
node victimWay_lo = bits(victimWayOH, 3, 0)
node _victimWay_T = orr(victimWay_hi)
node _victimWay_T_1 = or(victimWay_hi, victimWay_lo)
node victimWay_hi_1 = bits(_victimWay_T_1, 3, 2)
node victimWay_lo_1 = bits(_victimWay_T_1, 1, 0)
node _victimWay_T_2 = orr(victimWay_hi_1)
node _victimWay_T_3 = or(victimWay_hi_1, victimWay_lo_1)
node _victimWay_T_4 = bits(_victimWay_T_3, 1, 1)
node _victimWay_T_5 = cat(_victimWay_T_2, _victimWay_T_4)
node victimWay = cat(_victimWay_T, _victimWay_T_5)
node _T_58 = eq(ren1, UInt<1>(0h0))
node _T_59 = bits(victimLTE, 0, 0)
node _T_60 = eq(_T_59, UInt<1>(0h1))
node _T_61 = or(_T_58, _T_60)
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:121 assert (!ren2 || victimLTE(0) === 1.U)\n") : printf_2
assert(clock, _T_61, UInt<1>(0h1), "") : assert_2
node _T_65 = eq(ren1, UInt<1>(0h0))
node _T_66 = shr(victimSimp, 1)
node _T_67 = not(victimSimp)
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(_T_68, UInt<1>(0h0))
node _T_70 = or(_T_65, _T_69)
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:122 assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n") : printf_3
assert(clock, _T_70, UInt<1>(0h1), "") : assert_3
node _T_74 = eq(ren1, UInt<1>(0h0))
node _T_75 = bits(victimWayOH, 0, 0)
node _T_76 = bits(victimWayOH, 1, 1)
node _T_77 = bits(victimWayOH, 2, 2)
node _T_78 = bits(victimWayOH, 3, 3)
node _T_79 = bits(victimWayOH, 4, 4)
node _T_80 = bits(victimWayOH, 5, 5)
node _T_81 = bits(victimWayOH, 6, 6)
node _T_82 = bits(victimWayOH, 7, 7)
node _T_83 = add(_T_75, _T_76)
node _T_84 = bits(_T_83, 1, 0)
node _T_85 = add(_T_77, _T_78)
node _T_86 = bits(_T_85, 1, 0)
node _T_87 = add(_T_84, _T_86)
node _T_88 = bits(_T_87, 2, 0)
node _T_89 = add(_T_79, _T_80)
node _T_90 = bits(_T_89, 1, 0)
node _T_91 = add(_T_81, _T_82)
node _T_92 = bits(_T_91, 1, 0)
node _T_93 = add(_T_90, _T_92)
node _T_94 = bits(_T_93, 2, 0)
node _T_95 = add(_T_88, _T_94)
node _T_96 = bits(_T_95, 3, 0)
node _T_97 = eq(_T_96, UInt<1>(0h1))
node _T_98 = or(_T_74, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:123 assert (!ren2 || PopCount(victimWayOH) === 1.U)\n") : printf_4
assert(clock, _T_98, UInt<1>(0h1), "") : assert_4
node _setQuash_T = eq(write_q.io.deq.bits.set, set)
node setQuash = and(write_q.io.deq.valid, _setQuash_T)
node tagMatch = eq(write_q.io.deq.bits.data.tag, tag)
node wayMatch = eq(write_q.io.deq.bits.way, victimWay)
wire ways_0 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE : UInt<17>
connect _ways_WIRE, regout[0]
node _ways_T = bits(_ways_WIRE, 11, 0)
connect ways_0.tag, _ways_T
node _ways_T_1 = bits(_ways_WIRE, 13, 12)
connect ways_0.clients, _ways_T_1
node _ways_T_2 = bits(_ways_WIRE, 15, 14)
connect ways_0.state, _ways_T_2
node _ways_T_3 = bits(_ways_WIRE, 16, 16)
connect ways_0.dirty, _ways_T_3
wire ways_1 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_1 : UInt<17>
connect _ways_WIRE_1, regout[1]
node _ways_T_4 = bits(_ways_WIRE_1, 11, 0)
connect ways_1.tag, _ways_T_4
node _ways_T_5 = bits(_ways_WIRE_1, 13, 12)
connect ways_1.clients, _ways_T_5
node _ways_T_6 = bits(_ways_WIRE_1, 15, 14)
connect ways_1.state, _ways_T_6
node _ways_T_7 = bits(_ways_WIRE_1, 16, 16)
connect ways_1.dirty, _ways_T_7
wire ways_2 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_2 : UInt<17>
connect _ways_WIRE_2, regout[2]
node _ways_T_8 = bits(_ways_WIRE_2, 11, 0)
connect ways_2.tag, _ways_T_8
node _ways_T_9 = bits(_ways_WIRE_2, 13, 12)
connect ways_2.clients, _ways_T_9
node _ways_T_10 = bits(_ways_WIRE_2, 15, 14)
connect ways_2.state, _ways_T_10
node _ways_T_11 = bits(_ways_WIRE_2, 16, 16)
connect ways_2.dirty, _ways_T_11
wire ways_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_3 : UInt<17>
connect _ways_WIRE_3, regout[3]
node _ways_T_12 = bits(_ways_WIRE_3, 11, 0)
connect ways_3.tag, _ways_T_12
node _ways_T_13 = bits(_ways_WIRE_3, 13, 12)
connect ways_3.clients, _ways_T_13
node _ways_T_14 = bits(_ways_WIRE_3, 15, 14)
connect ways_3.state, _ways_T_14
node _ways_T_15 = bits(_ways_WIRE_3, 16, 16)
connect ways_3.dirty, _ways_T_15
wire ways_4 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_4 : UInt<17>
connect _ways_WIRE_4, regout[4]
node _ways_T_16 = bits(_ways_WIRE_4, 11, 0)
connect ways_4.tag, _ways_T_16
node _ways_T_17 = bits(_ways_WIRE_4, 13, 12)
connect ways_4.clients, _ways_T_17
node _ways_T_18 = bits(_ways_WIRE_4, 15, 14)
connect ways_4.state, _ways_T_18
node _ways_T_19 = bits(_ways_WIRE_4, 16, 16)
connect ways_4.dirty, _ways_T_19
wire ways_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_5 : UInt<17>
connect _ways_WIRE_5, regout[5]
node _ways_T_20 = bits(_ways_WIRE_5, 11, 0)
connect ways_5.tag, _ways_T_20
node _ways_T_21 = bits(_ways_WIRE_5, 13, 12)
connect ways_5.clients, _ways_T_21
node _ways_T_22 = bits(_ways_WIRE_5, 15, 14)
connect ways_5.state, _ways_T_22
node _ways_T_23 = bits(_ways_WIRE_5, 16, 16)
connect ways_5.dirty, _ways_T_23
wire ways_6 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_6 : UInt<17>
connect _ways_WIRE_6, regout[6]
node _ways_T_24 = bits(_ways_WIRE_6, 11, 0)
connect ways_6.tag, _ways_T_24
node _ways_T_25 = bits(_ways_WIRE_6, 13, 12)
connect ways_6.clients, _ways_T_25
node _ways_T_26 = bits(_ways_WIRE_6, 15, 14)
connect ways_6.state, _ways_T_26
node _ways_T_27 = bits(_ways_WIRE_6, 16, 16)
connect ways_6.dirty, _ways_T_27
wire ways_7 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
wire _ways_WIRE_7 : UInt<17>
connect _ways_WIRE_7, regout[7]
node _ways_T_28 = bits(_ways_WIRE_7, 11, 0)
connect ways_7.tag, _ways_T_28
node _ways_T_29 = bits(_ways_WIRE_7, 13, 12)
connect ways_7.clients, _ways_T_29
node _ways_T_30 = bits(_ways_WIRE_7, 15, 14)
connect ways_7.state, _ways_T_30
node _ways_T_31 = bits(_ways_WIRE_7, 16, 16)
connect ways_7.dirty, _ways_T_31
node _hits_T = eq(ways_0.tag, tag)
node _hits_T_1 = neq(ways_0.state, UInt<2>(0h0))
node _hits_T_2 = and(_hits_T, _hits_T_1)
node _hits_T_3 = eq(setQuash, UInt<1>(0h0))
node _hits_T_4 = neq(UInt<1>(0h0), write_q.io.deq.bits.way)
node _hits_T_5 = or(_hits_T_3, _hits_T_4)
node _hits_T_6 = and(_hits_T_2, _hits_T_5)
node _hits_T_7 = eq(ways_1.tag, tag)
node _hits_T_8 = neq(ways_1.state, UInt<2>(0h0))
node _hits_T_9 = and(_hits_T_7, _hits_T_8)
node _hits_T_10 = eq(setQuash, UInt<1>(0h0))
node _hits_T_11 = neq(UInt<1>(0h1), write_q.io.deq.bits.way)
node _hits_T_12 = or(_hits_T_10, _hits_T_11)
node _hits_T_13 = and(_hits_T_9, _hits_T_12)
node _hits_T_14 = eq(ways_2.tag, tag)
node _hits_T_15 = neq(ways_2.state, UInt<2>(0h0))
node _hits_T_16 = and(_hits_T_14, _hits_T_15)
node _hits_T_17 = eq(setQuash, UInt<1>(0h0))
node _hits_T_18 = neq(UInt<2>(0h2), write_q.io.deq.bits.way)
node _hits_T_19 = or(_hits_T_17, _hits_T_18)
node _hits_T_20 = and(_hits_T_16, _hits_T_19)
node _hits_T_21 = eq(ways_3.tag, tag)
node _hits_T_22 = neq(ways_3.state, UInt<2>(0h0))
node _hits_T_23 = and(_hits_T_21, _hits_T_22)
node _hits_T_24 = eq(setQuash, UInt<1>(0h0))
node _hits_T_25 = neq(UInt<2>(0h3), write_q.io.deq.bits.way)
node _hits_T_26 = or(_hits_T_24, _hits_T_25)
node _hits_T_27 = and(_hits_T_23, _hits_T_26)
node _hits_T_28 = eq(ways_4.tag, tag)
node _hits_T_29 = neq(ways_4.state, UInt<2>(0h0))
node _hits_T_30 = and(_hits_T_28, _hits_T_29)
node _hits_T_31 = eq(setQuash, UInt<1>(0h0))
node _hits_T_32 = neq(UInt<3>(0h4), write_q.io.deq.bits.way)
node _hits_T_33 = or(_hits_T_31, _hits_T_32)
node _hits_T_34 = and(_hits_T_30, _hits_T_33)
node _hits_T_35 = eq(ways_5.tag, tag)
node _hits_T_36 = neq(ways_5.state, UInt<2>(0h0))
node _hits_T_37 = and(_hits_T_35, _hits_T_36)
node _hits_T_38 = eq(setQuash, UInt<1>(0h0))
node _hits_T_39 = neq(UInt<3>(0h5), write_q.io.deq.bits.way)
node _hits_T_40 = or(_hits_T_38, _hits_T_39)
node _hits_T_41 = and(_hits_T_37, _hits_T_40)
node _hits_T_42 = eq(ways_6.tag, tag)
node _hits_T_43 = neq(ways_6.state, UInt<2>(0h0))
node _hits_T_44 = and(_hits_T_42, _hits_T_43)
node _hits_T_45 = eq(setQuash, UInt<1>(0h0))
node _hits_T_46 = neq(UInt<3>(0h6), write_q.io.deq.bits.way)
node _hits_T_47 = or(_hits_T_45, _hits_T_46)
node _hits_T_48 = and(_hits_T_44, _hits_T_47)
node _hits_T_49 = eq(ways_7.tag, tag)
node _hits_T_50 = neq(ways_7.state, UInt<2>(0h0))
node _hits_T_51 = and(_hits_T_49, _hits_T_50)
node _hits_T_52 = eq(setQuash, UInt<1>(0h0))
node _hits_T_53 = neq(UInt<3>(0h7), write_q.io.deq.bits.way)
node _hits_T_54 = or(_hits_T_52, _hits_T_53)
node _hits_T_55 = and(_hits_T_51, _hits_T_54)
node hits_lo_lo = cat(_hits_T_13, _hits_T_6)
node hits_lo_hi = cat(_hits_T_27, _hits_T_20)
node hits_lo = cat(hits_lo_hi, hits_lo_lo)
node hits_hi_lo = cat(_hits_T_41, _hits_T_34)
node hits_hi_hi = cat(_hits_T_55, _hits_T_48)
node hits_hi = cat(hits_hi_hi, hits_hi_lo)
node hits = cat(hits_hi, hits_lo)
node hit = orr(hits)
connect io.result.valid, ren1
node _view__T = bits(hits, 0, 0)
node _view__T_1 = bits(hits, 1, 1)
node _view__T_2 = bits(hits, 2, 2)
node _view__T_3 = bits(hits, 3, 3)
node _view__T_4 = bits(hits, 4, 4)
node _view__T_5 = bits(hits, 5, 5)
node _view__T_6 = bits(hits, 6, 6)
node _view__T_7 = bits(hits, 7, 7)
wire _view__WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
node _view__T_8 = mux(_view__T, ways_0.tag, UInt<1>(0h0))
node _view__T_9 = mux(_view__T_1, ways_1.tag, UInt<1>(0h0))
node _view__T_10 = mux(_view__T_2, ways_2.tag, UInt<1>(0h0))
node _view__T_11 = mux(_view__T_3, ways_3.tag, UInt<1>(0h0))
node _view__T_12 = mux(_view__T_4, ways_4.tag, UInt<1>(0h0))
node _view__T_13 = mux(_view__T_5, ways_5.tag, UInt<1>(0h0))
node _view__T_14 = mux(_view__T_6, ways_6.tag, UInt<1>(0h0))
node _view__T_15 = mux(_view__T_7, ways_7.tag, UInt<1>(0h0))
node _view__T_16 = or(_view__T_8, _view__T_9)
node _view__T_17 = or(_view__T_16, _view__T_10)
node _view__T_18 = or(_view__T_17, _view__T_11)
node _view__T_19 = or(_view__T_18, _view__T_12)
node _view__T_20 = or(_view__T_19, _view__T_13)
node _view__T_21 = or(_view__T_20, _view__T_14)
node _view__T_22 = or(_view__T_21, _view__T_15)
wire _view__WIRE_1 : UInt<12>
connect _view__WIRE_1, _view__T_22
connect _view__WIRE.tag, _view__WIRE_1
node _view__T_23 = mux(_view__T, ways_0.clients, UInt<1>(0h0))
node _view__T_24 = mux(_view__T_1, ways_1.clients, UInt<1>(0h0))
node _view__T_25 = mux(_view__T_2, ways_2.clients, UInt<1>(0h0))
node _view__T_26 = mux(_view__T_3, ways_3.clients, UInt<1>(0h0))
node _view__T_27 = mux(_view__T_4, ways_4.clients, UInt<1>(0h0))
node _view__T_28 = mux(_view__T_5, ways_5.clients, UInt<1>(0h0))
node _view__T_29 = mux(_view__T_6, ways_6.clients, UInt<1>(0h0))
node _view__T_30 = mux(_view__T_7, ways_7.clients, UInt<1>(0h0))
node _view__T_31 = or(_view__T_23, _view__T_24)
node _view__T_32 = or(_view__T_31, _view__T_25)
node _view__T_33 = or(_view__T_32, _view__T_26)
node _view__T_34 = or(_view__T_33, _view__T_27)
node _view__T_35 = or(_view__T_34, _view__T_28)
node _view__T_36 = or(_view__T_35, _view__T_29)
node _view__T_37 = or(_view__T_36, _view__T_30)
wire _view__WIRE_2 : UInt<2>
connect _view__WIRE_2, _view__T_37
connect _view__WIRE.clients, _view__WIRE_2
node _view__T_38 = mux(_view__T, ways_0.state, UInt<1>(0h0))
node _view__T_39 = mux(_view__T_1, ways_1.state, UInt<1>(0h0))
node _view__T_40 = mux(_view__T_2, ways_2.state, UInt<1>(0h0))
node _view__T_41 = mux(_view__T_3, ways_3.state, UInt<1>(0h0))
node _view__T_42 = mux(_view__T_4, ways_4.state, UInt<1>(0h0))
node _view__T_43 = mux(_view__T_5, ways_5.state, UInt<1>(0h0))
node _view__T_44 = mux(_view__T_6, ways_6.state, UInt<1>(0h0))
node _view__T_45 = mux(_view__T_7, ways_7.state, UInt<1>(0h0))
node _view__T_46 = or(_view__T_38, _view__T_39)
node _view__T_47 = or(_view__T_46, _view__T_40)
node _view__T_48 = or(_view__T_47, _view__T_41)
node _view__T_49 = or(_view__T_48, _view__T_42)
node _view__T_50 = or(_view__T_49, _view__T_43)
node _view__T_51 = or(_view__T_50, _view__T_44)
node _view__T_52 = or(_view__T_51, _view__T_45)
wire _view__WIRE_3 : UInt<2>
connect _view__WIRE_3, _view__T_52
connect _view__WIRE.state, _view__WIRE_3
node _view__T_53 = mux(_view__T, ways_0.dirty, UInt<1>(0h0))
node _view__T_54 = mux(_view__T_1, ways_1.dirty, UInt<1>(0h0))
node _view__T_55 = mux(_view__T_2, ways_2.dirty, UInt<1>(0h0))
node _view__T_56 = mux(_view__T_3, ways_3.dirty, UInt<1>(0h0))
node _view__T_57 = mux(_view__T_4, ways_4.dirty, UInt<1>(0h0))
node _view__T_58 = mux(_view__T_5, ways_5.dirty, UInt<1>(0h0))
node _view__T_59 = mux(_view__T_6, ways_6.dirty, UInt<1>(0h0))
node _view__T_60 = mux(_view__T_7, ways_7.dirty, UInt<1>(0h0))
node _view__T_61 = or(_view__T_53, _view__T_54)
node _view__T_62 = or(_view__T_61, _view__T_55)
node _view__T_63 = or(_view__T_62, _view__T_56)
node _view__T_64 = or(_view__T_63, _view__T_57)
node _view__T_65 = or(_view__T_64, _view__T_58)
node _view__T_66 = or(_view__T_65, _view__T_59)
node _view__T_67 = or(_view__T_66, _view__T_60)
wire _view__WIRE_4 : UInt<1>
connect _view__WIRE_4, _view__T_67
connect _view__WIRE.dirty, _view__WIRE_4
node _view__T_68 = or(tagMatch, wayMatch)
node _view__T_69 = and(setQuash, _view__T_68)
node _view__T_70 = bits(victimWayOH, 0, 0)
node _view__T_71 = bits(victimWayOH, 1, 1)
node _view__T_72 = bits(victimWayOH, 2, 2)
node _view__T_73 = bits(victimWayOH, 3, 3)
node _view__T_74 = bits(victimWayOH, 4, 4)
node _view__T_75 = bits(victimWayOH, 5, 5)
node _view__T_76 = bits(victimWayOH, 6, 6)
node _view__T_77 = bits(victimWayOH, 7, 7)
wire _view__WIRE_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}
node _view__T_78 = mux(_view__T_70, ways_0.tag, UInt<1>(0h0))
node _view__T_79 = mux(_view__T_71, ways_1.tag, UInt<1>(0h0))
node _view__T_80 = mux(_view__T_72, ways_2.tag, UInt<1>(0h0))
node _view__T_81 = mux(_view__T_73, ways_3.tag, UInt<1>(0h0))
node _view__T_82 = mux(_view__T_74, ways_4.tag, UInt<1>(0h0))
node _view__T_83 = mux(_view__T_75, ways_5.tag, UInt<1>(0h0))
node _view__T_84 = mux(_view__T_76, ways_6.tag, UInt<1>(0h0))
node _view__T_85 = mux(_view__T_77, ways_7.tag, UInt<1>(0h0))
node _view__T_86 = or(_view__T_78, _view__T_79)
node _view__T_87 = or(_view__T_86, _view__T_80)
node _view__T_88 = or(_view__T_87, _view__T_81)
node _view__T_89 = or(_view__T_88, _view__T_82)
node _view__T_90 = or(_view__T_89, _view__T_83)
node _view__T_91 = or(_view__T_90, _view__T_84)
node _view__T_92 = or(_view__T_91, _view__T_85)
wire _view__WIRE_6 : UInt<12>
connect _view__WIRE_6, _view__T_92
connect _view__WIRE_5.tag, _view__WIRE_6
node _view__T_93 = mux(_view__T_70, ways_0.clients, UInt<1>(0h0))
node _view__T_94 = mux(_view__T_71, ways_1.clients, UInt<1>(0h0))
node _view__T_95 = mux(_view__T_72, ways_2.clients, UInt<1>(0h0))
node _view__T_96 = mux(_view__T_73, ways_3.clients, UInt<1>(0h0))
node _view__T_97 = mux(_view__T_74, ways_4.clients, UInt<1>(0h0))
node _view__T_98 = mux(_view__T_75, ways_5.clients, UInt<1>(0h0))
node _view__T_99 = mux(_view__T_76, ways_6.clients, UInt<1>(0h0))
node _view__T_100 = mux(_view__T_77, ways_7.clients, UInt<1>(0h0))
node _view__T_101 = or(_view__T_93, _view__T_94)
node _view__T_102 = or(_view__T_101, _view__T_95)
node _view__T_103 = or(_view__T_102, _view__T_96)
node _view__T_104 = or(_view__T_103, _view__T_97)
node _view__T_105 = or(_view__T_104, _view__T_98)
node _view__T_106 = or(_view__T_105, _view__T_99)
node _view__T_107 = or(_view__T_106, _view__T_100)
wire _view__WIRE_7 : UInt<2>
connect _view__WIRE_7, _view__T_107
connect _view__WIRE_5.clients, _view__WIRE_7
node _view__T_108 = mux(_view__T_70, ways_0.state, UInt<1>(0h0))
node _view__T_109 = mux(_view__T_71, ways_1.state, UInt<1>(0h0))
node _view__T_110 = mux(_view__T_72, ways_2.state, UInt<1>(0h0))
node _view__T_111 = mux(_view__T_73, ways_3.state, UInt<1>(0h0))
node _view__T_112 = mux(_view__T_74, ways_4.state, UInt<1>(0h0))
node _view__T_113 = mux(_view__T_75, ways_5.state, UInt<1>(0h0))
node _view__T_114 = mux(_view__T_76, ways_6.state, UInt<1>(0h0))
node _view__T_115 = mux(_view__T_77, ways_7.state, UInt<1>(0h0))
node _view__T_116 = or(_view__T_108, _view__T_109)
node _view__T_117 = or(_view__T_116, _view__T_110)
node _view__T_118 = or(_view__T_117, _view__T_111)
node _view__T_119 = or(_view__T_118, _view__T_112)
node _view__T_120 = or(_view__T_119, _view__T_113)
node _view__T_121 = or(_view__T_120, _view__T_114)
node _view__T_122 = or(_view__T_121, _view__T_115)
wire _view__WIRE_8 : UInt<2>
connect _view__WIRE_8, _view__T_122
connect _view__WIRE_5.state, _view__WIRE_8
node _view__T_123 = mux(_view__T_70, ways_0.dirty, UInt<1>(0h0))
node _view__T_124 = mux(_view__T_71, ways_1.dirty, UInt<1>(0h0))
node _view__T_125 = mux(_view__T_72, ways_2.dirty, UInt<1>(0h0))
node _view__T_126 = mux(_view__T_73, ways_3.dirty, UInt<1>(0h0))
node _view__T_127 = mux(_view__T_74, ways_4.dirty, UInt<1>(0h0))
node _view__T_128 = mux(_view__T_75, ways_5.dirty, UInt<1>(0h0))
node _view__T_129 = mux(_view__T_76, ways_6.dirty, UInt<1>(0h0))
node _view__T_130 = mux(_view__T_77, ways_7.dirty, UInt<1>(0h0))
node _view__T_131 = or(_view__T_123, _view__T_124)
node _view__T_132 = or(_view__T_131, _view__T_125)
node _view__T_133 = or(_view__T_132, _view__T_126)
node _view__T_134 = or(_view__T_133, _view__T_127)
node _view__T_135 = or(_view__T_134, _view__T_128)
node _view__T_136 = or(_view__T_135, _view__T_129)
node _view__T_137 = or(_view__T_136, _view__T_130)
wire _view__WIRE_9 : UInt<1>
connect _view__WIRE_9, _view__T_137
connect _view__WIRE_5.dirty, _view__WIRE_9
node _view__T_138 = mux(_view__T_69, write_q.io.deq.bits.data, _view__WIRE_5)
node _view__T_139 = mux(hit, _view__WIRE, _view__T_138)
connect io.result.bits.tag, _view__T_139.tag
connect io.result.bits.clients, _view__T_139.clients
connect io.result.bits.state, _view__T_139.state
connect io.result.bits.dirty, _view__T_139.dirty
node _io_result_bits_hit_T = and(setQuash, tagMatch)
node _io_result_bits_hit_T_1 = neq(write_q.io.deq.bits.data.state, UInt<2>(0h0))
node _io_result_bits_hit_T_2 = and(_io_result_bits_hit_T, _io_result_bits_hit_T_1)
node _io_result_bits_hit_T_3 = or(hit, _io_result_bits_hit_T_2)
connect io.result.bits.hit, _io_result_bits_hit_T_3
node io_result_bits_way_hi = bits(hits, 7, 4)
node io_result_bits_way_lo = bits(hits, 3, 0)
node _io_result_bits_way_T = orr(io_result_bits_way_hi)
node _io_result_bits_way_T_1 = or(io_result_bits_way_hi, io_result_bits_way_lo)
node io_result_bits_way_hi_1 = bits(_io_result_bits_way_T_1, 3, 2)
node io_result_bits_way_lo_1 = bits(_io_result_bits_way_T_1, 1, 0)
node _io_result_bits_way_T_2 = orr(io_result_bits_way_hi_1)
node _io_result_bits_way_T_3 = or(io_result_bits_way_hi_1, io_result_bits_way_lo_1)
node _io_result_bits_way_T_4 = bits(_io_result_bits_way_T_3, 1, 1)
node _io_result_bits_way_T_5 = cat(_io_result_bits_way_T_2, _io_result_bits_way_T_4)
node _io_result_bits_way_T_6 = cat(_io_result_bits_way_T, _io_result_bits_way_T_5)
node _io_result_bits_way_T_7 = and(setQuash, tagMatch)
node _io_result_bits_way_T_8 = mux(_io_result_bits_way_T_7, write_q.io.deq.bits.way, victimWay)
node _io_result_bits_way_T_9 = mux(hit, _io_result_bits_way_T_6, _io_result_bits_way_T_8)
connect io.result.bits.way, _io_result_bits_way_T_9
node _T_102 = and(ren1, setQuash)
node _T_103 = and(_T_102, tagMatch)
node _T_104 = and(ren1, setQuash)
node _T_105 = eq(tagMatch, UInt<1>(0h0))
node _T_106 = and(_T_104, _T_105)
node _T_107 = and(_T_106, wayMatch) | module Directory( // @[Directory.scala:56:7]
input clock, // @[Directory.scala:56:7]
input reset, // @[Directory.scala:56:7]
output io_write_ready, // @[Directory.scala:58:14]
input io_write_valid, // @[Directory.scala:58:14]
input [9:0] io_write_bits_set, // @[Directory.scala:58:14]
input [2:0] io_write_bits_way, // @[Directory.scala:58:14]
input io_write_bits_data_dirty, // @[Directory.scala:58:14]
input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14]
input [1:0] io_write_bits_data_clients, // @[Directory.scala:58:14]
input [11:0] io_write_bits_data_tag, // @[Directory.scala:58:14]
input io_read_valid, // @[Directory.scala:58:14]
input [9:0] io_read_bits_set, // @[Directory.scala:58:14]
input [11:0] io_read_bits_tag, // @[Directory.scala:58:14]
output io_result_bits_dirty, // @[Directory.scala:58:14]
output [1:0] io_result_bits_state, // @[Directory.scala:58:14]
output [1:0] io_result_bits_clients, // @[Directory.scala:58:14]
output [11:0] io_result_bits_tag, // @[Directory.scala:58:14]
output io_result_bits_hit, // @[Directory.scala:58:14]
output [2:0] io_result_bits_way, // @[Directory.scala:58:14]
output io_ready // @[Directory.scala:58:14]
);
wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65]
wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65]
wire [16:0] _T_31; // @[Directory.scala:99:44]
wire [16:0] _T_29; // @[Directory.scala:99:44]
wire [16:0] _T_27; // @[Directory.scala:99:44]
wire [16:0] _T_25; // @[Directory.scala:99:44]
wire [16:0] _T_23; // @[Directory.scala:99:44]
wire [16:0] _T_21; // @[Directory.scala:99:44]
wire [16:0] _T_19; // @[Directory.scala:99:44]
wire [16:0] _T_17; // @[Directory.scala:99:44]
wire [9:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10]
wire cc_dir_MPORT_en; // @[Directory.scala:96:14]
wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22]
wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22]
wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [9:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21]
wire [2:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21]
wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21]
wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21]
wire [1:0] _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21]
wire [11:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21]
wire [135:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7]
wire [9:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7]
wire [2:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7]
wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7]
wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7]
wire [1:0] io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7]
wire [11:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7]
wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7]
wire [9:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7]
wire [11:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7]
wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43]
wire [9:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41]
wire _view__T_139_dirty; // @[Directory.scala:136:67]
wire [1:0] _view__T_139_state; // @[Directory.scala:136:67]
wire [1:0] _view__T_139_clients; // @[Directory.scala:136:67]
wire [11:0] _view__T_139_tag; // @[Directory.scala:136:67]
wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29]
wire [2:0] _io_result_bits_way_T_9; // @[Directory.scala:138:28]
wire wipeDone; // @[Directory.scala:81:27]
wire io_write_ready_0; // @[Directory.scala:56:7]
wire io_result_bits_dirty_0; // @[Directory.scala:56:7]
wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7]
wire [1:0] io_result_bits_clients_0; // @[Directory.scala:56:7]
wire [11:0] io_result_bits_tag_0; // @[Directory.scala:56:7]
wire io_result_bits_hit_0; // @[Directory.scala:56:7]
wire [2:0] io_result_bits_way_0; // @[Directory.scala:56:7]
wire io_result_valid; // @[Directory.scala:56:7]
wire io_ready_0; // @[Directory.scala:56:7]
wire [16:0] _ways_WIRE = _cc_dir_RW0_rdata[16:0]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[33:17]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[50:34]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[67:51]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[84:68]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[101:85]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[118:102]; // @[DescribedSRAM.scala:17:26]
wire [16:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[135:119]; // @[DescribedSRAM.scala:17:26]
reg [10:0] wipeCount; // @[Directory.scala:79:26]
reg wipeOff; // @[Directory.scala:80:24]
assign wipeDone = wipeCount[10]; // @[Directory.scala:79:26, :81:27]
assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27]
wire [9:0] wipeSet = wipeCount[9:0]; // @[Directory.scala:79:26, :82:26]
wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27]
wire [11:0] _wipeCount_T = {1'h0, wipeCount} + 12'h1; // @[Directory.scala:79:26, :85:57]
wire [10:0] _wipeCount_T_1 = _wipeCount_T[10:0]; // @[Directory.scala:85:57]
wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14]
wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}]
wire wen = _wen_T_2 | _write_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18]
assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14]
assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21]
wire [13:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21]
wire [13:0] lo; // @[Directory.scala:99:71]
assign lo = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_1; // @[Directory.scala:99:71]
assign lo_1 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_2; // @[Directory.scala:99:71]
assign lo_2 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_3; // @[Directory.scala:99:71]
assign lo_3 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_4; // @[Directory.scala:99:71]
assign lo_4 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_5; // @[Directory.scala:99:71]
assign lo_5 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_6; // @[Directory.scala:99:71]
assign lo_6 = _GEN; // @[Directory.scala:99:71]
wire [13:0] lo_7; // @[Directory.scala:99:71]
assign lo_7 = _GEN; // @[Directory.scala:99:71]
wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21]
wire [2:0] hi; // @[Directory.scala:99:71]
assign hi = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_1; // @[Directory.scala:99:71]
assign hi_1 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_2; // @[Directory.scala:99:71]
assign hi_2 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_3; // @[Directory.scala:99:71]
assign hi_3 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_4; // @[Directory.scala:99:71]
assign hi_4 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_5; // @[Directory.scala:99:71]
assign hi_5 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_6; // @[Directory.scala:99:71]
assign hi_6 = _GEN_0; // @[Directory.scala:99:71]
wire [2:0] hi_7; // @[Directory.scala:99:71]
assign hi_7 = _GEN_0; // @[Directory.scala:99:71]
assign _T_17 = wipeDone ? {hi, lo} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_19 = wipeDone ? {hi_1, lo_1} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_21 = wipeDone ? {hi_2, lo_2} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_23 = wipeDone ? {hi_3, lo_3} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_25 = wipeDone ? {hi_4, lo_4} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_27 = wipeDone ? {hi_5, lo_5} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_29 = wipeDone ? {hi_6, lo_6} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
assign _T_31 = wipeDone ? {hi_7, lo_7} : 17'h0; // @[Directory.scala:81:27, :99:{44,71}]
wire [2:0] shiftAmount; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_0 = shiftAmount == 3'h0 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_1 = shiftAmount == 3'h1 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_2 = shiftAmount == 3'h2 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_3 = shiftAmount == 3'h3 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_4 = shiftAmount == 3'h4 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_5 = shiftAmount == 3'h5 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_6 = shiftAmount == 3'h6 | ~wipeDone; // @[OneHot.scala:64:49]
assign cc_dir_MPORT_mask_7 = (&shiftAmount) | ~wipeDone; // @[OneHot.scala:64:49]
reg ren1; // @[Directory.scala:103:21]
assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21]
wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21]
reg [11:0] tag; // @[Directory.scala:111:36]
reg [9:0] set; // @[Directory.scala:112:36]
wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17]
wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17]
wire _victimLTE_T_1 = |(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_2 = |(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_3 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_4 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_5 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_6 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43]
wire _victimLTE_T_7 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43]
wire [1:0] victimLTE_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}]
wire [1:0] victimLTE_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}]
wire [3:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23]
wire [1:0] victimLTE_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}]
wire [1:0] victimLTE_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}]
wire [3:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23]
wire [7:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23]
wire [6:0] _victimSimp_T = victimLTE[7:1]; // @[Directory.scala:117:23, :118:43]
wire [7:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}]
wire [8:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23]
wire [7:0] _victimWayOH_T = victimSimp[7:0]; // @[Directory.scala:118:23, :119:31]
wire [7:0] _victimWayOH_T_1 = victimSimp[8:1]; // @[Directory.scala:118:23, :119:70]
wire [7:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}]
wire [7:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}]
wire [3:0] victimWay_hi = victimWayOH[7:4]; // @[OneHot.scala:30:18]
wire [3:0] victimWay_lo = victimWayOH[3:0]; // @[OneHot.scala:31:18]
wire _victimWay_T = |victimWay_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _victimWay_T_1 = victimWay_hi | victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] victimWay_hi_1 = _victimWay_T_1[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] victimWay_lo_1 = _victimWay_T_1[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _victimWay_T_2 = |victimWay_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _victimWay_T_3 = victimWay_hi_1 | victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _victimWay_T_4 = _victimWay_T_3[1]; // @[OneHot.scala:32:28]
wire [1:0] _victimWay_T_5 = {_victimWay_T_2, _victimWay_T_4}; // @[OneHot.scala:32:{10,14}]
wire [2:0] victimWay = {_victimWay_T, _victimWay_T_5}; // @[OneHot.scala:32:{10,14}]
wire _view__T_70 = victimWayOH[0]; // @[Mux.scala:32:36]
wire _view__T_71 = victimWayOH[1]; // @[Mux.scala:32:36]
wire _view__T_72 = victimWayOH[2]; // @[Mux.scala:32:36]
wire _view__T_73 = victimWayOH[3]; // @[Mux.scala:32:36]
wire _view__T_74 = victimWayOH[4]; // @[Mux.scala:32:36]
wire _view__T_75 = victimWayOH[5]; // @[Mux.scala:32:36]
wire _view__T_76 = victimWayOH[6]; // @[Mux.scala:32:36]
wire _view__T_77 = victimWayOH[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_19 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_19
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_19
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_19
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_19( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_19 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_19 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_19 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_176 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_193
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_176( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_193 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CounterController :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, flip event_io : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}}
inst counterfile of CounterFile
connect counterfile.clock, clock
connect counterfile.reset, reset
connect counterfile.io.event_io, io.event_io
reg out_reg : { rd : UInt<5>, data : UInt<64>}, clock
regreset out_valid_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node _io_in_ready_T = eq(out_valid_reg, UInt<1>(0h0))
connect io.in.ready, _io_in_ready_T
node _counterfile_io_addr_T = bits(io.in.bits.rs1, 6, 4)
connect counterfile.io.addr, _counterfile_io_addr_T
node _counterfile_io_counter_reset_T = bits(io.in.bits.rs1, 0, 0)
node _counterfile_io_counter_reset_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_counter_reset_T_2 = and(_counterfile_io_counter_reset_T, _counterfile_io_counter_reset_T_1)
connect counterfile.io.counter_reset, _counterfile_io_counter_reset_T_2
node _counterfile_io_snapshot_reset_T = bits(io.in.bits.rs1, 1, 1)
node _counterfile_io_snapshot_reset_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_snapshot_reset_T_2 = and(_counterfile_io_snapshot_reset_T, _counterfile_io_snapshot_reset_T_1)
connect counterfile.io.snapshot_reset, _counterfile_io_snapshot_reset_T_2
node _counterfile_io_snapshot_T = bits(io.in.bits.rs1, 2, 2)
node _counterfile_io_snapshot_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_snapshot_T_2 = and(_counterfile_io_snapshot_T, _counterfile_io_snapshot_T_1)
connect counterfile.io.snapshot, _counterfile_io_snapshot_T_2
node _counterfile_io_config_address_valid_T = bits(io.in.bits.rs1, 3, 3)
node _counterfile_io_config_address_valid_T_1 = and(io.in.ready, io.in.valid)
node _counterfile_io_config_address_valid_T_2 = and(_counterfile_io_config_address_valid_T, _counterfile_io_config_address_valid_T_1)
connect counterfile.io.config_address.valid, _counterfile_io_config_address_valid_T_2
node _counterfile_io_config_address_bits_T = bits(io.in.bits.rs1, 17, 12)
connect counterfile.io.config_address.bits, _counterfile_io_config_address_bits_T
node _counterfile_io_external_T = bits(io.in.bits.rs1, 31, 31)
connect counterfile.io.external, _counterfile_io_external_T
node _T = and(io.out.ready, io.out.valid)
when _T :
connect out_valid_reg, UInt<1>(0h0)
else :
node _T_1 = and(io.in.ready, io.in.valid)
when _T_1 :
connect out_valid_reg, UInt<1>(0h1)
connect out_reg.rd, io.in.bits.inst.rd
connect out_reg.data, UInt<1>(0h0)
connect out_reg.data, counterfile.io.data
connect io.out.valid, out_valid_reg
connect io.out.bits, out_reg | module CounterController( // @[CounterFile.scala:218:7]
input clock, // @[CounterFile.scala:218:7]
input reset, // @[CounterFile.scala:218:7]
output io_in_ready, // @[CounterFile.scala:219:14]
input io_in_valid, // @[CounterFile.scala:219:14]
input [6:0] io_in_bits_inst_funct, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rs2, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rs1, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xd, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xs1, // @[CounterFile.scala:219:14]
input io_in_bits_inst_xs2, // @[CounterFile.scala:219:14]
input [4:0] io_in_bits_inst_rd, // @[CounterFile.scala:219:14]
input [6:0] io_in_bits_inst_opcode, // @[CounterFile.scala:219:14]
input [63:0] io_in_bits_rs1, // @[CounterFile.scala:219:14]
input [63:0] io_in_bits_rs2, // @[CounterFile.scala:219:14]
input io_in_bits_status_debug, // @[CounterFile.scala:219:14]
input io_in_bits_status_cease, // @[CounterFile.scala:219:14]
input io_in_bits_status_wfi, // @[CounterFile.scala:219:14]
input [31:0] io_in_bits_status_isa, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_dprv, // @[CounterFile.scala:219:14]
input io_in_bits_status_dv, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_prv, // @[CounterFile.scala:219:14]
input io_in_bits_status_v, // @[CounterFile.scala:219:14]
input io_in_bits_status_sd, // @[CounterFile.scala:219:14]
input [22:0] io_in_bits_status_zero2, // @[CounterFile.scala:219:14]
input io_in_bits_status_mpv, // @[CounterFile.scala:219:14]
input io_in_bits_status_gva, // @[CounterFile.scala:219:14]
input io_in_bits_status_mbe, // @[CounterFile.scala:219:14]
input io_in_bits_status_sbe, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_sxl, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_uxl, // @[CounterFile.scala:219:14]
input io_in_bits_status_sd_rv32, // @[CounterFile.scala:219:14]
input [7:0] io_in_bits_status_zero1, // @[CounterFile.scala:219:14]
input io_in_bits_status_tsr, // @[CounterFile.scala:219:14]
input io_in_bits_status_tw, // @[CounterFile.scala:219:14]
input io_in_bits_status_tvm, // @[CounterFile.scala:219:14]
input io_in_bits_status_mxr, // @[CounterFile.scala:219:14]
input io_in_bits_status_sum, // @[CounterFile.scala:219:14]
input io_in_bits_status_mprv, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_xs, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_fs, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_mpp, // @[CounterFile.scala:219:14]
input [1:0] io_in_bits_status_vs, // @[CounterFile.scala:219:14]
input io_in_bits_status_spp, // @[CounterFile.scala:219:14]
input io_in_bits_status_mpie, // @[CounterFile.scala:219:14]
input io_in_bits_status_ube, // @[CounterFile.scala:219:14]
input io_in_bits_status_spie, // @[CounterFile.scala:219:14]
input io_in_bits_status_upie, // @[CounterFile.scala:219:14]
input io_in_bits_status_mie, // @[CounterFile.scala:219:14]
input io_in_bits_status_hie, // @[CounterFile.scala:219:14]
input io_in_bits_status_sie, // @[CounterFile.scala:219:14]
input io_in_bits_status_uie, // @[CounterFile.scala:219:14]
input io_out_ready, // @[CounterFile.scala:219:14]
output io_out_valid, // @[CounterFile.scala:219:14]
output [4:0] io_out_bits_rd, // @[CounterFile.scala:219:14]
output [63:0] io_out_bits_data, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_1, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_2, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_3, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_4, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_5, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_6, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_7, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_8, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_9, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_10, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_11, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_12, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_13, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_14, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_15, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_16, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_17, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_18, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_19, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_20, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_21, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_22, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_23, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_24, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_25, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_26, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_27, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_28, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_29, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_30, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_31, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_32, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_33, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_34, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_35, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_36, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_37, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_38, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_39, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_40, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_41, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_42, // @[CounterFile.scala:219:14]
input io_event_io_event_signal_43, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_1, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_2, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_3, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_4, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_5, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_6, // @[CounterFile.scala:219:14]
input [31:0] io_event_io_external_values_7, // @[CounterFile.scala:219:14]
output io_event_io_external_reset // @[CounterFile.scala:219:14]
);
wire [63:0] _counterfile_io_data; // @[CounterFile.scala:228:29]
wire io_in_valid_0 = io_in_valid; // @[CounterFile.scala:218:7]
wire [6:0] io_in_bits_inst_funct_0 = io_in_bits_inst_funct; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rs2_0 = io_in_bits_inst_rs2; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rs1_0 = io_in_bits_inst_rs1; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xd_0 = io_in_bits_inst_xd; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xs1_0 = io_in_bits_inst_xs1; // @[CounterFile.scala:218:7]
wire io_in_bits_inst_xs2_0 = io_in_bits_inst_xs2; // @[CounterFile.scala:218:7]
wire [4:0] io_in_bits_inst_rd_0 = io_in_bits_inst_rd; // @[CounterFile.scala:218:7]
wire [6:0] io_in_bits_inst_opcode_0 = io_in_bits_inst_opcode; // @[CounterFile.scala:218:7]
wire [63:0] io_in_bits_rs1_0 = io_in_bits_rs1; // @[CounterFile.scala:218:7]
wire [63:0] io_in_bits_rs2_0 = io_in_bits_rs2; // @[CounterFile.scala:218:7]
wire io_in_bits_status_debug_0 = io_in_bits_status_debug; // @[CounterFile.scala:218:7]
wire io_in_bits_status_cease_0 = io_in_bits_status_cease; // @[CounterFile.scala:218:7]
wire io_in_bits_status_wfi_0 = io_in_bits_status_wfi; // @[CounterFile.scala:218:7]
wire [31:0] io_in_bits_status_isa_0 = io_in_bits_status_isa; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_dprv_0 = io_in_bits_status_dprv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_dv_0 = io_in_bits_status_dv; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_prv_0 = io_in_bits_status_prv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_v_0 = io_in_bits_status_v; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sd_0 = io_in_bits_status_sd; // @[CounterFile.scala:218:7]
wire [22:0] io_in_bits_status_zero2_0 = io_in_bits_status_zero2; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mpv_0 = io_in_bits_status_mpv; // @[CounterFile.scala:218:7]
wire io_in_bits_status_gva_0 = io_in_bits_status_gva; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mbe_0 = io_in_bits_status_mbe; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sbe_0 = io_in_bits_status_sbe; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_sxl_0 = io_in_bits_status_sxl; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_uxl_0 = io_in_bits_status_uxl; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sd_rv32_0 = io_in_bits_status_sd_rv32; // @[CounterFile.scala:218:7]
wire [7:0] io_in_bits_status_zero1_0 = io_in_bits_status_zero1; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tsr_0 = io_in_bits_status_tsr; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tw_0 = io_in_bits_status_tw; // @[CounterFile.scala:218:7]
wire io_in_bits_status_tvm_0 = io_in_bits_status_tvm; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mxr_0 = io_in_bits_status_mxr; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sum_0 = io_in_bits_status_sum; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mprv_0 = io_in_bits_status_mprv; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_xs_0 = io_in_bits_status_xs; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_fs_0 = io_in_bits_status_fs; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_mpp_0 = io_in_bits_status_mpp; // @[CounterFile.scala:218:7]
wire [1:0] io_in_bits_status_vs_0 = io_in_bits_status_vs; // @[CounterFile.scala:218:7]
wire io_in_bits_status_spp_0 = io_in_bits_status_spp; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mpie_0 = io_in_bits_status_mpie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_ube_0 = io_in_bits_status_ube; // @[CounterFile.scala:218:7]
wire io_in_bits_status_spie_0 = io_in_bits_status_spie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_upie_0 = io_in_bits_status_upie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_mie_0 = io_in_bits_status_mie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_hie_0 = io_in_bits_status_hie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_sie_0 = io_in_bits_status_sie; // @[CounterFile.scala:218:7]
wire io_in_bits_status_uie_0 = io_in_bits_status_uie; // @[CounterFile.scala:218:7]
wire io_out_ready_0 = io_out_ready; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_1_0 = io_event_io_event_signal_1; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_2_0 = io_event_io_event_signal_2; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_3_0 = io_event_io_event_signal_3; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_4_0 = io_event_io_event_signal_4; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_5_0 = io_event_io_event_signal_5; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_6_0 = io_event_io_event_signal_6; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_7_0 = io_event_io_event_signal_7; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_8_0 = io_event_io_event_signal_8; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_9_0 = io_event_io_event_signal_9; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_10_0 = io_event_io_event_signal_10; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_11_0 = io_event_io_event_signal_11; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_12_0 = io_event_io_event_signal_12; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_13_0 = io_event_io_event_signal_13; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_14_0 = io_event_io_event_signal_14; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_15_0 = io_event_io_event_signal_15; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_16_0 = io_event_io_event_signal_16; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_17_0 = io_event_io_event_signal_17; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_18_0 = io_event_io_event_signal_18; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_19_0 = io_event_io_event_signal_19; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_20_0 = io_event_io_event_signal_20; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_21_0 = io_event_io_event_signal_21; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_22_0 = io_event_io_event_signal_22; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_23_0 = io_event_io_event_signal_23; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_24_0 = io_event_io_event_signal_24; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_25_0 = io_event_io_event_signal_25; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_26_0 = io_event_io_event_signal_26; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_27_0 = io_event_io_event_signal_27; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_28_0 = io_event_io_event_signal_28; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_29_0 = io_event_io_event_signal_29; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_30_0 = io_event_io_event_signal_30; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_31_0 = io_event_io_event_signal_31; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_32_0 = io_event_io_event_signal_32; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_33_0 = io_event_io_event_signal_33; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_34_0 = io_event_io_event_signal_34; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_35_0 = io_event_io_event_signal_35; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_36_0 = io_event_io_event_signal_36; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_37_0 = io_event_io_event_signal_37; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_38_0 = io_event_io_event_signal_38; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_39_0 = io_event_io_event_signal_39; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_40_0 = io_event_io_event_signal_40; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_41_0 = io_event_io_event_signal_41; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_42_0 = io_event_io_event_signal_42; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_43_0 = io_event_io_event_signal_43; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_1_0 = io_event_io_external_values_1; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_2_0 = io_event_io_external_values_2; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_3_0 = io_event_io_external_values_3; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_4_0 = io_event_io_external_values_4; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_5_0 = io_event_io_external_values_5; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_6_0 = io_event_io_external_values_6; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_7_0 = io_event_io_external_values_7; // @[CounterFile.scala:218:7]
wire [31:0] io_event_io_external_values_0 = 32'h0; // @[CounterFile.scala:218:7, :219:14, :228:29]
wire io_event_io_event_signal_0 = 1'h0; // @[CounterFile.scala:218:7]
wire io_event_io_event_signal_44 = 1'h0; // @[CounterFile.scala:218:7]
wire _io_in_ready_T; // @[CounterFile.scala:244:20]
wire io_in_ready_0; // @[CounterFile.scala:218:7]
wire [4:0] io_out_bits_rd_0; // @[CounterFile.scala:218:7]
wire [63:0] io_out_bits_data_0; // @[CounterFile.scala:218:7]
wire io_out_valid_0; // @[CounterFile.scala:218:7]
wire io_event_io_external_reset_0; // @[CounterFile.scala:218:7]
reg [4:0] out_reg_rd; // @[CounterFile.scala:231:22]
assign io_out_bits_rd_0 = out_reg_rd; // @[CounterFile.scala:218:7, :231:22]
reg [63:0] out_reg_data; // @[CounterFile.scala:231:22]
assign io_out_bits_data_0 = out_reg_data; // @[CounterFile.scala:218:7, :231:22]
reg out_valid_reg; // @[CounterFile.scala:232:32]
assign io_out_valid_0 = out_valid_reg; // @[CounterFile.scala:218:7, :232:32]
assign _io_in_ready_T = ~out_valid_reg; // @[CounterFile.scala:232:32, :244:20]
assign io_in_ready_0 = _io_in_ready_T; // @[CounterFile.scala:218:7, :244:20]
wire [2:0] _counterfile_io_addr_T = io_in_bits_rs1_0[6:4]; // @[CounterFile.scala:218:7, :245:42]
wire _counterfile_io_counter_reset_T = io_in_bits_rs1_0[0]; // @[CounterFile.scala:218:7, :246:51]
wire _T_1 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
wire _counterfile_io_counter_reset_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_counter_reset_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_reset_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_snapshot_reset_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_snapshot_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_config_address_valid_T_1; // @[Decoupled.scala:51:35]
assign _counterfile_io_config_address_valid_T_1 = _T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_counter_reset_T_2 = _counterfile_io_counter_reset_T & _counterfile_io_counter_reset_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_reset_T = io_in_bits_rs1_0[1]; // @[CounterFile.scala:218:7, :247:52]
wire _counterfile_io_snapshot_reset_T_2 = _counterfile_io_snapshot_reset_T & _counterfile_io_snapshot_reset_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_snapshot_T = io_in_bits_rs1_0[2]; // @[CounterFile.scala:218:7, :248:46]
wire _counterfile_io_snapshot_T_2 = _counterfile_io_snapshot_T & _counterfile_io_snapshot_T_1; // @[Decoupled.scala:51:35]
wire _counterfile_io_config_address_valid_T = io_in_bits_rs1_0[3]; // @[CounterFile.scala:218:7, :249:58]
wire _counterfile_io_config_address_valid_T_2 = _counterfile_io_config_address_valid_T & _counterfile_io_config_address_valid_T_1; // @[Decoupled.scala:51:35]
wire [5:0] _counterfile_io_config_address_bits_T = io_in_bits_rs1_0[17:12]; // @[CounterFile.scala:218:7, :250:57]
wire _counterfile_io_external_T = io_in_bits_rs1_0[31]; // @[CounterFile.scala:218:7, :251:46]
wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[CounterFile.scala:218:7]
if (_T | ~_T_1) begin // @[Decoupled.scala:51:35]
end
else begin // @[CounterFile.scala:231:22, :253:24, :255:30]
out_reg_rd <= io_in_bits_inst_rd_0; // @[CounterFile.scala:218:7, :231:22]
out_reg_data <= _counterfile_io_data; // @[CounterFile.scala:228:29, :231:22]
end
if (reset) // @[CounterFile.scala:218:7]
out_valid_reg <= 1'h0; // @[CounterFile.scala:232:32]
else // @[CounterFile.scala:218:7]
out_valid_reg <= ~_T & (_T_1 | out_valid_reg); // @[Decoupled.scala:51:35]
always @(posedge)
CounterFile counterfile ( // @[CounterFile.scala:228:29]
.clock (clock),
.reset (reset),
.io_counter_reset (_counterfile_io_counter_reset_T_2), // @[CounterFile.scala:246:55]
.io_snapshot (_counterfile_io_snapshot_T_2), // @[CounterFile.scala:248:50]
.io_snapshot_reset (_counterfile_io_snapshot_reset_T_2), // @[CounterFile.scala:247:56]
.io_addr (_counterfile_io_addr_T), // @[CounterFile.scala:245:42]
.io_data (_counterfile_io_data),
.io_config_address_valid (_counterfile_io_config_address_valid_T_2), // @[CounterFile.scala:249:62]
.io_config_address_bits (_counterfile_io_config_address_bits_T), // @[CounterFile.scala:250:57]
.io_external (_counterfile_io_external_T), // @[CounterFile.scala:251:46]
.io_event_io_event_signal_1 (io_event_io_event_signal_1_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_2 (io_event_io_event_signal_2_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_3 (io_event_io_event_signal_3_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_4 (io_event_io_event_signal_4_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_5 (io_event_io_event_signal_5_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_6 (io_event_io_event_signal_6_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_7 (io_event_io_event_signal_7_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_8 (io_event_io_event_signal_8_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_9 (io_event_io_event_signal_9_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_10 (io_event_io_event_signal_10_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_11 (io_event_io_event_signal_11_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_12 (io_event_io_event_signal_12_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_13 (io_event_io_event_signal_13_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_14 (io_event_io_event_signal_14_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_15 (io_event_io_event_signal_15_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_16 (io_event_io_event_signal_16_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_17 (io_event_io_event_signal_17_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_18 (io_event_io_event_signal_18_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_19 (io_event_io_event_signal_19_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_20 (io_event_io_event_signal_20_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_21 (io_event_io_event_signal_21_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_22 (io_event_io_event_signal_22_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_23 (io_event_io_event_signal_23_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_24 (io_event_io_event_signal_24_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_25 (io_event_io_event_signal_25_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_26 (io_event_io_event_signal_26_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_27 (io_event_io_event_signal_27_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_28 (io_event_io_event_signal_28_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_29 (io_event_io_event_signal_29_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_30 (io_event_io_event_signal_30_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_31 (io_event_io_event_signal_31_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_32 (io_event_io_event_signal_32_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_33 (io_event_io_event_signal_33_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_34 (io_event_io_event_signal_34_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_35 (io_event_io_event_signal_35_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_36 (io_event_io_event_signal_36_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_37 (io_event_io_event_signal_37_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_38 (io_event_io_event_signal_38_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_39 (io_event_io_event_signal_39_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_40 (io_event_io_event_signal_40_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_41 (io_event_io_event_signal_41_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_42 (io_event_io_event_signal_42_0), // @[CounterFile.scala:218:7]
.io_event_io_event_signal_43 (io_event_io_event_signal_43_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_1 (io_event_io_external_values_1_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_2 (io_event_io_external_values_2_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_3 (io_event_io_external_values_3_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_4 (io_event_io_external_values_4_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_5 (io_event_io_external_values_5_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_6 (io_event_io_external_values_6_0), // @[CounterFile.scala:218:7]
.io_event_io_external_values_7 (io_event_io_external_values_7_0), // @[CounterFile.scala:218:7]
.io_event_io_external_reset (io_event_io_external_reset_0)
); // @[CounterFile.scala:228:29]
assign io_in_ready = io_in_ready_0; // @[CounterFile.scala:218:7]
assign io_out_valid = io_out_valid_0; // @[CounterFile.scala:218:7]
assign io_out_bits_rd = io_out_bits_rd_0; // @[CounterFile.scala:218:7]
assign io_out_bits_data = io_out_bits_data_0; // @[CounterFile.scala:218:7]
assign io_event_io_external_reset = io_event_io_external_reset_0; // @[CounterFile.scala:218:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CLINT :
input clock : Clock
input reset : Reset
output auto : { int_out : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip rtcTick : UInt<1>}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_42
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire intnodeOut : UInt<1>[2]
invalidate intnodeOut[0]
invalidate intnodeOut[1]
connect nodeIn, auto.in
connect auto.int_out, intnodeOut
regreset time : UInt<64>, clock, reset, UInt<64>(0h0)
when io.rtcTick :
node _time_T = add(time, UInt<1>(0h1))
node _time_T_1 = tail(_time_T, 1)
connect time, _time_T_1
reg timecmp_0 : UInt<64>, clock
regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0)
node _intnodeOut_0_T = bits(ipi_0, 0, 0)
connect intnodeOut[0], _intnodeOut_0_T
node _intnodeOut_1_T = geq(time, timecmp_0)
connect intnodeOut[1], _intnodeOut_1_T
node pad = or(timecmp_0, UInt<64>(0h0))
node _oldBytes_T = bits(pad, 7, 0)
node _oldBytes_T_1 = bits(pad, 15, 8)
node _oldBytes_T_2 = bits(pad, 23, 16)
node _oldBytes_T_3 = bits(pad, 31, 24)
node _oldBytes_T_4 = bits(pad, 39, 32)
node _oldBytes_T_5 = bits(pad, 47, 40)
node _oldBytes_T_6 = bits(pad, 55, 48)
node _oldBytes_T_7 = bits(pad, 63, 56)
wire oldBytes : UInt<8>[8]
connect oldBytes[0], _oldBytes_T
connect oldBytes[1], _oldBytes_T_1
connect oldBytes[2], _oldBytes_T_2
connect oldBytes[3], _oldBytes_T_3
connect oldBytes[4], _oldBytes_T_4
connect oldBytes[5], _oldBytes_T_5
connect oldBytes[6], _oldBytes_T_6
connect oldBytes[7], _oldBytes_T_7
wire newBytes : UInt<8>[8]
connect newBytes, oldBytes
wire _valids_WIRE : UInt<1>[8]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
wire valids : UInt<1>[8]
connect valids, _valids_WIRE
node _T = or(valids[0], valids[1])
node _T_1 = or(_T, valids[2])
node _T_2 = or(_T_1, valids[3])
node _T_3 = or(_T_2, valids[4])
node _T_4 = or(_T_3, valids[5])
node _T_5 = or(_T_4, valids[6])
node _T_6 = or(_T_5, valids[7])
when _T_6 :
node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0])
node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2])
node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo)
node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4])
node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6])
node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo)
node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo)
connect timecmp_0, _timecmp_0_T
node pad_1 = or(time, UInt<64>(0h0))
node _oldBytes_T_8 = bits(pad_1, 7, 0)
node _oldBytes_T_9 = bits(pad_1, 15, 8)
node _oldBytes_T_10 = bits(pad_1, 23, 16)
node _oldBytes_T_11 = bits(pad_1, 31, 24)
node _oldBytes_T_12 = bits(pad_1, 39, 32)
node _oldBytes_T_13 = bits(pad_1, 47, 40)
node _oldBytes_T_14 = bits(pad_1, 55, 48)
node _oldBytes_T_15 = bits(pad_1, 63, 56)
wire oldBytes_1 : UInt<8>[8]
connect oldBytes_1[0], _oldBytes_T_8
connect oldBytes_1[1], _oldBytes_T_9
connect oldBytes_1[2], _oldBytes_T_10
connect oldBytes_1[3], _oldBytes_T_11
connect oldBytes_1[4], _oldBytes_T_12
connect oldBytes_1[5], _oldBytes_T_13
connect oldBytes_1[6], _oldBytes_T_14
connect oldBytes_1[7], _oldBytes_T_15
wire newBytes_1 : UInt<8>[8]
connect newBytes_1, oldBytes_1
wire _valids_WIRE_1 : UInt<1>[8]
connect _valids_WIRE_1[0], UInt<1>(0h0)
connect _valids_WIRE_1[1], UInt<1>(0h0)
connect _valids_WIRE_1[2], UInt<1>(0h0)
connect _valids_WIRE_1[3], UInt<1>(0h0)
connect _valids_WIRE_1[4], UInt<1>(0h0)
connect _valids_WIRE_1[5], UInt<1>(0h0)
connect _valids_WIRE_1[6], UInt<1>(0h0)
connect _valids_WIRE_1[7], UInt<1>(0h0)
wire valids_1 : UInt<1>[8]
connect valids_1, _valids_WIRE_1
node _T_7 = or(valids_1[0], valids_1[1])
node _T_8 = or(_T_7, valids_1[2])
node _T_9 = or(_T_8, valids_1[3])
node _T_10 = or(_T_9, valids_1[4])
node _T_11 = or(_T_10, valids_1[5])
node _T_12 = or(_T_11, valids_1[6])
node _T_13 = or(_T_12, valids_1[7])
when _T_13 :
node time_lo_lo = cat(newBytes_1[1], newBytes_1[0])
node time_lo_hi = cat(newBytes_1[3], newBytes_1[2])
node time_lo = cat(time_lo_hi, time_lo_lo)
node time_hi_lo = cat(newBytes_1[5], newBytes_1[4])
node time_hi_hi = cat(newBytes_1[7], newBytes_1[6])
node time_hi = cat(time_hi_hi, time_hi_lo)
node _time_T_2 = cat(time_hi, time_lo)
connect time, _time_T_2
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(nodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, nodeIn.a.bits.data
connect in.bits.mask, nodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<13>(0h1800))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<13>(0h0))
node _out_T_1 = eq(out_bindex, UInt<13>(0h0))
node _out_T_2 = eq(out_findex, UInt<13>(0h7ff))
node _out_T_3 = eq(out_bindex, UInt<13>(0h7ff))
node _out_T_4 = eq(out_findex, UInt<13>(0h0))
node _out_T_5 = eq(out_bindex, UInt<13>(0h0))
wire out_rivalid : UInt<1>[18]
wire out_wivalid : UInt<1>[18]
wire out_roready : UInt<1>[18]
wire out_woready : UInt<1>[18]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_6 = bits(out_front.bits.data, 0, 0)
when out_f_woready :
connect ipi_0, _out_T_6
node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1))
node _out_T_8 = and(UInt<1>(0h1), out_f_roready)
node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1))
node _out_T_10 = and(UInt<1>(0h1), out_f_woready)
node _out_T_11 = eq(out_rimask, UInt<1>(0h0))
node _out_T_12 = eq(out_wimask, UInt<1>(0h0))
node _out_T_13 = eq(out_romask, UInt<1>(0h0))
node _out_T_14 = eq(out_womask, UInt<1>(0h0))
node _out_T_15 = or(ipi_0, UInt<1>(0h0))
node _out_T_16 = bits(_out_T_15, 0, 0)
node _out_rimask_T_1 = bits(out_frontMask, 31, 1)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 31, 1)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 31, 1)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 31, 1)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_17 = bits(out_front.bits.data, 31, 1)
node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_16, UInt<1>(0h0))
node out_prepend = cat(UInt<1>(0h0), _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<32>(0h0))
node _out_T_25 = bits(_out_T_24, 31, 0)
node _out_rimask_T_2 = bits(out_frontMask, 7, 0)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 7, 0)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 7, 0)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 7, 0)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_front.bits.data, 7, 0)
connect valids_1[0], out_f_woready_2
when out_f_woready_2 :
connect newBytes_1[0], _out_T_26
node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1))
node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2)
node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_33 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_34 = eq(out_womask_2, UInt<1>(0h0))
node _out_T_35 = or(oldBytes_1[0], UInt<8>(0h0))
node _out_T_36 = bits(_out_T_35, 7, 0)
node _out_rimask_T_3 = bits(out_frontMask, 15, 8)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 15, 8)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 15, 8)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 15, 8)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
node _out_T_37 = bits(out_front.bits.data, 15, 8)
connect valids_1[1], out_f_woready_3
when out_f_woready_3 :
connect newBytes_1[1], _out_T_37
node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_40 = and(out_f_wivalid_3, UInt<1>(0h1))
node _out_T_41 = and(UInt<1>(0h1), out_f_woready_3)
node _out_T_42 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_43 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_44 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_45 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_36, UInt<8>(0h0))
node out_prepend_1 = cat(oldBytes_1[1], _out_prepend_T_1)
node _out_T_46 = or(out_prepend_1, UInt<16>(0h0))
node _out_T_47 = bits(_out_T_46, 15, 0)
node _out_rimask_T_4 = bits(out_frontMask, 23, 16)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 23, 16)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 23, 16)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 23, 16)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_48 = bits(out_front.bits.data, 23, 16)
connect valids_1[2], out_f_woready_4
when out_f_woready_4 :
connect newBytes_1[2], _out_T_48
node _out_T_49 = and(out_f_rivalid_4, UInt<1>(0h1))
node _out_T_50 = and(UInt<1>(0h1), out_f_roready_4)
node _out_T_51 = and(out_f_wivalid_4, UInt<1>(0h1))
node _out_T_52 = and(UInt<1>(0h1), out_f_woready_4)
node _out_T_53 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_54 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_55 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_56 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_47, UInt<16>(0h0))
node out_prepend_2 = cat(oldBytes_1[2], _out_prepend_T_2)
node _out_T_57 = or(out_prepend_2, UInt<24>(0h0))
node _out_T_58 = bits(_out_T_57, 23, 0)
node _out_rimask_T_5 = bits(out_frontMask, 31, 24)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 31, 24)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 31, 24)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 31, 24)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_59 = bits(out_front.bits.data, 31, 24)
connect valids_1[3], out_f_woready_5
when out_f_woready_5 :
connect newBytes_1[3], _out_T_59
node _out_T_60 = and(out_f_rivalid_5, UInt<1>(0h1))
node _out_T_61 = and(UInt<1>(0h1), out_f_roready_5)
node _out_T_62 = and(out_f_wivalid_5, UInt<1>(0h1))
node _out_T_63 = and(UInt<1>(0h1), out_f_woready_5)
node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_66 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_67 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_58, UInt<24>(0h0))
node out_prepend_3 = cat(oldBytes_1[3], _out_prepend_T_3)
node _out_T_68 = or(out_prepend_3, UInt<32>(0h0))
node _out_T_69 = bits(_out_T_68, 31, 0)
node _out_rimask_T_6 = bits(out_frontMask, 39, 32)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 39, 32)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 39, 32)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 39, 32)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_70 = bits(out_front.bits.data, 39, 32)
connect valids_1[4], out_f_woready_6
when out_f_woready_6 :
connect newBytes_1[4], _out_T_70
node _out_T_71 = and(out_f_rivalid_6, UInt<1>(0h1))
node _out_T_72 = and(UInt<1>(0h1), out_f_roready_6)
node _out_T_73 = and(out_f_wivalid_6, UInt<1>(0h1))
node _out_T_74 = and(UInt<1>(0h1), out_f_woready_6)
node _out_T_75 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_76 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_77 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_78 = eq(out_womask_6, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_69, UInt<32>(0h0))
node out_prepend_4 = cat(oldBytes_1[4], _out_prepend_T_4)
node _out_T_79 = or(out_prepend_4, UInt<40>(0h0))
node _out_T_80 = bits(_out_T_79, 39, 0)
node _out_rimask_T_7 = bits(out_frontMask, 47, 40)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 47, 40)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 47, 40)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 47, 40)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_81 = bits(out_front.bits.data, 47, 40)
connect valids_1[5], out_f_woready_7
when out_f_woready_7 :
connect newBytes_1[5], _out_T_81
node _out_T_82 = and(out_f_rivalid_7, UInt<1>(0h1))
node _out_T_83 = and(UInt<1>(0h1), out_f_roready_7)
node _out_T_84 = and(out_f_wivalid_7, UInt<1>(0h1))
node _out_T_85 = and(UInt<1>(0h1), out_f_woready_7)
node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_88 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_89 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_80, UInt<40>(0h0))
node out_prepend_5 = cat(oldBytes_1[5], _out_prepend_T_5)
node _out_T_90 = or(out_prepend_5, UInt<48>(0h0))
node _out_T_91 = bits(_out_T_90, 47, 0)
node _out_rimask_T_8 = bits(out_frontMask, 55, 48)
node out_rimask_8 = orr(_out_rimask_T_8)
node _out_wimask_T_8 = bits(out_frontMask, 55, 48)
node out_wimask_8 = andr(_out_wimask_T_8)
node _out_romask_T_8 = bits(out_backMask, 55, 48)
node out_romask_8 = orr(_out_romask_T_8)
node _out_womask_T_8 = bits(out_backMask, 55, 48)
node out_womask_8 = andr(_out_womask_T_8)
node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8)
node out_f_roready_8 = and(out_roready[8], out_romask_8)
node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8)
node out_f_woready_8 = and(out_woready[8], out_womask_8)
node _out_T_92 = bits(out_front.bits.data, 55, 48)
connect valids_1[6], out_f_woready_8
when out_f_woready_8 :
connect newBytes_1[6], _out_T_92
node _out_T_93 = and(out_f_rivalid_8, UInt<1>(0h1))
node _out_T_94 = and(UInt<1>(0h1), out_f_roready_8)
node _out_T_95 = and(out_f_wivalid_8, UInt<1>(0h1))
node _out_T_96 = and(UInt<1>(0h1), out_f_woready_8)
node _out_T_97 = eq(out_rimask_8, UInt<1>(0h0))
node _out_T_98 = eq(out_wimask_8, UInt<1>(0h0))
node _out_T_99 = eq(out_romask_8, UInt<1>(0h0))
node _out_T_100 = eq(out_womask_8, UInt<1>(0h0))
node _out_prepend_T_6 = or(_out_T_91, UInt<48>(0h0))
node out_prepend_6 = cat(oldBytes_1[6], _out_prepend_T_6)
node _out_T_101 = or(out_prepend_6, UInt<56>(0h0))
node _out_T_102 = bits(_out_T_101, 55, 0)
node _out_rimask_T_9 = bits(out_frontMask, 63, 56)
node out_rimask_9 = orr(_out_rimask_T_9)
node _out_wimask_T_9 = bits(out_frontMask, 63, 56)
node out_wimask_9 = andr(_out_wimask_T_9)
node _out_romask_T_9 = bits(out_backMask, 63, 56)
node out_romask_9 = orr(_out_romask_T_9)
node _out_womask_T_9 = bits(out_backMask, 63, 56)
node out_womask_9 = andr(_out_womask_T_9)
node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9)
node out_f_roready_9 = and(out_roready[9], out_romask_9)
node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9)
node out_f_woready_9 = and(out_woready[9], out_womask_9)
node _out_T_103 = bits(out_front.bits.data, 63, 56)
connect valids_1[7], out_f_woready_9
when out_f_woready_9 :
connect newBytes_1[7], _out_T_103
node _out_T_104 = and(out_f_rivalid_9, UInt<1>(0h1))
node _out_T_105 = and(UInt<1>(0h1), out_f_roready_9)
node _out_T_106 = and(out_f_wivalid_9, UInt<1>(0h1))
node _out_T_107 = and(UInt<1>(0h1), out_f_woready_9)
node _out_T_108 = eq(out_rimask_9, UInt<1>(0h0))
node _out_T_109 = eq(out_wimask_9, UInt<1>(0h0))
node _out_T_110 = eq(out_romask_9, UInt<1>(0h0))
node _out_T_111 = eq(out_womask_9, UInt<1>(0h0))
node _out_prepend_T_7 = or(_out_T_102, UInt<56>(0h0))
node out_prepend_7 = cat(oldBytes_1[7], _out_prepend_T_7)
node _out_T_112 = or(out_prepend_7, UInt<64>(0h0))
node _out_T_113 = bits(_out_T_112, 63, 0)
node _out_rimask_T_10 = bits(out_frontMask, 7, 0)
node out_rimask_10 = orr(_out_rimask_T_10)
node _out_wimask_T_10 = bits(out_frontMask, 7, 0)
node out_wimask_10 = andr(_out_wimask_T_10)
node _out_romask_T_10 = bits(out_backMask, 7, 0)
node out_romask_10 = orr(_out_romask_T_10)
node _out_womask_T_10 = bits(out_backMask, 7, 0)
node out_womask_10 = andr(_out_womask_T_10)
node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10)
node out_f_roready_10 = and(out_roready[10], out_romask_10)
node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10)
node out_f_woready_10 = and(out_woready[10], out_womask_10)
node _out_T_114 = bits(out_front.bits.data, 7, 0)
connect valids[0], out_f_woready_10
when out_f_woready_10 :
connect newBytes[0], _out_T_114
node _out_T_115 = and(out_f_rivalid_10, UInt<1>(0h1))
node _out_T_116 = and(UInt<1>(0h1), out_f_roready_10)
node _out_T_117 = and(out_f_wivalid_10, UInt<1>(0h1))
node _out_T_118 = and(UInt<1>(0h1), out_f_woready_10)
node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0))
node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0))
node _out_T_121 = eq(out_romask_10, UInt<1>(0h0))
node _out_T_122 = eq(out_womask_10, UInt<1>(0h0))
node _out_T_123 = or(oldBytes[0], UInt<8>(0h0))
node _out_T_124 = bits(_out_T_123, 7, 0)
node _out_rimask_T_11 = bits(out_frontMask, 15, 8)
node out_rimask_11 = orr(_out_rimask_T_11)
node _out_wimask_T_11 = bits(out_frontMask, 15, 8)
node out_wimask_11 = andr(_out_wimask_T_11)
node _out_romask_T_11 = bits(out_backMask, 15, 8)
node out_romask_11 = orr(_out_romask_T_11)
node _out_womask_T_11 = bits(out_backMask, 15, 8)
node out_womask_11 = andr(_out_womask_T_11)
node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11)
node out_f_roready_11 = and(out_roready[11], out_romask_11)
node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11)
node out_f_woready_11 = and(out_woready[11], out_womask_11)
node _out_T_125 = bits(out_front.bits.data, 15, 8)
connect valids[1], out_f_woready_11
when out_f_woready_11 :
connect newBytes[1], _out_T_125
node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1))
node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11)
node _out_T_128 = and(out_f_wivalid_11, UInt<1>(0h1))
node _out_T_129 = and(UInt<1>(0h1), out_f_woready_11)
node _out_T_130 = eq(out_rimask_11, UInt<1>(0h0))
node _out_T_131 = eq(out_wimask_11, UInt<1>(0h0))
node _out_T_132 = eq(out_romask_11, UInt<1>(0h0))
node _out_T_133 = eq(out_womask_11, UInt<1>(0h0))
node _out_prepend_T_8 = or(_out_T_124, UInt<8>(0h0))
node out_prepend_8 = cat(oldBytes[1], _out_prepend_T_8)
node _out_T_134 = or(out_prepend_8, UInt<16>(0h0))
node _out_T_135 = bits(_out_T_134, 15, 0)
node _out_rimask_T_12 = bits(out_frontMask, 23, 16)
node out_rimask_12 = orr(_out_rimask_T_12)
node _out_wimask_T_12 = bits(out_frontMask, 23, 16)
node out_wimask_12 = andr(_out_wimask_T_12)
node _out_romask_T_12 = bits(out_backMask, 23, 16)
node out_romask_12 = orr(_out_romask_T_12)
node _out_womask_T_12 = bits(out_backMask, 23, 16)
node out_womask_12 = andr(_out_womask_T_12)
node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12)
node out_f_roready_12 = and(out_roready[12], out_romask_12)
node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12)
node out_f_woready_12 = and(out_woready[12], out_womask_12)
node _out_T_136 = bits(out_front.bits.data, 23, 16)
connect valids[2], out_f_woready_12
when out_f_woready_12 :
connect newBytes[2], _out_T_136
node _out_T_137 = and(out_f_rivalid_12, UInt<1>(0h1))
node _out_T_138 = and(UInt<1>(0h1), out_f_roready_12)
node _out_T_139 = and(out_f_wivalid_12, UInt<1>(0h1))
node _out_T_140 = and(UInt<1>(0h1), out_f_woready_12)
node _out_T_141 = eq(out_rimask_12, UInt<1>(0h0))
node _out_T_142 = eq(out_wimask_12, UInt<1>(0h0))
node _out_T_143 = eq(out_romask_12, UInt<1>(0h0))
node _out_T_144 = eq(out_womask_12, UInt<1>(0h0))
node _out_prepend_T_9 = or(_out_T_135, UInt<16>(0h0))
node out_prepend_9 = cat(oldBytes[2], _out_prepend_T_9)
node _out_T_145 = or(out_prepend_9, UInt<24>(0h0))
node _out_T_146 = bits(_out_T_145, 23, 0)
node _out_rimask_T_13 = bits(out_frontMask, 31, 24)
node out_rimask_13 = orr(_out_rimask_T_13)
node _out_wimask_T_13 = bits(out_frontMask, 31, 24)
node out_wimask_13 = andr(_out_wimask_T_13)
node _out_romask_T_13 = bits(out_backMask, 31, 24)
node out_romask_13 = orr(_out_romask_T_13)
node _out_womask_T_13 = bits(out_backMask, 31, 24)
node out_womask_13 = andr(_out_womask_T_13)
node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13)
node out_f_roready_13 = and(out_roready[13], out_romask_13)
node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13)
node out_f_woready_13 = and(out_woready[13], out_womask_13)
node _out_T_147 = bits(out_front.bits.data, 31, 24)
connect valids[3], out_f_woready_13
when out_f_woready_13 :
connect newBytes[3], _out_T_147
node _out_T_148 = and(out_f_rivalid_13, UInt<1>(0h1))
node _out_T_149 = and(UInt<1>(0h1), out_f_roready_13)
node _out_T_150 = and(out_f_wivalid_13, UInt<1>(0h1))
node _out_T_151 = and(UInt<1>(0h1), out_f_woready_13)
node _out_T_152 = eq(out_rimask_13, UInt<1>(0h0))
node _out_T_153 = eq(out_wimask_13, UInt<1>(0h0))
node _out_T_154 = eq(out_romask_13, UInt<1>(0h0))
node _out_T_155 = eq(out_womask_13, UInt<1>(0h0))
node _out_prepend_T_10 = or(_out_T_146, UInt<24>(0h0))
node out_prepend_10 = cat(oldBytes[3], _out_prepend_T_10)
node _out_T_156 = or(out_prepend_10, UInt<32>(0h0))
node _out_T_157 = bits(_out_T_156, 31, 0)
node _out_rimask_T_14 = bits(out_frontMask, 39, 32)
node out_rimask_14 = orr(_out_rimask_T_14)
node _out_wimask_T_14 = bits(out_frontMask, 39, 32)
node out_wimask_14 = andr(_out_wimask_T_14)
node _out_romask_T_14 = bits(out_backMask, 39, 32)
node out_romask_14 = orr(_out_romask_T_14)
node _out_womask_T_14 = bits(out_backMask, 39, 32)
node out_womask_14 = andr(_out_womask_T_14)
node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14)
node out_f_roready_14 = and(out_roready[14], out_romask_14)
node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14)
node out_f_woready_14 = and(out_woready[14], out_womask_14)
node _out_T_158 = bits(out_front.bits.data, 39, 32)
connect valids[4], out_f_woready_14
when out_f_woready_14 :
connect newBytes[4], _out_T_158
node _out_T_159 = and(out_f_rivalid_14, UInt<1>(0h1))
node _out_T_160 = and(UInt<1>(0h1), out_f_roready_14)
node _out_T_161 = and(out_f_wivalid_14, UInt<1>(0h1))
node _out_T_162 = and(UInt<1>(0h1), out_f_woready_14)
node _out_T_163 = eq(out_rimask_14, UInt<1>(0h0))
node _out_T_164 = eq(out_wimask_14, UInt<1>(0h0))
node _out_T_165 = eq(out_romask_14, UInt<1>(0h0))
node _out_T_166 = eq(out_womask_14, UInt<1>(0h0))
node _out_prepend_T_11 = or(_out_T_157, UInt<32>(0h0))
node out_prepend_11 = cat(oldBytes[4], _out_prepend_T_11)
node _out_T_167 = or(out_prepend_11, UInt<40>(0h0))
node _out_T_168 = bits(_out_T_167, 39, 0)
node _out_rimask_T_15 = bits(out_frontMask, 47, 40)
node out_rimask_15 = orr(_out_rimask_T_15)
node _out_wimask_T_15 = bits(out_frontMask, 47, 40)
node out_wimask_15 = andr(_out_wimask_T_15)
node _out_romask_T_15 = bits(out_backMask, 47, 40)
node out_romask_15 = orr(_out_romask_T_15)
node _out_womask_T_15 = bits(out_backMask, 47, 40)
node out_womask_15 = andr(_out_womask_T_15)
node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15)
node out_f_roready_15 = and(out_roready[15], out_romask_15)
node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15)
node out_f_woready_15 = and(out_woready[15], out_womask_15)
node _out_T_169 = bits(out_front.bits.data, 47, 40)
connect valids[5], out_f_woready_15
when out_f_woready_15 :
connect newBytes[5], _out_T_169
node _out_T_170 = and(out_f_rivalid_15, UInt<1>(0h1))
node _out_T_171 = and(UInt<1>(0h1), out_f_roready_15)
node _out_T_172 = and(out_f_wivalid_15, UInt<1>(0h1))
node _out_T_173 = and(UInt<1>(0h1), out_f_woready_15)
node _out_T_174 = eq(out_rimask_15, UInt<1>(0h0))
node _out_T_175 = eq(out_wimask_15, UInt<1>(0h0))
node _out_T_176 = eq(out_romask_15, UInt<1>(0h0))
node _out_T_177 = eq(out_womask_15, UInt<1>(0h0))
node _out_prepend_T_12 = or(_out_T_168, UInt<40>(0h0))
node out_prepend_12 = cat(oldBytes[5], _out_prepend_T_12)
node _out_T_178 = or(out_prepend_12, UInt<48>(0h0))
node _out_T_179 = bits(_out_T_178, 47, 0)
node _out_rimask_T_16 = bits(out_frontMask, 55, 48)
node out_rimask_16 = orr(_out_rimask_T_16)
node _out_wimask_T_16 = bits(out_frontMask, 55, 48)
node out_wimask_16 = andr(_out_wimask_T_16)
node _out_romask_T_16 = bits(out_backMask, 55, 48)
node out_romask_16 = orr(_out_romask_T_16)
node _out_womask_T_16 = bits(out_backMask, 55, 48)
node out_womask_16 = andr(_out_womask_T_16)
node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16)
node out_f_roready_16 = and(out_roready[16], out_romask_16)
node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16)
node out_f_woready_16 = and(out_woready[16], out_womask_16)
node _out_T_180 = bits(out_front.bits.data, 55, 48)
connect valids[6], out_f_woready_16
when out_f_woready_16 :
connect newBytes[6], _out_T_180
node _out_T_181 = and(out_f_rivalid_16, UInt<1>(0h1))
node _out_T_182 = and(UInt<1>(0h1), out_f_roready_16)
node _out_T_183 = and(out_f_wivalid_16, UInt<1>(0h1))
node _out_T_184 = and(UInt<1>(0h1), out_f_woready_16)
node _out_T_185 = eq(out_rimask_16, UInt<1>(0h0))
node _out_T_186 = eq(out_wimask_16, UInt<1>(0h0))
node _out_T_187 = eq(out_romask_16, UInt<1>(0h0))
node _out_T_188 = eq(out_womask_16, UInt<1>(0h0))
node _out_prepend_T_13 = or(_out_T_179, UInt<48>(0h0))
node out_prepend_13 = cat(oldBytes[6], _out_prepend_T_13)
node _out_T_189 = or(out_prepend_13, UInt<56>(0h0))
node _out_T_190 = bits(_out_T_189, 55, 0)
node _out_rimask_T_17 = bits(out_frontMask, 63, 56)
node out_rimask_17 = orr(_out_rimask_T_17)
node _out_wimask_T_17 = bits(out_frontMask, 63, 56)
node out_wimask_17 = andr(_out_wimask_T_17)
node _out_romask_T_17 = bits(out_backMask, 63, 56)
node out_romask_17 = orr(_out_romask_T_17)
node _out_womask_T_17 = bits(out_backMask, 63, 56)
node out_womask_17 = andr(_out_womask_T_17)
node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17)
node out_f_roready_17 = and(out_roready[17], out_romask_17)
node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17)
node out_f_woready_17 = and(out_woready[17], out_womask_17)
node _out_T_191 = bits(out_front.bits.data, 63, 56)
connect valids[7], out_f_woready_17
when out_f_woready_17 :
connect newBytes[7], _out_T_191
node _out_T_192 = and(out_f_rivalid_17, UInt<1>(0h1))
node _out_T_193 = and(UInt<1>(0h1), out_f_roready_17)
node _out_T_194 = and(out_f_wivalid_17, UInt<1>(0h1))
node _out_T_195 = and(UInt<1>(0h1), out_f_woready_17)
node _out_T_196 = eq(out_rimask_17, UInt<1>(0h0))
node _out_T_197 = eq(out_wimask_17, UInt<1>(0h0))
node _out_T_198 = eq(out_romask_17, UInt<1>(0h0))
node _out_T_199 = eq(out_womask_17, UInt<1>(0h0))
node _out_prepend_T_14 = or(_out_T_190, UInt<56>(0h0))
node out_prepend_14 = cat(oldBytes[7], _out_prepend_T_14)
node _out_T_200 = or(out_prepend_14, UInt<64>(0h0))
node _out_T_201 = bits(_out_T_200, 63, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9)
node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10)
node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11)
node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12)
node out_iindex = cat(_out_iindex_T_12, _out_iindex_T_11)
node _out_oindex_T = bits(out_front.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8)
node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9)
node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10)
node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11)
node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12)
node out_oindex = cat(_out_oindex_T_12, _out_oindex_T_11)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[17], _out_rifireMux_T_7
connect out_rivalid[16], _out_rifireMux_T_7
connect out_rivalid[15], _out_rifireMux_T_7
connect out_rivalid[14], _out_rifireMux_T_7
connect out_rivalid[13], _out_rifireMux_T_7
connect out_rivalid[12], _out_rifireMux_T_7
connect out_rivalid[11], _out_rifireMux_T_7
connect out_rivalid[10], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[9], _out_rifireMux_T_11
connect out_rivalid[8], _out_rifireMux_T_11
connect out_rivalid[7], _out_rifireMux_T_11
connect out_rivalid[6], _out_rifireMux_T_11
connect out_rivalid[5], _out_rifireMux_T_11
connect out_rivalid[4], _out_rifireMux_T_11
connect out_rivalid[3], _out_rifireMux_T_11
connect out_rivalid[2], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1))
connect out_rifireMux_out_3, UInt<1>(0h1)
node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4))
wire _out_rifireMux_WIRE : UInt<1>[4]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[17], _out_wifireMux_T_8
connect out_wivalid[16], _out_wifireMux_T_8
connect out_wivalid[15], _out_wifireMux_T_8
connect out_wivalid[14], _out_wifireMux_T_8
connect out_wivalid[13], _out_wifireMux_T_8
connect out_wivalid[12], _out_wifireMux_T_8
connect out_wivalid[11], _out_wifireMux_T_8
connect out_wivalid[10], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[9], _out_wifireMux_T_12
connect out_wivalid[8], _out_wifireMux_T_12
connect out_wivalid[7], _out_wifireMux_T_12
connect out_wivalid[6], _out_wifireMux_T_12
connect out_wivalid[5], _out_wifireMux_T_12
connect out_wivalid[4], _out_wifireMux_T_12
connect out_wivalid[3], _out_wifireMux_T_12
connect out_wivalid[2], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1))
connect out_wifireMux_out_3, UInt<1>(0h1)
node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4))
wire _out_wifireMux_WIRE : UInt<1>[4]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[17], _out_rofireMux_T_7
connect out_roready[16], _out_rofireMux_T_7
connect out_roready[15], _out_rofireMux_T_7
connect out_roready[14], _out_rofireMux_T_7
connect out_roready[13], _out_rofireMux_T_7
connect out_roready[12], _out_rofireMux_T_7
connect out_roready[11], _out_rofireMux_T_7
connect out_roready[10], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[9], _out_rofireMux_T_11
connect out_roready[8], _out_rofireMux_T_11
connect out_roready[7], _out_rofireMux_T_11
connect out_roready[6], _out_rofireMux_T_11
connect out_roready[5], _out_rofireMux_T_11
connect out_roready[4], _out_rofireMux_T_11
connect out_roready[3], _out_rofireMux_T_11
connect out_roready[2], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1))
connect out_rofireMux_out_3, UInt<1>(0h1)
node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4))
wire _out_rofireMux_WIRE : UInt<1>[4]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[17], _out_wofireMux_T_8
connect out_woready[16], _out_wofireMux_T_8
connect out_woready[15], _out_wofireMux_T_8
connect out_woready[14], _out_wofireMux_T_8
connect out_woready[13], _out_wofireMux_T_8
connect out_woready[12], _out_wofireMux_T_8
connect out_woready[11], _out_wofireMux_T_8
connect out_woready[10], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[9], _out_wofireMux_T_12
connect out_woready[8], _out_wofireMux_T_12
connect out_woready[7], _out_wofireMux_T_12
connect out_woready[6], _out_wofireMux_T_12
connect out_woready[5], _out_wofireMux_T_12
connect out_woready[4], _out_wofireMux_T_12
connect out_woready[3], _out_wofireMux_T_12
connect out_woready[2], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1))
connect out_wofireMux_out_3, UInt<1>(0h1)
node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4))
wire _out_wofireMux_WIRE : UInt<1>[4]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE : UInt<1>[4]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_5
connect _out_out_bits_data_WIRE[2], _out_T_3
connect _out_out_bits_data_WIRE[3], UInt<1>(0h1)
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE_1 : UInt<64>[4]
connect _out_out_bits_data_WIRE_1[0], _out_T_25
connect _out_out_bits_data_WIRE_1[1], _out_T_201
connect _out_out_bits_data_WIRE_1[2], _out_T_113
connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0)
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, nodeIn.a.valid
connect nodeIn.a.ready, in.ready
connect nodeIn.d.valid, out.valid
connect out.ready, nodeIn.d.ready
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate nodeIn_d_bits_d.data
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
connect nodeIn.d.bits.data, out.bits.data
node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module CLINT( // @[CLINT.scala:65:9]
input clock, // @[CLINT.scala:65:9]
input reset, // @[CLINT.scala:65:9]
output auto_int_out_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_1, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_rtcTick // @[CLINT.scala:69:16]
);
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_17; // @[RegisterRouter.scala:87:24]
reg [63:0] time_0; // @[CLINT.scala:73:23]
reg [63:0] pad; // @[CLINT.scala:77:41]
reg ipi_0; // @[CLINT.scala:78:41]
wire in_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
wire _out_T_5 = auto_in_a_bits_address[13:3] == 11'h0; // @[RegisterRouter.scala:75:19, :87:24]
wire valids_1_0 = out_woready_9 & auto_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire valids_1_1 = out_woready_9 & auto_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire valids_1_2 = out_woready_9 & auto_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire valids_1_3 = out_woready_9 & auto_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire valids_1_4 = out_woready_9 & auto_in_a_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire valids_1_5 = out_woready_9 & auto_in_a_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire valids_1_6 = out_woready_9 & auto_in_a_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire valids_1_7 = out_woready_9 & auto_in_a_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire valids_0 = out_woready_17 & auto_in_a_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire valids_1 = out_woready_17 & auto_in_a_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire valids_2 = out_woready_17 & auto_in_a_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire valids_3 = out_woready_17 & auto_in_a_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire valids_4 = out_woready_17 & auto_in_a_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire valids_5 = out_woready_17 & auto_in_a_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire valids_6 = out_woready_17 & auto_in_a_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire valids_7 = out_woready_17 & auto_in_a_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24]
assign out_woready_17 = _out_wofireMux_T_2 & auto_in_a_bits_address[15:14] == 2'h1 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_2 & auto_in_a_bits_address[15:14] == 2'h2 & (&(auto_in_a_bits_address[13:3])); // @[RegisterRouter.scala:75:19, :87:24]
wire [3:0] _GEN = {{1'h1}, {&(auto_in_a_bits_address[13:3])}, {_out_T_5}, {_out_T_5}}; // @[MuxLiteral.scala:49:10]
wire [3:0][63:0] _GEN_0 = {{64'h0}, {time_0}, {pad}, {{63'h0, ipi_0}}}; // @[MuxLiteral.scala:49:{10,48}]
wire [2:0] nodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19]
always @(posedge clock) begin // @[CLINT.scala:65:9]
if (reset) begin // @[CLINT.scala:65:9]
time_0 <= 64'h0; // @[CLINT.scala:73:23]
ipi_0 <= 1'h0; // @[CLINT.scala:78:41]
end
else begin // @[CLINT.scala:65:9]
if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegisterRouter.scala:87:24]
time_0 <= {valids_1_7 ? auto_in_a_bits_data[63:56] : time_0[63:56], valids_1_6 ? auto_in_a_bits_data[55:48] : time_0[55:48], valids_1_5 ? auto_in_a_bits_data[47:40] : time_0[47:40], valids_1_4 ? auto_in_a_bits_data[39:32] : time_0[39:32], valids_1_3 ? auto_in_a_bits_data[31:24] : time_0[31:24], valids_1_2 ? auto_in_a_bits_data[23:16] : time_0[23:16], valids_1_1 ? auto_in_a_bits_data[15:8] : time_0[15:8], valids_1_0 ? auto_in_a_bits_data[7:0] : time_0[7:0]}; // @[RegisterRouter.scala:87:24]
else if (io_rtcTick) // @[CLINT.scala:69:16]
time_0 <= time_0 + 64'h1; // @[CLINT.scala:73:23, :74:38]
if (_out_wofireMux_T_2 & auto_in_a_bits_address[15:14] == 2'h0 & _out_T_5 & auto_in_a_bits_mask[0]) // @[RegisterRouter.scala:87:24]
ipi_0 <= auto_in_a_bits_data[0]; // @[RegisterRouter.scala:87:24]
end
if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegisterRouter.scala:87:24]
pad <= {valids_7 ? auto_in_a_bits_data[63:56] : pad[63:56], valids_6 ? auto_in_a_bits_data[55:48] : pad[55:48], valids_5 ? auto_in_a_bits_data[47:40] : pad[47:40], valids_4 ? auto_in_a_bits_data[39:32] : pad[39:32], valids_3 ? auto_in_a_bits_data[31:24] : pad[31:24], valids_2 ? auto_in_a_bits_data[23:16] : pad[23:16], valids_1 ? auto_in_a_bits_data[15:8] : pad[15:8], valids_0 ? auto_in_a_bits_data[7:0] : pad[7:0]}; // @[RegisterRouter.scala:87:24]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_9 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_9( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_in_i2_o1_a32d64s7k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_16
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_17
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 5, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<7>(0h40))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<1>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<1>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<7>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<7>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<7>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<7>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<7>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<6>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 5, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 6)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<6>(0h3f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<7>(0h40))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<6>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 5, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 6)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<6>(0h3f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<7>(0h40))
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<7>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<7>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
extmodule plusarg_reader_36 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_37 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_cbus_in_i2_o1_a32d64s7k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_22 = 3'h0; // @[Mux.scala:30:73]
wire [3:0] auto_anon_in_1_a_bits_size = 4'h2; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = 4'h2; // @[MixedNode.scala:551:17]
wire [3:0] in_1_a_bits_size = 4'h2; // @[Xbar.scala:159:18]
wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h2; // @[Xbar.scala:352:24]
wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:46:9]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsAI_opdata_T_1 = 1'h0; // @[Edges.scala:92:37]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire [7:0] auto_anon_in_1_a_bits_mask = 8'hF; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17]
wire [7:0] in_1_a_bits_mask = 8'hF; // @[Xbar.scala:159:18]
wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hF; // @[Xbar.scala:352:24]
wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire beatsAI_opdata_1 = 1'h1; // @[Edges.scala:92:28]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [8:0] beatsAI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [6:0] _addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _addressC_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _addressC_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] _requestBOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _requestBOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] _beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _beatsCI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _beatsCI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] _portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] portsBIO_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] _portsCOI_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _portsCOI_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] portsCOI_filtered_1_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [6:0] in_1_a_bits_source = 7'h40; // @[Xbar.scala:159:18]
wire [6:0] _in_1_a_bits_source_T = 7'h40; // @[Xbar.scala:166:55]
wire [6:0] portsAOI_filtered_1_0_bits_source = 7'h40; // @[Xbar.scala:352:24]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_5 = 12'h3; // @[package.scala:243:46]
wire [11:0] _beatsAI_decode_T_4 = 12'hFFC; // @[package.scala:243:76]
wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC; // @[package.scala:243:71]
wire [5:0] requestBOI_uncommonBits = 6'h0; // @[Parameters.scala:52:56]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [5:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [6:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[5:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [6:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [5:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[6]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire requestDOI_0_1 = out_0_d_bits_source == 7'h40; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module CharacterCountExample :
input clock : Clock
input reset : Reset
output auto : { atl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0], ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}[0], fpu_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
wire atlNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate atlNodeOut.d.bits.corrupt
invalidate atlNodeOut.d.bits.data
invalidate atlNodeOut.d.bits.denied
invalidate atlNodeOut.d.bits.sink
invalidate atlNodeOut.d.bits.source
invalidate atlNodeOut.d.bits.size
invalidate atlNodeOut.d.bits.param
invalidate atlNodeOut.d.bits.opcode
invalidate atlNodeOut.d.valid
invalidate atlNodeOut.d.ready
invalidate atlNodeOut.a.bits.corrupt
invalidate atlNodeOut.a.bits.data
invalidate atlNodeOut.a.bits.mask
invalidate atlNodeOut.a.bits.address
invalidate atlNodeOut.a.bits.source
invalidate atlNodeOut.a.bits.size
invalidate atlNodeOut.a.bits.param
invalidate atlNodeOut.a.bits.opcode
invalidate atlNodeOut.a.valid
invalidate atlNodeOut.a.ready
connect auto.atl_out, atlNodeOut
invalidate io.fpu_resp.bits.exc
invalidate io.fpu_resp.bits.data
invalidate io.fpu_resp.valid
invalidate io.fpu_resp.ready
invalidate io.fpu_req.bits.in3
invalidate io.fpu_req.bits.in2
invalidate io.fpu_req.bits.in1
invalidate io.fpu_req.bits.fmt
invalidate io.fpu_req.bits.typ
invalidate io.fpu_req.bits.fmaCmd
invalidate io.fpu_req.bits.rm
invalidate io.fpu_req.bits.vec
invalidate io.fpu_req.bits.wflags
invalidate io.fpu_req.bits.sqrt
invalidate io.fpu_req.bits.div
invalidate io.fpu_req.bits.fma
invalidate io.fpu_req.bits.fastpipe
invalidate io.fpu_req.bits.toint
invalidate io.fpu_req.bits.fromint
invalidate io.fpu_req.bits.typeTagOut
invalidate io.fpu_req.bits.typeTagIn
invalidate io.fpu_req.bits.swap23
invalidate io.fpu_req.bits.swap12
invalidate io.fpu_req.bits.ren3
invalidate io.fpu_req.bits.ren2
invalidate io.fpu_req.bits.ren1
invalidate io.fpu_req.bits.wen
invalidate io.fpu_req.bits.ldst
invalidate io.fpu_req.valid
invalidate io.fpu_req.ready
invalidate io.exception
invalidate io.interrupt
invalidate io.busy
invalidate io.mem.clock_enabled
invalidate io.mem.keep_clock_enabled
invalidate io.mem.perf.storeBufferEmptyAfterStore
invalidate io.mem.perf.storeBufferEmptyAfterLoad
invalidate io.mem.perf.canAcceptLoadThenLoad
invalidate io.mem.perf.canAcceptStoreThenRMW
invalidate io.mem.perf.canAcceptStoreThenLoad
invalidate io.mem.perf.blocked
invalidate io.mem.perf.tlbMiss
invalidate io.mem.perf.grant
invalidate io.mem.perf.release
invalidate io.mem.perf.acquire
invalidate io.mem.store_pending
invalidate io.mem.ordered
invalidate io.mem.s2_gpa_is_pte
invalidate io.mem.s2_gpa
invalidate io.mem.s2_xcpt.ae.st
invalidate io.mem.s2_xcpt.ae.ld
invalidate io.mem.s2_xcpt.gf.st
invalidate io.mem.s2_xcpt.gf.ld
invalidate io.mem.s2_xcpt.pf.st
invalidate io.mem.s2_xcpt.pf.ld
invalidate io.mem.s2_xcpt.ma.st
invalidate io.mem.s2_xcpt.ma.ld
invalidate io.mem.replay_next
invalidate io.mem.resp.bits.store_data
invalidate io.mem.resp.bits.data_raw
invalidate io.mem.resp.bits.data_word_bypass
invalidate io.mem.resp.bits.has_data
invalidate io.mem.resp.bits.replay
invalidate io.mem.resp.bits.mask
invalidate io.mem.resp.bits.data
invalidate io.mem.resp.bits.dv
invalidate io.mem.resp.bits.dprv
invalidate io.mem.resp.bits.signed
invalidate io.mem.resp.bits.size
invalidate io.mem.resp.bits.cmd
invalidate io.mem.resp.bits.tag
invalidate io.mem.resp.bits.addr
invalidate io.mem.resp.valid
invalidate io.mem.s2_paddr
invalidate io.mem.s2_uncached
invalidate io.mem.s2_kill
invalidate io.mem.s2_nack_cause_raw
invalidate io.mem.s2_nack
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
invalidate io.mem.s1_kill
invalidate io.mem.req.bits.mask
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_resp
invalidate io.mem.req.bits.phys
invalidate io.mem.req.bits.dv
invalidate io.mem.req.bits.dprv
invalidate io.mem.req.bits.signed
invalidate io.mem.req.bits.size
invalidate io.mem.req.bits.cmd
invalidate io.mem.req.bits.tag
invalidate io.mem.req.bits.addr
invalidate io.mem.req.valid
invalidate io.mem.req.ready
invalidate io.resp.bits.data
invalidate io.resp.bits.rd
invalidate io.resp.valid
invalidate io.resp.ready
invalidate io.cmd.bits.status.uie
invalidate io.cmd.bits.status.sie
invalidate io.cmd.bits.status.hie
invalidate io.cmd.bits.status.mie
invalidate io.cmd.bits.status.upie
invalidate io.cmd.bits.status.spie
invalidate io.cmd.bits.status.ube
invalidate io.cmd.bits.status.mpie
invalidate io.cmd.bits.status.spp
invalidate io.cmd.bits.status.vs
invalidate io.cmd.bits.status.mpp
invalidate io.cmd.bits.status.fs
invalidate io.cmd.bits.status.xs
invalidate io.cmd.bits.status.mprv
invalidate io.cmd.bits.status.sum
invalidate io.cmd.bits.status.mxr
invalidate io.cmd.bits.status.tvm
invalidate io.cmd.bits.status.tw
invalidate io.cmd.bits.status.tsr
invalidate io.cmd.bits.status.zero1
invalidate io.cmd.bits.status.sd_rv32
invalidate io.cmd.bits.status.uxl
invalidate io.cmd.bits.status.sxl
invalidate io.cmd.bits.status.sbe
invalidate io.cmd.bits.status.mbe
invalidate io.cmd.bits.status.gva
invalidate io.cmd.bits.status.mpv
invalidate io.cmd.bits.status.zero2
invalidate io.cmd.bits.status.sd
invalidate io.cmd.bits.status.v
invalidate io.cmd.bits.status.prv
invalidate io.cmd.bits.status.dv
invalidate io.cmd.bits.status.dprv
invalidate io.cmd.bits.status.isa
invalidate io.cmd.bits.status.wfi
invalidate io.cmd.bits.status.cease
invalidate io.cmd.bits.status.debug
invalidate io.cmd.bits.rs2
invalidate io.cmd.bits.rs1
invalidate io.cmd.bits.inst.opcode
invalidate io.cmd.bits.inst.rd
invalidate io.cmd.bits.inst.xs2
invalidate io.cmd.bits.inst.xs1
invalidate io.cmd.bits.inst.xd
invalidate io.cmd.bits.inst.rs1
invalidate io.cmd.bits.inst.rs2
invalidate io.cmd.bits.inst.funct
invalidate io.cmd.valid
invalidate io.cmd.ready
reg needle : UInt<8>, clock
reg addr : UInt<40>, clock
reg count : UInt<64>, clock
reg resp_rd : UInt<5>, clock
node addr_block = bits(addr, 39, 6)
node offset = bits(addr, 5, 0)
node _next_addr_T = add(addr_block, UInt<1>(0h1))
node _next_addr_T_1 = tail(_next_addr_T, 1)
node next_addr = dshl(_next_addr_T_1, UInt<3>(0h6))
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
reg recv_data : UInt<64>, clock
regreset recv_beat : UInt<4>, clock, reset, UInt<4>(0h0)
node _data_bytes_T = bits(recv_data, 7, 0)
node _data_bytes_T_1 = bits(recv_data, 15, 8)
node _data_bytes_T_2 = bits(recv_data, 23, 16)
node _data_bytes_T_3 = bits(recv_data, 31, 24)
node _data_bytes_T_4 = bits(recv_data, 39, 32)
node _data_bytes_T_5 = bits(recv_data, 47, 40)
node _data_bytes_T_6 = bits(recv_data, 55, 48)
node _data_bytes_T_7 = bits(recv_data, 63, 56)
wire data_bytes : UInt<8>[8]
connect data_bytes[0], _data_bytes_T
connect data_bytes[1], _data_bytes_T_1
connect data_bytes[2], _data_bytes_T_2
connect data_bytes[3], _data_bytes_T_3
connect data_bytes[4], _data_bytes_T_4
connect data_bytes[5], _data_bytes_T_5
connect data_bytes[6], _data_bytes_T_6
connect data_bytes[7], _data_bytes_T_7
node zero_match_0 = eq(data_bytes[0], UInt<1>(0h0))
node zero_match_1 = eq(data_bytes[1], UInt<1>(0h0))
node zero_match_2 = eq(data_bytes[2], UInt<1>(0h0))
node zero_match_3 = eq(data_bytes[3], UInt<1>(0h0))
node zero_match_4 = eq(data_bytes[4], UInt<1>(0h0))
node zero_match_5 = eq(data_bytes[5], UInt<1>(0h0))
node zero_match_6 = eq(data_bytes[6], UInt<1>(0h0))
node zero_match_7 = eq(data_bytes[7], UInt<1>(0h0))
node needle_match_0 = eq(data_bytes[0], needle)
node needle_match_1 = eq(data_bytes[1], needle)
node needle_match_2 = eq(data_bytes[2], needle)
node needle_match_3 = eq(data_bytes[3], needle)
node needle_match_4 = eq(data_bytes[4], needle)
node needle_match_5 = eq(data_bytes[5], needle)
node needle_match_6 = eq(data_bytes[6], needle)
node needle_match_7 = eq(data_bytes[7], needle)
node _first_zero_T = mux(zero_match_6, UInt<3>(0h6), UInt<3>(0h7))
node _first_zero_T_1 = mux(zero_match_5, UInt<3>(0h5), _first_zero_T)
node _first_zero_T_2 = mux(zero_match_4, UInt<3>(0h4), _first_zero_T_1)
node _first_zero_T_3 = mux(zero_match_3, UInt<2>(0h3), _first_zero_T_2)
node _first_zero_T_4 = mux(zero_match_2, UInt<2>(0h2), _first_zero_T_3)
node _first_zero_T_5 = mux(zero_match_1, UInt<1>(0h1), _first_zero_T_4)
node first_zero = mux(zero_match_0, UInt<1>(0h0), _first_zero_T_5)
node _chars_found_idx_T = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_1 = tail(_chars_found_idx_T, 1)
node chars_found_idx = cat(_chars_found_idx_T_1, UInt<3>(0h0))
node _chars_found_T = geq(chars_found_idx, offset)
node _chars_found_T_1 = and(needle_match_0, _chars_found_T)
node _chars_found_T_2 = leq(UInt<1>(0h0), first_zero)
node _chars_found_T_3 = and(_chars_found_T_1, _chars_found_T_2)
node _chars_found_idx_T_2 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_3 = tail(_chars_found_idx_T_2, 1)
node chars_found_idx_1 = cat(_chars_found_idx_T_3, UInt<3>(0h1))
node _chars_found_T_4 = geq(chars_found_idx_1, offset)
node _chars_found_T_5 = and(needle_match_1, _chars_found_T_4)
node _chars_found_T_6 = leq(UInt<1>(0h1), first_zero)
node _chars_found_T_7 = and(_chars_found_T_5, _chars_found_T_6)
node _chars_found_idx_T_4 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_5 = tail(_chars_found_idx_T_4, 1)
node chars_found_idx_2 = cat(_chars_found_idx_T_5, UInt<3>(0h2))
node _chars_found_T_8 = geq(chars_found_idx_2, offset)
node _chars_found_T_9 = and(needle_match_2, _chars_found_T_8)
node _chars_found_T_10 = leq(UInt<2>(0h2), first_zero)
node _chars_found_T_11 = and(_chars_found_T_9, _chars_found_T_10)
node _chars_found_idx_T_6 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_7 = tail(_chars_found_idx_T_6, 1)
node chars_found_idx_3 = cat(_chars_found_idx_T_7, UInt<3>(0h3))
node _chars_found_T_12 = geq(chars_found_idx_3, offset)
node _chars_found_T_13 = and(needle_match_3, _chars_found_T_12)
node _chars_found_T_14 = leq(UInt<2>(0h3), first_zero)
node _chars_found_T_15 = and(_chars_found_T_13, _chars_found_T_14)
node _chars_found_idx_T_8 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_9 = tail(_chars_found_idx_T_8, 1)
node chars_found_idx_4 = cat(_chars_found_idx_T_9, UInt<3>(0h4))
node _chars_found_T_16 = geq(chars_found_idx_4, offset)
node _chars_found_T_17 = and(needle_match_4, _chars_found_T_16)
node _chars_found_T_18 = leq(UInt<3>(0h4), first_zero)
node _chars_found_T_19 = and(_chars_found_T_17, _chars_found_T_18)
node _chars_found_idx_T_10 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_11 = tail(_chars_found_idx_T_10, 1)
node chars_found_idx_5 = cat(_chars_found_idx_T_11, UInt<3>(0h5))
node _chars_found_T_20 = geq(chars_found_idx_5, offset)
node _chars_found_T_21 = and(needle_match_5, _chars_found_T_20)
node _chars_found_T_22 = leq(UInt<3>(0h5), first_zero)
node _chars_found_T_23 = and(_chars_found_T_21, _chars_found_T_22)
node _chars_found_idx_T_12 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_13 = tail(_chars_found_idx_T_12, 1)
node chars_found_idx_6 = cat(_chars_found_idx_T_13, UInt<3>(0h6))
node _chars_found_T_24 = geq(chars_found_idx_6, offset)
node _chars_found_T_25 = and(needle_match_6, _chars_found_T_24)
node _chars_found_T_26 = leq(UInt<3>(0h6), first_zero)
node _chars_found_T_27 = and(_chars_found_T_25, _chars_found_T_26)
node _chars_found_idx_T_14 = sub(recv_beat, UInt<1>(0h1))
node _chars_found_idx_T_15 = tail(_chars_found_idx_T_14, 1)
node chars_found_idx_7 = cat(_chars_found_idx_T_15, UInt<3>(0h7))
node _chars_found_T_28 = geq(chars_found_idx_7, offset)
node _chars_found_T_29 = and(needle_match_7, _chars_found_T_28)
node _chars_found_T_30 = leq(UInt<3>(0h7), first_zero)
node _chars_found_T_31 = and(_chars_found_T_29, _chars_found_T_30)
node _chars_found_T_32 = add(_chars_found_T_3, _chars_found_T_7)
node _chars_found_T_33 = bits(_chars_found_T_32, 1, 0)
node _chars_found_T_34 = add(_chars_found_T_11, _chars_found_T_15)
node _chars_found_T_35 = bits(_chars_found_T_34, 1, 0)
node _chars_found_T_36 = add(_chars_found_T_33, _chars_found_T_35)
node _chars_found_T_37 = bits(_chars_found_T_36, 2, 0)
node _chars_found_T_38 = add(_chars_found_T_19, _chars_found_T_23)
node _chars_found_T_39 = bits(_chars_found_T_38, 1, 0)
node _chars_found_T_40 = add(_chars_found_T_27, _chars_found_T_31)
node _chars_found_T_41 = bits(_chars_found_T_40, 1, 0)
node _chars_found_T_42 = add(_chars_found_T_39, _chars_found_T_41)
node _chars_found_T_43 = bits(_chars_found_T_42, 2, 0)
node _chars_found_T_44 = add(_chars_found_T_37, _chars_found_T_43)
node chars_found = bits(_chars_found_T_44, 3, 0)
node _zero_found_T = or(zero_match_0, zero_match_1)
node _zero_found_T_1 = or(_zero_found_T, zero_match_2)
node _zero_found_T_2 = or(_zero_found_T_1, zero_match_3)
node _zero_found_T_3 = or(_zero_found_T_2, zero_match_4)
node _zero_found_T_4 = or(_zero_found_T_3, zero_match_5)
node _zero_found_T_5 = or(_zero_found_T_4, zero_match_6)
node zero_found = or(_zero_found_T_5, zero_match_7)
reg finished : UInt<1>, clock
node _io_cmd_ready_T = eq(state, UInt<3>(0h0))
connect io.cmd.ready, _io_cmd_ready_T
node _io_resp_valid_T = eq(state, UInt<3>(0h4))
connect io.resp.valid, _io_resp_valid_T
connect io.resp.bits.rd, resp_rd
connect io.resp.bits.data, count
node _atlNodeOut_a_valid_T = eq(state, UInt<3>(0h1))
connect atlNodeOut.a.valid, _atlNodeOut_a_valid_T
node _atlNodeOut_a_bits_T = shl(addr_block, 6)
node _atlNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6))
node _atlNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc))
node _atlNodeOut_a_bits_legal_T_2 = and(_atlNodeOut_a_bits_legal_T, _atlNodeOut_a_bits_legal_T_1)
node _atlNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _atlNodeOut_a_bits_legal_T_2)
node _atlNodeOut_a_bits_legal_T_4 = xor(_atlNodeOut_a_bits_T, UInt<14>(0h3000))
node _atlNodeOut_a_bits_legal_T_5 = cvt(_atlNodeOut_a_bits_legal_T_4)
node _atlNodeOut_a_bits_legal_T_6 = and(_atlNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0hffefb000)))
node _atlNodeOut_a_bits_legal_T_7 = asSInt(_atlNodeOut_a_bits_legal_T_6)
node _atlNodeOut_a_bits_legal_T_8 = eq(_atlNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_9 = and(_atlNodeOut_a_bits_legal_T_3, _atlNodeOut_a_bits_legal_T_8)
node _atlNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6))
node _atlNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6))
node _atlNodeOut_a_bits_legal_T_12 = and(_atlNodeOut_a_bits_legal_T_10, _atlNodeOut_a_bits_legal_T_11)
node _atlNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _atlNodeOut_a_bits_legal_T_12)
node _atlNodeOut_a_bits_legal_T_14 = xor(_atlNodeOut_a_bits_T, UInt<1>(0h0))
node _atlNodeOut_a_bits_legal_T_15 = cvt(_atlNodeOut_a_bits_legal_T_14)
node _atlNodeOut_a_bits_legal_T_16 = and(_atlNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0hffefa000)))
node _atlNodeOut_a_bits_legal_T_17 = asSInt(_atlNodeOut_a_bits_legal_T_16)
node _atlNodeOut_a_bits_legal_T_18 = eq(_atlNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_19 = xor(_atlNodeOut_a_bits_T, UInt<17>(0h10000))
node _atlNodeOut_a_bits_legal_T_20 = cvt(_atlNodeOut_a_bits_legal_T_19)
node _atlNodeOut_a_bits_legal_T_21 = and(_atlNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0hfdefb000)))
node _atlNodeOut_a_bits_legal_T_22 = asSInt(_atlNodeOut_a_bits_legal_T_21)
node _atlNodeOut_a_bits_legal_T_23 = eq(_atlNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_24 = xor(_atlNodeOut_a_bits_T, UInt<17>(0h10000))
node _atlNodeOut_a_bits_legal_T_25 = cvt(_atlNodeOut_a_bits_legal_T_24)
node _atlNodeOut_a_bits_legal_T_26 = and(_atlNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0hffef0000)))
node _atlNodeOut_a_bits_legal_T_27 = asSInt(_atlNodeOut_a_bits_legal_T_26)
node _atlNodeOut_a_bits_legal_T_28 = eq(_atlNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_29 = xor(_atlNodeOut_a_bits_T, UInt<26>(0h2000000))
node _atlNodeOut_a_bits_legal_T_30 = cvt(_atlNodeOut_a_bits_legal_T_29)
node _atlNodeOut_a_bits_legal_T_31 = and(_atlNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0hffef0000)))
node _atlNodeOut_a_bits_legal_T_32 = asSInt(_atlNodeOut_a_bits_legal_T_31)
node _atlNodeOut_a_bits_legal_T_33 = eq(_atlNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_34 = xor(_atlNodeOut_a_bits_T, UInt<28>(0h8000000))
node _atlNodeOut_a_bits_legal_T_35 = cvt(_atlNodeOut_a_bits_legal_T_34)
node _atlNodeOut_a_bits_legal_T_36 = and(_atlNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0hffef0000)))
node _atlNodeOut_a_bits_legal_T_37 = asSInt(_atlNodeOut_a_bits_legal_T_36)
node _atlNodeOut_a_bits_legal_T_38 = eq(_atlNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_39 = xor(_atlNodeOut_a_bits_T, UInt<28>(0hc000000))
node _atlNodeOut_a_bits_legal_T_40 = cvt(_atlNodeOut_a_bits_legal_T_39)
node _atlNodeOut_a_bits_legal_T_41 = and(_atlNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0hfc000000)))
node _atlNodeOut_a_bits_legal_T_42 = asSInt(_atlNodeOut_a_bits_legal_T_41)
node _atlNodeOut_a_bits_legal_T_43 = eq(_atlNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_44 = xor(_atlNodeOut_a_bits_T, UInt<29>(0h10020000))
node _atlNodeOut_a_bits_legal_T_45 = cvt(_atlNodeOut_a_bits_legal_T_44)
node _atlNodeOut_a_bits_legal_T_46 = and(_atlNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0hffefb000)))
node _atlNodeOut_a_bits_legal_T_47 = asSInt(_atlNodeOut_a_bits_legal_T_46)
node _atlNodeOut_a_bits_legal_T_48 = eq(_atlNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_49 = xor(_atlNodeOut_a_bits_T, UInt<32>(0h80000000))
node _atlNodeOut_a_bits_legal_T_50 = cvt(_atlNodeOut_a_bits_legal_T_49)
node _atlNodeOut_a_bits_legal_T_51 = and(_atlNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0hf0000000)))
node _atlNodeOut_a_bits_legal_T_52 = asSInt(_atlNodeOut_a_bits_legal_T_51)
node _atlNodeOut_a_bits_legal_T_53 = eq(_atlNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_54 = or(_atlNodeOut_a_bits_legal_T_18, _atlNodeOut_a_bits_legal_T_23)
node _atlNodeOut_a_bits_legal_T_55 = or(_atlNodeOut_a_bits_legal_T_54, _atlNodeOut_a_bits_legal_T_28)
node _atlNodeOut_a_bits_legal_T_56 = or(_atlNodeOut_a_bits_legal_T_55, _atlNodeOut_a_bits_legal_T_33)
node _atlNodeOut_a_bits_legal_T_57 = or(_atlNodeOut_a_bits_legal_T_56, _atlNodeOut_a_bits_legal_T_38)
node _atlNodeOut_a_bits_legal_T_58 = or(_atlNodeOut_a_bits_legal_T_57, _atlNodeOut_a_bits_legal_T_43)
node _atlNodeOut_a_bits_legal_T_59 = or(_atlNodeOut_a_bits_legal_T_58, _atlNodeOut_a_bits_legal_T_48)
node _atlNodeOut_a_bits_legal_T_60 = or(_atlNodeOut_a_bits_legal_T_59, _atlNodeOut_a_bits_legal_T_53)
node _atlNodeOut_a_bits_legal_T_61 = and(_atlNodeOut_a_bits_legal_T_13, _atlNodeOut_a_bits_legal_T_60)
node _atlNodeOut_a_bits_legal_T_62 = leq(UInt<1>(0h0), UInt<3>(0h6))
node _atlNodeOut_a_bits_legal_T_63 = leq(UInt<3>(0h6), UInt<2>(0h3))
node _atlNodeOut_a_bits_legal_T_64 = and(_atlNodeOut_a_bits_legal_T_62, _atlNodeOut_a_bits_legal_T_63)
node _atlNodeOut_a_bits_legal_T_65 = or(UInt<1>(0h0), _atlNodeOut_a_bits_legal_T_64)
node _atlNodeOut_a_bits_legal_T_66 = xor(_atlNodeOut_a_bits_T, UInt<18>(0h20000))
node _atlNodeOut_a_bits_legal_T_67 = cvt(_atlNodeOut_a_bits_legal_T_66)
node _atlNodeOut_a_bits_legal_T_68 = and(_atlNodeOut_a_bits_legal_T_67, asSInt(UInt<33>(0hffef8000)))
node _atlNodeOut_a_bits_legal_T_69 = asSInt(_atlNodeOut_a_bits_legal_T_68)
node _atlNodeOut_a_bits_legal_T_70 = eq(_atlNodeOut_a_bits_legal_T_69, asSInt(UInt<1>(0h0)))
node _atlNodeOut_a_bits_legal_T_71 = and(_atlNodeOut_a_bits_legal_T_65, _atlNodeOut_a_bits_legal_T_70)
node _atlNodeOut_a_bits_legal_T_72 = or(UInt<1>(0h0), _atlNodeOut_a_bits_legal_T_9)
node _atlNodeOut_a_bits_legal_T_73 = or(_atlNodeOut_a_bits_legal_T_72, _atlNodeOut_a_bits_legal_T_61)
node atlNodeOut_a_bits_legal = or(_atlNodeOut_a_bits_legal_T_73, _atlNodeOut_a_bits_legal_T_71)
wire atlNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atlNodeOut_a_bits_a.opcode, UInt<3>(0h4)
connect atlNodeOut_a_bits_a.param, UInt<1>(0h0)
connect atlNodeOut_a_bits_a.size, UInt<3>(0h6)
connect atlNodeOut_a_bits_a.source, UInt<1>(0h0)
connect atlNodeOut_a_bits_a.address, _atlNodeOut_a_bits_T
node _atlNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node atlNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_atlNodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _atlNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atlNodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _atlNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_atlNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0)
node atlNodeOut_a_bits_a_mask_sizeOH = or(_atlNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atlNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node atlNodeOut_a_bits_a_mask_sub_sub_size = bits(atlNodeOut_a_bits_a_mask_sizeOH, 2, 2)
node atlNodeOut_a_bits_a_mask_sub_sub_bit = bits(_atlNodeOut_a_bits_T, 2, 2)
node atlNodeOut_a_bits_a_mask_sub_sub_nbit = eq(atlNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node atlNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atlNodeOut_a_bits_a_mask_sub_sub_nbit)
node _atlNodeOut_a_bits_a_mask_sub_sub_acc_T = and(atlNodeOut_a_bits_a_mask_sub_sub_size, atlNodeOut_a_bits_a_mask_sub_sub_0_2)
node atlNodeOut_a_bits_a_mask_sub_sub_0_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _atlNodeOut_a_bits_a_mask_sub_sub_acc_T)
node atlNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atlNodeOut_a_bits_a_mask_sub_sub_bit)
node _atlNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(atlNodeOut_a_bits_a_mask_sub_sub_size, atlNodeOut_a_bits_a_mask_sub_sub_1_2)
node atlNodeOut_a_bits_a_mask_sub_sub_1_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _atlNodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node atlNodeOut_a_bits_a_mask_sub_size = bits(atlNodeOut_a_bits_a_mask_sizeOH, 1, 1)
node atlNodeOut_a_bits_a_mask_sub_bit = bits(_atlNodeOut_a_bits_T, 1, 1)
node atlNodeOut_a_bits_a_mask_sub_nbit = eq(atlNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node atlNodeOut_a_bits_a_mask_sub_0_2 = and(atlNodeOut_a_bits_a_mask_sub_sub_0_2, atlNodeOut_a_bits_a_mask_sub_nbit)
node _atlNodeOut_a_bits_a_mask_sub_acc_T = and(atlNodeOut_a_bits_a_mask_sub_size, atlNodeOut_a_bits_a_mask_sub_0_2)
node atlNodeOut_a_bits_a_mask_sub_0_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_0_1, _atlNodeOut_a_bits_a_mask_sub_acc_T)
node atlNodeOut_a_bits_a_mask_sub_1_2 = and(atlNodeOut_a_bits_a_mask_sub_sub_0_2, atlNodeOut_a_bits_a_mask_sub_bit)
node _atlNodeOut_a_bits_a_mask_sub_acc_T_1 = and(atlNodeOut_a_bits_a_mask_sub_size, atlNodeOut_a_bits_a_mask_sub_1_2)
node atlNodeOut_a_bits_a_mask_sub_1_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_0_1, _atlNodeOut_a_bits_a_mask_sub_acc_T_1)
node atlNodeOut_a_bits_a_mask_sub_2_2 = and(atlNodeOut_a_bits_a_mask_sub_sub_1_2, atlNodeOut_a_bits_a_mask_sub_nbit)
node _atlNodeOut_a_bits_a_mask_sub_acc_T_2 = and(atlNodeOut_a_bits_a_mask_sub_size, atlNodeOut_a_bits_a_mask_sub_2_2)
node atlNodeOut_a_bits_a_mask_sub_2_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_1_1, _atlNodeOut_a_bits_a_mask_sub_acc_T_2)
node atlNodeOut_a_bits_a_mask_sub_3_2 = and(atlNodeOut_a_bits_a_mask_sub_sub_1_2, atlNodeOut_a_bits_a_mask_sub_bit)
node _atlNodeOut_a_bits_a_mask_sub_acc_T_3 = and(atlNodeOut_a_bits_a_mask_sub_size, atlNodeOut_a_bits_a_mask_sub_3_2)
node atlNodeOut_a_bits_a_mask_sub_3_1 = or(atlNodeOut_a_bits_a_mask_sub_sub_1_1, _atlNodeOut_a_bits_a_mask_sub_acc_T_3)
node atlNodeOut_a_bits_a_mask_size = bits(atlNodeOut_a_bits_a_mask_sizeOH, 0, 0)
node atlNodeOut_a_bits_a_mask_bit = bits(_atlNodeOut_a_bits_T, 0, 0)
node atlNodeOut_a_bits_a_mask_nbit = eq(atlNodeOut_a_bits_a_mask_bit, UInt<1>(0h0))
node atlNodeOut_a_bits_a_mask_eq = and(atlNodeOut_a_bits_a_mask_sub_0_2, atlNodeOut_a_bits_a_mask_nbit)
node _atlNodeOut_a_bits_a_mask_acc_T = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq)
node atlNodeOut_a_bits_a_mask_acc = or(atlNodeOut_a_bits_a_mask_sub_0_1, _atlNodeOut_a_bits_a_mask_acc_T)
node atlNodeOut_a_bits_a_mask_eq_1 = and(atlNodeOut_a_bits_a_mask_sub_0_2, atlNodeOut_a_bits_a_mask_bit)
node _atlNodeOut_a_bits_a_mask_acc_T_1 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_1)
node atlNodeOut_a_bits_a_mask_acc_1 = or(atlNodeOut_a_bits_a_mask_sub_0_1, _atlNodeOut_a_bits_a_mask_acc_T_1)
node atlNodeOut_a_bits_a_mask_eq_2 = and(atlNodeOut_a_bits_a_mask_sub_1_2, atlNodeOut_a_bits_a_mask_nbit)
node _atlNodeOut_a_bits_a_mask_acc_T_2 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_2)
node atlNodeOut_a_bits_a_mask_acc_2 = or(atlNodeOut_a_bits_a_mask_sub_1_1, _atlNodeOut_a_bits_a_mask_acc_T_2)
node atlNodeOut_a_bits_a_mask_eq_3 = and(atlNodeOut_a_bits_a_mask_sub_1_2, atlNodeOut_a_bits_a_mask_bit)
node _atlNodeOut_a_bits_a_mask_acc_T_3 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_3)
node atlNodeOut_a_bits_a_mask_acc_3 = or(atlNodeOut_a_bits_a_mask_sub_1_1, _atlNodeOut_a_bits_a_mask_acc_T_3)
node atlNodeOut_a_bits_a_mask_eq_4 = and(atlNodeOut_a_bits_a_mask_sub_2_2, atlNodeOut_a_bits_a_mask_nbit)
node _atlNodeOut_a_bits_a_mask_acc_T_4 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_4)
node atlNodeOut_a_bits_a_mask_acc_4 = or(atlNodeOut_a_bits_a_mask_sub_2_1, _atlNodeOut_a_bits_a_mask_acc_T_4)
node atlNodeOut_a_bits_a_mask_eq_5 = and(atlNodeOut_a_bits_a_mask_sub_2_2, atlNodeOut_a_bits_a_mask_bit)
node _atlNodeOut_a_bits_a_mask_acc_T_5 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_5)
node atlNodeOut_a_bits_a_mask_acc_5 = or(atlNodeOut_a_bits_a_mask_sub_2_1, _atlNodeOut_a_bits_a_mask_acc_T_5)
node atlNodeOut_a_bits_a_mask_eq_6 = and(atlNodeOut_a_bits_a_mask_sub_3_2, atlNodeOut_a_bits_a_mask_nbit)
node _atlNodeOut_a_bits_a_mask_acc_T_6 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_6)
node atlNodeOut_a_bits_a_mask_acc_6 = or(atlNodeOut_a_bits_a_mask_sub_3_1, _atlNodeOut_a_bits_a_mask_acc_T_6)
node atlNodeOut_a_bits_a_mask_eq_7 = and(atlNodeOut_a_bits_a_mask_sub_3_2, atlNodeOut_a_bits_a_mask_bit)
node _atlNodeOut_a_bits_a_mask_acc_T_7 = and(atlNodeOut_a_bits_a_mask_size, atlNodeOut_a_bits_a_mask_eq_7)
node atlNodeOut_a_bits_a_mask_acc_7 = or(atlNodeOut_a_bits_a_mask_sub_3_1, _atlNodeOut_a_bits_a_mask_acc_T_7)
node atlNodeOut_a_bits_a_mask_lo_lo = cat(atlNodeOut_a_bits_a_mask_acc_1, atlNodeOut_a_bits_a_mask_acc)
node atlNodeOut_a_bits_a_mask_lo_hi = cat(atlNodeOut_a_bits_a_mask_acc_3, atlNodeOut_a_bits_a_mask_acc_2)
node atlNodeOut_a_bits_a_mask_lo = cat(atlNodeOut_a_bits_a_mask_lo_hi, atlNodeOut_a_bits_a_mask_lo_lo)
node atlNodeOut_a_bits_a_mask_hi_lo = cat(atlNodeOut_a_bits_a_mask_acc_5, atlNodeOut_a_bits_a_mask_acc_4)
node atlNodeOut_a_bits_a_mask_hi_hi = cat(atlNodeOut_a_bits_a_mask_acc_7, atlNodeOut_a_bits_a_mask_acc_6)
node atlNodeOut_a_bits_a_mask_hi = cat(atlNodeOut_a_bits_a_mask_hi_hi, atlNodeOut_a_bits_a_mask_hi_lo)
node _atlNodeOut_a_bits_a_mask_T = cat(atlNodeOut_a_bits_a_mask_hi, atlNodeOut_a_bits_a_mask_lo)
connect atlNodeOut_a_bits_a.mask, _atlNodeOut_a_bits_a_mask_T
invalidate atlNodeOut_a_bits_a.data
connect atlNodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect atlNodeOut.a.bits, atlNodeOut_a_bits_a
node _atlNodeOut_d_ready_T = eq(state, UInt<3>(0h2))
connect atlNodeOut.d.ready, _atlNodeOut_d_ready_T
node _T = and(io.cmd.ready, io.cmd.valid)
when _T :
connect addr, io.cmd.bits.rs1
connect needle, io.cmd.bits.rs2
connect resp_rd, io.cmd.bits.inst.rd
connect count, UInt<1>(0h0)
connect finished, UInt<1>(0h0)
connect state, UInt<3>(0h1)
node _T_1 = and(atlNodeOut.a.ready, atlNodeOut.a.valid)
when _T_1 :
connect state, UInt<3>(0h2)
node _T_2 = and(atlNodeOut.d.ready, atlNodeOut.d.valid)
when _T_2 :
node _recv_beat_T = add(recv_beat, UInt<1>(0h1))
node _recv_beat_T_1 = tail(_recv_beat_T, 1)
connect recv_beat, _recv_beat_T_1
connect recv_data, atlNodeOut.d.bits.data
connect state, UInt<3>(0h3)
node _T_3 = eq(state, UInt<3>(0h3))
when _T_3 :
node _T_4 = eq(finished, UInt<1>(0h0))
when _T_4 :
node _count_T = add(count, chars_found)
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
when zero_found :
connect finished, UInt<1>(0h1)
node _T_5 = eq(recv_beat, UInt<4>(0h8))
when _T_5 :
connect addr, next_addr
node _state_T = or(zero_found, finished)
node _state_T_1 = mux(_state_T, UInt<3>(0h4), UInt<3>(0h1))
connect state, _state_T_1
connect recv_beat, UInt<1>(0h0)
else :
connect state, UInt<3>(0h2)
node _T_6 = and(io.resp.ready, io.resp.valid)
when _T_6 :
connect state, UInt<3>(0h0)
node _io_busy_T = neq(state, UInt<3>(0h0))
connect io.busy, _io_busy_T
connect io.interrupt, UInt<1>(0h0)
connect io.mem.req.valid, UInt<1>(0h0)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0) | module CharacterCountExample( // @[LazyRoCC.scala:242:7]
input clock, // @[LazyRoCC.scala:242:7]
input reset, // @[LazyRoCC.scala:242:7]
input auto_atl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_atl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_atl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_atl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_atl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_atl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_atl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_atl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_atl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_atl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_atl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_atl_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_cmd_ready, // @[LazyRoCC.scala:78:14]
input io_cmd_valid, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_funct, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xd, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rd, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_opcode, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs1, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_debug, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_cease, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_cmd_bits_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_dprv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_prv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_v, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd, // @[LazyRoCC.scala:78:14]
input [22:0] io_cmd_bits_status_zero2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_gva, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mbe, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_sxl, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_uxl, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd_rv32, // @[LazyRoCC.scala:78:14]
input [7:0] io_cmd_bits_status_zero1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tsr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tw, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tvm, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mxr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sum, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_xs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_vs, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spp, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_ube, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_upie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_hie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_uie, // @[LazyRoCC.scala:78:14]
input io_resp_ready, // @[LazyRoCC.scala:78:14]
output io_resp_valid, // @[LazyRoCC.scala:78:14]
output [4:0] io_resp_bits_rd, // @[LazyRoCC.scala:78:14]
output [63:0] io_resp_bits_data, // @[LazyRoCC.scala:78:14]
input io_mem_req_ready, // @[LazyRoCC.scala:78:14]
input io_mem_resp_valid, // @[LazyRoCC.scala:78:14]
input [39:0] io_mem_resp_bits_addr, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_tag, // @[LazyRoCC.scala:78:14]
input [4:0] io_mem_resp_bits_cmd, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_size, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_signed, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_dprv, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_dv, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_mask, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_replay, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_has_data, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_raw, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_store_data, // @[LazyRoCC.scala:78:14]
output io_busy // @[LazyRoCC.scala:78:14]
);
wire auto_atl_out_a_ready_0 = auto_atl_out_a_ready; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_d_valid_0 = auto_atl_out_d_valid; // @[LazyRoCC.scala:242:7]
wire [2:0] auto_atl_out_d_bits_opcode_0 = auto_atl_out_d_bits_opcode; // @[LazyRoCC.scala:242:7]
wire [1:0] auto_atl_out_d_bits_param_0 = auto_atl_out_d_bits_param; // @[LazyRoCC.scala:242:7]
wire [3:0] auto_atl_out_d_bits_size_0 = auto_atl_out_d_bits_size; // @[LazyRoCC.scala:242:7]
wire [2:0] auto_atl_out_d_bits_sink_0 = auto_atl_out_d_bits_sink; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_d_bits_denied_0 = auto_atl_out_d_bits_denied; // @[LazyRoCC.scala:242:7]
wire [63:0] auto_atl_out_d_bits_data_0 = auto_atl_out_d_bits_data; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_d_bits_corrupt_0 = auto_atl_out_d_bits_corrupt; // @[LazyRoCC.scala:242:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[LazyRoCC.scala:242:7]
wire [6:0] io_cmd_bits_inst_funct_0 = io_cmd_bits_inst_funct; // @[LazyRoCC.scala:242:7]
wire [4:0] io_cmd_bits_inst_rs2_0 = io_cmd_bits_inst_rs2; // @[LazyRoCC.scala:242:7]
wire [4:0] io_cmd_bits_inst_rs1_0 = io_cmd_bits_inst_rs1; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_inst_xd_0 = io_cmd_bits_inst_xd; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_inst_xs1_0 = io_cmd_bits_inst_xs1; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_inst_xs2_0 = io_cmd_bits_inst_xs2; // @[LazyRoCC.scala:242:7]
wire [4:0] io_cmd_bits_inst_rd_0 = io_cmd_bits_inst_rd; // @[LazyRoCC.scala:242:7]
wire [6:0] io_cmd_bits_inst_opcode_0 = io_cmd_bits_inst_opcode; // @[LazyRoCC.scala:242:7]
wire [63:0] io_cmd_bits_rs1_0 = io_cmd_bits_rs1; // @[LazyRoCC.scala:242:7]
wire [63:0] io_cmd_bits_rs2_0 = io_cmd_bits_rs2; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_debug_0 = io_cmd_bits_status_debug; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_cease_0 = io_cmd_bits_status_cease; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_wfi_0 = io_cmd_bits_status_wfi; // @[LazyRoCC.scala:242:7]
wire [31:0] io_cmd_bits_status_isa_0 = io_cmd_bits_status_isa; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_dprv_0 = io_cmd_bits_status_dprv; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_dv_0 = io_cmd_bits_status_dv; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_prv_0 = io_cmd_bits_status_prv; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_v_0 = io_cmd_bits_status_v; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_sd_0 = io_cmd_bits_status_sd; // @[LazyRoCC.scala:242:7]
wire [22:0] io_cmd_bits_status_zero2_0 = io_cmd_bits_status_zero2; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mpv_0 = io_cmd_bits_status_mpv; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_gva_0 = io_cmd_bits_status_gva; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mbe_0 = io_cmd_bits_status_mbe; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_sbe_0 = io_cmd_bits_status_sbe; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_sxl_0 = io_cmd_bits_status_sxl; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_uxl_0 = io_cmd_bits_status_uxl; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_sd_rv32_0 = io_cmd_bits_status_sd_rv32; // @[LazyRoCC.scala:242:7]
wire [7:0] io_cmd_bits_status_zero1_0 = io_cmd_bits_status_zero1; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_tsr_0 = io_cmd_bits_status_tsr; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_tw_0 = io_cmd_bits_status_tw; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_tvm_0 = io_cmd_bits_status_tvm; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mxr_0 = io_cmd_bits_status_mxr; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_sum_0 = io_cmd_bits_status_sum; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mprv_0 = io_cmd_bits_status_mprv; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_xs_0 = io_cmd_bits_status_xs; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_fs_0 = io_cmd_bits_status_fs; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_mpp_0 = io_cmd_bits_status_mpp; // @[LazyRoCC.scala:242:7]
wire [1:0] io_cmd_bits_status_vs_0 = io_cmd_bits_status_vs; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_spp_0 = io_cmd_bits_status_spp; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mpie_0 = io_cmd_bits_status_mpie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_ube_0 = io_cmd_bits_status_ube; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_spie_0 = io_cmd_bits_status_spie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_upie_0 = io_cmd_bits_status_upie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_mie_0 = io_cmd_bits_status_mie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_hie_0 = io_cmd_bits_status_hie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_sie_0 = io_cmd_bits_status_sie; // @[LazyRoCC.scala:242:7]
wire io_cmd_bits_status_uie_0 = io_cmd_bits_status_uie; // @[LazyRoCC.scala:242:7]
wire io_resp_ready_0 = io_resp_ready; // @[LazyRoCC.scala:242:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[LazyRoCC.scala:242:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[LazyRoCC.scala:242:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[LazyRoCC.scala:242:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[LazyRoCC.scala:242:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[LazyRoCC.scala:242:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[LazyRoCC.scala:242:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[LazyRoCC.scala:242:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[LazyRoCC.scala:242:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[LazyRoCC.scala:242:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[LazyRoCC.scala:242:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[LazyRoCC.scala:242:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[LazyRoCC.scala:242:7]
wire [2:0] _atlNodeOut_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [1:0] atlNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _atlNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [2:0] atlNodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire _chars_found_T_2 = 1'h1; // @[LazyRoCC.scala:275:39]
wire _atlNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atlNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atlNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atlNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atlNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _atlNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _atlNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _atlNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atlNodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:92:28]
wire atlNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire atlNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire atlNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire atlNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire atlNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire [1:0] atlNodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] atlNodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] atlNodeOut_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] atlNodeOut_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [3:0] atlNodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] atlNodeOut_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [64:0] io_fpu_req_bits_in1 = 65'h0; // @[LazyRoCC.scala:242:7]
wire [64:0] io_fpu_req_bits_in2 = 65'h0; // @[LazyRoCC.scala:242:7]
wire [64:0] io_fpu_req_bits_in3 = 65'h0; // @[LazyRoCC.scala:242:7]
wire [64:0] io_fpu_resp_bits_data = 65'h0; // @[LazyRoCC.scala:242:7]
wire [31:0] io_mem_s2_paddr = 32'h0; // @[LazyRoCC.scala:78:14, :242:7]
wire [1:0] io_mem_req_bits_size = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_mem_req_bits_dprv = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_fpu_req_bits_typeTagIn = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_fpu_req_bits_typeTagOut = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_fpu_req_bits_fmaCmd = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_fpu_req_bits_typ = 2'h0; // @[LazyRoCC.scala:242:7]
wire [1:0] io_fpu_req_bits_fmt = 2'h0; // @[LazyRoCC.scala:242:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[LazyRoCC.scala:242:7]
wire [4:0] io_fpu_resp_bits_exc = 5'h0; // @[LazyRoCC.scala:242:7]
wire [7:0] io_mem_req_bits_tag = 8'h0; // @[LazyRoCC.scala:242:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[LazyRoCC.scala:242:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[LazyRoCC.scala:242:7]
wire [39:0] io_mem_req_bits_addr = 40'h0; // @[LazyRoCC.scala:242:7]
wire [39:0] io_mem_s2_gpa = 40'h0; // @[LazyRoCC.scala:242:7]
wire [63:0] auto_atl_out_a_bits_data = 64'h0; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[LazyRoCC.scala:242:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[LazyRoCC.scala:242:7]
wire [63:0] atlNodeOut_a_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] atlNodeOut_a_bits_a_data = 64'h0; // @[Edges.scala:460:17]
wire [7:0] auto_atl_out_a_bits_mask = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] atlNodeOut_a_bits_mask = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] atlNodeOut_a_bits_a_mask = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] _atlNodeOut_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire auto_atl_out_a_bits_source = 1'h0; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_a_bits_corrupt = 1'h0; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_d_bits_source = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_valid = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_signed = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_dv = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_phys = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s1_kill = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_nack = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_nack_cause_raw = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_kill = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_uncached = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_replay_next = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_ma_st = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_pf_st = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_xcpt_ae_st = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_ordered = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_store_pending = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_acquire = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_release = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_grant = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_tlbMiss = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_blocked = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_mem_clock_enabled = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_interrupt = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_exception = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_ready = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_valid = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_ldst = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_wen = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_ren1 = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_ren2 = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_ren3 = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_swap12 = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_swap23 = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_fromint = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_toint = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_fastpipe = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_fma = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_div = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_sqrt = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_wflags = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_req_bits_vec = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_resp_ready = 1'h0; // @[LazyRoCC.scala:242:7]
wire io_fpu_resp_valid = 1'h0; // @[LazyRoCC.scala:242:7]
wire atlNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire atlNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire atlNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _atlNodeOut_a_bits_legal_T_63 = 1'h0; // @[Parameters.scala:92:38]
wire _atlNodeOut_a_bits_legal_T_64 = 1'h0; // @[Parameters.scala:92:33]
wire _atlNodeOut_a_bits_legal_T_65 = 1'h0; // @[Parameters.scala:684:29]
wire _atlNodeOut_a_bits_legal_T_71 = 1'h0; // @[Parameters.scala:684:54]
wire atlNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17]
wire atlNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17]
wire atlNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _atlNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _atlNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _atlNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _atlNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire [3:0] auto_atl_out_a_bits_size = 4'h6; // @[LazyRoCC.scala:242:7]
wire [3:0] atlNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] atlNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17]
wire [2:0] auto_atl_out_a_bits_param = 3'h0; // @[LazyRoCC.scala:242:7]
wire [2:0] io_fpu_req_bits_rm = 3'h0; // @[LazyRoCC.scala:242:7]
wire [2:0] atlNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] atlNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] auto_atl_out_a_bits_opcode = 3'h4; // @[LazyRoCC.scala:242:7]
wire [2:0] atlNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17]
wire [2:0] atlNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] _atlNodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire atlNodeOut_a_ready = auto_atl_out_a_ready_0; // @[LazyRoCC.scala:242:7]
wire atlNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] atlNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire atlNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire atlNodeOut_d_valid = auto_atl_out_d_valid_0; // @[LazyRoCC.scala:242:7]
wire [2:0] atlNodeOut_d_bits_opcode = auto_atl_out_d_bits_opcode_0; // @[LazyRoCC.scala:242:7]
wire [1:0] atlNodeOut_d_bits_param = auto_atl_out_d_bits_param_0; // @[LazyRoCC.scala:242:7]
wire [3:0] atlNodeOut_d_bits_size = auto_atl_out_d_bits_size_0; // @[LazyRoCC.scala:242:7]
wire [2:0] atlNodeOut_d_bits_sink = auto_atl_out_d_bits_sink_0; // @[LazyRoCC.scala:242:7]
wire atlNodeOut_d_bits_denied = auto_atl_out_d_bits_denied_0; // @[LazyRoCC.scala:242:7]
wire [63:0] atlNodeOut_d_bits_data = auto_atl_out_d_bits_data_0; // @[LazyRoCC.scala:242:7]
wire atlNodeOut_d_bits_corrupt = auto_atl_out_d_bits_corrupt_0; // @[LazyRoCC.scala:242:7]
wire _io_cmd_ready_T; // @[LazyRoCC.scala:280:26]
wire _io_resp_valid_T; // @[LazyRoCC.scala:281:27]
wire _io_busy_T; // @[LazyRoCC.scala:324:21]
wire [31:0] auto_atl_out_a_bits_address_0; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_a_valid_0; // @[LazyRoCC.scala:242:7]
wire auto_atl_out_d_ready_0; // @[LazyRoCC.scala:242:7]
wire io_cmd_ready_0; // @[LazyRoCC.scala:242:7]
wire [4:0] io_resp_bits_rd_0; // @[LazyRoCC.scala:242:7]
wire [63:0] io_resp_bits_data_0; // @[LazyRoCC.scala:242:7]
wire io_resp_valid_0; // @[LazyRoCC.scala:242:7]
wire io_busy_0; // @[LazyRoCC.scala:242:7]
wire _atlNodeOut_a_valid_T; // @[LazyRoCC.scala:284:28]
assign auto_atl_out_a_valid_0 = atlNodeOut_a_valid; // @[LazyRoCC.scala:242:7]
wire [31:0] atlNodeOut_a_bits_a_address; // @[Edges.scala:460:17]
assign auto_atl_out_a_bits_address_0 = atlNodeOut_a_bits_address; // @[LazyRoCC.scala:242:7]
wire _atlNodeOut_d_ready_T; // @[LazyRoCC.scala:289:28]
assign auto_atl_out_d_ready_0 = atlNodeOut_d_ready; // @[LazyRoCC.scala:242:7]
reg [7:0] needle; // @[LazyRoCC.scala:250:19]
reg [39:0] addr; // @[LazyRoCC.scala:251:17]
reg [63:0] count; // @[LazyRoCC.scala:252:18]
assign io_resp_bits_data_0 = count; // @[LazyRoCC.scala:242:7, :252:18]
reg [4:0] resp_rd; // @[LazyRoCC.scala:253:20]
assign io_resp_bits_rd_0 = resp_rd; // @[LazyRoCC.scala:242:7, :253:20]
wire [33:0] addr_block = addr[39:6]; // @[LazyRoCC.scala:251:17, :255:24]
wire [5:0] offset = addr[5:0]; // @[LazyRoCC.scala:251:17, :256:20]
wire [34:0] _next_addr_T = {1'h0, addr_block} + 35'h1; // @[LazyRoCC.scala:255:24, :257:31]
wire [33:0] _next_addr_T_1 = _next_addr_T[33:0]; // @[LazyRoCC.scala:257:31]
wire [40:0] next_addr = {1'h0, _next_addr_T_1, 6'h0}; // @[LazyRoCC.scala:257:{31,38}]
reg [2:0] state; // @[LazyRoCC.scala:260:22]
reg [63:0] recv_data; // @[LazyRoCC.scala:264:22]
reg [3:0] recv_beat; // @[LazyRoCC.scala:265:26]
wire [7:0] _data_bytes_T = recv_data[7:0]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_0 = _data_bytes_T; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_1 = recv_data[15:8]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_1 = _data_bytes_T_1; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_2 = recv_data[23:16]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_2 = _data_bytes_T_2; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_3 = recv_data[31:24]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_3 = _data_bytes_T_3; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_4 = recv_data[39:32]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_4 = _data_bytes_T_4; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_5 = recv_data[47:40]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_5 = _data_bytes_T_5; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_6 = recv_data[55:48]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_6 = _data_bytes_T_6; // @[LazyRoCC.scala:267:{27,74}]
wire [7:0] _data_bytes_T_7 = recv_data[63:56]; // @[LazyRoCC.scala:264:22, :267:74]
wire [7:0] data_bytes_7 = _data_bytes_T_7; // @[LazyRoCC.scala:267:{27,74}]
wire zero_match_0 = data_bytes_0 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_1 = data_bytes_1 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_2 = data_bytes_2 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_3 = data_bytes_3 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_4 = data_bytes_4 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_5 = data_bytes_5 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_6 = data_bytes_6 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire zero_match_7 = data_bytes_7 == 8'h0; // @[LazyRoCC.scala:267:27, :268:37]
wire needle_match_0 = data_bytes_0 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_1 = data_bytes_1 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_2 = data_bytes_2 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_3 = data_bytes_3 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_4 = data_bytes_4 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_5 = data_bytes_5 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_6 = data_bytes_6 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire needle_match_7 = data_bytes_7 == needle; // @[LazyRoCC.scala:250:19, :267:27, :269:39]
wire [2:0] _first_zero_T = {2'h3, ~zero_match_6}; // @[Mux.scala:50:70]
wire [2:0] _first_zero_T_1 = zero_match_5 ? 3'h5 : _first_zero_T; // @[Mux.scala:50:70]
wire [2:0] _first_zero_T_2 = zero_match_4 ? 3'h4 : _first_zero_T_1; // @[Mux.scala:50:70]
wire [2:0] _first_zero_T_3 = zero_match_3 ? 3'h3 : _first_zero_T_2; // @[Mux.scala:50:70]
wire [2:0] _first_zero_T_4 = zero_match_2 ? 3'h2 : _first_zero_T_3; // @[Mux.scala:50:70]
wire [2:0] _first_zero_T_5 = zero_match_1 ? 3'h1 : _first_zero_T_4; // @[Mux.scala:50:70]
wire [2:0] first_zero = zero_match_0 ? 3'h0 : _first_zero_T_5; // @[Mux.scala:50:70]
wire [4:0] _GEN = {1'h0, recv_beat}; // @[LazyRoCC.scala:265:26, :274:31]
wire [4:0] _GEN_0 = _GEN - 5'h1; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_2; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_2 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_4; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_4 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_6; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_6 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_8; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_8 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_10; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_10 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_12; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_12 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [4:0] _chars_found_idx_T_14; // @[LazyRoCC.scala:274:31]
assign _chars_found_idx_T_14 = _GEN_0; // @[LazyRoCC.scala:274:31]
wire [3:0] _chars_found_idx_T_1 = _chars_found_idx_T[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx = {_chars_found_idx_T_1, 3'h0}; // @[LazyRoCC.scala:274:{20,31}]
wire [6:0] _GEN_1 = {1'h0, offset}; // @[LazyRoCC.scala:256:20, :275:22]
wire _chars_found_T = chars_found_idx >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_1 = needle_match_0 & _chars_found_T; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_3 = _chars_found_T_1; // @[LazyRoCC.scala:275:{15,32}]
wire [3:0] _chars_found_idx_T_3 = _chars_found_idx_T_2[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_1 = {_chars_found_idx_T_3, 3'h1}; // @[LazyRoCC.scala:274:{20,31}, :275:39]
wire _chars_found_T_4 = chars_found_idx_1 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_5 = needle_match_1 & _chars_found_T_4; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_6 = |first_zero; // @[Mux.scala:50:70]
wire _chars_found_T_7 = _chars_found_T_5 & _chars_found_T_6; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_5 = _chars_found_idx_T_4[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_2 = {_chars_found_idx_T_5, 3'h2}; // @[LazyRoCC.scala:274:{20,31}]
wire _chars_found_T_8 = chars_found_idx_2 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_9 = needle_match_2 & _chars_found_T_8; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_10 = |(first_zero[2:1]); // @[Mux.scala:50:70]
wire _chars_found_T_11 = _chars_found_T_9 & _chars_found_T_10; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_7 = _chars_found_idx_T_6[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_3 = {_chars_found_idx_T_7, 3'h3}; // @[LazyRoCC.scala:274:{20,31}, :275:39]
wire _chars_found_T_12 = chars_found_idx_3 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_13 = needle_match_3 & _chars_found_T_12; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_14 = first_zero > 3'h2; // @[Mux.scala:50:70]
wire _chars_found_T_15 = _chars_found_T_13 & _chars_found_T_14; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_9 = _chars_found_idx_T_8[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_4 = {_chars_found_idx_T_9, 3'h4}; // @[LazyRoCC.scala:274:{20,31}]
wire _chars_found_T_16 = chars_found_idx_4 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_17 = needle_match_4 & _chars_found_T_16; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_18 = first_zero[2]; // @[Mux.scala:50:70]
wire _chars_found_T_19 = _chars_found_T_17 & _chars_found_T_18; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_11 = _chars_found_idx_T_10[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_5 = {_chars_found_idx_T_11, 3'h5}; // @[LazyRoCC.scala:274:{20,31}]
wire _chars_found_T_20 = chars_found_idx_5 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_21 = needle_match_5 & _chars_found_T_20; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_22 = first_zero > 3'h4; // @[Mux.scala:50:70]
wire _chars_found_T_23 = _chars_found_T_21 & _chars_found_T_22; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_13 = _chars_found_idx_T_12[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_6 = {_chars_found_idx_T_13, 3'h6}; // @[LazyRoCC.scala:274:{20,31}]
wire _chars_found_T_24 = chars_found_idx_6 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_25 = needle_match_6 & _chars_found_T_24; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_26 = first_zero > 3'h5; // @[Mux.scala:50:70]
wire _chars_found_T_27 = _chars_found_T_25 & _chars_found_T_26; // @[LazyRoCC.scala:275:{15,32,39}]
wire [3:0] _chars_found_idx_T_15 = _chars_found_idx_T_14[3:0]; // @[LazyRoCC.scala:274:31]
wire [6:0] chars_found_idx_7 = {_chars_found_idx_T_15, 3'h7}; // @[LazyRoCC.scala:274:{20,31}]
wire _chars_found_T_28 = chars_found_idx_7 >= _GEN_1; // @[LazyRoCC.scala:274:20, :275:22]
wire _chars_found_T_29 = needle_match_7 & _chars_found_T_28; // @[LazyRoCC.scala:269:39, :275:{15,22}]
wire _chars_found_T_30 = &first_zero; // @[Mux.scala:50:70]
wire _chars_found_T_31 = _chars_found_T_29 & _chars_found_T_30; // @[LazyRoCC.scala:275:{15,32,39}]
wire [1:0] _chars_found_T_32 = {1'h0, _chars_found_T_3} + {1'h0, _chars_found_T_7}; // @[LazyRoCC.scala:272:29, :275:32]
wire [1:0] _chars_found_T_33 = _chars_found_T_32; // @[LazyRoCC.scala:272:29]
wire [1:0] _chars_found_T_34 = {1'h0, _chars_found_T_11} + {1'h0, _chars_found_T_15}; // @[LazyRoCC.scala:272:29, :275:32]
wire [1:0] _chars_found_T_35 = _chars_found_T_34; // @[LazyRoCC.scala:272:29]
wire [2:0] _chars_found_T_36 = {1'h0, _chars_found_T_33} + {1'h0, _chars_found_T_35}; // @[LazyRoCC.scala:272:29]
wire [2:0] _chars_found_T_37 = _chars_found_T_36; // @[LazyRoCC.scala:272:29]
wire [1:0] _chars_found_T_38 = {1'h0, _chars_found_T_19} + {1'h0, _chars_found_T_23}; // @[LazyRoCC.scala:272:29, :275:32]
wire [1:0] _chars_found_T_39 = _chars_found_T_38; // @[LazyRoCC.scala:272:29]
wire [1:0] _chars_found_T_40 = {1'h0, _chars_found_T_27} + {1'h0, _chars_found_T_31}; // @[LazyRoCC.scala:272:29, :275:32]
wire [1:0] _chars_found_T_41 = _chars_found_T_40; // @[LazyRoCC.scala:272:29]
wire [2:0] _chars_found_T_42 = {1'h0, _chars_found_T_39} + {1'h0, _chars_found_T_41}; // @[LazyRoCC.scala:272:29]
wire [2:0] _chars_found_T_43 = _chars_found_T_42; // @[LazyRoCC.scala:272:29]
wire [3:0] _chars_found_T_44 = {1'h0, _chars_found_T_37} + {1'h0, _chars_found_T_43}; // @[LazyRoCC.scala:272:29]
wire [3:0] chars_found = _chars_found_T_44; // @[LazyRoCC.scala:272:29]
wire _zero_found_T = zero_match_0 | zero_match_1; // @[LazyRoCC.scala:268:37, :277:40]
wire _zero_found_T_1 = _zero_found_T | zero_match_2; // @[LazyRoCC.scala:268:37, :277:40]
wire _zero_found_T_2 = _zero_found_T_1 | zero_match_3; // @[LazyRoCC.scala:268:37, :277:40]
wire _zero_found_T_3 = _zero_found_T_2 | zero_match_4; // @[LazyRoCC.scala:268:37, :277:40]
wire _zero_found_T_4 = _zero_found_T_3 | zero_match_5; // @[LazyRoCC.scala:268:37, :277:40]
wire _zero_found_T_5 = _zero_found_T_4 | zero_match_6; // @[LazyRoCC.scala:268:37, :277:40]
wire zero_found = _zero_found_T_5 | zero_match_7; // @[LazyRoCC.scala:268:37, :277:40]
reg finished; // @[LazyRoCC.scala:278:21]
assign _io_cmd_ready_T = ~(|state); // @[LazyRoCC.scala:260:22, :280:26]
assign io_cmd_ready_0 = _io_cmd_ready_T; // @[LazyRoCC.scala:242:7, :280:26]
assign _io_resp_valid_T = state == 3'h4; // @[LazyRoCC.scala:260:22, :281:27]
assign io_resp_valid_0 = _io_resp_valid_T; // @[LazyRoCC.scala:242:7, :281:27]
assign _atlNodeOut_a_valid_T = state == 3'h1; // @[LazyRoCC.scala:260:22, :275:39, :284:28]
assign atlNodeOut_a_valid = _atlNodeOut_a_valid_T; // @[LazyRoCC.scala:284:28]
wire [39:0] _atlNodeOut_a_bits_T = {addr_block, 6'h0}; // @[LazyRoCC.scala:255:24, :257:38, :287:47]
wire [39:0] _atlNodeOut_a_bits_legal_T_14 = _atlNodeOut_a_bits_T; // @[LazyRoCC.scala:287:47]
wire [39:0] _atlNodeOut_a_bits_legal_T_4 = {_atlNodeOut_a_bits_T[39:14], _atlNodeOut_a_bits_T[13:0] ^ 14'h3000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_5 = {1'h0, _atlNodeOut_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_6 = _atlNodeOut_a_bits_legal_T_5 & 41'hFFEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_7 = _atlNodeOut_a_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_8 = _atlNodeOut_a_bits_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atlNodeOut_a_bits_legal_T_9 = _atlNodeOut_a_bits_legal_T_8; // @[Parameters.scala:684:54]
wire _atlNodeOut_a_bits_legal_T_72 = _atlNodeOut_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atlNodeOut_a_bits_legal_T_15 = {1'h0, _atlNodeOut_a_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_16 = _atlNodeOut_a_bits_legal_T_15 & 41'hFFEFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_17 = _atlNodeOut_a_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_18 = _atlNodeOut_a_bits_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {_atlNodeOut_a_bits_T[39:17], _atlNodeOut_a_bits_T[16:0] ^ 17'h10000}; // @[LazyRoCC.scala:287:47]
wire [39:0] _atlNodeOut_a_bits_legal_T_19; // @[Parameters.scala:137:31]
assign _atlNodeOut_a_bits_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atlNodeOut_a_bits_legal_T_24; // @[Parameters.scala:137:31]
assign _atlNodeOut_a_bits_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _atlNodeOut_a_bits_legal_T_20 = {1'h0, _atlNodeOut_a_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_21 = _atlNodeOut_a_bits_legal_T_20 & 41'hFDEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_22 = _atlNodeOut_a_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_23 = _atlNodeOut_a_bits_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atlNodeOut_a_bits_legal_T_25 = {1'h0, _atlNodeOut_a_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_26 = _atlNodeOut_a_bits_legal_T_25 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_27 = _atlNodeOut_a_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_28 = _atlNodeOut_a_bits_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _atlNodeOut_a_bits_legal_T_29 = {_atlNodeOut_a_bits_T[39:26], _atlNodeOut_a_bits_T[25:0] ^ 26'h2000000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_30 = {1'h0, _atlNodeOut_a_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_31 = _atlNodeOut_a_bits_legal_T_30 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_32 = _atlNodeOut_a_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_33 = _atlNodeOut_a_bits_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _atlNodeOut_a_bits_legal_T_34 = {_atlNodeOut_a_bits_T[39:28], _atlNodeOut_a_bits_T[27:0] ^ 28'h8000000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_35 = {1'h0, _atlNodeOut_a_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_36 = _atlNodeOut_a_bits_legal_T_35 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_37 = _atlNodeOut_a_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_38 = _atlNodeOut_a_bits_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _atlNodeOut_a_bits_legal_T_39 = {_atlNodeOut_a_bits_T[39:28], _atlNodeOut_a_bits_T[27:0] ^ 28'hC000000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_40 = {1'h0, _atlNodeOut_a_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_41 = _atlNodeOut_a_bits_legal_T_40 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_42 = _atlNodeOut_a_bits_legal_T_41; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_43 = _atlNodeOut_a_bits_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _atlNodeOut_a_bits_legal_T_44 = {_atlNodeOut_a_bits_T[39:29], _atlNodeOut_a_bits_T[28:0] ^ 29'h10020000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_45 = {1'h0, _atlNodeOut_a_bits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_46 = _atlNodeOut_a_bits_legal_T_45 & 41'hFFEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_47 = _atlNodeOut_a_bits_legal_T_46; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_48 = _atlNodeOut_a_bits_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign atlNodeOut_a_bits_a_address = _atlNodeOut_a_bits_T[31:0]; // @[Edges.scala:460:17]
wire [39:0] _atlNodeOut_a_bits_legal_T_49 = {_atlNodeOut_a_bits_T[39:32], atlNodeOut_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:460:17]
wire [40:0] _atlNodeOut_a_bits_legal_T_50 = {1'h0, _atlNodeOut_a_bits_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_51 = _atlNodeOut_a_bits_legal_T_50 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_52 = _atlNodeOut_a_bits_legal_T_51; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_53 = _atlNodeOut_a_bits_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atlNodeOut_a_bits_legal_T_54 = _atlNodeOut_a_bits_legal_T_18 | _atlNodeOut_a_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_55 = _atlNodeOut_a_bits_legal_T_54 | _atlNodeOut_a_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_56 = _atlNodeOut_a_bits_legal_T_55 | _atlNodeOut_a_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_57 = _atlNodeOut_a_bits_legal_T_56 | _atlNodeOut_a_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_58 = _atlNodeOut_a_bits_legal_T_57 | _atlNodeOut_a_bits_legal_T_43; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_59 = _atlNodeOut_a_bits_legal_T_58 | _atlNodeOut_a_bits_legal_T_48; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_60 = _atlNodeOut_a_bits_legal_T_59 | _atlNodeOut_a_bits_legal_T_53; // @[Parameters.scala:685:42]
wire _atlNodeOut_a_bits_legal_T_61 = _atlNodeOut_a_bits_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [39:0] _atlNodeOut_a_bits_legal_T_66 = {_atlNodeOut_a_bits_T[39:18], _atlNodeOut_a_bits_T[17:0] ^ 18'h20000}; // @[LazyRoCC.scala:287:47]
wire [40:0] _atlNodeOut_a_bits_legal_T_67 = {1'h0, _atlNodeOut_a_bits_legal_T_66}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atlNodeOut_a_bits_legal_T_68 = _atlNodeOut_a_bits_legal_T_67 & 41'hFFEF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atlNodeOut_a_bits_legal_T_69 = _atlNodeOut_a_bits_legal_T_68; // @[Parameters.scala:137:46]
wire _atlNodeOut_a_bits_legal_T_70 = _atlNodeOut_a_bits_legal_T_69 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atlNodeOut_a_bits_legal_T_73 = _atlNodeOut_a_bits_legal_T_72 | _atlNodeOut_a_bits_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire atlNodeOut_a_bits_legal = _atlNodeOut_a_bits_legal_T_73; // @[Parameters.scala:686:26]
assign atlNodeOut_a_bits_address = atlNodeOut_a_bits_a_address; // @[Edges.scala:460:17]
wire atlNodeOut_a_bits_a_mask_sub_sub_bit = _atlNodeOut_a_bits_T[2]; // @[Misc.scala:210:26]
wire atlNodeOut_a_bits_a_mask_sub_sub_1_2 = atlNodeOut_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atlNodeOut_a_bits_a_mask_sub_sub_nbit = ~atlNodeOut_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atlNodeOut_a_bits_a_mask_sub_sub_0_2 = atlNodeOut_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atlNodeOut_a_bits_a_mask_sub_sub_acc_T = atlNodeOut_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _atlNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = atlNodeOut_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_sub_bit = _atlNodeOut_a_bits_T[1]; // @[Misc.scala:210:26]
wire atlNodeOut_a_bits_a_mask_sub_nbit = ~atlNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atlNodeOut_a_bits_a_mask_sub_0_2 = atlNodeOut_a_bits_a_mask_sub_sub_0_2 & atlNodeOut_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire atlNodeOut_a_bits_a_mask_sub_1_2 = atlNodeOut_a_bits_a_mask_sub_sub_0_2 & atlNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atlNodeOut_a_bits_a_mask_sub_2_2 = atlNodeOut_a_bits_a_mask_sub_sub_1_2 & atlNodeOut_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire atlNodeOut_a_bits_a_mask_sub_3_2 = atlNodeOut_a_bits_a_mask_sub_sub_1_2 & atlNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atlNodeOut_a_bits_a_mask_bit = _atlNodeOut_a_bits_T[0]; // @[Misc.scala:210:26]
wire atlNodeOut_a_bits_a_mask_nbit = ~atlNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atlNodeOut_a_bits_a_mask_eq = atlNodeOut_a_bits_a_mask_sub_0_2 & atlNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T = atlNodeOut_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_1 = atlNodeOut_a_bits_a_mask_sub_0_2 & atlNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_1 = atlNodeOut_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_2 = atlNodeOut_a_bits_a_mask_sub_1_2 & atlNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_2 = atlNodeOut_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_3 = atlNodeOut_a_bits_a_mask_sub_1_2 & atlNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_3 = atlNodeOut_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_4 = atlNodeOut_a_bits_a_mask_sub_2_2 & atlNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_4 = atlNodeOut_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_5 = atlNodeOut_a_bits_a_mask_sub_2_2 & atlNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_5 = atlNodeOut_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_6 = atlNodeOut_a_bits_a_mask_sub_3_2 & atlNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_6 = atlNodeOut_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire atlNodeOut_a_bits_a_mask_eq_7 = atlNodeOut_a_bits_a_mask_sub_3_2 & atlNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atlNodeOut_a_bits_a_mask_acc_T_7 = atlNodeOut_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
assign _atlNodeOut_d_ready_T = state == 3'h2; // @[LazyRoCC.scala:260:22, :289:28]
assign atlNodeOut_d_ready = _atlNodeOut_d_ready_T; // @[LazyRoCC.scala:289:28]
wire [4:0] _recv_beat_T = _GEN + 5'h1; // @[LazyRoCC.scala:274:31, :303:28]
wire [3:0] _recv_beat_T_1 = _recv_beat_T[3:0]; // @[LazyRoCC.scala:303:28]
wire [64:0] _count_T = {1'h0, count} + {61'h0, chars_found}; // @[LazyRoCC.scala:252:18, :272:29, :310:22]
wire [63:0] _count_T_1 = _count_T[63:0]; // @[LazyRoCC.scala:310:22]
wire _state_T = zero_found | finished; // @[LazyRoCC.scala:277:40, :278:21, :315:31]
wire [2:0] _state_T_1 = _state_T ? 3'h4 : 3'h1; // @[LazyRoCC.scala:275:39, :315:{19,31}]
assign _io_busy_T = |state; // @[LazyRoCC.scala:260:22, :280:26, :324:21]
assign io_busy_0 = _io_busy_T; // @[LazyRoCC.scala:242:7, :324:21]
wire _T = io_cmd_ready_0 & io_cmd_valid_0; // @[Decoupled.scala:51:35]
wire _T_2 = atlNodeOut_d_ready & atlNodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _T_3 = state == 3'h3; // @[LazyRoCC.scala:260:22, :275:39, :308:15]
wire _T_5 = recv_beat == 4'h8; // @[LazyRoCC.scala:265:26, :313:21]
wire _GEN_3 = _T_3 & _T_5; // @[LazyRoCC.scala:291:22, :308:{15,28}, :313:{21,43}, :314:12]
always @(posedge clock) begin // @[LazyRoCC.scala:242:7]
if (_T) begin // @[Decoupled.scala:51:35]
needle <= io_cmd_bits_rs2_0[7:0]; // @[LazyRoCC.scala:242:7, :250:19, :293:12]
resp_rd <= io_cmd_bits_inst_rd_0; // @[LazyRoCC.scala:242:7, :253:20]
end
if (_GEN_3) // @[LazyRoCC.scala:291:22, :308:28, :313:43, :314:12]
addr <= next_addr[39:0]; // @[LazyRoCC.scala:251:17, :257:38, :314:12]
else if (_T) // @[Decoupled.scala:51:35]
addr <= io_cmd_bits_rs1_0[39:0]; // @[LazyRoCC.scala:242:7, :251:17, :292:10]
if (_T_3 & ~finished) // @[LazyRoCC.scala:278:21, :291:22, :308:{15,28}, :309:{11,22}, :310:13]
count <= _count_T_1; // @[LazyRoCC.scala:252:18, :310:22]
else if (_T) // @[Decoupled.scala:51:35]
count <= 64'h0; // @[LazyRoCC.scala:252:18]
if (_T_2) // @[Decoupled.scala:51:35]
recv_data <= atlNodeOut_d_bits_data; // @[LazyRoCC.scala:264:22]
finished <= _T_3 & zero_found | ~_T & finished; // @[Decoupled.scala:51:35]
if (reset) begin // @[LazyRoCC.scala:242:7]
state <= 3'h0; // @[LazyRoCC.scala:260:22]
recv_beat <= 4'h0; // @[LazyRoCC.scala:265:26]
end
else begin // @[LazyRoCC.scala:242:7]
if (io_resp_ready_0 & io_resp_valid_0) // @[Decoupled.scala:51:35]
state <= 3'h0; // @[LazyRoCC.scala:260:22]
else if (_T_3) // @[LazyRoCC.scala:308:15]
state <= _T_5 ? _state_T_1 : 3'h2; // @[LazyRoCC.scala:260:22, :313:{21,43}, :315:{13,19}, :318:13]
else if (_T_2) // @[Decoupled.scala:51:35]
state <= 3'h3; // @[LazyRoCC.scala:260:22, :275:39]
else if (atlNodeOut_a_ready & atlNodeOut_a_valid) // @[Decoupled.scala:51:35]
state <= 3'h2; // @[LazyRoCC.scala:260:22]
else if (_T) // @[Decoupled.scala:51:35]
state <= 3'h1; // @[LazyRoCC.scala:260:22, :275:39]
if (_GEN_3) // @[LazyRoCC.scala:291:22, :308:28, :313:43, :314:12]
recv_beat <= 4'h0; // @[LazyRoCC.scala:265:26]
else if (_T_2) // @[Decoupled.scala:51:35]
recv_beat <= _recv_beat_T_1; // @[LazyRoCC.scala:265:26, :303:28]
end
always @(posedge)
assign auto_atl_out_a_valid = auto_atl_out_a_valid_0; // @[LazyRoCC.scala:242:7]
assign auto_atl_out_a_bits_address = auto_atl_out_a_bits_address_0; // @[LazyRoCC.scala:242:7]
assign auto_atl_out_d_ready = auto_atl_out_d_ready_0; // @[LazyRoCC.scala:242:7]
assign io_cmd_ready = io_cmd_ready_0; // @[LazyRoCC.scala:242:7]
assign io_resp_valid = io_resp_valid_0; // @[LazyRoCC.scala:242:7]
assign io_resp_bits_rd = io_resp_bits_rd_0; // @[LazyRoCC.scala:242:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[LazyRoCC.scala:242:7]
assign io_busy = io_busy_0; // @[LazyRoCC.scala:242:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RocketTile :
input clock : Clock
input reset : Reset
output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>}
inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c
connect tlMasterXbar.clock, clock
connect tlMasterXbar.reset, reset
inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u
connect tlSlaveXbar.clock, clock
connect tlSlaveXbar.reset, reset
inst intXbar of IntXbar_i4_o1
inst broadcast of BundleBridgeNexus_UInt1
inst broadcast_1 of BundleBridgeNexus_UInt32
inst nexus of BundleBridgeNexus_NoOutput_6
inst nexus_1 of BundleBridgeNexus_TraceAux
inst broadcast_2 of BundleBridgeNexus_NoOutput_7
inst widget of TLWidthWidget8_8
connect widget.clock, clock
connect widget.reset, reset
inst dcache of DCache
connect dcache.clock, clock
connect dcache.reset, reset
inst frontend of Frontend
connect frontend.clock, clock
connect frontend.reset, reset
inst widget_1 of TLWidthWidget8_9
connect widget_1.clock, clock
connect widget_1.reset, reset
inst fragmenter of TLFragmenter
connect fragmenter.clock, clock
connect fragmenter.reset, reset
inst widget_2 of TLWidthWidget8_10
connect widget_2.clock, clock
connect widget_2.reset, reset
inst buffer of TLBuffer_a32d64s2k3z4c
connect buffer.clock, clock
connect buffer.reset, reset
inst buffer_1 of TLBuffer_1
connect buffer_1.clock, clock
connect buffer_1.reset, reset
wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlOtherMastersNodeOut.e.bits.sink
invalidate tlOtherMastersNodeOut.e.valid
invalidate tlOtherMastersNodeOut.e.ready
invalidate tlOtherMastersNodeOut.d.bits.corrupt
invalidate tlOtherMastersNodeOut.d.bits.data
invalidate tlOtherMastersNodeOut.d.bits.denied
invalidate tlOtherMastersNodeOut.d.bits.sink
invalidate tlOtherMastersNodeOut.d.bits.source
invalidate tlOtherMastersNodeOut.d.bits.size
invalidate tlOtherMastersNodeOut.d.bits.param
invalidate tlOtherMastersNodeOut.d.bits.opcode
invalidate tlOtherMastersNodeOut.d.valid
invalidate tlOtherMastersNodeOut.d.ready
invalidate tlOtherMastersNodeOut.c.bits.corrupt
invalidate tlOtherMastersNodeOut.c.bits.data
invalidate tlOtherMastersNodeOut.c.bits.address
invalidate tlOtherMastersNodeOut.c.bits.source
invalidate tlOtherMastersNodeOut.c.bits.size
invalidate tlOtherMastersNodeOut.c.bits.param
invalidate tlOtherMastersNodeOut.c.bits.opcode
invalidate tlOtherMastersNodeOut.c.valid
invalidate tlOtherMastersNodeOut.c.ready
invalidate tlOtherMastersNodeOut.b.bits.corrupt
invalidate tlOtherMastersNodeOut.b.bits.data
invalidate tlOtherMastersNodeOut.b.bits.mask
invalidate tlOtherMastersNodeOut.b.bits.address
invalidate tlOtherMastersNodeOut.b.bits.source
invalidate tlOtherMastersNodeOut.b.bits.size
invalidate tlOtherMastersNodeOut.b.bits.param
invalidate tlOtherMastersNodeOut.b.bits.opcode
invalidate tlOtherMastersNodeOut.b.valid
invalidate tlOtherMastersNodeOut.b.ready
invalidate tlOtherMastersNodeOut.a.bits.corrupt
invalidate tlOtherMastersNodeOut.a.bits.data
invalidate tlOtherMastersNodeOut.a.bits.mask
invalidate tlOtherMastersNodeOut.a.bits.address
invalidate tlOtherMastersNodeOut.a.bits.source
invalidate tlOtherMastersNodeOut.a.bits.size
invalidate tlOtherMastersNodeOut.a.bits.param
invalidate tlOtherMastersNodeOut.a.bits.opcode
invalidate tlOtherMastersNodeOut.a.valid
invalidate tlOtherMastersNodeOut.a.ready
wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlOtherMastersNodeIn.e.bits.sink
invalidate tlOtherMastersNodeIn.e.valid
invalidate tlOtherMastersNodeIn.e.ready
invalidate tlOtherMastersNodeIn.d.bits.corrupt
invalidate tlOtherMastersNodeIn.d.bits.data
invalidate tlOtherMastersNodeIn.d.bits.denied
invalidate tlOtherMastersNodeIn.d.bits.sink
invalidate tlOtherMastersNodeIn.d.bits.source
invalidate tlOtherMastersNodeIn.d.bits.size
invalidate tlOtherMastersNodeIn.d.bits.param
invalidate tlOtherMastersNodeIn.d.bits.opcode
invalidate tlOtherMastersNodeIn.d.valid
invalidate tlOtherMastersNodeIn.d.ready
invalidate tlOtherMastersNodeIn.c.bits.corrupt
invalidate tlOtherMastersNodeIn.c.bits.data
invalidate tlOtherMastersNodeIn.c.bits.address
invalidate tlOtherMastersNodeIn.c.bits.source
invalidate tlOtherMastersNodeIn.c.bits.size
invalidate tlOtherMastersNodeIn.c.bits.param
invalidate tlOtherMastersNodeIn.c.bits.opcode
invalidate tlOtherMastersNodeIn.c.valid
invalidate tlOtherMastersNodeIn.c.ready
invalidate tlOtherMastersNodeIn.b.bits.corrupt
invalidate tlOtherMastersNodeIn.b.bits.data
invalidate tlOtherMastersNodeIn.b.bits.mask
invalidate tlOtherMastersNodeIn.b.bits.address
invalidate tlOtherMastersNodeIn.b.bits.source
invalidate tlOtherMastersNodeIn.b.bits.size
invalidate tlOtherMastersNodeIn.b.bits.param
invalidate tlOtherMastersNodeIn.b.bits.opcode
invalidate tlOtherMastersNodeIn.b.valid
invalidate tlOtherMastersNodeIn.b.ready
invalidate tlOtherMastersNodeIn.a.bits.corrupt
invalidate tlOtherMastersNodeIn.a.bits.data
invalidate tlOtherMastersNodeIn.a.bits.mask
invalidate tlOtherMastersNodeIn.a.bits.address
invalidate tlOtherMastersNodeIn.a.bits.source
invalidate tlOtherMastersNodeIn.a.bits.size
invalidate tlOtherMastersNodeIn.a.bits.param
invalidate tlOtherMastersNodeIn.a.bits.opcode
invalidate tlOtherMastersNodeIn.a.valid
invalidate tlOtherMastersNodeIn.a.ready
connect tlOtherMastersNodeOut, tlOtherMastersNodeIn
wire hartIdSinkNodeIn : UInt<1>
invalidate hartIdSinkNodeIn
wire hartidOut : UInt<1>
invalidate hartidOut
wire hartidIn : UInt<1>
invalidate hartidIn
connect hartidOut, hartidIn
wire resetVectorSinkNodeIn : UInt<32>
invalidate resetVectorSinkNodeIn
wire reset_vectorOut : UInt<32>
invalidate reset_vectorOut
wire reset_vectorIn : UInt<32>
invalidate reset_vectorIn
connect reset_vectorOut, reset_vectorIn
wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}
invalidate traceSourceNodeOut.time
invalidate traceSourceNodeOut.insns[0].tval
invalidate traceSourceNodeOut.insns[0].cause
invalidate traceSourceNodeOut.insns[0].interrupt
invalidate traceSourceNodeOut.insns[0].exception
invalidate traceSourceNodeOut.insns[0].priv
invalidate traceSourceNodeOut.insns[0].insn
invalidate traceSourceNodeOut.insns[0].iaddr
invalidate traceSourceNodeOut.insns[0].valid
wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreSourceNodeOut.cause
invalidate traceCoreSourceNodeOut.tval
invalidate traceCoreSourceNodeOut.priv
invalidate traceCoreSourceNodeOut.group[0].ilastsize
invalidate traceCoreSourceNodeOut.group[0].itype
invalidate traceCoreSourceNodeOut.group[0].iaddr
invalidate traceCoreSourceNodeOut.group[0].iretire
wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>}
connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0)
connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0)
wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>}
invalidate traceAuxSinkNodeIn.stall
invalidate traceAuxSinkNodeIn.enable
wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]
invalidate bpwatchSourceNodeOut[0].action
invalidate bpwatchSourceNodeOut[0].ivalid[0]
invalidate bpwatchSourceNodeOut[0].wvalid[0]
invalidate bpwatchSourceNodeOut[0].rvalid[0]
invalidate bpwatchSourceNodeOut[0].valid[0]
wire int_localOut : UInt<1>[1]
invalidate int_localOut[0]
wire x1_int_localOut : UInt<1>[2]
invalidate x1_int_localOut[0]
invalidate x1_int_localOut[1]
wire x1_int_localOut_1 : UInt<1>[1]
invalidate x1_int_localOut_1[0]
wire x1_int_localOut_2 : UInt<1>[1]
invalidate x1_int_localOut_2[0]
wire int_localIn : UInt<1>[1]
invalidate int_localIn[0]
wire x1_int_localIn : UInt<1>[2]
invalidate x1_int_localIn[0]
invalidate x1_int_localIn[1]
wire x1_int_localIn_1 : UInt<1>[1]
invalidate x1_int_localIn_1[0]
wire x1_int_localIn_2 : UInt<1>[1]
invalidate x1_int_localIn_2[0]
connect int_localOut, int_localIn
connect x1_int_localOut, x1_int_localIn
connect x1_int_localOut_1, x1_int_localIn_1
connect x1_int_localOut_2, x1_int_localIn_2
wire intSinkNodeIn : UInt<1>[5]
invalidate intSinkNodeIn[0]
invalidate intSinkNodeIn[1]
invalidate intSinkNodeIn[2]
invalidate intSinkNodeIn[3]
invalidate intSinkNodeIn[4]
wire haltNodeOut : UInt<1>[1]
invalidate haltNodeOut[0]
wire ceaseNodeOut : UInt<1>[1]
invalidate ceaseNodeOut[0]
wire wfiNodeOut : UInt<1>[1]
invalidate wfiNodeOut[0]
connect buffer.auto.in, tlOtherMastersNodeOut
connect tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits
connect tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid
connect tlMasterXbar.auto.anon_out.e.ready, tlOtherMastersNodeIn.e.ready
connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d
connect tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits
connect tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid
connect tlMasterXbar.auto.anon_out.c.ready, tlOtherMastersNodeIn.c.ready
connect tlMasterXbar.auto.anon_out.b, tlOtherMastersNodeIn.b
connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits
connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid
connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready
connect intSinkNodeIn, intXbar.auto.anon_out
connect hartIdSinkNodeIn, broadcast.auto.out
connect broadcast.auto.in, hartidOut
connect resetVectorSinkNodeIn, broadcast_1.auto.out_0
connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1
connect broadcast_1.auto.in, reset_vectorOut
connect traceAuxSinkNodeIn, nexus_1.auto.out
connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0]
connect intXbar.auto.anon_in_0[0], int_localOut[0]
connect intXbar.auto.anon_in_1[0], x1_int_localOut[0]
connect intXbar.auto.anon_in_1[1], x1_int_localOut[1]
connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0]
connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0]
connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out
connect widget.auto.anon_in, dcache.auto.out
connect widget_1.auto.anon_in, frontend.auto.icache_master_out
connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out
connect hartidIn, auto.hartid_in
connect reset_vectorIn, auto.reset_vector_in
connect auto.trace_source_out, traceSourceNodeOut
connect auto.trace_core_source_out, traceCoreSourceNodeOut
connect int_localIn, auto.int_local_in_0
connect x1_int_localIn, auto.int_local_in_1
connect x1_int_localIn_1, auto.int_local_in_2
connect x1_int_localIn_2, auto.int_local_in_3
connect auto.halt_out, haltNodeOut
connect auto.cease_out, ceaseNodeOut
connect auto.wfi_out, wfiNodeOut
connect auto.buffer_out.e.bits, buffer.auto.out.e.bits
connect auto.buffer_out.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, auto.buffer_out.e.ready
connect buffer.auto.out.d, auto.buffer_out.d
connect auto.buffer_out.c.bits, buffer.auto.out.c.bits
connect auto.buffer_out.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, auto.buffer_out.c.ready
connect buffer.auto.out.b, auto.buffer_out.b
connect auto.buffer_out.a.bits, buffer.auto.out.a.bits
connect auto.buffer_out.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, auto.buffer_out.a.ready
invalidate dcache.io.tlb_port.s2_kill
invalidate dcache.io.tlb_port.s1_resp.cmd
invalidate dcache.io.tlb_port.s1_resp.size
invalidate dcache.io.tlb_port.s1_resp.prefetchable
invalidate dcache.io.tlb_port.s1_resp.must_alloc
invalidate dcache.io.tlb_port.s1_resp.cacheable
invalidate dcache.io.tlb_port.s1_resp.ma.inst
invalidate dcache.io.tlb_port.s1_resp.ma.st
invalidate dcache.io.tlb_port.s1_resp.ma.ld
invalidate dcache.io.tlb_port.s1_resp.ae.inst
invalidate dcache.io.tlb_port.s1_resp.ae.st
invalidate dcache.io.tlb_port.s1_resp.ae.ld
invalidate dcache.io.tlb_port.s1_resp.gf.inst
invalidate dcache.io.tlb_port.s1_resp.gf.st
invalidate dcache.io.tlb_port.s1_resp.gf.ld
invalidate dcache.io.tlb_port.s1_resp.pf.inst
invalidate dcache.io.tlb_port.s1_resp.pf.st
invalidate dcache.io.tlb_port.s1_resp.pf.ld
invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte
invalidate dcache.io.tlb_port.s1_resp.gpa
invalidate dcache.io.tlb_port.s1_resp.paddr
invalidate dcache.io.tlb_port.s1_resp.miss
invalidate dcache.io.tlb_port.req.bits.v
invalidate dcache.io.tlb_port.req.bits.prv
invalidate dcache.io.tlb_port.req.bits.cmd
invalidate dcache.io.tlb_port.req.bits.size
invalidate dcache.io.tlb_port.req.bits.passthrough
invalidate dcache.io.tlb_port.req.bits.vaddr
invalidate dcache.io.tlb_port.req.valid
invalidate dcache.io.tlb_port.req.ready
inst fpuOpt of FPU
connect fpuOpt.clock, clock
connect fpuOpt.reset, reset
connect fpuOpt.io.cp_req.valid, UInt<1>(0h0)
invalidate fpuOpt.io.cp_req.bits.in3
invalidate fpuOpt.io.cp_req.bits.in2
invalidate fpuOpt.io.cp_req.bits.in1
invalidate fpuOpt.io.cp_req.bits.fmt
invalidate fpuOpt.io.cp_req.bits.typ
invalidate fpuOpt.io.cp_req.bits.fmaCmd
invalidate fpuOpt.io.cp_req.bits.rm
invalidate fpuOpt.io.cp_req.bits.vec
invalidate fpuOpt.io.cp_req.bits.wflags
invalidate fpuOpt.io.cp_req.bits.sqrt
invalidate fpuOpt.io.cp_req.bits.div
invalidate fpuOpt.io.cp_req.bits.fma
invalidate fpuOpt.io.cp_req.bits.fastpipe
invalidate fpuOpt.io.cp_req.bits.toint
invalidate fpuOpt.io.cp_req.bits.fromint
invalidate fpuOpt.io.cp_req.bits.typeTagOut
invalidate fpuOpt.io.cp_req.bits.typeTagIn
invalidate fpuOpt.io.cp_req.bits.swap23
invalidate fpuOpt.io.cp_req.bits.swap12
invalidate fpuOpt.io.cp_req.bits.ren3
invalidate fpuOpt.io.cp_req.bits.ren2
invalidate fpuOpt.io.cp_req.bits.ren1
invalidate fpuOpt.io.cp_req.bits.wen
invalidate fpuOpt.io.cp_req.bits.ldst
connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0)
inst dcacheArb of HellaCacheArbiter
connect dcacheArb.clock, clock
connect dcacheArb.reset, reset
connect dcache.io.cpu, dcacheArb.io.mem
inst ptw of PTW
connect ptw.clock, clock
connect ptw.reset, reset
invalidate ptw.io.mem.clock_enabled
invalidate ptw.io.mem.keep_clock_enabled
invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore
invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad
invalidate ptw.io.mem.perf.canAcceptLoadThenLoad
invalidate ptw.io.mem.perf.canAcceptStoreThenRMW
invalidate ptw.io.mem.perf.canAcceptStoreThenLoad
invalidate ptw.io.mem.perf.blocked
invalidate ptw.io.mem.perf.tlbMiss
invalidate ptw.io.mem.perf.grant
invalidate ptw.io.mem.perf.release
invalidate ptw.io.mem.perf.acquire
invalidate ptw.io.mem.store_pending
invalidate ptw.io.mem.ordered
invalidate ptw.io.mem.s2_gpa_is_pte
invalidate ptw.io.mem.s2_gpa
invalidate ptw.io.mem.s2_xcpt.ae.st
invalidate ptw.io.mem.s2_xcpt.ae.ld
invalidate ptw.io.mem.s2_xcpt.gf.st
invalidate ptw.io.mem.s2_xcpt.gf.ld
invalidate ptw.io.mem.s2_xcpt.pf.st
invalidate ptw.io.mem.s2_xcpt.pf.ld
invalidate ptw.io.mem.s2_xcpt.ma.st
invalidate ptw.io.mem.s2_xcpt.ma.ld
invalidate ptw.io.mem.replay_next
invalidate ptw.io.mem.resp.bits.store_data
invalidate ptw.io.mem.resp.bits.data_raw
invalidate ptw.io.mem.resp.bits.data_word_bypass
invalidate ptw.io.mem.resp.bits.has_data
invalidate ptw.io.mem.resp.bits.replay
invalidate ptw.io.mem.resp.bits.mask
invalidate ptw.io.mem.resp.bits.data
invalidate ptw.io.mem.resp.bits.dv
invalidate ptw.io.mem.resp.bits.dprv
invalidate ptw.io.mem.resp.bits.signed
invalidate ptw.io.mem.resp.bits.size
invalidate ptw.io.mem.resp.bits.cmd
invalidate ptw.io.mem.resp.bits.tag
invalidate ptw.io.mem.resp.bits.addr
invalidate ptw.io.mem.resp.valid
invalidate ptw.io.mem.s2_paddr
invalidate ptw.io.mem.s2_uncached
invalidate ptw.io.mem.s2_kill
invalidate ptw.io.mem.s2_nack_cause_raw
invalidate ptw.io.mem.s2_nack
invalidate ptw.io.mem.s1_data.mask
invalidate ptw.io.mem.s1_data.data
invalidate ptw.io.mem.s1_kill
invalidate ptw.io.mem.req.bits.mask
invalidate ptw.io.mem.req.bits.data
invalidate ptw.io.mem.req.bits.no_xcpt
invalidate ptw.io.mem.req.bits.no_alloc
invalidate ptw.io.mem.req.bits.no_resp
invalidate ptw.io.mem.req.bits.phys
invalidate ptw.io.mem.req.bits.dv
invalidate ptw.io.mem.req.bits.dprv
invalidate ptw.io.mem.req.bits.signed
invalidate ptw.io.mem.req.bits.size
invalidate ptw.io.mem.req.bits.cmd
invalidate ptw.io.mem.req.bits.tag
invalidate ptw.io.mem.req.bits.addr
invalidate ptw.io.mem.req.valid
invalidate ptw.io.mem.req.ready
inst core of Rocket
connect core.clock, clock
connect core.reset, reset
invalidate core.io.reset_vector
connect haltNodeOut[0], UInt<1>(0h0)
connect ceaseNodeOut[0], UInt<1>(0h0)
regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0)
connect wfiNodeOut_0_REG, core.io.wfi
connect wfiNodeOut[0], wfiNodeOut_0_REG
connect core.io.interrupts.debug, intSinkNodeIn[0]
connect core.io.interrupts.msip, intSinkNodeIn[1]
connect core.io.interrupts.mtip, intSinkNodeIn[2]
connect core.io.interrupts.meip, intSinkNodeIn[3]
connect core.io.interrupts.seip, intSinkNodeIn[4]
connect traceSourceNodeOut, core.io.trace
connect core.io.traceStall, traceAuxSinkNodeIn.stall
connect bpwatchSourceNodeOut, core.io.bpwatch
connect core.io.hartid, hartIdSinkNodeIn
connect frontend.io.cpu, core.io.imem
connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled
connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra
connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr
connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set
connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec
connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags
connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt
connect core.io.fpu.dec.div, fpuOpt.io.dec.div
connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma
connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe
connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint
connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint
connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut
connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn
connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23
connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12
connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3
connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2
connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1
connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen
connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst
connect fpuOpt.io.killm, core.io.fpu.killm
connect fpuOpt.io.killx, core.io.fpu.killx
connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm
connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem
connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy
connect fpuOpt.io.valid, core.io.fpu.valid
connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data
connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag
connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type
connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val
connect core.io.fpu.toint_data, fpuOpt.io.toint_data
connect core.io.fpu.store_data, fpuOpt.io.store_data
connect fpuOpt.io.v_sew, core.io.fpu.v_sew
connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits
connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid
connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm
connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data
connect fpuOpt.io.inst, core.io.fpu.inst
connect fpuOpt.io.time, core.io.fpu.time
connect fpuOpt.io.hartid, core.io.fpu.hartid
connect core.io.ptw, ptw.io.dpath
connect core.io.rocc.cmd.ready, UInt<1>(0h0)
connect core.io.rocc.resp.valid, UInt<1>(0h0)
invalidate core.io.rocc.resp.bits.data
invalidate core.io.rocc.resp.bits.rd
invalidate core.io.rocc.busy
invalidate core.io.rocc.interrupt
invalidate core.io.rocc.mem.clock_enabled
invalidate core.io.rocc.mem.keep_clock_enabled
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad
invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad
invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW
invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad
invalidate core.io.rocc.mem.perf.blocked
invalidate core.io.rocc.mem.perf.tlbMiss
invalidate core.io.rocc.mem.perf.grant
invalidate core.io.rocc.mem.perf.release
invalidate core.io.rocc.mem.perf.acquire
invalidate core.io.rocc.mem.store_pending
invalidate core.io.rocc.mem.ordered
invalidate core.io.rocc.mem.s2_gpa_is_pte
invalidate core.io.rocc.mem.s2_gpa
invalidate core.io.rocc.mem.s2_xcpt.ae.st
invalidate core.io.rocc.mem.s2_xcpt.ae.ld
invalidate core.io.rocc.mem.s2_xcpt.gf.st
invalidate core.io.rocc.mem.s2_xcpt.gf.ld
invalidate core.io.rocc.mem.s2_xcpt.pf.st
invalidate core.io.rocc.mem.s2_xcpt.pf.ld
invalidate core.io.rocc.mem.s2_xcpt.ma.st
invalidate core.io.rocc.mem.s2_xcpt.ma.ld
invalidate core.io.rocc.mem.replay_next
invalidate core.io.rocc.mem.resp.bits.store_data
invalidate core.io.rocc.mem.resp.bits.data_raw
invalidate core.io.rocc.mem.resp.bits.data_word_bypass
invalidate core.io.rocc.mem.resp.bits.has_data
invalidate core.io.rocc.mem.resp.bits.replay
invalidate core.io.rocc.mem.resp.bits.mask
invalidate core.io.rocc.mem.resp.bits.data
invalidate core.io.rocc.mem.resp.bits.dv
invalidate core.io.rocc.mem.resp.bits.dprv
invalidate core.io.rocc.mem.resp.bits.signed
invalidate core.io.rocc.mem.resp.bits.size
invalidate core.io.rocc.mem.resp.bits.cmd
invalidate core.io.rocc.mem.resp.bits.tag
invalidate core.io.rocc.mem.resp.bits.addr
invalidate core.io.rocc.mem.resp.valid
invalidate core.io.rocc.mem.s2_paddr
invalidate core.io.rocc.mem.s2_uncached
invalidate core.io.rocc.mem.s2_kill
invalidate core.io.rocc.mem.s2_nack_cause_raw
invalidate core.io.rocc.mem.s2_nack
invalidate core.io.rocc.mem.s1_data.mask
invalidate core.io.rocc.mem.s1_data.data
invalidate core.io.rocc.mem.s1_kill
invalidate core.io.rocc.mem.req.bits.mask
invalidate core.io.rocc.mem.req.bits.data
invalidate core.io.rocc.mem.req.bits.no_xcpt
invalidate core.io.rocc.mem.req.bits.no_alloc
invalidate core.io.rocc.mem.req.bits.no_resp
invalidate core.io.rocc.mem.req.bits.phys
invalidate core.io.rocc.mem.req.bits.dv
invalidate core.io.rocc.mem.req.bits.dprv
invalidate core.io.rocc.mem.req.bits.signed
invalidate core.io.rocc.mem.req.bits.size
invalidate core.io.rocc.mem.req.bits.cmd
invalidate core.io.rocc.mem.req.bits.tag
invalidate core.io.rocc.mem.req.bits.addr
invalidate core.io.rocc.mem.req.valid
invalidate core.io.rocc.mem.req.ready
connect dcacheArb.io.requestor[0], ptw.io.mem
connect dcacheArb.io.requestor[1], core.io.dmem
connect ptw.io.requestor[0], dcache.io.ptw
connect ptw.io.requestor[1], frontend.io.ptw | module RocketTile( // @[RocketTile.scala:141:7]
input clock, // @[RocketTile.scala:141:7]
input reset, // @[RocketTile.scala:141:7]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input auto_hartid_in // @[LazyModuleImp.scala:107:25]
);
wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9]
wire _core_io_imem_might_request; // @[RocketTile.scala:147:20]
wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20]
wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20]
wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20]
wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20]
wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20]
wire _core_io_imem_progress; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20]
wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20]
wire [6:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20]
wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20]
wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20]
wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20]
wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_sd; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sd; // @[RocketTile.scala:147:20]
wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20]
wire _core_io_fpu_hartid; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20]
wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20]
wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20]
wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20]
wire _core_io_fpu_valid; // @[RocketTile.scala:147:20]
wire _core_io_fpu_killx; // @[RocketTile.scala:147:20]
wire _core_io_fpu_killm; // @[RocketTile.scala:147:20]
wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20]
wire _core_io_wfi; // @[RocketTile.scala:147:20]
wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_sd; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sd; // @[PTW.scala:802:19]
wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19]
wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19]
wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19]
wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19]
wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_sd; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sd; // @[PTW.scala:802:19]
wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19]
wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19]
wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19]
wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19]
wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19]
wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19]
wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19]
wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19]
wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25]
wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25]
wire [6:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25]
wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25]
wire [6:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25]
wire [6:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25]
wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62]
wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62]
wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62]
wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62]
wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62]
wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62]
wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62]
wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28]
wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28]
wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28]
wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28]
wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28]
wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28]
wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43]
wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43]
wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43]
wire [6:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43]
wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43]
wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43]
wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43]
wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43]
wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43]
wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43]
wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43]
wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43]
wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[RocketTile.scala:141:7]
wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[RocketTile.scala:141:7]
wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[RocketTile.scala:141:7]
wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[RocketTile.scala:141:7]
wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[RocketTile.scala:141:7]
wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[RocketTile.scala:141:7]
wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[RocketTile.scala:141:7]
wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[RocketTile.scala:141:7]
wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[RocketTile.scala:141:7]
wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7]
wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7]
wire auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7]
wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7]
wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7]
wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7]
wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7]
wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17]
wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17]
wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7]
wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7]
wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire wfiNodeOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7]
wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7]
wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17]
wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
wire hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7]
wire [7:0] auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7]
wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7]
wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7]
wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7]
wire hartidOut; // @[MixedNode.scala:542:17]
wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17]
wire broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9]
wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17]
assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17]
wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17]
wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
assign buffer_auto_in_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17]
assign buffer_auto_in_b_ready = tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_valid = tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17]
assign buffer_auto_in_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
assign buffer_auto_in_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_e_valid = tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign buffer_auto_in_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17]
assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17]
assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7]
assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17]
assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17]
wire int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17]
assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17]
wire intSinkNodeIn_0; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_1; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_2; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_3; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_4; // @[MixedNode.scala:551:17]
assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7]
reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36]
assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36]
always @(posedge clock) begin // @[RocketTile.scala:141:7]
if (reset) // @[RocketTile.scala:141:7]
wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36]
else // @[RocketTile.scala:141:7]
wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20]
always @(posedge)
TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42]
.clock (clock),
.reset (reset),
.auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready),
.auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid),
.auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param),
.auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready),
.auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid),
.auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode),
.auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param),
.auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size),
.auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source),
.auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address),
.auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask),
.auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt),
.auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready),
.auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid),
.auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode),
.auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param),
.auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size),
.auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source),
.auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink),
.auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied),
.auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready),
.auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9]
.auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data),
.auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready),
.auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid),
.auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode),
.auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param),
.auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size),
.auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source),
.auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address),
.auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data),
.auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready),
.auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid),
.auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink)
); // @[HierarchicalElement.scala:55:42]
TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41]
.clock (clock),
.reset (reset)
); // @[HierarchicalElement.scala:56:41]
IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37]
.auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17]
.auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17]
.auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_out_0 (intSinkNodeIn_0),
.auto_anon_out_1 (intSinkNodeIn_1),
.auto_anon_out_2 (intSinkNodeIn_2),
.auto_anon_out_3 (intSinkNodeIn_3),
.auto_anon_out_4 (intSinkNodeIn_4)
); // @[HierarchicalElement.scala:57:37]
DCache dcache ( // @[HellaCache.scala:278:43]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_cpu_req_ready (_dcache_io_cpu_req_ready),
.io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25]
.io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25]
.io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25]
.io_cpu_s1_data_mask (8'h0), // @[RocketTile.scala:147:20]
.io_cpu_s2_nack (_dcache_io_cpu_s2_nack),
.io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw),
.io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached),
.io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr),
.io_cpu_resp_valid (_dcache_io_cpu_resp_valid),
.io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr),
.io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag),
.io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd),
.io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size),
.io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed),
.io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv),
.io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv),
.io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data),
.io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask),
.io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay),
.io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data),
.io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass),
.io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw),
.io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data),
.io_cpu_replay_next (_dcache_io_cpu_replay_next),
.io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld),
.io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st),
.io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld),
.io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st),
.io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld),
.io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st),
.io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa),
.io_cpu_ordered (_dcache_io_cpu_ordered),
.io_cpu_store_pending (_dcache_io_cpu_store_pending),
.io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire),
.io_cpu_perf_release (_dcache_io_cpu_perf_release),
.io_cpu_perf_grant (_dcache_io_cpu_perf_grant),
.io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss),
.io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked),
.io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad),
.io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW),
.io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad),
.io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad),
.io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore),
.io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25]
.io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19]
.io_ptw_req_valid (_dcache_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19]
.io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19]
.io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19]
.io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19]
.io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19]
.io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19]
.io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19]
.io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19]
.io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19]
.io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19]
.io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19]
.io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19]
.io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[PTW.scala:802:19]
.io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19]
.io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19]
.io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19]
.io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19]
.io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19]
.io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19]
.io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19]
.io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19]
.io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19]
.io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19]
.io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19]
.io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19]
.io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19]
.io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19]
.io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19]
.io_ptw_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19]
.io_ptw_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19]
.io_ptw_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19]
.io_ptw_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19]
.io_ptw_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19]
.io_ptw_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19]
.io_ptw_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19]
.io_ptw_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19]
.io_ptw_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19]
.io_ptw_gstatus_sd (_ptw_io_requestor_0_gstatus_sd), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19]
.io_ptw_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19]
.io_ptw_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19]
.io_ptw_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19]
.io_ptw_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19]
.io_ptw_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19]
.io_ptw_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19]
.io_ptw_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19]
.io_ptw_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19]
.io_ptw_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19]
.io_ptw_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19]
.io_ptw_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19]
.io_ptw_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19]
.io_ptw_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19]
.io_ptw_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19]
.io_ptw_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19]
.io_ptw_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19]
); // @[HellaCache.scala:278:43]
Frontend frontend ( // @[Frontend.scala:393:28]
.clock (clock),
.reset (reset),
.auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20]
.io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20]
.io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20]
.io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20]
.io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20]
.io_cpu_resp_valid (_frontend_io_cpu_resp_valid),
.io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType),
.io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken),
.io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask),
.io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx),
.io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target),
.io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry),
.io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history),
.io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value),
.io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc),
.io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data),
.io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask),
.io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst),
.io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst),
.io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst),
.io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay),
.io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid),
.io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits),
.io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte),
.io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20]
.io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20]
.io_cpu_npc (_frontend_io_cpu_npc),
.io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire),
.io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss),
.io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20]
.io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19]
.io_ptw_req_valid (_frontend_io_ptw_req_valid),
.io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19]
.io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19]
.io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19]
.io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19]
.io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19]
.io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19]
.io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19]
.io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19]
.io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19]
.io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19]
.io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19]
.io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19]
.io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[PTW.scala:802:19]
.io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19]
.io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19]
.io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19]
.io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19]
.io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19]
.io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19]
.io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19]
.io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19]
.io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19]
.io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19]
.io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19]
.io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19]
.io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19]
.io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19]
.io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19]
.io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19]
.io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19]
.io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19]
.io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19]
.io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19]
.io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19]
.io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19]
.io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19]
.io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19]
.io_ptw_gstatus_sd (_ptw_io_requestor_1_gstatus_sd), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19]
.io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19]
.io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19]
.io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19]
.io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19]
.io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19]
.io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19]
.io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19]
.io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19]
.io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19]
.io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19]
.io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19]
.io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19]
.io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19]
.io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19]
.io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19]
.io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19]
); // @[Frontend.scala:393:28]
TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset)
); // @[Fragmenter.scala:345:34]
FPU fpuOpt ( // @[RocketTile.scala:242:62]
.clock (clock),
.reset (reset),
.io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20]
.io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20]
.io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20]
.io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20]
.io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20]
.io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid),
.io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits),
.io_store_data (_fpuOpt_io_store_data),
.io_toint_data (_fpuOpt_io_toint_data),
.io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20]
.io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20]
.io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20]
.io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20]
.io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20]
.io_fcsr_rdy (_fpuOpt_io_fcsr_rdy),
.io_nack_mem (_fpuOpt_io_nack_mem),
.io_illegal_rm (_fpuOpt_io_illegal_rm),
.io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20]
.io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20]
.io_dec_ldst (_fpuOpt_io_dec_ldst),
.io_dec_wen (_fpuOpt_io_dec_wen),
.io_dec_ren1 (_fpuOpt_io_dec_ren1),
.io_dec_ren2 (_fpuOpt_io_dec_ren2),
.io_dec_ren3 (_fpuOpt_io_dec_ren3),
.io_dec_swap12 (_fpuOpt_io_dec_swap12),
.io_dec_swap23 (_fpuOpt_io_dec_swap23),
.io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn),
.io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut),
.io_dec_fromint (_fpuOpt_io_dec_fromint),
.io_dec_toint (_fpuOpt_io_dec_toint),
.io_dec_fastpipe (_fpuOpt_io_dec_fastpipe),
.io_dec_fma (_fpuOpt_io_dec_fma),
.io_dec_div (_fpuOpt_io_dec_div),
.io_dec_sqrt (_fpuOpt_io_dec_sqrt),
.io_dec_wflags (_fpuOpt_io_dec_wflags),
.io_dec_vec (_fpuOpt_io_dec_vec),
.io_sboard_set (_fpuOpt_io_sboard_set),
.io_sboard_clr (_fpuOpt_io_sboard_clr),
.io_sboard_clra (_fpuOpt_io_sboard_clra),
.io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20]
); // @[RocketTile.scala:242:62]
HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19]
.io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack),
.io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw),
.io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached),
.io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr),
.io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag),
.io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd),
.io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size),
.io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed),
.io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv),
.io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv),
.io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask),
.io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay),
.io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data),
.io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass),
.io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw),
.io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data),
.io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next),
.io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa),
.io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered),
.io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending),
.io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire),
.io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release),
.io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant),
.io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss),
.io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked),
.io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad),
.io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW),
.io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad),
.io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad),
.io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore),
.io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20]
.io_requestor_1_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20]
.io_requestor_1_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20]
.io_requestor_1_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20]
.io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack),
.io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw),
.io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached),
.io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr),
.io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr),
.io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag),
.io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd),
.io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size),
.io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed),
.io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv),
.io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv),
.io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data),
.io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask),
.io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay),
.io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data),
.io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass),
.io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw),
.io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data),
.io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next),
.io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld),
.io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st),
.io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld),
.io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st),
.io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld),
.io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st),
.io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa),
.io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered),
.io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending),
.io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire),
.io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release),
.io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant),
.io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss),
.io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked),
.io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad),
.io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW),
.io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad),
.io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad),
.io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore),
.io_requestor_1_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20]
.io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43]
.io_mem_req_valid (_dcacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag),
.io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd),
.io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size),
.io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed),
.io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv),
.io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv),
.io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys),
.io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp),
.io_mem_s1_kill (_dcacheArb_io_mem_s1_kill),
.io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data),
.io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43]
.io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43]
.io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43]
.io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43]
.io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43]
.io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43]
.io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43]
.io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43]
.io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43]
.io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43]
.io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43]
.io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43]
.io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43]
.io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43]
.io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled)
); // @[HellaCache.scala:292:25]
PTW ptw ( // @[PTW.scala:802:19]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43]
.io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43]
.io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp),
.io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv),
.io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva),
.io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug),
.io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease),
.io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi),
.io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa),
.io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv),
.io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv),
.io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv),
.io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v),
.io_requestor_0_gstatus_sd (_ptw_io_requestor_0_gstatus_sd),
.io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2),
.io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv),
.io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva),
.io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe),
.io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe),
.io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl),
.io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1),
.io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr),
.io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw),
.io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm),
.io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr),
.io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum),
.io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv),
.io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs),
.io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp),
.io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs),
.io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp),
.io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie),
.io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube),
.io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie),
.io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie),
.io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie),
.io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie),
.io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie),
.io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie),
.io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l),
.io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a),
.io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x),
.io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w),
.io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r),
.io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr),
.io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask),
.io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l),
.io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a),
.io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x),
.io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w),
.io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r),
.io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr),
.io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask),
.io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l),
.io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a),
.io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x),
.io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w),
.io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r),
.io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr),
.io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask),
.io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l),
.io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a),
.io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x),
.io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w),
.io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r),
.io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr),
.io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask),
.io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l),
.io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a),
.io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x),
.io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w),
.io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r),
.io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr),
.io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask),
.io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l),
.io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a),
.io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x),
.io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w),
.io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r),
.io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr),
.io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask),
.io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l),
.io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a),
.io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x),
.io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w),
.io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r),
.io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr),
.io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask),
.io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l),
.io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a),
.io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x),
.io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w),
.io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r),
.io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr),
.io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask),
.io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren),
.io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen),
.io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata),
.io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value),
.io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren),
.io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen),
.io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata),
.io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value),
.io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren),
.io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen),
.io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata),
.io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value),
.io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren),
.io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen),
.io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata),
.io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value),
.io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28]
.io_requestor_1_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28]
.io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28]
.io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28]
.io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw),
.io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final),
.io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf),
.io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf),
.io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr),
.io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw),
.io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx),
.io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future),
.io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn),
.io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
.io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d),
.io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a),
.io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g),
.io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u),
.io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x),
.io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w),
.io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r),
.io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v),
.io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level),
.io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous),
.io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid),
.io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits),
.io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte),
.io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode),
.io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn),
.io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug),
.io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease),
.io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi),
.io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa),
.io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv),
.io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv),
.io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv),
.io_requestor_1_status_v (_ptw_io_requestor_1_status_v),
.io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd),
.io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv),
.io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva),
.io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr),
.io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw),
.io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm),
.io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr),
.io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum),
.io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv),
.io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs),
.io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp),
.io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp),
.io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie),
.io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie),
.io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie),
.io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie),
.io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp),
.io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv),
.io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva),
.io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug),
.io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease),
.io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi),
.io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa),
.io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv),
.io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv),
.io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv),
.io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v),
.io_requestor_1_gstatus_sd (_ptw_io_requestor_1_gstatus_sd),
.io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2),
.io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv),
.io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva),
.io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe),
.io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe),
.io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl),
.io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1),
.io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr),
.io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw),
.io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm),
.io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr),
.io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum),
.io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv),
.io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs),
.io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp),
.io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs),
.io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp),
.io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie),
.io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube),
.io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie),
.io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie),
.io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie),
.io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie),
.io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie),
.io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie),
.io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l),
.io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a),
.io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x),
.io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w),
.io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r),
.io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr),
.io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask),
.io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l),
.io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a),
.io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x),
.io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w),
.io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r),
.io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr),
.io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask),
.io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l),
.io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a),
.io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x),
.io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w),
.io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r),
.io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr),
.io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask),
.io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l),
.io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a),
.io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x),
.io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w),
.io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r),
.io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr),
.io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask),
.io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l),
.io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a),
.io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x),
.io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w),
.io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r),
.io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr),
.io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask),
.io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l),
.io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a),
.io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x),
.io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w),
.io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r),
.io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr),
.io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask),
.io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l),
.io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a),
.io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x),
.io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w),
.io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r),
.io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr),
.io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask),
.io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l),
.io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a),
.io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x),
.io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w),
.io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r),
.io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr),
.io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask),
.io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren),
.io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen),
.io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata),
.io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value),
.io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren),
.io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen),
.io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata),
.io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value),
.io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren),
.io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen),
.io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata),
.io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value),
.io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren),
.io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen),
.io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata),
.io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value),
.io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25]
.io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25]
.io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25]
.io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25]
.io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25]
.io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25]
.io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25]
.io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25]
.io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25]
.io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25]
.io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25]
.io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25]
.io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25]
.io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25]
.io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20]
.io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20]
.io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20]
.io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20]
.io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20]
.io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20]
.io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20]
.io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20]
.io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20]
.io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20]
.io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20]
.io_dpath_status_sd (_core_io_ptw_status_sd), // @[RocketTile.scala:147:20]
.io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20]
.io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20]
.io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20]
.io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20]
.io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20]
.io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20]
.io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20]
.io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20]
.io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20]
.io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20]
.io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20]
.io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20]
.io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20]
.io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20]
.io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sd (_core_io_ptw_gstatus_sd), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20]
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit),
.io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20]
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[PTW.scala:802:19]
Rocket core ( // @[RocketTile.scala:147:20]
.clock (clock),
.reset (reset),
.io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17]
.io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17]
.io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17]
.io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17]
.io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17]
.io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17]
.io_imem_might_request (_core_io_imem_might_request),
.io_imem_req_valid (_core_io_imem_req_valid),
.io_imem_req_bits_pc (_core_io_imem_req_bits_pc),
.io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative),
.io_imem_sfence_valid (_core_io_imem_sfence_valid),
.io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1),
.io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2),
.io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr),
.io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid),
.io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv),
.io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg),
.io_imem_resp_ready (_core_io_imem_resp_ready),
.io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28]
.io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28]
.io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28]
.io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28]
.io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28]
.io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28]
.io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28]
.io_imem_btb_update_valid (_core_io_imem_btb_update_valid),
.io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType),
.io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken),
.io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask),
.io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx),
.io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target),
.io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry),
.io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history),
.io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value),
.io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc),
.io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target),
.io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid),
.io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc),
.io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType),
.io_imem_bht_update_valid (_core_io_imem_bht_update_valid),
.io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history),
.io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value),
.io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc),
.io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch),
.io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken),
.io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict),
.io_imem_flush_icache (_core_io_imem_flush_icache),
.io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28]
.io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28]
.io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28]
.io_imem_progress (_core_io_imem_progress),
.io_dmem_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25]
.io_dmem_req_valid (_core_io_dmem_req_valid),
.io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr),
.io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag),
.io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd),
.io_dmem_req_bits_size (_core_io_dmem_req_bits_size),
.io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed),
.io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv),
.io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv),
.io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp),
.io_dmem_s1_kill (_core_io_dmem_s1_kill),
.io_dmem_s1_data_data (_core_io_dmem_s1_data_data),
.io_dmem_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25]
.io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25]
.io_dmem_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25]
.io_dmem_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25]
.io_dmem_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25]
.io_dmem_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25]
.io_dmem_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25]
.io_dmem_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25]
.io_dmem_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25]
.io_dmem_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25]
.io_dmem_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25]
.io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25]
.io_dmem_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25]
.io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled),
.io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode),
.io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_core_io_ptw_sfence_valid),
.io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1),
.io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2),
.io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr),
.io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid),
.io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv),
.io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg),
.io_ptw_status_debug (_core_io_ptw_status_debug),
.io_ptw_status_cease (_core_io_ptw_status_cease),
.io_ptw_status_wfi (_core_io_ptw_status_wfi),
.io_ptw_status_isa (_core_io_ptw_status_isa),
.io_ptw_status_dprv (_core_io_ptw_status_dprv),
.io_ptw_status_dv (_core_io_ptw_status_dv),
.io_ptw_status_prv (_core_io_ptw_status_prv),
.io_ptw_status_v (_core_io_ptw_status_v),
.io_ptw_status_sd (_core_io_ptw_status_sd),
.io_ptw_status_mpv (_core_io_ptw_status_mpv),
.io_ptw_status_gva (_core_io_ptw_status_gva),
.io_ptw_status_tsr (_core_io_ptw_status_tsr),
.io_ptw_status_tw (_core_io_ptw_status_tw),
.io_ptw_status_tvm (_core_io_ptw_status_tvm),
.io_ptw_status_mxr (_core_io_ptw_status_mxr),
.io_ptw_status_sum (_core_io_ptw_status_sum),
.io_ptw_status_mprv (_core_io_ptw_status_mprv),
.io_ptw_status_fs (_core_io_ptw_status_fs),
.io_ptw_status_mpp (_core_io_ptw_status_mpp),
.io_ptw_status_spp (_core_io_ptw_status_spp),
.io_ptw_status_mpie (_core_io_ptw_status_mpie),
.io_ptw_status_spie (_core_io_ptw_status_spie),
.io_ptw_status_mie (_core_io_ptw_status_mie),
.io_ptw_status_sie (_core_io_ptw_status_sie),
.io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp),
.io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv),
.io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva),
.io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug),
.io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease),
.io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi),
.io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa),
.io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv),
.io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv),
.io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv),
.io_ptw_gstatus_v (_core_io_ptw_gstatus_v),
.io_ptw_gstatus_sd (_core_io_ptw_gstatus_sd),
.io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2),
.io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv),
.io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva),
.io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe),
.io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe),
.io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl),
.io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1),
.io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr),
.io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw),
.io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm),
.io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr),
.io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum),
.io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv),
.io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs),
.io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp),
.io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs),
.io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp),
.io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie),
.io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube),
.io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie),
.io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie),
.io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie),
.io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie),
.io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie),
.io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie),
.io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask),
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19]
.io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren),
.io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen),
.io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata),
.io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value),
.io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren),
.io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen),
.io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata),
.io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value),
.io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren),
.io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen),
.io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata),
.io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value),
.io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren),
.io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen),
.io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata),
.io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value),
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19]
.io_fpu_hartid (_core_io_fpu_hartid),
.io_fpu_time (_core_io_fpu_time),
.io_fpu_inst (_core_io_fpu_inst),
.io_fpu_fromint_data (_core_io_fpu_fromint_data),
.io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm),
.io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62]
.io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62]
.io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62]
.io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62]
.io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val),
.io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type),
.io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag),
.io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data),
.io_fpu_valid (_core_io_fpu_valid),
.io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62]
.io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62]
.io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62]
.io_fpu_killx (_core_io_fpu_killx),
.io_fpu_killm (_core_io_fpu_killm),
.io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62]
.io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62]
.io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62]
.io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62]
.io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62]
.io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62]
.io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62]
.io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62]
.io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62]
.io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62]
.io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62]
.io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62]
.io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62]
.io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62]
.io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62]
.io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62]
.io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62]
.io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled),
.io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid),
.io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr),
.io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn),
.io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv),
.io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception),
.io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt),
.io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause),
.io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval),
.io_trace_time (traceSourceNodeOut_time),
.io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0),
.io_bpwatch_0_action (bpwatchSourceNodeOut_0_action),
.io_wfi (_core_io_wfi)
); // @[RocketTile.scala:147:20]
assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[RocketTile.scala:141:7]
assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_511 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_511( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_94 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_94( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a15d64s7k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved.corrupt, io.enq.bits.corrupt
connect saved.data, io.enq.bits.data
connect saved.mask, io.enq.bits.mask
connect saved.user, io.enq.bits.user
connect saved.address, io.enq.bits.address
connect saved.source, io.enq.bits.source
connect saved.size, io.enq.bits.size
connect saved.param, io.enq.bits.param
connect saved.opcode, io.enq.bits.opcode
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a15d64s7k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [14:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_bufferable, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_modifiable, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_readalloc, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_writealloc, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_privileged, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_secure, // @[Repeater.scala:13:14]
input io_enq_bits_user_amba_prot_fetch, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [14:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_bufferable, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_modifiable, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_readalloc, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_writealloc, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_privileged, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_secure, // @[Repeater.scala:13:14]
output io_deq_bits_user_amba_prot_fetch, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
reg full; // @[Repeater.scala:20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [6:0] saved_source; // @[Repeater.scala:21:18]
reg [14:0] saved_address; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_bufferable; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_modifiable; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_readalloc; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_writealloc; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_privileged; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_secure; // @[Repeater.scala:21:18]
reg saved_user_amba_prot_fetch; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32]
wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}]
wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35]
if (_GEN) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18]
saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18]
saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18]
saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18]
saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18]
saved_user_amba_prot_bufferable <= io_enq_bits_user_amba_prot_bufferable; // @[Repeater.scala:21:18]
saved_user_amba_prot_modifiable <= io_enq_bits_user_amba_prot_modifiable; // @[Repeater.scala:21:18]
saved_user_amba_prot_readalloc <= io_enq_bits_user_amba_prot_readalloc; // @[Repeater.scala:21:18]
saved_user_amba_prot_writealloc <= io_enq_bits_user_amba_prot_writealloc; // @[Repeater.scala:21:18]
saved_user_amba_prot_privileged <= io_enq_bits_user_amba_prot_privileged; // @[Repeater.scala:21:18]
saved_user_amba_prot_secure <= io_enq_bits_user_amba_prot_secure; // @[Repeater.scala:21:18]
saved_user_amba_prot_fetch <= io_enq_bits_user_amba_prot_fetch; // @[Repeater.scala:21:18]
saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18]
saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_22ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_source_nodes_out_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_20
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3
connect routers.auto.dest_nodes_in_4, auto.routers_dest_nodes_in_4
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free
connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return
connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit
connect routers.auto.source_nodes_out_4.vc_free, auto.routers_source_nodes_out_4.vc_free
connect routers.auto.source_nodes_out_4.credit_return, auto.routers_source_nodes_out_4.credit_return
connect auto.routers_source_nodes_out_4.flit, routers.auto.source_nodes_out_4.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_router_22ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_4_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_4_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_4_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_4_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_4_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_4_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_20 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4),
.auto_source_nodes_out_4_flit_0_valid (auto_routers_source_nodes_out_4_flit_0_valid),
.auto_source_nodes_out_4_flit_0_bits_head (auto_routers_source_nodes_out_4_flit_0_bits_head),
.auto_source_nodes_out_4_flit_0_bits_tail (auto_routers_source_nodes_out_4_flit_0_bits_tail),
.auto_source_nodes_out_4_flit_0_bits_payload (auto_routers_source_nodes_out_4_flit_0_bits_payload),
.auto_source_nodes_out_4_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_4_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_4_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_4_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_4_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_4_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_4_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_4_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_4_credit_return (auto_routers_source_nodes_out_4_credit_return),
.auto_source_nodes_out_4_vc_free (auto_routers_source_nodes_out_4_vc_free),
.auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid),
.auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head),
.auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail),
.auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload),
.auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return),
.auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_4_flit_0_valid (auto_routers_dest_nodes_in_4_flit_0_valid),
.auto_dest_nodes_in_4_flit_0_bits_head (auto_routers_dest_nodes_in_4_flit_0_bits_head),
.auto_dest_nodes_in_4_flit_0_bits_tail (auto_routers_dest_nodes_in_4_flit_0_bits_tail),
.auto_dest_nodes_in_4_flit_0_bits_payload (auto_routers_dest_nodes_in_4_flit_0_bits_payload),
.auto_dest_nodes_in_4_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_4_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_4_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_4_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_4_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_4_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_4_credit_return (auto_routers_dest_nodes_in_4_credit_return),
.auto_dest_nodes_in_4_vc_free (auto_routers_dest_nodes_in_4_vc_free),
.auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid),
.auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head),
.auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail),
.auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload),
.auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return),
.auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_76 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<5>(0h14)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<4>(0h8)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = or(_T_24, _T_29)
node _T_31 = and(_T_19, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = and(_T_18, _T_32)
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_33, UInt<1>(0h1), "") : assert_2
node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_39 = and(_T_37, _T_38)
node _T_40 = or(UInt<1>(0h0), _T_39)
node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<5>(0h14)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_47 = cvt(_T_46)
node _T_48 = and(_T_47, asSInt(UInt<4>(0h8)))
node _T_49 = asSInt(_T_48)
node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0)))
node _T_51 = or(_T_45, _T_50)
node _T_52 = and(_T_40, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = and(UInt<1>(0h0), _T_53)
node _T_55 = asUInt(reset)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
node _T_57 = eq(_T_54, UInt<1>(0h0))
when _T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_54, UInt<1>(0h1), "") : assert_3
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_61, UInt<1>(0h1), "") : assert_5
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(is_aligned, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_68, UInt<1>(0h1), "") : assert_7
node _T_72 = not(io.in.a.bits.mask)
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_73, UInt<1>(0h1), "") : assert_8
node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_77, UInt<1>(0h1), "") : assert_9
node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_81 :
node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_83 = and(UInt<1>(0h0), _T_82)
node _T_84 = or(UInt<1>(0h0), _T_83)
node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_87 = cvt(_T_86)
node _T_88 = and(_T_87, asSInt(UInt<5>(0h14)))
node _T_89 = asSInt(_T_88)
node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0)))
node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_92 = cvt(_T_91)
node _T_93 = and(_T_92, asSInt(UInt<4>(0h8)))
node _T_94 = asSInt(_T_93)
node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0)))
node _T_96 = or(_T_90, _T_95)
node _T_97 = and(_T_85, _T_96)
node _T_98 = or(UInt<1>(0h0), _T_97)
node _T_99 = and(_T_84, _T_98)
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_105 = and(_T_103, _T_104)
node _T_106 = or(UInt<1>(0h0), _T_105)
node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<5>(0h14)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<4>(0h8)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(UInt<1>(0h0), _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_120, UInt<1>(0h1), "") : assert_11
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_127, UInt<1>(0h1), "") : assert_13
node _T_131 = asUInt(reset)
node _T_132 = eq(_T_131, UInt<1>(0h0))
when _T_132 :
node _T_133 = eq(is_aligned, UInt<1>(0h0))
when _T_133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_134, UInt<1>(0h1), "") : assert_15
node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_139 = asUInt(reset)
node _T_140 = eq(_T_139, UInt<1>(0h0))
when _T_140 :
node _T_141 = eq(_T_138, UInt<1>(0h0))
when _T_141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_138, UInt<1>(0h1), "") : assert_16
node _T_142 = not(io.in.a.bits.mask)
node _T_143 = eq(_T_142, UInt<1>(0h0))
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(_T_143, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_143, UInt<1>(0h1), "") : assert_17
node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_148 = asUInt(reset)
node _T_149 = eq(_T_148, UInt<1>(0h0))
when _T_149 :
node _T_150 = eq(_T_147, UInt<1>(0h0))
when _T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_147, UInt<1>(0h1), "") : assert_18
node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_151 :
node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(UInt<1>(0h0), _T_161)
node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<5>(0h14)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<4>(0h8)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = or(_T_167, _T_172)
node _T_174 = and(_T_162, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_175, UInt<1>(0h1), "") : assert_20
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_182 = asUInt(reset)
node _T_183 = eq(_T_182, UInt<1>(0h0))
when _T_183 :
node _T_184 = eq(is_aligned, UInt<1>(0h0))
when _T_184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_185, UInt<1>(0h1), "") : assert_23
node _T_189 = eq(io.in.a.bits.mask, mask)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_189, UInt<1>(0h1), "") : assert_24
node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_193, UInt<1>(0h1), "") : assert_25
node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_200 = and(_T_198, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_204 = and(_T_202, _T_203)
node _T_205 = or(UInt<1>(0h0), _T_204)
node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<5>(0h14)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<4>(0h8)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = or(_T_210, _T_215)
node _T_217 = and(_T_205, _T_216)
node _T_218 = or(UInt<1>(0h0), _T_217)
node _T_219 = and(_T_201, _T_218)
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_T_219, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_219, UInt<1>(0h1), "") : assert_26
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(is_aligned, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_229, UInt<1>(0h1), "") : assert_29
node _T_233 = eq(io.in.a.bits.mask, mask)
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_233, UInt<1>(0h1), "") : assert_30
node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_237 :
node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_239 = and(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_243 = and(_T_241, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<5>(0h14)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<4>(0h8)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = and(_T_244, _T_255)
node _T_257 = or(UInt<1>(0h0), _T_256)
node _T_258 = and(_T_240, _T_257)
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_258, UInt<1>(0h1), "") : assert_31
node _T_262 = asUInt(reset)
node _T_263 = eq(_T_262, UInt<1>(0h0))
when _T_263 :
node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(is_aligned, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_268, UInt<1>(0h1), "") : assert_34
node _T_272 = not(mask)
node _T_273 = and(io.in.a.bits.mask, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_274, UInt<1>(0h1), "") : assert_35
node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_278 :
node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_280 = and(UInt<1>(0h0), _T_279)
node _T_281 = or(UInt<1>(0h0), _T_280)
node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<5>(0h14)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<4>(0h8)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = or(_T_287, _T_292)
node _T_294 = and(_T_282, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = and(_T_281, _T_295)
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_296, UInt<1>(0h1), "") : assert_36
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(is_aligned, UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_307 = asUInt(reset)
node _T_308 = eq(_T_307, UInt<1>(0h0))
when _T_308 :
node _T_309 = eq(_T_306, UInt<1>(0h0))
when _T_309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_306, UInt<1>(0h1), "") : assert_39
node _T_310 = eq(io.in.a.bits.mask, mask)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_310, UInt<1>(0h1), "") : assert_40
node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_314 :
node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_316 = and(UInt<1>(0h0), _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<5>(0h14)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<4>(0h8)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = or(_T_323, _T_328)
node _T_330 = and(_T_318, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = and(_T_317, _T_331)
node _T_333 = asUInt(reset)
node _T_334 = eq(_T_333, UInt<1>(0h0))
when _T_334 :
node _T_335 = eq(_T_332, UInt<1>(0h0))
when _T_335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_332, UInt<1>(0h1), "") : assert_41
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(is_aligned, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_342, UInt<1>(0h1), "") : assert_44
node _T_346 = eq(io.in.a.bits.mask, mask)
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_346, UInt<1>(0h1), "") : assert_45
node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_350 :
node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_352 = and(UInt<1>(0h0), _T_351)
node _T_353 = or(UInt<1>(0h0), _T_352)
node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40))
node _T_356 = cvt(_T_355)
node _T_357 = and(_T_356, asSInt(UInt<5>(0h14)))
node _T_358 = asSInt(_T_357)
node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0)))
node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50))
node _T_361 = cvt(_T_360)
node _T_362 = and(_T_361, asSInt(UInt<4>(0h8)))
node _T_363 = asSInt(_T_362)
node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0)))
node _T_365 = or(_T_359, _T_364)
node _T_366 = and(_T_354, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_T_353, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_368, UInt<1>(0h1), "") : assert_46
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(is_aligned, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_378, UInt<1>(0h1), "") : assert_49
node _T_382 = eq(io.in.a.bits.mask, mask)
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_382, UInt<1>(0h1), "") : assert_50
node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_386, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_390, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_394 :
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_398, UInt<1>(0h1), "") : assert_54
node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_402, UInt<1>(0h1), "") : assert_55
node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_406, UInt<1>(0h1), "") : assert_56
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = asUInt(reset)
node _T_412 = eq(_T_411, UInt<1>(0h0))
when _T_412 :
node _T_413 = eq(_T_410, UInt<1>(0h0))
when _T_413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_410, UInt<1>(0h1), "") : assert_57
node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_414 :
node _T_415 = asUInt(reset)
node _T_416 = eq(_T_415, UInt<1>(0h0))
when _T_416 :
node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(sink_ok, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_T_421, UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_421, UInt<1>(0h1), "") : assert_60
node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_425, UInt<1>(0h1), "") : assert_61
node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_T_429, UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_429, UInt<1>(0h1), "") : assert_62
node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_433, UInt<1>(0h1), "") : assert_63
node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_438 = or(UInt<1>(0h0), _T_437)
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_T_438, UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_438, UInt<1>(0h1), "") : assert_64
node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_442 :
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(sink_ok, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_449, UInt<1>(0h1), "") : assert_67
node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_453, UInt<1>(0h1), "") : assert_68
node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_457, UInt<1>(0h1), "") : assert_69
node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_462 = or(_T_461, io.in.d.bits.corrupt)
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_462, UInt<1>(0h1), "") : assert_70
node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_467 = or(UInt<1>(0h0), _T_466)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_467, UInt<1>(0h1), "") : assert_71
node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_471 :
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_475, UInt<1>(0h1), "") : assert_73
node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_479, UInt<1>(0h1), "") : assert_74
node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_484, UInt<1>(0h1), "") : assert_75
node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_488 :
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_492, UInt<1>(0h1), "") : assert_77
node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_497 = or(_T_496, io.in.d.bits.corrupt)
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(_T_497, UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_497, UInt<1>(0h1), "") : assert_78
node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_502 = or(UInt<1>(0h0), _T_501)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_502, UInt<1>(0h1), "") : assert_79
node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_506 :
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_510, UInt<1>(0h1), "") : assert_81
node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_514, UInt<1>(0h1), "") : assert_82
node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_519 = or(UInt<1>(0h0), _T_518)
node _T_520 = asUInt(reset)
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(_T_519, UInt<1>(0h0))
when _T_522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_519, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<7>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_523, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<7>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_528 = asUInt(reset)
node _T_529 = eq(_T_528, UInt<1>(0h0))
when _T_529 :
node _T_530 = eq(_T_527, UInt<1>(0h0))
when _T_530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_527, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(_T_531, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_531, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_535 = eq(a_first, UInt<1>(0h0))
node _T_536 = and(io.in.a.valid, _T_535)
when _T_536 :
node _T_537 = eq(io.in.a.bits.opcode, opcode)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_537, UInt<1>(0h1), "") : assert_87
node _T_541 = eq(io.in.a.bits.param, param)
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(_T_541, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_541, UInt<1>(0h1), "") : assert_88
node _T_545 = eq(io.in.a.bits.size, size)
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_545, UInt<1>(0h1), "") : assert_89
node _T_549 = eq(io.in.a.bits.source, source)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_549, UInt<1>(0h1), "") : assert_90
node _T_553 = eq(io.in.a.bits.address, address)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_553, UInt<1>(0h1), "") : assert_91
node _T_557 = and(io.in.a.ready, io.in.a.valid)
node _T_558 = and(_T_557, a_first)
when _T_558 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_559 = eq(d_first, UInt<1>(0h0))
node _T_560 = and(io.in.d.valid, _T_559)
when _T_560 :
node _T_561 = eq(io.in.d.bits.opcode, opcode_1)
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(_T_561, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_561, UInt<1>(0h1), "") : assert_92
node _T_565 = eq(io.in.d.bits.param, param_1)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_565, UInt<1>(0h1), "") : assert_93
node _T_569 = eq(io.in.d.bits.size, size_1)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_569, UInt<1>(0h1), "") : assert_94
node _T_573 = eq(io.in.d.bits.source, source_1)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_573, UInt<1>(0h1), "") : assert_95
node _T_577 = eq(io.in.d.bits.sink, sink)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_577, UInt<1>(0h1), "") : assert_96
node _T_581 = eq(io.in.d.bits.denied, denied)
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_581, UInt<1>(0h1), "") : assert_97
node _T_585 = and(io.in.d.ready, io.in.d.valid)
node _T_586 = and(_T_585, d_first)
when _T_586 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_587 = and(io.in.a.valid, a_first_1)
node _T_588 = and(_T_587, UInt<1>(0h1))
when _T_588 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_589 = and(io.in.a.ready, io.in.a.valid)
node _T_590 = and(_T_589, a_first_1)
node _T_591 = and(_T_590, UInt<1>(0h1))
when _T_591 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_592 = dshr(inflight, io.in.a.bits.source)
node _T_593 = bits(_T_592, 0, 0)
node _T_594 = eq(_T_593, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_594, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_598 = and(io.in.d.valid, d_first_1)
node _T_599 = and(_T_598, UInt<1>(0h1))
node _T_600 = eq(d_release_ack, UInt<1>(0h0))
node _T_601 = and(_T_599, _T_600)
when _T_601 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_602 = and(io.in.d.ready, io.in.d.valid)
node _T_603 = and(_T_602, d_first_1)
node _T_604 = and(_T_603, UInt<1>(0h1))
node _T_605 = eq(d_release_ack, UInt<1>(0h0))
node _T_606 = and(_T_604, _T_605)
when _T_606 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_607 = and(io.in.d.valid, d_first_1)
node _T_608 = and(_T_607, UInt<1>(0h1))
node _T_609 = eq(d_release_ack, UInt<1>(0h0))
node _T_610 = and(_T_608, _T_609)
when _T_610 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_611 = dshr(inflight, io.in.d.bits.source)
node _T_612 = bits(_T_611, 0, 0)
node _T_613 = or(_T_612, same_cycle_resp)
node _T_614 = asUInt(reset)
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(_T_613, UInt<1>(0h0))
when _T_616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_613, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_619 = or(_T_617, _T_618)
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(_T_619, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_619, UInt<1>(0h1), "") : assert_100
node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_623, UInt<1>(0h1), "") : assert_101
else :
node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_629 = or(_T_627, _T_628)
node _T_630 = asUInt(reset)
node _T_631 = eq(_T_630, UInt<1>(0h0))
when _T_631 :
node _T_632 = eq(_T_629, UInt<1>(0h0))
when _T_632 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_629, UInt<1>(0h1), "") : assert_102
node _T_633 = eq(io.in.d.bits.size, a_size_lookup)
node _T_634 = asUInt(reset)
node _T_635 = eq(_T_634, UInt<1>(0h0))
when _T_635 :
node _T_636 = eq(_T_633, UInt<1>(0h0))
when _T_636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_633, UInt<1>(0h1), "") : assert_103
node _T_637 = and(io.in.d.valid, d_first_1)
node _T_638 = and(_T_637, a_first_1)
node _T_639 = and(_T_638, io.in.a.valid)
node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(d_release_ack, UInt<1>(0h0))
node _T_643 = and(_T_641, _T_642)
when _T_643 :
node _T_644 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_645 = or(_T_644, io.in.a.ready)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_645, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_160
node _T_649 = orr(inflight)
node _T_650 = eq(_T_649, UInt<1>(0h0))
node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_652 = or(_T_650, _T_651)
node _T_653 = lt(watchdog, plusarg_reader.out)
node _T_654 = or(_T_652, _T_653)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_654, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_658 = and(io.in.a.ready, io.in.a.valid)
node _T_659 = and(io.in.d.ready, io.in.d.valid)
node _T_660 = or(_T_658, _T_659)
when _T_660 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<7>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<7>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_661 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<7>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_664 = and(_T_662, _T_663)
node _T_665 = and(_T_661, _T_664)
when _T_665 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<7>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_667 = and(_T_666, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<7>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_670 = and(_T_668, _T_669)
node _T_671 = and(_T_667, _T_670)
when _T_671 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<7>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_672 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_673 = bits(_T_672, 0, 0)
node _T_674 = eq(_T_673, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_674, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_678 = and(io.in.d.valid, d_first_2)
node _T_679 = and(_T_678, UInt<1>(0h1))
node _T_680 = and(_T_679, d_release_ack_1)
when _T_680 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_681 = and(io.in.d.ready, io.in.d.valid)
node _T_682 = and(_T_681, d_first_2)
node _T_683 = and(_T_682, UInt<1>(0h1))
node _T_684 = and(_T_683, d_release_ack_1)
when _T_684 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_688 = dshr(inflight_1, io.in.d.bits.source)
node _T_689 = bits(_T_688, 0, 0)
node _T_690 = or(_T_689, same_cycle_resp_1)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_690, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<7>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(_T_694, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_694, UInt<1>(0h1), "") : assert_108
else :
node _T_698 = eq(io.in.d.bits.size, c_size_lookup)
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_698, UInt<1>(0h1), "") : assert_109
node _T_702 = and(io.in.d.valid, d_first_2)
node _T_703 = and(_T_702, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<7>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_704 = and(_T_703, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<7>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_706 = and(_T_704, _T_705)
node _T_707 = and(_T_706, d_release_ack_1)
node _T_708 = eq(c_probe_ack, UInt<1>(0h0))
node _T_709 = and(_T_707, _T_708)
when _T_709 :
node _T_710 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<7>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_711 = or(_T_710, _WIRE_23.ready)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_711, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_161
node _T_715 = orr(inflight_1)
node _T_716 = eq(_T_715, UInt<1>(0h0))
node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_718 = or(_T_716, _T_717)
node _T_719 = lt(watchdog_1, plusarg_reader_1.out)
node _T_720 = or(_T_718, _T_719)
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(_T_720, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_720, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<7>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_725 = and(io.in.d.ready, io.in.d.valid)
node _T_726 = or(_T_724, _T_725)
when _T_726 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_76( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_658; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [6:0] address; // @[Monitor.scala:391:22]
wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_726; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46]
wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_71 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_143
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_71( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_143 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater :
input clock : Clock
input reset : Reset
output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}}
wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clock_gaterOut.member.allClocks_uncore.reset
invalidate clock_gaterOut.member.allClocks_uncore.clock
wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clock_gaterIn.member.allClocks_uncore.reset
invalidate clock_gaterIn.member.allClocks_uncore.clock
connect clock_gaterOut, clock_gaterIn
wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate clock_gaterIn_1.d.bits.corrupt
invalidate clock_gaterIn_1.d.bits.data
invalidate clock_gaterIn_1.d.bits.denied
invalidate clock_gaterIn_1.d.bits.sink
invalidate clock_gaterIn_1.d.bits.source
invalidate clock_gaterIn_1.d.bits.size
invalidate clock_gaterIn_1.d.bits.param
invalidate clock_gaterIn_1.d.bits.opcode
invalidate clock_gaterIn_1.d.valid
invalidate clock_gaterIn_1.d.ready
invalidate clock_gaterIn_1.a.bits.corrupt
invalidate clock_gaterIn_1.a.bits.data
invalidate clock_gaterIn_1.a.bits.mask
invalidate clock_gaterIn_1.a.bits.address
invalidate clock_gaterIn_1.a.bits.source
invalidate clock_gaterIn_1.a.bits.size
invalidate clock_gaterIn_1.a.bits.param
invalidate clock_gaterIn_1.a.bits.opcode
invalidate clock_gaterIn_1.a.valid
invalidate clock_gaterIn_1.a.ready
inst monitor of TLMonitor_105
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt
connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data
connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied
connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink
connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source
connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size
connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param
connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode
connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid
connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready
connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt
connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data
connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask
connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address
connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source
connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size
connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param
connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode
connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid
connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready
connect auto.clock_gater_out, clock_gaterOut
connect clock_gaterIn, auto.clock_gater_in_0
connect clock_gaterIn_1, auto.clock_gater_in_1
inst regs_0 of AsyncResetRegVec_w1_i1
connect regs_0.clock, clock
connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset
connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, clock_gaterIn_1.a.bits.data
connect in.bits.mask, clock_gaterIn_1.a.bits.mask
connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source
connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h0))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[1]
wire out_wivalid : UInt<1>[1]
wire out_roready : UInt<1>[1]
wire out_woready : UInt<1>[1]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_2 = bits(out_front.bits.data, 0, 0)
connect regs_0.io.en, out_f_woready
connect regs_0.io.d, _out_T_2
node _out_T_3 = eq(out_rimask, UInt<1>(0h0))
node _out_T_4 = eq(out_wimask, UInt<1>(0h0))
node _out_T_5 = eq(out_romask, UInt<1>(0h0))
node _out_T_6 = eq(out_womask, UInt<1>(0h0))
node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0))
node _out_T_8 = bits(_out_T_7, 0, 0)
node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rifireMux_WIRE : UInt<1>[1]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wifireMux_WIRE : UInt<1>[1]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rofireMux_WIRE : UInt<1>[1]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wofireMux_WIRE : UInt<1>[1]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE : UInt<1>[1]
connect _out_out_bits_data_WIRE[0], _out_T_1
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0])
node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE_1 : UInt<1>[1]
connect _out_out_bits_data_WIRE_1[0], _out_T_8
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, clock_gaterIn_1.a.valid
connect clock_gaterIn_1.a.ready, in.ready
connect clock_gaterIn_1.d.valid, out.valid
connect out.ready, clock_gaterIn_1.d.ready
wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0)
connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0)
invalidate clock_gaterIn_d_bits_d.data
connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0)
connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt
connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data
connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied
connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink
connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source
connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size
connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param
connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode
connect clock_gaterIn_1.d.bits.data, out.bits.data
node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
extmodule plusarg_reader_285 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_286 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TileClockGater( // @[TileClockGater.scala:27:25]
input clock, // @[TileClockGater.scala:27:25]
input reset, // @[TileClockGater.scala:27:25]
output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25]
);
wire _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _regs_0_io_q; // @[TileClockGater.scala:33:53]
wire in_bits_read = auto_clock_gater_in_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
wire _out_T_1 = auto_clock_gater_in_1_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24]
assign _out_wofireMux_T_1 = ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24]
wire [2:0] monitor_io_in_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19]
TLMonitor_105 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_clock_gater_in_1_d_ready),
.io_in_a_valid (auto_clock_gater_in_1_a_valid),
.io_in_a_bits_opcode (auto_clock_gater_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_clock_gater_in_1_a_bits_param),
.io_in_a_bits_size (auto_clock_gater_in_1_a_bits_size),
.io_in_a_bits_source (auto_clock_gater_in_1_a_bits_source),
.io_in_a_bits_address (auto_clock_gater_in_1_a_bits_address),
.io_in_a_bits_mask (auto_clock_gater_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_clock_gater_in_1_a_bits_corrupt),
.io_in_d_ready (auto_clock_gater_in_1_d_ready),
.io_in_d_valid (auto_clock_gater_in_1_a_valid),
.io_in_d_bits_opcode (monitor_io_in_d_bits_opcode), // @[RegisterRouter.scala:105:19]
.io_in_d_bits_size (auto_clock_gater_in_1_a_bits_size),
.io_in_d_bits_source (auto_clock_gater_in_1_a_bits_source)
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53]
.clock (clock),
.reset (auto_clock_gater_in_0_member_allClocks_uncore_reset),
.io_d (auto_clock_gater_in_1_a_bits_data[0]), // @[RegisterRouter.scala:87:24]
.io_q (_regs_0_io_q),
.io_en (auto_clock_gater_in_1_a_valid & auto_clock_gater_in_1_d_ready & _out_wofireMux_T_1 & _out_T_1 & auto_clock_gater_in_1_a_bits_mask[0]) // @[RegisterRouter.scala:87:24]
); // @[TileClockGater.scala:33:53]
assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_opcode = monitor_io_in_d_bits_opcode; // @[RegisterRouter.scala:105:19]
assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_in_1_d_bits_data = {63'h0, _out_T_1 & _regs_0_io_q}; // @[RegisterRouter.scala:87:24]
assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25]
assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSink_a32d64s2k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<3>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<3>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
invalidate nodeIn.e.safe.sink_reset_n
invalidate nodeIn.e.safe.source_reset_n
invalidate nodeIn.e.safe.widx_valid
invalidate nodeIn.e.safe.ridx_valid
invalidate nodeIn.e.widx
invalidate nodeIn.e.ridx
invalidate nodeIn.e.mem[0].sink
invalidate nodeIn.e.mem[1].sink
invalidate nodeIn.e.mem[2].sink
invalidate nodeIn.e.mem[3].sink
invalidate nodeIn.e.mem[4].sink
invalidate nodeIn.e.mem[5].sink
invalidate nodeIn.e.mem[6].sink
invalidate nodeIn.e.mem[7].sink
invalidate nodeIn.d.safe.sink_reset_n
invalidate nodeIn.d.safe.source_reset_n
invalidate nodeIn.d.safe.widx_valid
invalidate nodeIn.d.safe.ridx_valid
invalidate nodeIn.d.widx
invalidate nodeIn.d.ridx
invalidate nodeIn.d.mem[0].corrupt
invalidate nodeIn.d.mem[0].data
invalidate nodeIn.d.mem[0].denied
invalidate nodeIn.d.mem[0].sink
invalidate nodeIn.d.mem[0].source
invalidate nodeIn.d.mem[0].size
invalidate nodeIn.d.mem[0].param
invalidate nodeIn.d.mem[0].opcode
invalidate nodeIn.d.mem[1].corrupt
invalidate nodeIn.d.mem[1].data
invalidate nodeIn.d.mem[1].denied
invalidate nodeIn.d.mem[1].sink
invalidate nodeIn.d.mem[1].source
invalidate nodeIn.d.mem[1].size
invalidate nodeIn.d.mem[1].param
invalidate nodeIn.d.mem[1].opcode
invalidate nodeIn.d.mem[2].corrupt
invalidate nodeIn.d.mem[2].data
invalidate nodeIn.d.mem[2].denied
invalidate nodeIn.d.mem[2].sink
invalidate nodeIn.d.mem[2].source
invalidate nodeIn.d.mem[2].size
invalidate nodeIn.d.mem[2].param
invalidate nodeIn.d.mem[2].opcode
invalidate nodeIn.d.mem[3].corrupt
invalidate nodeIn.d.mem[3].data
invalidate nodeIn.d.mem[3].denied
invalidate nodeIn.d.mem[3].sink
invalidate nodeIn.d.mem[3].source
invalidate nodeIn.d.mem[3].size
invalidate nodeIn.d.mem[3].param
invalidate nodeIn.d.mem[3].opcode
invalidate nodeIn.d.mem[4].corrupt
invalidate nodeIn.d.mem[4].data
invalidate nodeIn.d.mem[4].denied
invalidate nodeIn.d.mem[4].sink
invalidate nodeIn.d.mem[4].source
invalidate nodeIn.d.mem[4].size
invalidate nodeIn.d.mem[4].param
invalidate nodeIn.d.mem[4].opcode
invalidate nodeIn.d.mem[5].corrupt
invalidate nodeIn.d.mem[5].data
invalidate nodeIn.d.mem[5].denied
invalidate nodeIn.d.mem[5].sink
invalidate nodeIn.d.mem[5].source
invalidate nodeIn.d.mem[5].size
invalidate nodeIn.d.mem[5].param
invalidate nodeIn.d.mem[5].opcode
invalidate nodeIn.d.mem[6].corrupt
invalidate nodeIn.d.mem[6].data
invalidate nodeIn.d.mem[6].denied
invalidate nodeIn.d.mem[6].sink
invalidate nodeIn.d.mem[6].source
invalidate nodeIn.d.mem[6].size
invalidate nodeIn.d.mem[6].param
invalidate nodeIn.d.mem[6].opcode
invalidate nodeIn.d.mem[7].corrupt
invalidate nodeIn.d.mem[7].data
invalidate nodeIn.d.mem[7].denied
invalidate nodeIn.d.mem[7].sink
invalidate nodeIn.d.mem[7].source
invalidate nodeIn.d.mem[7].size
invalidate nodeIn.d.mem[7].param
invalidate nodeIn.d.mem[7].opcode
invalidate nodeIn.c.safe.sink_reset_n
invalidate nodeIn.c.safe.source_reset_n
invalidate nodeIn.c.safe.widx_valid
invalidate nodeIn.c.safe.ridx_valid
invalidate nodeIn.c.widx
invalidate nodeIn.c.ridx
invalidate nodeIn.c.mem[0].corrupt
invalidate nodeIn.c.mem[0].data
invalidate nodeIn.c.mem[0].address
invalidate nodeIn.c.mem[0].source
invalidate nodeIn.c.mem[0].size
invalidate nodeIn.c.mem[0].param
invalidate nodeIn.c.mem[0].opcode
invalidate nodeIn.c.mem[1].corrupt
invalidate nodeIn.c.mem[1].data
invalidate nodeIn.c.mem[1].address
invalidate nodeIn.c.mem[1].source
invalidate nodeIn.c.mem[1].size
invalidate nodeIn.c.mem[1].param
invalidate nodeIn.c.mem[1].opcode
invalidate nodeIn.c.mem[2].corrupt
invalidate nodeIn.c.mem[2].data
invalidate nodeIn.c.mem[2].address
invalidate nodeIn.c.mem[2].source
invalidate nodeIn.c.mem[2].size
invalidate nodeIn.c.mem[2].param
invalidate nodeIn.c.mem[2].opcode
invalidate nodeIn.c.mem[3].corrupt
invalidate nodeIn.c.mem[3].data
invalidate nodeIn.c.mem[3].address
invalidate nodeIn.c.mem[3].source
invalidate nodeIn.c.mem[3].size
invalidate nodeIn.c.mem[3].param
invalidate nodeIn.c.mem[3].opcode
invalidate nodeIn.c.mem[4].corrupt
invalidate nodeIn.c.mem[4].data
invalidate nodeIn.c.mem[4].address
invalidate nodeIn.c.mem[4].source
invalidate nodeIn.c.mem[4].size
invalidate nodeIn.c.mem[4].param
invalidate nodeIn.c.mem[4].opcode
invalidate nodeIn.c.mem[5].corrupt
invalidate nodeIn.c.mem[5].data
invalidate nodeIn.c.mem[5].address
invalidate nodeIn.c.mem[5].source
invalidate nodeIn.c.mem[5].size
invalidate nodeIn.c.mem[5].param
invalidate nodeIn.c.mem[5].opcode
invalidate nodeIn.c.mem[6].corrupt
invalidate nodeIn.c.mem[6].data
invalidate nodeIn.c.mem[6].address
invalidate nodeIn.c.mem[6].source
invalidate nodeIn.c.mem[6].size
invalidate nodeIn.c.mem[6].param
invalidate nodeIn.c.mem[6].opcode
invalidate nodeIn.c.mem[7].corrupt
invalidate nodeIn.c.mem[7].data
invalidate nodeIn.c.mem[7].address
invalidate nodeIn.c.mem[7].source
invalidate nodeIn.c.mem[7].size
invalidate nodeIn.c.mem[7].param
invalidate nodeIn.c.mem[7].opcode
invalidate nodeIn.b.safe.sink_reset_n
invalidate nodeIn.b.safe.source_reset_n
invalidate nodeIn.b.safe.widx_valid
invalidate nodeIn.b.safe.ridx_valid
invalidate nodeIn.b.widx
invalidate nodeIn.b.ridx
invalidate nodeIn.b.mem[0].corrupt
invalidate nodeIn.b.mem[0].data
invalidate nodeIn.b.mem[0].mask
invalidate nodeIn.b.mem[0].address
invalidate nodeIn.b.mem[0].source
invalidate nodeIn.b.mem[0].size
invalidate nodeIn.b.mem[0].param
invalidate nodeIn.b.mem[0].opcode
invalidate nodeIn.b.mem[1].corrupt
invalidate nodeIn.b.mem[1].data
invalidate nodeIn.b.mem[1].mask
invalidate nodeIn.b.mem[1].address
invalidate nodeIn.b.mem[1].source
invalidate nodeIn.b.mem[1].size
invalidate nodeIn.b.mem[1].param
invalidate nodeIn.b.mem[1].opcode
invalidate nodeIn.b.mem[2].corrupt
invalidate nodeIn.b.mem[2].data
invalidate nodeIn.b.mem[2].mask
invalidate nodeIn.b.mem[2].address
invalidate nodeIn.b.mem[2].source
invalidate nodeIn.b.mem[2].size
invalidate nodeIn.b.mem[2].param
invalidate nodeIn.b.mem[2].opcode
invalidate nodeIn.b.mem[3].corrupt
invalidate nodeIn.b.mem[3].data
invalidate nodeIn.b.mem[3].mask
invalidate nodeIn.b.mem[3].address
invalidate nodeIn.b.mem[3].source
invalidate nodeIn.b.mem[3].size
invalidate nodeIn.b.mem[3].param
invalidate nodeIn.b.mem[3].opcode
invalidate nodeIn.b.mem[4].corrupt
invalidate nodeIn.b.mem[4].data
invalidate nodeIn.b.mem[4].mask
invalidate nodeIn.b.mem[4].address
invalidate nodeIn.b.mem[4].source
invalidate nodeIn.b.mem[4].size
invalidate nodeIn.b.mem[4].param
invalidate nodeIn.b.mem[4].opcode
invalidate nodeIn.b.mem[5].corrupt
invalidate nodeIn.b.mem[5].data
invalidate nodeIn.b.mem[5].mask
invalidate nodeIn.b.mem[5].address
invalidate nodeIn.b.mem[5].source
invalidate nodeIn.b.mem[5].size
invalidate nodeIn.b.mem[5].param
invalidate nodeIn.b.mem[5].opcode
invalidate nodeIn.b.mem[6].corrupt
invalidate nodeIn.b.mem[6].data
invalidate nodeIn.b.mem[6].mask
invalidate nodeIn.b.mem[6].address
invalidate nodeIn.b.mem[6].source
invalidate nodeIn.b.mem[6].size
invalidate nodeIn.b.mem[6].param
invalidate nodeIn.b.mem[6].opcode
invalidate nodeIn.b.mem[7].corrupt
invalidate nodeIn.b.mem[7].data
invalidate nodeIn.b.mem[7].mask
invalidate nodeIn.b.mem[7].address
invalidate nodeIn.b.mem[7].source
invalidate nodeIn.b.mem[7].size
invalidate nodeIn.b.mem[7].param
invalidate nodeIn.b.mem[7].opcode
invalidate nodeIn.a.safe.sink_reset_n
invalidate nodeIn.a.safe.source_reset_n
invalidate nodeIn.a.safe.widx_valid
invalidate nodeIn.a.safe.ridx_valid
invalidate nodeIn.a.widx
invalidate nodeIn.a.ridx
invalidate nodeIn.a.mem[0].corrupt
invalidate nodeIn.a.mem[0].data
invalidate nodeIn.a.mem[0].mask
invalidate nodeIn.a.mem[0].address
invalidate nodeIn.a.mem[0].source
invalidate nodeIn.a.mem[0].size
invalidate nodeIn.a.mem[0].param
invalidate nodeIn.a.mem[0].opcode
invalidate nodeIn.a.mem[1].corrupt
invalidate nodeIn.a.mem[1].data
invalidate nodeIn.a.mem[1].mask
invalidate nodeIn.a.mem[1].address
invalidate nodeIn.a.mem[1].source
invalidate nodeIn.a.mem[1].size
invalidate nodeIn.a.mem[1].param
invalidate nodeIn.a.mem[1].opcode
invalidate nodeIn.a.mem[2].corrupt
invalidate nodeIn.a.mem[2].data
invalidate nodeIn.a.mem[2].mask
invalidate nodeIn.a.mem[2].address
invalidate nodeIn.a.mem[2].source
invalidate nodeIn.a.mem[2].size
invalidate nodeIn.a.mem[2].param
invalidate nodeIn.a.mem[2].opcode
invalidate nodeIn.a.mem[3].corrupt
invalidate nodeIn.a.mem[3].data
invalidate nodeIn.a.mem[3].mask
invalidate nodeIn.a.mem[3].address
invalidate nodeIn.a.mem[3].source
invalidate nodeIn.a.mem[3].size
invalidate nodeIn.a.mem[3].param
invalidate nodeIn.a.mem[3].opcode
invalidate nodeIn.a.mem[4].corrupt
invalidate nodeIn.a.mem[4].data
invalidate nodeIn.a.mem[4].mask
invalidate nodeIn.a.mem[4].address
invalidate nodeIn.a.mem[4].source
invalidate nodeIn.a.mem[4].size
invalidate nodeIn.a.mem[4].param
invalidate nodeIn.a.mem[4].opcode
invalidate nodeIn.a.mem[5].corrupt
invalidate nodeIn.a.mem[5].data
invalidate nodeIn.a.mem[5].mask
invalidate nodeIn.a.mem[5].address
invalidate nodeIn.a.mem[5].source
invalidate nodeIn.a.mem[5].size
invalidate nodeIn.a.mem[5].param
invalidate nodeIn.a.mem[5].opcode
invalidate nodeIn.a.mem[6].corrupt
invalidate nodeIn.a.mem[6].data
invalidate nodeIn.a.mem[6].mask
invalidate nodeIn.a.mem[6].address
invalidate nodeIn.a.mem[6].source
invalidate nodeIn.a.mem[6].size
invalidate nodeIn.a.mem[6].param
invalidate nodeIn.a.mem[6].opcode
invalidate nodeIn.a.mem[7].corrupt
invalidate nodeIn.a.mem[7].data
invalidate nodeIn.a.mem[7].mask
invalidate nodeIn.a.mem[7].address
invalidate nodeIn.a.mem[7].source
invalidate nodeIn.a.mem[7].size
invalidate nodeIn.a.mem[7].param
invalidate nodeIn.a.mem[7].opcode
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_sink of AsyncQueueSink_TLBundleA_a32d64s2k3z4c
connect nodeOut_a_sink.clock, clock
connect nodeOut_a_sink.reset, reset
connect nodeOut_a_sink.io.async, nodeIn.a
connect nodeOut.a.bits, nodeOut_a_sink.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_sink.io.deq.valid
connect nodeOut_a_sink.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_source of AsyncQueueSource_TLBundleD_a32d64s2k3z4c
connect nodeIn_d_source.clock, clock
connect nodeIn_d_source.reset, reset
connect nodeIn_d_source.io.enq, nodeOut.d
connect nodeIn_d_source.io.async.safe.sink_reset_n, nodeIn.d.safe.sink_reset_n
connect nodeIn.d.safe.source_reset_n, nodeIn_d_source.io.async.safe.source_reset_n
connect nodeIn.d.safe.widx_valid, nodeIn_d_source.io.async.safe.widx_valid
connect nodeIn_d_source.io.async.safe.ridx_valid, nodeIn.d.safe.ridx_valid
connect nodeIn.d.widx, nodeIn_d_source.io.async.widx
connect nodeIn_d_source.io.async.ridx, nodeIn.d.ridx
connect nodeIn.d.mem, nodeIn_d_source.io.async.mem
node _T = and(nodeOut.a.valid, nodeOut.a.ready)
node _T_1 = eq(nodeOut.a.ready, UInt<1>(0h0))
node _T_2 = and(nodeOut.a.valid, _T_1)
node _T_3 = eq(nodeOut.a.valid, UInt<1>(0h0))
node _T_4 = and(_T_3, nodeOut.a.ready)
node _T_5 = eq(nodeOut.a.valid, UInt<1>(0h0))
node _T_6 = eq(nodeOut.a.ready, UInt<1>(0h0))
node _T_7 = and(_T_5, _T_6)
node _T_8 = and(nodeOut.d.valid, nodeOut.d.ready)
node _T_9 = eq(nodeOut.d.ready, UInt<1>(0h0))
node _T_10 = and(nodeOut.d.valid, _T_9)
node _T_11 = eq(nodeOut.d.valid, UInt<1>(0h0))
node _T_12 = and(_T_11, nodeOut.d.ready)
node _T_13 = eq(nodeOut.d.valid, UInt<1>(0h0))
node _T_14 = eq(nodeOut.d.ready, UInt<1>(0h0))
node _T_15 = and(_T_13, _T_14)
inst nodeIn_b_source of AsyncQueueSource_TLBundleB_a32d64s2k3z4c
connect nodeIn_b_source.clock, clock
connect nodeIn_b_source.reset, reset
connect nodeIn_b_source.io.enq, nodeOut.b
connect nodeIn_b_source.io.async.safe.sink_reset_n, nodeIn.b.safe.sink_reset_n
connect nodeIn.b.safe.source_reset_n, nodeIn_b_source.io.async.safe.source_reset_n
connect nodeIn.b.safe.widx_valid, nodeIn_b_source.io.async.safe.widx_valid
connect nodeIn_b_source.io.async.safe.ridx_valid, nodeIn.b.safe.ridx_valid
connect nodeIn.b.widx, nodeIn_b_source.io.async.widx
connect nodeIn_b_source.io.async.ridx, nodeIn.b.ridx
connect nodeIn.b.mem, nodeIn_b_source.io.async.mem
inst nodeOut_c_sink of AsyncQueueSink_TLBundleC_a32d64s2k3z4c
connect nodeOut_c_sink.clock, clock
connect nodeOut_c_sink.reset, reset
connect nodeOut_c_sink.io.async, nodeIn.c
connect nodeOut.c.bits, nodeOut_c_sink.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_sink.io.deq.valid
connect nodeOut_c_sink.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_sink of AsyncQueueSink_TLBundleE_a32d64s2k3z4c
connect nodeOut_e_sink.clock, clock
connect nodeOut_e_sink.reset, reset
connect nodeOut_e_sink.io.async, nodeIn.e
connect nodeOut.e.bits, nodeOut_e_sink.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_sink.io.deq.valid
connect nodeOut_e_sink.io.deq.ready, nodeOut.e.ready
node _T_16 = and(nodeOut.b.valid, nodeOut.b.ready)
node _T_17 = eq(nodeOut.b.ready, UInt<1>(0h0))
node _T_18 = and(nodeOut.b.valid, _T_17)
node _T_19 = eq(nodeOut.b.valid, UInt<1>(0h0))
node _T_20 = and(_T_19, nodeOut.b.ready)
node _T_21 = eq(nodeOut.b.valid, UInt<1>(0h0))
node _T_22 = eq(nodeOut.b.ready, UInt<1>(0h0))
node _T_23 = and(_T_21, _T_22)
node _T_24 = and(nodeOut.c.valid, nodeOut.c.ready)
node _T_25 = eq(nodeOut.c.ready, UInt<1>(0h0))
node _T_26 = and(nodeOut.c.valid, _T_25)
node _T_27 = eq(nodeOut.c.valid, UInt<1>(0h0))
node _T_28 = and(_T_27, nodeOut.c.ready)
node _T_29 = eq(nodeOut.c.valid, UInt<1>(0h0))
node _T_30 = eq(nodeOut.c.ready, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = and(nodeOut.e.valid, nodeOut.e.ready)
node _T_33 = eq(nodeOut.e.ready, UInt<1>(0h0))
node _T_34 = and(nodeOut.e.valid, _T_33)
node _T_35 = eq(nodeOut.e.valid, UInt<1>(0h0))
node _T_36 = and(_T_35, nodeOut.e.ready)
node _T_37 = eq(nodeOut.e.valid, UInt<1>(0h0))
node _T_38 = eq(nodeOut.e.ready, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38) | module TLAsyncCrossingSink_a32d64s2k3z4c( // @[AsyncCrossing.scala:59:9]
input clock, // @[AsyncCrossing.scala:59:9]
input reset, // @[AsyncCrossing.scala:59:9]
input [2:0] auto_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_0_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_0_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_0_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_1_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_1_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_1_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_1_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_1_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_1_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_2_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_2_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_2_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_2_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_2_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_2_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_3_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_3_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_3_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_3_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_3_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_3_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_4_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_4_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_4_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_4_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_4_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_4_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_5_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_5_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_5_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_5_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_5_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_5_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_6_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_6_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_6_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_6_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_6_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_6_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_mem_7_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_mem_7_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_mem_7_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_mem_7_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_mem_7_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_mem_7_data, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_a_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_widx, // @[LazyModuleImp.scala:107:25]
output auto_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_0_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_1_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_1_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_2_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_2_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_3_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_3_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_4_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_4_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_5_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_5_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_6_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_6_address, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_mem_7_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_mem_7_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_b_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_widx, // @[LazyModuleImp.scala:107:25]
input auto_in_b_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_b_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_b_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_in_b_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_0_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_0_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_0_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_0_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_1_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_1_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_1_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_1_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_1_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_2_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_2_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_2_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_2_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_2_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_3_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_3_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_3_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_3_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_3_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_4_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_4_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_4_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_4_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_4_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_5_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_5_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_5_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_5_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_5_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_6_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_6_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_6_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_6_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_6_data, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_mem_7_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_mem_7_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_mem_7_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_mem_7_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_mem_7_data, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_c_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_widx, // @[LazyModuleImp.scala:107:25]
output auto_in_c_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_c_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_c_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_in_c_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_0_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_0_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_0_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_0_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_1_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_1_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_1_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_1_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_1_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_1_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_1_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_2_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_2_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_2_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_2_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_2_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_2_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_2_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_3_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_3_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_3_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_3_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_3_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_3_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_3_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_4_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_4_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_4_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_4_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_4_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_4_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_4_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_5_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_5_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_5_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_5_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_5_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_5_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_5_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_6_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_6_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_6_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_6_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_6_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_6_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_6_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_7_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_mem_7_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_mem_7_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_mem_7_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_7_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_mem_7_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_mem_7_corrupt, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_d_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_widx, // @[LazyModuleImp.scala:107:25]
input auto_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_0_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_1_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_2_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_3_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_4_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_5_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_6_sink, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_mem_7_sink, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_e_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_e_widx, // @[LazyModuleImp.scala:107:25]
output auto_in_e_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_e_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_in_e_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_in_e_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [2:0] auto_in_a_mem_0_opcode_0 = auto_in_a_mem_0_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_0_param_0 = auto_in_a_mem_0_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_0_size_0 = auto_in_a_mem_0_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_0_source_0 = auto_in_a_mem_0_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_0_address_0 = auto_in_a_mem_0_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_0_mask_0 = auto_in_a_mem_0_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_0_data_0 = auto_in_a_mem_0_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_1_opcode_0 = auto_in_a_mem_1_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_1_param_0 = auto_in_a_mem_1_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_1_size_0 = auto_in_a_mem_1_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_1_source_0 = auto_in_a_mem_1_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_1_address_0 = auto_in_a_mem_1_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_1_mask_0 = auto_in_a_mem_1_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_1_data_0 = auto_in_a_mem_1_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_2_opcode_0 = auto_in_a_mem_2_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_2_param_0 = auto_in_a_mem_2_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_2_size_0 = auto_in_a_mem_2_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_2_source_0 = auto_in_a_mem_2_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_2_address_0 = auto_in_a_mem_2_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_2_mask_0 = auto_in_a_mem_2_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_2_data_0 = auto_in_a_mem_2_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_3_opcode_0 = auto_in_a_mem_3_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_3_param_0 = auto_in_a_mem_3_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_3_size_0 = auto_in_a_mem_3_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_3_source_0 = auto_in_a_mem_3_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_3_address_0 = auto_in_a_mem_3_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_3_mask_0 = auto_in_a_mem_3_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_3_data_0 = auto_in_a_mem_3_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_4_opcode_0 = auto_in_a_mem_4_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_4_param_0 = auto_in_a_mem_4_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_4_size_0 = auto_in_a_mem_4_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_4_source_0 = auto_in_a_mem_4_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_4_address_0 = auto_in_a_mem_4_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_4_mask_0 = auto_in_a_mem_4_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_4_data_0 = auto_in_a_mem_4_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_5_opcode_0 = auto_in_a_mem_5_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_5_param_0 = auto_in_a_mem_5_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_5_size_0 = auto_in_a_mem_5_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_5_source_0 = auto_in_a_mem_5_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_5_address_0 = auto_in_a_mem_5_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_5_mask_0 = auto_in_a_mem_5_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_5_data_0 = auto_in_a_mem_5_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_6_opcode_0 = auto_in_a_mem_6_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_6_param_0 = auto_in_a_mem_6_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_6_size_0 = auto_in_a_mem_6_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_6_source_0 = auto_in_a_mem_6_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_6_address_0 = auto_in_a_mem_6_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_6_mask_0 = auto_in_a_mem_6_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_6_data_0 = auto_in_a_mem_6_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_7_opcode_0 = auto_in_a_mem_7_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_a_mem_7_param_0 = auto_in_a_mem_7_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_mem_7_size_0 = auto_in_a_mem_7_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_a_mem_7_source_0 = auto_in_a_mem_7_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_a_mem_7_address_0 = auto_in_a_mem_7_address; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_a_mem_7_mask_0 = auto_in_a_mem_7_mask; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_a_mem_7_data_0 = auto_in_a_mem_7_data; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_widx_0 = auto_in_a_widx; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_safe_widx_valid_0 = auto_in_a_safe_widx_valid; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_safe_source_reset_n_0 = auto_in_a_safe_source_reset_n; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_ridx_0 = auto_in_b_ridx; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_safe_ridx_valid_0 = auto_in_b_safe_ridx_valid; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_safe_sink_reset_n_0 = auto_in_b_safe_sink_reset_n; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_0_opcode_0 = auto_in_c_mem_0_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_0_param_0 = auto_in_c_mem_0_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_0_size_0 = auto_in_c_mem_0_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_0_source_0 = auto_in_c_mem_0_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_0_address_0 = auto_in_c_mem_0_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_0_data_0 = auto_in_c_mem_0_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_1_opcode_0 = auto_in_c_mem_1_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_1_param_0 = auto_in_c_mem_1_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_1_size_0 = auto_in_c_mem_1_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_1_source_0 = auto_in_c_mem_1_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_1_address_0 = auto_in_c_mem_1_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_1_data_0 = auto_in_c_mem_1_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_2_opcode_0 = auto_in_c_mem_2_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_2_param_0 = auto_in_c_mem_2_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_2_size_0 = auto_in_c_mem_2_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_2_source_0 = auto_in_c_mem_2_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_2_address_0 = auto_in_c_mem_2_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_2_data_0 = auto_in_c_mem_2_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_3_opcode_0 = auto_in_c_mem_3_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_3_param_0 = auto_in_c_mem_3_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_3_size_0 = auto_in_c_mem_3_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_3_source_0 = auto_in_c_mem_3_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_3_address_0 = auto_in_c_mem_3_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_3_data_0 = auto_in_c_mem_3_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_4_opcode_0 = auto_in_c_mem_4_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_4_param_0 = auto_in_c_mem_4_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_4_size_0 = auto_in_c_mem_4_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_4_source_0 = auto_in_c_mem_4_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_4_address_0 = auto_in_c_mem_4_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_4_data_0 = auto_in_c_mem_4_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_5_opcode_0 = auto_in_c_mem_5_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_5_param_0 = auto_in_c_mem_5_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_5_size_0 = auto_in_c_mem_5_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_5_source_0 = auto_in_c_mem_5_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_5_address_0 = auto_in_c_mem_5_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_5_data_0 = auto_in_c_mem_5_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_6_opcode_0 = auto_in_c_mem_6_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_6_param_0 = auto_in_c_mem_6_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_6_size_0 = auto_in_c_mem_6_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_6_source_0 = auto_in_c_mem_6_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_6_address_0 = auto_in_c_mem_6_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_6_data_0 = auto_in_c_mem_6_data; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_7_opcode_0 = auto_in_c_mem_7_opcode; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_c_mem_7_param_0 = auto_in_c_mem_7_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_mem_7_size_0 = auto_in_c_mem_7_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_c_mem_7_source_0 = auto_in_c_mem_7_source; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_c_mem_7_address_0 = auto_in_c_mem_7_address; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_c_mem_7_data_0 = auto_in_c_mem_7_data; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_widx_0 = auto_in_c_widx; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_safe_widx_valid_0 = auto_in_c_safe_widx_valid; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_safe_source_reset_n_0 = auto_in_c_safe_source_reset_n; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_ridx_0 = auto_in_d_ridx; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_safe_ridx_valid_0 = auto_in_d_safe_ridx_valid; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_safe_sink_reset_n_0 = auto_in_d_safe_sink_reset_n; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_0_sink_0 = auto_in_e_mem_0_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_1_sink_0 = auto_in_e_mem_1_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_2_sink_0 = auto_in_e_mem_2_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_3_sink_0 = auto_in_e_mem_3_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_4_sink_0 = auto_in_e_mem_4_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_5_sink_0 = auto_in_e_mem_5_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_6_sink_0 = auto_in_e_mem_6_sink; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_e_mem_7_sink_0 = auto_in_e_mem_7_sink; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_e_widx_0 = auto_in_e_widx; // @[AsyncCrossing.scala:59:9]
wire auto_in_e_safe_widx_valid_0 = auto_in_e_safe_widx_valid; // @[AsyncCrossing.scala:59:9]
wire auto_in_e_safe_source_reset_n_0 = auto_in_e_safe_source_reset_n; // @[AsyncCrossing.scala:59:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AsyncCrossing.scala:59:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[AsyncCrossing.scala:59:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[AsyncCrossing.scala:59:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AsyncCrossing.scala:59:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AsyncCrossing.scala:59:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AsyncCrossing.scala:59:9]
wire auto_out_e_ready = 1'h1; // @[AsyncQueue.scala:211:22]
wire nodeOut_e_ready = 1'h1; // @[AsyncQueue.scala:211:22]
wire [63:0] auto_in_b_mem_0_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_1_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_2_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_3_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_4_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_5_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_6_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_b_mem_7_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_b_mem_0_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_1_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_2_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_3_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_4_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_5_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_6_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_mem_7_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [7:0] auto_in_b_mem_0_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_1_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_2_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_3_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_4_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_5_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_6_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_in_b_mem_7_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_b_mem_0_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_1_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_2_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_3_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_4_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_5_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_6_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_mem_7_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [1:0] auto_in_b_mem_0_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_1_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_2_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_3_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_4_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_5_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_6_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_7_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_b_bits_source = 2'h0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_b_mem_0_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_1_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_2_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_3_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_4_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_5_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_6_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_7_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_in_b_mem_0_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_1_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_2_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_3_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_4_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_5_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_6_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_mem_7_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_b_mem_0_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_1_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_2_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_3_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_4_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_5_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_6_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_mem_7_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [2:0] auto_in_b_mem_0_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_1_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_2_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_3_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_4_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_5_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_6_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_b_mem_7_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_b_mem_0_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_1_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_2_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_3_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_4_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_5_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_6_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_mem_7_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire auto_in_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire auto_out_b_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_1_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_2_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_3_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_4_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_5_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_6_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_mem_7_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_1_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_2_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_3_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_4_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_5_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_6_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_b_mem_7_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_1_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_2_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_3_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_4_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_5_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_6_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_c_mem_7_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeIn_a_mem_0_opcode = auto_in_a_mem_0_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_0_param = auto_in_a_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_0_size = auto_in_a_mem_0_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_0_source = auto_in_a_mem_0_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_0_address = auto_in_a_mem_0_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_0_mask = auto_in_a_mem_0_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_0_data = auto_in_a_mem_0_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_1_opcode = auto_in_a_mem_1_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_1_param = auto_in_a_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_1_size = auto_in_a_mem_1_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_1_source = auto_in_a_mem_1_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_1_address = auto_in_a_mem_1_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_1_mask = auto_in_a_mem_1_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_1_data = auto_in_a_mem_1_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_2_opcode = auto_in_a_mem_2_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_2_param = auto_in_a_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_2_size = auto_in_a_mem_2_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_2_source = auto_in_a_mem_2_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_2_address = auto_in_a_mem_2_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_2_mask = auto_in_a_mem_2_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_2_data = auto_in_a_mem_2_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_3_opcode = auto_in_a_mem_3_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_3_param = auto_in_a_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_3_size = auto_in_a_mem_3_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_3_source = auto_in_a_mem_3_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_3_address = auto_in_a_mem_3_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_3_mask = auto_in_a_mem_3_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_3_data = auto_in_a_mem_3_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_4_opcode = auto_in_a_mem_4_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_4_param = auto_in_a_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_4_size = auto_in_a_mem_4_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_4_source = auto_in_a_mem_4_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_4_address = auto_in_a_mem_4_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_4_mask = auto_in_a_mem_4_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_4_data = auto_in_a_mem_4_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_5_opcode = auto_in_a_mem_5_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_5_param = auto_in_a_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_5_size = auto_in_a_mem_5_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_5_source = auto_in_a_mem_5_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_5_address = auto_in_a_mem_5_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_5_mask = auto_in_a_mem_5_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_5_data = auto_in_a_mem_5_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_6_opcode = auto_in_a_mem_6_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_6_param = auto_in_a_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_6_size = auto_in_a_mem_6_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_6_source = auto_in_a_mem_6_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_6_address = auto_in_a_mem_6_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_6_mask = auto_in_a_mem_6_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_6_data = auto_in_a_mem_6_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_7_opcode = auto_in_a_mem_7_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_a_mem_7_param = auto_in_a_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_mem_7_size = auto_in_a_mem_7_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_a_mem_7_source = auto_in_a_mem_7_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_a_mem_7_address = auto_in_a_mem_7_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] nodeIn_a_mem_7_mask = auto_in_a_mem_7_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_a_mem_7_data = auto_in_a_mem_7_data_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_a_ridx; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_a_widx = auto_in_a_widx_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_a_safe_ridx_valid; // @[MixedNode.scala:551:17]
wire nodeIn_a_safe_widx_valid = auto_in_a_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_a_safe_source_reset_n = auto_in_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_a_safe_sink_reset_n; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_0_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_0_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_1_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_1_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_2_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_2_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_3_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_3_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_4_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_4_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_5_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_5_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_6_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_6_address; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_mem_7_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_mem_7_address; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_ridx = auto_in_b_ridx_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_b_widx; // @[MixedNode.scala:551:17]
wire nodeIn_b_safe_ridx_valid = auto_in_b_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_b_safe_widx_valid; // @[MixedNode.scala:551:17]
wire nodeIn_b_safe_source_reset_n; // @[MixedNode.scala:551:17]
wire nodeIn_b_safe_sink_reset_n = auto_in_b_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_0_opcode = auto_in_c_mem_0_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_0_param = auto_in_c_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_0_size = auto_in_c_mem_0_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_0_source = auto_in_c_mem_0_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_0_address = auto_in_c_mem_0_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_0_data = auto_in_c_mem_0_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_1_opcode = auto_in_c_mem_1_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_1_param = auto_in_c_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_1_size = auto_in_c_mem_1_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_1_source = auto_in_c_mem_1_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_1_address = auto_in_c_mem_1_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_1_data = auto_in_c_mem_1_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_2_opcode = auto_in_c_mem_2_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_2_param = auto_in_c_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_2_size = auto_in_c_mem_2_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_2_source = auto_in_c_mem_2_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_2_address = auto_in_c_mem_2_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_2_data = auto_in_c_mem_2_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_3_opcode = auto_in_c_mem_3_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_3_param = auto_in_c_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_3_size = auto_in_c_mem_3_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_3_source = auto_in_c_mem_3_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_3_address = auto_in_c_mem_3_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_3_data = auto_in_c_mem_3_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_4_opcode = auto_in_c_mem_4_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_4_param = auto_in_c_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_4_size = auto_in_c_mem_4_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_4_source = auto_in_c_mem_4_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_4_address = auto_in_c_mem_4_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_4_data = auto_in_c_mem_4_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_5_opcode = auto_in_c_mem_5_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_5_param = auto_in_c_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_5_size = auto_in_c_mem_5_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_5_source = auto_in_c_mem_5_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_5_address = auto_in_c_mem_5_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_5_data = auto_in_c_mem_5_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_6_opcode = auto_in_c_mem_6_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_6_param = auto_in_c_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_6_size = auto_in_c_mem_6_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_6_source = auto_in_c_mem_6_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_6_address = auto_in_c_mem_6_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_6_data = auto_in_c_mem_6_data_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_7_opcode = auto_in_c_mem_7_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_c_mem_7_param = auto_in_c_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_mem_7_size = auto_in_c_mem_7_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeIn_c_mem_7_source = auto_in_c_mem_7_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeIn_c_mem_7_address = auto_in_c_mem_7_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeIn_c_mem_7_data = auto_in_c_mem_7_data_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_c_ridx; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_c_widx = auto_in_c_widx_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_c_safe_ridx_valid; // @[MixedNode.scala:551:17]
wire nodeIn_c_safe_widx_valid = auto_in_c_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_c_safe_source_reset_n = auto_in_c_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_c_safe_sink_reset_n; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_0_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_0_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_0_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_0_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_0_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_0_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_0_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_0_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_1_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_1_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_1_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_1_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_1_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_1_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_1_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_1_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_2_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_2_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_2_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_2_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_2_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_2_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_2_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_2_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_3_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_3_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_3_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_3_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_3_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_3_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_3_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_3_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_4_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_4_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_4_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_4_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_4_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_4_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_4_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_4_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_5_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_5_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_5_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_5_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_5_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_5_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_5_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_5_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_6_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_6_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_6_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_6_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_6_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_6_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_6_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_6_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_7_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_7_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_mem_7_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_mem_7_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_mem_7_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_7_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_mem_7_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_mem_7_corrupt; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_ridx = auto_in_d_ridx_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_d_widx; // @[MixedNode.scala:551:17]
wire nodeIn_d_safe_ridx_valid = auto_in_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_d_safe_widx_valid; // @[MixedNode.scala:551:17]
wire nodeIn_d_safe_source_reset_n; // @[MixedNode.scala:551:17]
wire nodeIn_d_safe_sink_reset_n = auto_in_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_0_sink = auto_in_e_mem_0_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_1_sink = auto_in_e_mem_1_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_2_sink = auto_in_e_mem_2_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_3_sink = auto_in_e_mem_3_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_4_sink = auto_in_e_mem_4_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_5_sink = auto_in_e_mem_5_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_6_sink = auto_in_e_mem_6_sink_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeIn_e_mem_7_sink = auto_in_e_mem_7_sink_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeIn_e_ridx; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_e_widx = auto_in_e_widx_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_e_safe_ridx_valid; // @[MixedNode.scala:551:17]
wire nodeIn_e_safe_widx_valid = auto_in_e_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_e_safe_source_reset_n = auto_in_e_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire nodeIn_e_safe_sink_reset_n; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_a_ridx_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_0_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_1_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_2_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_3_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_4_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_5_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_6_address_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_b_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_in_b_mem_7_address_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_b_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_b_widx_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_c_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_c_ridx_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_0_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_0_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_0_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_0_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_0_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_0_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_0_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_1_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_1_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_1_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_1_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_1_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_1_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_1_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_2_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_2_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_2_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_2_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_2_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_2_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_2_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_3_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_3_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_3_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_3_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_3_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_3_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_3_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_4_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_4_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_4_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_4_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_4_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_4_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_4_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_5_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_5_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_5_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_5_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_5_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_5_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_5_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_6_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_6_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_6_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_6_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_6_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_6_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_6_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_7_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_mem_7_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_in_d_mem_7_source_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_in_d_mem_7_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_7_denied_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_in_d_mem_7_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_mem_7_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_d_widx_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_e_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_in_e_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_in_e_ridx_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_a_bits_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_out_a_bits_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_a_bits_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_out_a_bits_address_0; // @[AsyncCrossing.scala:59:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_out_a_bits_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_a_bits_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_a_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_b_ready_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_c_bits_param_0; // @[AsyncCrossing.scala:59:9]
wire [3:0] auto_out_c_bits_size_0; // @[AsyncCrossing.scala:59:9]
wire [1:0] auto_out_c_bits_source_0; // @[AsyncCrossing.scala:59:9]
wire [31:0] auto_out_c_bits_address_0; // @[AsyncCrossing.scala:59:9]
wire [63:0] auto_out_c_bits_data_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_c_bits_corrupt_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_c_valid_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_d_ready_0; // @[AsyncCrossing.scala:59:9]
wire [2:0] auto_out_e_bits_sink_0; // @[AsyncCrossing.scala:59:9]
wire auto_out_e_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_a_ridx_0 = nodeIn_a_ridx; // @[AsyncCrossing.scala:59:9]
assign auto_in_a_safe_ridx_valid_0 = nodeIn_a_safe_ridx_valid; // @[AsyncCrossing.scala:59:9]
assign auto_in_a_safe_sink_reset_n_0 = nodeIn_a_safe_sink_reset_n; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_0_param_0 = nodeIn_b_mem_0_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_0_address_0 = nodeIn_b_mem_0_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_1_param_0 = nodeIn_b_mem_1_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_1_address_0 = nodeIn_b_mem_1_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_2_param_0 = nodeIn_b_mem_2_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_2_address_0 = nodeIn_b_mem_2_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_3_param_0 = nodeIn_b_mem_3_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_3_address_0 = nodeIn_b_mem_3_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_4_param_0 = nodeIn_b_mem_4_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_4_address_0 = nodeIn_b_mem_4_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_5_param_0 = nodeIn_b_mem_5_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_5_address_0 = nodeIn_b_mem_5_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_6_param_0 = nodeIn_b_mem_6_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_6_address_0 = nodeIn_b_mem_6_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_7_param_0 = nodeIn_b_mem_7_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_7_address_0 = nodeIn_b_mem_7_address; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_widx_0 = nodeIn_b_widx; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_safe_widx_valid_0 = nodeIn_b_safe_widx_valid; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_safe_source_reset_n_0 = nodeIn_b_safe_source_reset_n; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_ridx_0 = nodeIn_c_ridx; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_safe_ridx_valid_0 = nodeIn_c_safe_ridx_valid; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_safe_sink_reset_n_0 = nodeIn_c_safe_sink_reset_n; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_opcode_0 = nodeIn_d_mem_0_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_param_0 = nodeIn_d_mem_0_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_size_0 = nodeIn_d_mem_0_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_source_0 = nodeIn_d_mem_0_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_sink_0 = nodeIn_d_mem_0_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_denied_0 = nodeIn_d_mem_0_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_data_0 = nodeIn_d_mem_0_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_corrupt_0 = nodeIn_d_mem_0_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_opcode_0 = nodeIn_d_mem_1_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_param_0 = nodeIn_d_mem_1_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_size_0 = nodeIn_d_mem_1_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_source_0 = nodeIn_d_mem_1_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_sink_0 = nodeIn_d_mem_1_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_denied_0 = nodeIn_d_mem_1_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_data_0 = nodeIn_d_mem_1_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_corrupt_0 = nodeIn_d_mem_1_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_opcode_0 = nodeIn_d_mem_2_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_param_0 = nodeIn_d_mem_2_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_size_0 = nodeIn_d_mem_2_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_source_0 = nodeIn_d_mem_2_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_sink_0 = nodeIn_d_mem_2_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_denied_0 = nodeIn_d_mem_2_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_data_0 = nodeIn_d_mem_2_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_corrupt_0 = nodeIn_d_mem_2_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_opcode_0 = nodeIn_d_mem_3_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_param_0 = nodeIn_d_mem_3_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_size_0 = nodeIn_d_mem_3_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_source_0 = nodeIn_d_mem_3_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_sink_0 = nodeIn_d_mem_3_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_denied_0 = nodeIn_d_mem_3_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_data_0 = nodeIn_d_mem_3_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_corrupt_0 = nodeIn_d_mem_3_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_opcode_0 = nodeIn_d_mem_4_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_param_0 = nodeIn_d_mem_4_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_size_0 = nodeIn_d_mem_4_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_source_0 = nodeIn_d_mem_4_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_sink_0 = nodeIn_d_mem_4_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_denied_0 = nodeIn_d_mem_4_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_data_0 = nodeIn_d_mem_4_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_corrupt_0 = nodeIn_d_mem_4_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_opcode_0 = nodeIn_d_mem_5_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_param_0 = nodeIn_d_mem_5_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_size_0 = nodeIn_d_mem_5_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_source_0 = nodeIn_d_mem_5_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_sink_0 = nodeIn_d_mem_5_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_denied_0 = nodeIn_d_mem_5_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_data_0 = nodeIn_d_mem_5_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_corrupt_0 = nodeIn_d_mem_5_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_opcode_0 = nodeIn_d_mem_6_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_param_0 = nodeIn_d_mem_6_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_size_0 = nodeIn_d_mem_6_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_source_0 = nodeIn_d_mem_6_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_sink_0 = nodeIn_d_mem_6_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_denied_0 = nodeIn_d_mem_6_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_data_0 = nodeIn_d_mem_6_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_corrupt_0 = nodeIn_d_mem_6_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_opcode_0 = nodeIn_d_mem_7_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_param_0 = nodeIn_d_mem_7_param; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_size_0 = nodeIn_d_mem_7_size; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_source_0 = nodeIn_d_mem_7_source; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_sink_0 = nodeIn_d_mem_7_sink; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_denied_0 = nodeIn_d_mem_7_denied; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_data_0 = nodeIn_d_mem_7_data; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_corrupt_0 = nodeIn_d_mem_7_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_widx_0 = nodeIn_d_widx; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_safe_widx_valid_0 = nodeIn_d_safe_widx_valid; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_safe_source_reset_n_0 = nodeIn_d_safe_source_reset_n; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_ridx_0 = nodeIn_e_ridx; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_safe_ridx_valid_0 = nodeIn_e_safe_ridx_valid; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_safe_sink_reset_n_0 = nodeIn_e_safe_sink_reset_n; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[AsyncCrossing.scala:59:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AsyncCrossing.scala:59:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[AsyncCrossing.scala:59:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[AsyncCrossing.scala:59:9]
AsyncQueueSink_TLBundleA_a32d64s2k3z4c nodeOut_a_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt),
.io_async_mem_0_opcode (nodeIn_a_mem_0_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_0_param (nodeIn_a_mem_0_param), // @[MixedNode.scala:551:17]
.io_async_mem_0_size (nodeIn_a_mem_0_size), // @[MixedNode.scala:551:17]
.io_async_mem_0_source (nodeIn_a_mem_0_source), // @[MixedNode.scala:551:17]
.io_async_mem_0_address (nodeIn_a_mem_0_address), // @[MixedNode.scala:551:17]
.io_async_mem_0_mask (nodeIn_a_mem_0_mask), // @[MixedNode.scala:551:17]
.io_async_mem_0_data (nodeIn_a_mem_0_data), // @[MixedNode.scala:551:17]
.io_async_mem_1_opcode (nodeIn_a_mem_1_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_1_param (nodeIn_a_mem_1_param), // @[MixedNode.scala:551:17]
.io_async_mem_1_size (nodeIn_a_mem_1_size), // @[MixedNode.scala:551:17]
.io_async_mem_1_source (nodeIn_a_mem_1_source), // @[MixedNode.scala:551:17]
.io_async_mem_1_address (nodeIn_a_mem_1_address), // @[MixedNode.scala:551:17]
.io_async_mem_1_mask (nodeIn_a_mem_1_mask), // @[MixedNode.scala:551:17]
.io_async_mem_1_data (nodeIn_a_mem_1_data), // @[MixedNode.scala:551:17]
.io_async_mem_2_opcode (nodeIn_a_mem_2_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_2_param (nodeIn_a_mem_2_param), // @[MixedNode.scala:551:17]
.io_async_mem_2_size (nodeIn_a_mem_2_size), // @[MixedNode.scala:551:17]
.io_async_mem_2_source (nodeIn_a_mem_2_source), // @[MixedNode.scala:551:17]
.io_async_mem_2_address (nodeIn_a_mem_2_address), // @[MixedNode.scala:551:17]
.io_async_mem_2_mask (nodeIn_a_mem_2_mask), // @[MixedNode.scala:551:17]
.io_async_mem_2_data (nodeIn_a_mem_2_data), // @[MixedNode.scala:551:17]
.io_async_mem_3_opcode (nodeIn_a_mem_3_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_3_param (nodeIn_a_mem_3_param), // @[MixedNode.scala:551:17]
.io_async_mem_3_size (nodeIn_a_mem_3_size), // @[MixedNode.scala:551:17]
.io_async_mem_3_source (nodeIn_a_mem_3_source), // @[MixedNode.scala:551:17]
.io_async_mem_3_address (nodeIn_a_mem_3_address), // @[MixedNode.scala:551:17]
.io_async_mem_3_mask (nodeIn_a_mem_3_mask), // @[MixedNode.scala:551:17]
.io_async_mem_3_data (nodeIn_a_mem_3_data), // @[MixedNode.scala:551:17]
.io_async_mem_4_opcode (nodeIn_a_mem_4_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_4_param (nodeIn_a_mem_4_param), // @[MixedNode.scala:551:17]
.io_async_mem_4_size (nodeIn_a_mem_4_size), // @[MixedNode.scala:551:17]
.io_async_mem_4_source (nodeIn_a_mem_4_source), // @[MixedNode.scala:551:17]
.io_async_mem_4_address (nodeIn_a_mem_4_address), // @[MixedNode.scala:551:17]
.io_async_mem_4_mask (nodeIn_a_mem_4_mask), // @[MixedNode.scala:551:17]
.io_async_mem_4_data (nodeIn_a_mem_4_data), // @[MixedNode.scala:551:17]
.io_async_mem_5_opcode (nodeIn_a_mem_5_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_5_param (nodeIn_a_mem_5_param), // @[MixedNode.scala:551:17]
.io_async_mem_5_size (nodeIn_a_mem_5_size), // @[MixedNode.scala:551:17]
.io_async_mem_5_source (nodeIn_a_mem_5_source), // @[MixedNode.scala:551:17]
.io_async_mem_5_address (nodeIn_a_mem_5_address), // @[MixedNode.scala:551:17]
.io_async_mem_5_mask (nodeIn_a_mem_5_mask), // @[MixedNode.scala:551:17]
.io_async_mem_5_data (nodeIn_a_mem_5_data), // @[MixedNode.scala:551:17]
.io_async_mem_6_opcode (nodeIn_a_mem_6_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_6_param (nodeIn_a_mem_6_param), // @[MixedNode.scala:551:17]
.io_async_mem_6_size (nodeIn_a_mem_6_size), // @[MixedNode.scala:551:17]
.io_async_mem_6_source (nodeIn_a_mem_6_source), // @[MixedNode.scala:551:17]
.io_async_mem_6_address (nodeIn_a_mem_6_address), // @[MixedNode.scala:551:17]
.io_async_mem_6_mask (nodeIn_a_mem_6_mask), // @[MixedNode.scala:551:17]
.io_async_mem_6_data (nodeIn_a_mem_6_data), // @[MixedNode.scala:551:17]
.io_async_mem_7_opcode (nodeIn_a_mem_7_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_7_param (nodeIn_a_mem_7_param), // @[MixedNode.scala:551:17]
.io_async_mem_7_size (nodeIn_a_mem_7_size), // @[MixedNode.scala:551:17]
.io_async_mem_7_source (nodeIn_a_mem_7_source), // @[MixedNode.scala:551:17]
.io_async_mem_7_address (nodeIn_a_mem_7_address), // @[MixedNode.scala:551:17]
.io_async_mem_7_mask (nodeIn_a_mem_7_mask), // @[MixedNode.scala:551:17]
.io_async_mem_7_data (nodeIn_a_mem_7_data), // @[MixedNode.scala:551:17]
.io_async_ridx (nodeIn_a_ridx),
.io_async_widx (nodeIn_a_widx), // @[MixedNode.scala:551:17]
.io_async_safe_ridx_valid (nodeIn_a_safe_ridx_valid),
.io_async_safe_widx_valid (nodeIn_a_safe_widx_valid), // @[MixedNode.scala:551:17]
.io_async_safe_source_reset_n (nodeIn_a_safe_source_reset_n), // @[MixedNode.scala:551:17]
.io_async_safe_sink_reset_n (nodeIn_a_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
AsyncQueueSource_TLBundleD_a32d64s2k3z4c nodeIn_d_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_0_opcode (nodeIn_d_mem_0_opcode),
.io_async_mem_0_param (nodeIn_d_mem_0_param),
.io_async_mem_0_size (nodeIn_d_mem_0_size),
.io_async_mem_0_source (nodeIn_d_mem_0_source),
.io_async_mem_0_sink (nodeIn_d_mem_0_sink),
.io_async_mem_0_denied (nodeIn_d_mem_0_denied),
.io_async_mem_0_data (nodeIn_d_mem_0_data),
.io_async_mem_0_corrupt (nodeIn_d_mem_0_corrupt),
.io_async_mem_1_opcode (nodeIn_d_mem_1_opcode),
.io_async_mem_1_param (nodeIn_d_mem_1_param),
.io_async_mem_1_size (nodeIn_d_mem_1_size),
.io_async_mem_1_source (nodeIn_d_mem_1_source),
.io_async_mem_1_sink (nodeIn_d_mem_1_sink),
.io_async_mem_1_denied (nodeIn_d_mem_1_denied),
.io_async_mem_1_data (nodeIn_d_mem_1_data),
.io_async_mem_1_corrupt (nodeIn_d_mem_1_corrupt),
.io_async_mem_2_opcode (nodeIn_d_mem_2_opcode),
.io_async_mem_2_param (nodeIn_d_mem_2_param),
.io_async_mem_2_size (nodeIn_d_mem_2_size),
.io_async_mem_2_source (nodeIn_d_mem_2_source),
.io_async_mem_2_sink (nodeIn_d_mem_2_sink),
.io_async_mem_2_denied (nodeIn_d_mem_2_denied),
.io_async_mem_2_data (nodeIn_d_mem_2_data),
.io_async_mem_2_corrupt (nodeIn_d_mem_2_corrupt),
.io_async_mem_3_opcode (nodeIn_d_mem_3_opcode),
.io_async_mem_3_param (nodeIn_d_mem_3_param),
.io_async_mem_3_size (nodeIn_d_mem_3_size),
.io_async_mem_3_source (nodeIn_d_mem_3_source),
.io_async_mem_3_sink (nodeIn_d_mem_3_sink),
.io_async_mem_3_denied (nodeIn_d_mem_3_denied),
.io_async_mem_3_data (nodeIn_d_mem_3_data),
.io_async_mem_3_corrupt (nodeIn_d_mem_3_corrupt),
.io_async_mem_4_opcode (nodeIn_d_mem_4_opcode),
.io_async_mem_4_param (nodeIn_d_mem_4_param),
.io_async_mem_4_size (nodeIn_d_mem_4_size),
.io_async_mem_4_source (nodeIn_d_mem_4_source),
.io_async_mem_4_sink (nodeIn_d_mem_4_sink),
.io_async_mem_4_denied (nodeIn_d_mem_4_denied),
.io_async_mem_4_data (nodeIn_d_mem_4_data),
.io_async_mem_4_corrupt (nodeIn_d_mem_4_corrupt),
.io_async_mem_5_opcode (nodeIn_d_mem_5_opcode),
.io_async_mem_5_param (nodeIn_d_mem_5_param),
.io_async_mem_5_size (nodeIn_d_mem_5_size),
.io_async_mem_5_source (nodeIn_d_mem_5_source),
.io_async_mem_5_sink (nodeIn_d_mem_5_sink),
.io_async_mem_5_denied (nodeIn_d_mem_5_denied),
.io_async_mem_5_data (nodeIn_d_mem_5_data),
.io_async_mem_5_corrupt (nodeIn_d_mem_5_corrupt),
.io_async_mem_6_opcode (nodeIn_d_mem_6_opcode),
.io_async_mem_6_param (nodeIn_d_mem_6_param),
.io_async_mem_6_size (nodeIn_d_mem_6_size),
.io_async_mem_6_source (nodeIn_d_mem_6_source),
.io_async_mem_6_sink (nodeIn_d_mem_6_sink),
.io_async_mem_6_denied (nodeIn_d_mem_6_denied),
.io_async_mem_6_data (nodeIn_d_mem_6_data),
.io_async_mem_6_corrupt (nodeIn_d_mem_6_corrupt),
.io_async_mem_7_opcode (nodeIn_d_mem_7_opcode),
.io_async_mem_7_param (nodeIn_d_mem_7_param),
.io_async_mem_7_size (nodeIn_d_mem_7_size),
.io_async_mem_7_source (nodeIn_d_mem_7_source),
.io_async_mem_7_sink (nodeIn_d_mem_7_sink),
.io_async_mem_7_denied (nodeIn_d_mem_7_denied),
.io_async_mem_7_data (nodeIn_d_mem_7_data),
.io_async_mem_7_corrupt (nodeIn_d_mem_7_corrupt),
.io_async_ridx (nodeIn_d_ridx), // @[MixedNode.scala:551:17]
.io_async_widx (nodeIn_d_widx),
.io_async_safe_ridx_valid (nodeIn_d_safe_ridx_valid), // @[MixedNode.scala:551:17]
.io_async_safe_widx_valid (nodeIn_d_safe_widx_valid),
.io_async_safe_source_reset_n (nodeIn_d_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeIn_d_safe_sink_reset_n) // @[MixedNode.scala:551:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSource_TLBundleB_a32d64s2k3z4c nodeIn_b_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_async_mem_0_param (nodeIn_b_mem_0_param),
.io_async_mem_0_address (nodeIn_b_mem_0_address),
.io_async_mem_1_param (nodeIn_b_mem_1_param),
.io_async_mem_1_address (nodeIn_b_mem_1_address),
.io_async_mem_2_param (nodeIn_b_mem_2_param),
.io_async_mem_2_address (nodeIn_b_mem_2_address),
.io_async_mem_3_param (nodeIn_b_mem_3_param),
.io_async_mem_3_address (nodeIn_b_mem_3_address),
.io_async_mem_4_param (nodeIn_b_mem_4_param),
.io_async_mem_4_address (nodeIn_b_mem_4_address),
.io_async_mem_5_param (nodeIn_b_mem_5_param),
.io_async_mem_5_address (nodeIn_b_mem_5_address),
.io_async_mem_6_param (nodeIn_b_mem_6_param),
.io_async_mem_6_address (nodeIn_b_mem_6_address),
.io_async_mem_7_param (nodeIn_b_mem_7_param),
.io_async_mem_7_address (nodeIn_b_mem_7_address),
.io_async_ridx (nodeIn_b_ridx), // @[MixedNode.scala:551:17]
.io_async_widx (nodeIn_b_widx),
.io_async_safe_ridx_valid (nodeIn_b_safe_ridx_valid), // @[MixedNode.scala:551:17]
.io_async_safe_widx_valid (nodeIn_b_safe_widx_valid),
.io_async_safe_source_reset_n (nodeIn_b_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeIn_b_safe_sink_reset_n) // @[MixedNode.scala:551:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSink_TLBundleC_a32d64s2k3z4c nodeOut_c_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt),
.io_async_mem_0_opcode (nodeIn_c_mem_0_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_0_param (nodeIn_c_mem_0_param), // @[MixedNode.scala:551:17]
.io_async_mem_0_size (nodeIn_c_mem_0_size), // @[MixedNode.scala:551:17]
.io_async_mem_0_source (nodeIn_c_mem_0_source), // @[MixedNode.scala:551:17]
.io_async_mem_0_address (nodeIn_c_mem_0_address), // @[MixedNode.scala:551:17]
.io_async_mem_0_data (nodeIn_c_mem_0_data), // @[MixedNode.scala:551:17]
.io_async_mem_1_opcode (nodeIn_c_mem_1_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_1_param (nodeIn_c_mem_1_param), // @[MixedNode.scala:551:17]
.io_async_mem_1_size (nodeIn_c_mem_1_size), // @[MixedNode.scala:551:17]
.io_async_mem_1_source (nodeIn_c_mem_1_source), // @[MixedNode.scala:551:17]
.io_async_mem_1_address (nodeIn_c_mem_1_address), // @[MixedNode.scala:551:17]
.io_async_mem_1_data (nodeIn_c_mem_1_data), // @[MixedNode.scala:551:17]
.io_async_mem_2_opcode (nodeIn_c_mem_2_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_2_param (nodeIn_c_mem_2_param), // @[MixedNode.scala:551:17]
.io_async_mem_2_size (nodeIn_c_mem_2_size), // @[MixedNode.scala:551:17]
.io_async_mem_2_source (nodeIn_c_mem_2_source), // @[MixedNode.scala:551:17]
.io_async_mem_2_address (nodeIn_c_mem_2_address), // @[MixedNode.scala:551:17]
.io_async_mem_2_data (nodeIn_c_mem_2_data), // @[MixedNode.scala:551:17]
.io_async_mem_3_opcode (nodeIn_c_mem_3_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_3_param (nodeIn_c_mem_3_param), // @[MixedNode.scala:551:17]
.io_async_mem_3_size (nodeIn_c_mem_3_size), // @[MixedNode.scala:551:17]
.io_async_mem_3_source (nodeIn_c_mem_3_source), // @[MixedNode.scala:551:17]
.io_async_mem_3_address (nodeIn_c_mem_3_address), // @[MixedNode.scala:551:17]
.io_async_mem_3_data (nodeIn_c_mem_3_data), // @[MixedNode.scala:551:17]
.io_async_mem_4_opcode (nodeIn_c_mem_4_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_4_param (nodeIn_c_mem_4_param), // @[MixedNode.scala:551:17]
.io_async_mem_4_size (nodeIn_c_mem_4_size), // @[MixedNode.scala:551:17]
.io_async_mem_4_source (nodeIn_c_mem_4_source), // @[MixedNode.scala:551:17]
.io_async_mem_4_address (nodeIn_c_mem_4_address), // @[MixedNode.scala:551:17]
.io_async_mem_4_data (nodeIn_c_mem_4_data), // @[MixedNode.scala:551:17]
.io_async_mem_5_opcode (nodeIn_c_mem_5_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_5_param (nodeIn_c_mem_5_param), // @[MixedNode.scala:551:17]
.io_async_mem_5_size (nodeIn_c_mem_5_size), // @[MixedNode.scala:551:17]
.io_async_mem_5_source (nodeIn_c_mem_5_source), // @[MixedNode.scala:551:17]
.io_async_mem_5_address (nodeIn_c_mem_5_address), // @[MixedNode.scala:551:17]
.io_async_mem_5_data (nodeIn_c_mem_5_data), // @[MixedNode.scala:551:17]
.io_async_mem_6_opcode (nodeIn_c_mem_6_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_6_param (nodeIn_c_mem_6_param), // @[MixedNode.scala:551:17]
.io_async_mem_6_size (nodeIn_c_mem_6_size), // @[MixedNode.scala:551:17]
.io_async_mem_6_source (nodeIn_c_mem_6_source), // @[MixedNode.scala:551:17]
.io_async_mem_6_address (nodeIn_c_mem_6_address), // @[MixedNode.scala:551:17]
.io_async_mem_6_data (nodeIn_c_mem_6_data), // @[MixedNode.scala:551:17]
.io_async_mem_7_opcode (nodeIn_c_mem_7_opcode), // @[MixedNode.scala:551:17]
.io_async_mem_7_param (nodeIn_c_mem_7_param), // @[MixedNode.scala:551:17]
.io_async_mem_7_size (nodeIn_c_mem_7_size), // @[MixedNode.scala:551:17]
.io_async_mem_7_source (nodeIn_c_mem_7_source), // @[MixedNode.scala:551:17]
.io_async_mem_7_address (nodeIn_c_mem_7_address), // @[MixedNode.scala:551:17]
.io_async_mem_7_data (nodeIn_c_mem_7_data), // @[MixedNode.scala:551:17]
.io_async_ridx (nodeIn_c_ridx),
.io_async_widx (nodeIn_c_widx), // @[MixedNode.scala:551:17]
.io_async_safe_ridx_valid (nodeIn_c_safe_ridx_valid),
.io_async_safe_widx_valid (nodeIn_c_safe_widx_valid), // @[MixedNode.scala:551:17]
.io_async_safe_source_reset_n (nodeIn_c_safe_source_reset_n), // @[MixedNode.scala:551:17]
.io_async_safe_sink_reset_n (nodeIn_c_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
AsyncQueueSink_TLBundleE_a32d64s2k3z4c nodeOut_e_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink),
.io_async_mem_0_sink (nodeIn_e_mem_0_sink), // @[MixedNode.scala:551:17]
.io_async_mem_1_sink (nodeIn_e_mem_1_sink), // @[MixedNode.scala:551:17]
.io_async_mem_2_sink (nodeIn_e_mem_2_sink), // @[MixedNode.scala:551:17]
.io_async_mem_3_sink (nodeIn_e_mem_3_sink), // @[MixedNode.scala:551:17]
.io_async_mem_4_sink (nodeIn_e_mem_4_sink), // @[MixedNode.scala:551:17]
.io_async_mem_5_sink (nodeIn_e_mem_5_sink), // @[MixedNode.scala:551:17]
.io_async_mem_6_sink (nodeIn_e_mem_6_sink), // @[MixedNode.scala:551:17]
.io_async_mem_7_sink (nodeIn_e_mem_7_sink), // @[MixedNode.scala:551:17]
.io_async_ridx (nodeIn_e_ridx),
.io_async_widx (nodeIn_e_widx), // @[MixedNode.scala:551:17]
.io_async_safe_ridx_valid (nodeIn_e_safe_ridx_valid),
.io_async_safe_widx_valid (nodeIn_e_safe_widx_valid), // @[MixedNode.scala:551:17]
.io_async_safe_source_reset_n (nodeIn_e_safe_source_reset_n), // @[MixedNode.scala:551:17]
.io_async_safe_sink_reset_n (nodeIn_e_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
assign auto_in_a_ridx = auto_in_a_ridx_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_a_safe_ridx_valid = auto_in_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_a_safe_sink_reset_n = auto_in_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_0_param = auto_in_b_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_0_address = auto_in_b_mem_0_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_1_param = auto_in_b_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_1_address = auto_in_b_mem_1_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_2_param = auto_in_b_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_2_address = auto_in_b_mem_2_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_3_param = auto_in_b_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_3_address = auto_in_b_mem_3_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_4_param = auto_in_b_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_4_address = auto_in_b_mem_4_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_5_param = auto_in_b_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_5_address = auto_in_b_mem_5_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_6_param = auto_in_b_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_6_address = auto_in_b_mem_6_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_7_param = auto_in_b_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_mem_7_address = auto_in_b_mem_7_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_widx = auto_in_b_widx_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_safe_widx_valid = auto_in_b_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_b_safe_source_reset_n = auto_in_b_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_ridx = auto_in_c_ridx_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_safe_ridx_valid = auto_in_c_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_c_safe_sink_reset_n = auto_in_c_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_opcode = auto_in_d_mem_0_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_param = auto_in_d_mem_0_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_size = auto_in_d_mem_0_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_source = auto_in_d_mem_0_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_sink = auto_in_d_mem_0_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_denied = auto_in_d_mem_0_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_data = auto_in_d_mem_0_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_0_corrupt = auto_in_d_mem_0_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_opcode = auto_in_d_mem_1_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_param = auto_in_d_mem_1_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_size = auto_in_d_mem_1_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_source = auto_in_d_mem_1_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_sink = auto_in_d_mem_1_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_denied = auto_in_d_mem_1_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_data = auto_in_d_mem_1_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_1_corrupt = auto_in_d_mem_1_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_opcode = auto_in_d_mem_2_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_param = auto_in_d_mem_2_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_size = auto_in_d_mem_2_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_source = auto_in_d_mem_2_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_sink = auto_in_d_mem_2_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_denied = auto_in_d_mem_2_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_data = auto_in_d_mem_2_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_2_corrupt = auto_in_d_mem_2_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_opcode = auto_in_d_mem_3_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_param = auto_in_d_mem_3_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_size = auto_in_d_mem_3_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_source = auto_in_d_mem_3_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_sink = auto_in_d_mem_3_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_denied = auto_in_d_mem_3_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_data = auto_in_d_mem_3_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_3_corrupt = auto_in_d_mem_3_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_opcode = auto_in_d_mem_4_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_param = auto_in_d_mem_4_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_size = auto_in_d_mem_4_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_source = auto_in_d_mem_4_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_sink = auto_in_d_mem_4_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_denied = auto_in_d_mem_4_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_data = auto_in_d_mem_4_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_4_corrupt = auto_in_d_mem_4_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_opcode = auto_in_d_mem_5_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_param = auto_in_d_mem_5_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_size = auto_in_d_mem_5_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_source = auto_in_d_mem_5_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_sink = auto_in_d_mem_5_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_denied = auto_in_d_mem_5_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_data = auto_in_d_mem_5_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_5_corrupt = auto_in_d_mem_5_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_opcode = auto_in_d_mem_6_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_param = auto_in_d_mem_6_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_size = auto_in_d_mem_6_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_source = auto_in_d_mem_6_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_sink = auto_in_d_mem_6_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_denied = auto_in_d_mem_6_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_data = auto_in_d_mem_6_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_6_corrupt = auto_in_d_mem_6_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_opcode = auto_in_d_mem_7_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_param = auto_in_d_mem_7_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_size = auto_in_d_mem_7_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_source = auto_in_d_mem_7_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_sink = auto_in_d_mem_7_sink_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_denied = auto_in_d_mem_7_denied_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_data = auto_in_d_mem_7_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_mem_7_corrupt = auto_in_d_mem_7_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_widx = auto_in_d_widx_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_safe_widx_valid = auto_in_d_safe_widx_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_d_safe_source_reset_n = auto_in_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_ridx = auto_in_e_ridx_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_safe_ridx_valid = auto_in_e_safe_ridx_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_in_e_safe_sink_reset_n = auto_in_e_safe_sink_reset_n_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[AsyncCrossing.scala:59:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[AsyncCrossing.scala:59:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_168 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_168( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ALUUnit :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[3], brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip get_ftq_pc : { flip ftq_idx : UInt<4>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<4>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}}
connect io.bypass[0].valid, UInt<1>(0h0)
invalidate io.bypass[0].bits.fflags.bits.flags
invalidate io.bypass[0].bits.fflags.bits.uop.debug_tsrc
invalidate io.bypass[0].bits.fflags.bits.uop.debug_fsrc
invalidate io.bypass[0].bits.fflags.bits.uop.bp_xcpt_if
invalidate io.bypass[0].bits.fflags.bits.uop.bp_debug_if
invalidate io.bypass[0].bits.fflags.bits.uop.xcpt_ma_if
invalidate io.bypass[0].bits.fflags.bits.uop.xcpt_ae_if
invalidate io.bypass[0].bits.fflags.bits.uop.xcpt_pf_if
invalidate io.bypass[0].bits.fflags.bits.uop.fp_single
invalidate io.bypass[0].bits.fflags.bits.uop.fp_val
invalidate io.bypass[0].bits.fflags.bits.uop.frs3_en
invalidate io.bypass[0].bits.fflags.bits.uop.lrs2_rtype
invalidate io.bypass[0].bits.fflags.bits.uop.lrs1_rtype
invalidate io.bypass[0].bits.fflags.bits.uop.dst_rtype
invalidate io.bypass[0].bits.fflags.bits.uop.ldst_val
invalidate io.bypass[0].bits.fflags.bits.uop.lrs3
invalidate io.bypass[0].bits.fflags.bits.uop.lrs2
invalidate io.bypass[0].bits.fflags.bits.uop.lrs1
invalidate io.bypass[0].bits.fflags.bits.uop.ldst
invalidate io.bypass[0].bits.fflags.bits.uop.ldst_is_rs1
invalidate io.bypass[0].bits.fflags.bits.uop.flush_on_commit
invalidate io.bypass[0].bits.fflags.bits.uop.is_unique
invalidate io.bypass[0].bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.bypass[0].bits.fflags.bits.uop.uses_stq
invalidate io.bypass[0].bits.fflags.bits.uop.uses_ldq
invalidate io.bypass[0].bits.fflags.bits.uop.is_amo
invalidate io.bypass[0].bits.fflags.bits.uop.is_fencei
invalidate io.bypass[0].bits.fflags.bits.uop.is_fence
invalidate io.bypass[0].bits.fflags.bits.uop.mem_signed
invalidate io.bypass[0].bits.fflags.bits.uop.mem_size
invalidate io.bypass[0].bits.fflags.bits.uop.mem_cmd
invalidate io.bypass[0].bits.fflags.bits.uop.bypassable
invalidate io.bypass[0].bits.fflags.bits.uop.exc_cause
invalidate io.bypass[0].bits.fflags.bits.uop.exception
invalidate io.bypass[0].bits.fflags.bits.uop.stale_pdst
invalidate io.bypass[0].bits.fflags.bits.uop.ppred_busy
invalidate io.bypass[0].bits.fflags.bits.uop.prs3_busy
invalidate io.bypass[0].bits.fflags.bits.uop.prs2_busy
invalidate io.bypass[0].bits.fflags.bits.uop.prs1_busy
invalidate io.bypass[0].bits.fflags.bits.uop.ppred
invalidate io.bypass[0].bits.fflags.bits.uop.prs3
invalidate io.bypass[0].bits.fflags.bits.uop.prs2
invalidate io.bypass[0].bits.fflags.bits.uop.prs1
invalidate io.bypass[0].bits.fflags.bits.uop.pdst
invalidate io.bypass[0].bits.fflags.bits.uop.rxq_idx
invalidate io.bypass[0].bits.fflags.bits.uop.stq_idx
invalidate io.bypass[0].bits.fflags.bits.uop.ldq_idx
invalidate io.bypass[0].bits.fflags.bits.uop.rob_idx
invalidate io.bypass[0].bits.fflags.bits.uop.csr_addr
invalidate io.bypass[0].bits.fflags.bits.uop.imm_packed
invalidate io.bypass[0].bits.fflags.bits.uop.taken
invalidate io.bypass[0].bits.fflags.bits.uop.pc_lob
invalidate io.bypass[0].bits.fflags.bits.uop.edge_inst
invalidate io.bypass[0].bits.fflags.bits.uop.ftq_idx
invalidate io.bypass[0].bits.fflags.bits.uop.br_tag
invalidate io.bypass[0].bits.fflags.bits.uop.br_mask
invalidate io.bypass[0].bits.fflags.bits.uop.is_sfb
invalidate io.bypass[0].bits.fflags.bits.uop.is_jal
invalidate io.bypass[0].bits.fflags.bits.uop.is_jalr
invalidate io.bypass[0].bits.fflags.bits.uop.is_br
invalidate io.bypass[0].bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.bypass[0].bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.bypass[0].bits.fflags.bits.uop.iw_state
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.is_std
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.is_sta
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.is_load
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.bypass[0].bits.fflags.bits.uop.ctrl.br_type
invalidate io.bypass[0].bits.fflags.bits.uop.fu_code
invalidate io.bypass[0].bits.fflags.bits.uop.iq_type
invalidate io.bypass[0].bits.fflags.bits.uop.debug_pc
invalidate io.bypass[0].bits.fflags.bits.uop.is_rvc
invalidate io.bypass[0].bits.fflags.bits.uop.debug_inst
invalidate io.bypass[0].bits.fflags.bits.uop.inst
invalidate io.bypass[0].bits.fflags.bits.uop.uopc
invalidate io.bypass[0].bits.fflags.valid
invalidate io.bypass[0].bits.predicated
invalidate io.bypass[0].bits.data
invalidate io.bypass[0].bits.uop.debug_tsrc
invalidate io.bypass[0].bits.uop.debug_fsrc
invalidate io.bypass[0].bits.uop.bp_xcpt_if
invalidate io.bypass[0].bits.uop.bp_debug_if
invalidate io.bypass[0].bits.uop.xcpt_ma_if
invalidate io.bypass[0].bits.uop.xcpt_ae_if
invalidate io.bypass[0].bits.uop.xcpt_pf_if
invalidate io.bypass[0].bits.uop.fp_single
invalidate io.bypass[0].bits.uop.fp_val
invalidate io.bypass[0].bits.uop.frs3_en
invalidate io.bypass[0].bits.uop.lrs2_rtype
invalidate io.bypass[0].bits.uop.lrs1_rtype
invalidate io.bypass[0].bits.uop.dst_rtype
invalidate io.bypass[0].bits.uop.ldst_val
invalidate io.bypass[0].bits.uop.lrs3
invalidate io.bypass[0].bits.uop.lrs2
invalidate io.bypass[0].bits.uop.lrs1
invalidate io.bypass[0].bits.uop.ldst
invalidate io.bypass[0].bits.uop.ldst_is_rs1
invalidate io.bypass[0].bits.uop.flush_on_commit
invalidate io.bypass[0].bits.uop.is_unique
invalidate io.bypass[0].bits.uop.is_sys_pc2epc
invalidate io.bypass[0].bits.uop.uses_stq
invalidate io.bypass[0].bits.uop.uses_ldq
invalidate io.bypass[0].bits.uop.is_amo
invalidate io.bypass[0].bits.uop.is_fencei
invalidate io.bypass[0].bits.uop.is_fence
invalidate io.bypass[0].bits.uop.mem_signed
invalidate io.bypass[0].bits.uop.mem_size
invalidate io.bypass[0].bits.uop.mem_cmd
invalidate io.bypass[0].bits.uop.bypassable
invalidate io.bypass[0].bits.uop.exc_cause
invalidate io.bypass[0].bits.uop.exception
invalidate io.bypass[0].bits.uop.stale_pdst
invalidate io.bypass[0].bits.uop.ppred_busy
invalidate io.bypass[0].bits.uop.prs3_busy
invalidate io.bypass[0].bits.uop.prs2_busy
invalidate io.bypass[0].bits.uop.prs1_busy
invalidate io.bypass[0].bits.uop.ppred
invalidate io.bypass[0].bits.uop.prs3
invalidate io.bypass[0].bits.uop.prs2
invalidate io.bypass[0].bits.uop.prs1
invalidate io.bypass[0].bits.uop.pdst
invalidate io.bypass[0].bits.uop.rxq_idx
invalidate io.bypass[0].bits.uop.stq_idx
invalidate io.bypass[0].bits.uop.ldq_idx
invalidate io.bypass[0].bits.uop.rob_idx
invalidate io.bypass[0].bits.uop.csr_addr
invalidate io.bypass[0].bits.uop.imm_packed
invalidate io.bypass[0].bits.uop.taken
invalidate io.bypass[0].bits.uop.pc_lob
invalidate io.bypass[0].bits.uop.edge_inst
invalidate io.bypass[0].bits.uop.ftq_idx
invalidate io.bypass[0].bits.uop.br_tag
invalidate io.bypass[0].bits.uop.br_mask
invalidate io.bypass[0].bits.uop.is_sfb
invalidate io.bypass[0].bits.uop.is_jal
invalidate io.bypass[0].bits.uop.is_jalr
invalidate io.bypass[0].bits.uop.is_br
invalidate io.bypass[0].bits.uop.iw_p2_poisoned
invalidate io.bypass[0].bits.uop.iw_p1_poisoned
invalidate io.bypass[0].bits.uop.iw_state
invalidate io.bypass[0].bits.uop.ctrl.is_std
invalidate io.bypass[0].bits.uop.ctrl.is_sta
invalidate io.bypass[0].bits.uop.ctrl.is_load
invalidate io.bypass[0].bits.uop.ctrl.csr_cmd
invalidate io.bypass[0].bits.uop.ctrl.fcn_dw
invalidate io.bypass[0].bits.uop.ctrl.op_fcn
invalidate io.bypass[0].bits.uop.ctrl.imm_sel
invalidate io.bypass[0].bits.uop.ctrl.op2_sel
invalidate io.bypass[0].bits.uop.ctrl.op1_sel
invalidate io.bypass[0].bits.uop.ctrl.br_type
invalidate io.bypass[0].bits.uop.fu_code
invalidate io.bypass[0].bits.uop.iq_type
invalidate io.bypass[0].bits.uop.debug_pc
invalidate io.bypass[0].bits.uop.is_rvc
invalidate io.bypass[0].bits.uop.debug_inst
invalidate io.bypass[0].bits.uop.inst
invalidate io.bypass[0].bits.uop.uopc
connect io.bypass[1].valid, UInt<1>(0h0)
invalidate io.bypass[1].bits.fflags.bits.flags
invalidate io.bypass[1].bits.fflags.bits.uop.debug_tsrc
invalidate io.bypass[1].bits.fflags.bits.uop.debug_fsrc
invalidate io.bypass[1].bits.fflags.bits.uop.bp_xcpt_if
invalidate io.bypass[1].bits.fflags.bits.uop.bp_debug_if
invalidate io.bypass[1].bits.fflags.bits.uop.xcpt_ma_if
invalidate io.bypass[1].bits.fflags.bits.uop.xcpt_ae_if
invalidate io.bypass[1].bits.fflags.bits.uop.xcpt_pf_if
invalidate io.bypass[1].bits.fflags.bits.uop.fp_single
invalidate io.bypass[1].bits.fflags.bits.uop.fp_val
invalidate io.bypass[1].bits.fflags.bits.uop.frs3_en
invalidate io.bypass[1].bits.fflags.bits.uop.lrs2_rtype
invalidate io.bypass[1].bits.fflags.bits.uop.lrs1_rtype
invalidate io.bypass[1].bits.fflags.bits.uop.dst_rtype
invalidate io.bypass[1].bits.fflags.bits.uop.ldst_val
invalidate io.bypass[1].bits.fflags.bits.uop.lrs3
invalidate io.bypass[1].bits.fflags.bits.uop.lrs2
invalidate io.bypass[1].bits.fflags.bits.uop.lrs1
invalidate io.bypass[1].bits.fflags.bits.uop.ldst
invalidate io.bypass[1].bits.fflags.bits.uop.ldst_is_rs1
invalidate io.bypass[1].bits.fflags.bits.uop.flush_on_commit
invalidate io.bypass[1].bits.fflags.bits.uop.is_unique
invalidate io.bypass[1].bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.bypass[1].bits.fflags.bits.uop.uses_stq
invalidate io.bypass[1].bits.fflags.bits.uop.uses_ldq
invalidate io.bypass[1].bits.fflags.bits.uop.is_amo
invalidate io.bypass[1].bits.fflags.bits.uop.is_fencei
invalidate io.bypass[1].bits.fflags.bits.uop.is_fence
invalidate io.bypass[1].bits.fflags.bits.uop.mem_signed
invalidate io.bypass[1].bits.fflags.bits.uop.mem_size
invalidate io.bypass[1].bits.fflags.bits.uop.mem_cmd
invalidate io.bypass[1].bits.fflags.bits.uop.bypassable
invalidate io.bypass[1].bits.fflags.bits.uop.exc_cause
invalidate io.bypass[1].bits.fflags.bits.uop.exception
invalidate io.bypass[1].bits.fflags.bits.uop.stale_pdst
invalidate io.bypass[1].bits.fflags.bits.uop.ppred_busy
invalidate io.bypass[1].bits.fflags.bits.uop.prs3_busy
invalidate io.bypass[1].bits.fflags.bits.uop.prs2_busy
invalidate io.bypass[1].bits.fflags.bits.uop.prs1_busy
invalidate io.bypass[1].bits.fflags.bits.uop.ppred
invalidate io.bypass[1].bits.fflags.bits.uop.prs3
invalidate io.bypass[1].bits.fflags.bits.uop.prs2
invalidate io.bypass[1].bits.fflags.bits.uop.prs1
invalidate io.bypass[1].bits.fflags.bits.uop.pdst
invalidate io.bypass[1].bits.fflags.bits.uop.rxq_idx
invalidate io.bypass[1].bits.fflags.bits.uop.stq_idx
invalidate io.bypass[1].bits.fflags.bits.uop.ldq_idx
invalidate io.bypass[1].bits.fflags.bits.uop.rob_idx
invalidate io.bypass[1].bits.fflags.bits.uop.csr_addr
invalidate io.bypass[1].bits.fflags.bits.uop.imm_packed
invalidate io.bypass[1].bits.fflags.bits.uop.taken
invalidate io.bypass[1].bits.fflags.bits.uop.pc_lob
invalidate io.bypass[1].bits.fflags.bits.uop.edge_inst
invalidate io.bypass[1].bits.fflags.bits.uop.ftq_idx
invalidate io.bypass[1].bits.fflags.bits.uop.br_tag
invalidate io.bypass[1].bits.fflags.bits.uop.br_mask
invalidate io.bypass[1].bits.fflags.bits.uop.is_sfb
invalidate io.bypass[1].bits.fflags.bits.uop.is_jal
invalidate io.bypass[1].bits.fflags.bits.uop.is_jalr
invalidate io.bypass[1].bits.fflags.bits.uop.is_br
invalidate io.bypass[1].bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.bypass[1].bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.bypass[1].bits.fflags.bits.uop.iw_state
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.is_std
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.is_sta
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.is_load
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.bypass[1].bits.fflags.bits.uop.ctrl.br_type
invalidate io.bypass[1].bits.fflags.bits.uop.fu_code
invalidate io.bypass[1].bits.fflags.bits.uop.iq_type
invalidate io.bypass[1].bits.fflags.bits.uop.debug_pc
invalidate io.bypass[1].bits.fflags.bits.uop.is_rvc
invalidate io.bypass[1].bits.fflags.bits.uop.debug_inst
invalidate io.bypass[1].bits.fflags.bits.uop.inst
invalidate io.bypass[1].bits.fflags.bits.uop.uopc
invalidate io.bypass[1].bits.fflags.valid
invalidate io.bypass[1].bits.predicated
invalidate io.bypass[1].bits.data
invalidate io.bypass[1].bits.uop.debug_tsrc
invalidate io.bypass[1].bits.uop.debug_fsrc
invalidate io.bypass[1].bits.uop.bp_xcpt_if
invalidate io.bypass[1].bits.uop.bp_debug_if
invalidate io.bypass[1].bits.uop.xcpt_ma_if
invalidate io.bypass[1].bits.uop.xcpt_ae_if
invalidate io.bypass[1].bits.uop.xcpt_pf_if
invalidate io.bypass[1].bits.uop.fp_single
invalidate io.bypass[1].bits.uop.fp_val
invalidate io.bypass[1].bits.uop.frs3_en
invalidate io.bypass[1].bits.uop.lrs2_rtype
invalidate io.bypass[1].bits.uop.lrs1_rtype
invalidate io.bypass[1].bits.uop.dst_rtype
invalidate io.bypass[1].bits.uop.ldst_val
invalidate io.bypass[1].bits.uop.lrs3
invalidate io.bypass[1].bits.uop.lrs2
invalidate io.bypass[1].bits.uop.lrs1
invalidate io.bypass[1].bits.uop.ldst
invalidate io.bypass[1].bits.uop.ldst_is_rs1
invalidate io.bypass[1].bits.uop.flush_on_commit
invalidate io.bypass[1].bits.uop.is_unique
invalidate io.bypass[1].bits.uop.is_sys_pc2epc
invalidate io.bypass[1].bits.uop.uses_stq
invalidate io.bypass[1].bits.uop.uses_ldq
invalidate io.bypass[1].bits.uop.is_amo
invalidate io.bypass[1].bits.uop.is_fencei
invalidate io.bypass[1].bits.uop.is_fence
invalidate io.bypass[1].bits.uop.mem_signed
invalidate io.bypass[1].bits.uop.mem_size
invalidate io.bypass[1].bits.uop.mem_cmd
invalidate io.bypass[1].bits.uop.bypassable
invalidate io.bypass[1].bits.uop.exc_cause
invalidate io.bypass[1].bits.uop.exception
invalidate io.bypass[1].bits.uop.stale_pdst
invalidate io.bypass[1].bits.uop.ppred_busy
invalidate io.bypass[1].bits.uop.prs3_busy
invalidate io.bypass[1].bits.uop.prs2_busy
invalidate io.bypass[1].bits.uop.prs1_busy
invalidate io.bypass[1].bits.uop.ppred
invalidate io.bypass[1].bits.uop.prs3
invalidate io.bypass[1].bits.uop.prs2
invalidate io.bypass[1].bits.uop.prs1
invalidate io.bypass[1].bits.uop.pdst
invalidate io.bypass[1].bits.uop.rxq_idx
invalidate io.bypass[1].bits.uop.stq_idx
invalidate io.bypass[1].bits.uop.ldq_idx
invalidate io.bypass[1].bits.uop.rob_idx
invalidate io.bypass[1].bits.uop.csr_addr
invalidate io.bypass[1].bits.uop.imm_packed
invalidate io.bypass[1].bits.uop.taken
invalidate io.bypass[1].bits.uop.pc_lob
invalidate io.bypass[1].bits.uop.edge_inst
invalidate io.bypass[1].bits.uop.ftq_idx
invalidate io.bypass[1].bits.uop.br_tag
invalidate io.bypass[1].bits.uop.br_mask
invalidate io.bypass[1].bits.uop.is_sfb
invalidate io.bypass[1].bits.uop.is_jal
invalidate io.bypass[1].bits.uop.is_jalr
invalidate io.bypass[1].bits.uop.is_br
invalidate io.bypass[1].bits.uop.iw_p2_poisoned
invalidate io.bypass[1].bits.uop.iw_p1_poisoned
invalidate io.bypass[1].bits.uop.iw_state
invalidate io.bypass[1].bits.uop.ctrl.is_std
invalidate io.bypass[1].bits.uop.ctrl.is_sta
invalidate io.bypass[1].bits.uop.ctrl.is_load
invalidate io.bypass[1].bits.uop.ctrl.csr_cmd
invalidate io.bypass[1].bits.uop.ctrl.fcn_dw
invalidate io.bypass[1].bits.uop.ctrl.op_fcn
invalidate io.bypass[1].bits.uop.ctrl.imm_sel
invalidate io.bypass[1].bits.uop.ctrl.op2_sel
invalidate io.bypass[1].bits.uop.ctrl.op1_sel
invalidate io.bypass[1].bits.uop.ctrl.br_type
invalidate io.bypass[1].bits.uop.fu_code
invalidate io.bypass[1].bits.uop.iq_type
invalidate io.bypass[1].bits.uop.debug_pc
invalidate io.bypass[1].bits.uop.is_rvc
invalidate io.bypass[1].bits.uop.debug_inst
invalidate io.bypass[1].bits.uop.inst
invalidate io.bypass[1].bits.uop.uopc
connect io.bypass[2].valid, UInt<1>(0h0)
invalidate io.bypass[2].bits.fflags.bits.flags
invalidate io.bypass[2].bits.fflags.bits.uop.debug_tsrc
invalidate io.bypass[2].bits.fflags.bits.uop.debug_fsrc
invalidate io.bypass[2].bits.fflags.bits.uop.bp_xcpt_if
invalidate io.bypass[2].bits.fflags.bits.uop.bp_debug_if
invalidate io.bypass[2].bits.fflags.bits.uop.xcpt_ma_if
invalidate io.bypass[2].bits.fflags.bits.uop.xcpt_ae_if
invalidate io.bypass[2].bits.fflags.bits.uop.xcpt_pf_if
invalidate io.bypass[2].bits.fflags.bits.uop.fp_single
invalidate io.bypass[2].bits.fflags.bits.uop.fp_val
invalidate io.bypass[2].bits.fflags.bits.uop.frs3_en
invalidate io.bypass[2].bits.fflags.bits.uop.lrs2_rtype
invalidate io.bypass[2].bits.fflags.bits.uop.lrs1_rtype
invalidate io.bypass[2].bits.fflags.bits.uop.dst_rtype
invalidate io.bypass[2].bits.fflags.bits.uop.ldst_val
invalidate io.bypass[2].bits.fflags.bits.uop.lrs3
invalidate io.bypass[2].bits.fflags.bits.uop.lrs2
invalidate io.bypass[2].bits.fflags.bits.uop.lrs1
invalidate io.bypass[2].bits.fflags.bits.uop.ldst
invalidate io.bypass[2].bits.fflags.bits.uop.ldst_is_rs1
invalidate io.bypass[2].bits.fflags.bits.uop.flush_on_commit
invalidate io.bypass[2].bits.fflags.bits.uop.is_unique
invalidate io.bypass[2].bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.bypass[2].bits.fflags.bits.uop.uses_stq
invalidate io.bypass[2].bits.fflags.bits.uop.uses_ldq
invalidate io.bypass[2].bits.fflags.bits.uop.is_amo
invalidate io.bypass[2].bits.fflags.bits.uop.is_fencei
invalidate io.bypass[2].bits.fflags.bits.uop.is_fence
invalidate io.bypass[2].bits.fflags.bits.uop.mem_signed
invalidate io.bypass[2].bits.fflags.bits.uop.mem_size
invalidate io.bypass[2].bits.fflags.bits.uop.mem_cmd
invalidate io.bypass[2].bits.fflags.bits.uop.bypassable
invalidate io.bypass[2].bits.fflags.bits.uop.exc_cause
invalidate io.bypass[2].bits.fflags.bits.uop.exception
invalidate io.bypass[2].bits.fflags.bits.uop.stale_pdst
invalidate io.bypass[2].bits.fflags.bits.uop.ppred_busy
invalidate io.bypass[2].bits.fflags.bits.uop.prs3_busy
invalidate io.bypass[2].bits.fflags.bits.uop.prs2_busy
invalidate io.bypass[2].bits.fflags.bits.uop.prs1_busy
invalidate io.bypass[2].bits.fflags.bits.uop.ppred
invalidate io.bypass[2].bits.fflags.bits.uop.prs3
invalidate io.bypass[2].bits.fflags.bits.uop.prs2
invalidate io.bypass[2].bits.fflags.bits.uop.prs1
invalidate io.bypass[2].bits.fflags.bits.uop.pdst
invalidate io.bypass[2].bits.fflags.bits.uop.rxq_idx
invalidate io.bypass[2].bits.fflags.bits.uop.stq_idx
invalidate io.bypass[2].bits.fflags.bits.uop.ldq_idx
invalidate io.bypass[2].bits.fflags.bits.uop.rob_idx
invalidate io.bypass[2].bits.fflags.bits.uop.csr_addr
invalidate io.bypass[2].bits.fflags.bits.uop.imm_packed
invalidate io.bypass[2].bits.fflags.bits.uop.taken
invalidate io.bypass[2].bits.fflags.bits.uop.pc_lob
invalidate io.bypass[2].bits.fflags.bits.uop.edge_inst
invalidate io.bypass[2].bits.fflags.bits.uop.ftq_idx
invalidate io.bypass[2].bits.fflags.bits.uop.br_tag
invalidate io.bypass[2].bits.fflags.bits.uop.br_mask
invalidate io.bypass[2].bits.fflags.bits.uop.is_sfb
invalidate io.bypass[2].bits.fflags.bits.uop.is_jal
invalidate io.bypass[2].bits.fflags.bits.uop.is_jalr
invalidate io.bypass[2].bits.fflags.bits.uop.is_br
invalidate io.bypass[2].bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.bypass[2].bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.bypass[2].bits.fflags.bits.uop.iw_state
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.is_std
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.is_sta
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.is_load
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.bypass[2].bits.fflags.bits.uop.ctrl.br_type
invalidate io.bypass[2].bits.fflags.bits.uop.fu_code
invalidate io.bypass[2].bits.fflags.bits.uop.iq_type
invalidate io.bypass[2].bits.fflags.bits.uop.debug_pc
invalidate io.bypass[2].bits.fflags.bits.uop.is_rvc
invalidate io.bypass[2].bits.fflags.bits.uop.debug_inst
invalidate io.bypass[2].bits.fflags.bits.uop.inst
invalidate io.bypass[2].bits.fflags.bits.uop.uopc
invalidate io.bypass[2].bits.fflags.valid
invalidate io.bypass[2].bits.predicated
invalidate io.bypass[2].bits.data
invalidate io.bypass[2].bits.uop.debug_tsrc
invalidate io.bypass[2].bits.uop.debug_fsrc
invalidate io.bypass[2].bits.uop.bp_xcpt_if
invalidate io.bypass[2].bits.uop.bp_debug_if
invalidate io.bypass[2].bits.uop.xcpt_ma_if
invalidate io.bypass[2].bits.uop.xcpt_ae_if
invalidate io.bypass[2].bits.uop.xcpt_pf_if
invalidate io.bypass[2].bits.uop.fp_single
invalidate io.bypass[2].bits.uop.fp_val
invalidate io.bypass[2].bits.uop.frs3_en
invalidate io.bypass[2].bits.uop.lrs2_rtype
invalidate io.bypass[2].bits.uop.lrs1_rtype
invalidate io.bypass[2].bits.uop.dst_rtype
invalidate io.bypass[2].bits.uop.ldst_val
invalidate io.bypass[2].bits.uop.lrs3
invalidate io.bypass[2].bits.uop.lrs2
invalidate io.bypass[2].bits.uop.lrs1
invalidate io.bypass[2].bits.uop.ldst
invalidate io.bypass[2].bits.uop.ldst_is_rs1
invalidate io.bypass[2].bits.uop.flush_on_commit
invalidate io.bypass[2].bits.uop.is_unique
invalidate io.bypass[2].bits.uop.is_sys_pc2epc
invalidate io.bypass[2].bits.uop.uses_stq
invalidate io.bypass[2].bits.uop.uses_ldq
invalidate io.bypass[2].bits.uop.is_amo
invalidate io.bypass[2].bits.uop.is_fencei
invalidate io.bypass[2].bits.uop.is_fence
invalidate io.bypass[2].bits.uop.mem_signed
invalidate io.bypass[2].bits.uop.mem_size
invalidate io.bypass[2].bits.uop.mem_cmd
invalidate io.bypass[2].bits.uop.bypassable
invalidate io.bypass[2].bits.uop.exc_cause
invalidate io.bypass[2].bits.uop.exception
invalidate io.bypass[2].bits.uop.stale_pdst
invalidate io.bypass[2].bits.uop.ppred_busy
invalidate io.bypass[2].bits.uop.prs3_busy
invalidate io.bypass[2].bits.uop.prs2_busy
invalidate io.bypass[2].bits.uop.prs1_busy
invalidate io.bypass[2].bits.uop.ppred
invalidate io.bypass[2].bits.uop.prs3
invalidate io.bypass[2].bits.uop.prs2
invalidate io.bypass[2].bits.uop.prs1
invalidate io.bypass[2].bits.uop.pdst
invalidate io.bypass[2].bits.uop.rxq_idx
invalidate io.bypass[2].bits.uop.stq_idx
invalidate io.bypass[2].bits.uop.ldq_idx
invalidate io.bypass[2].bits.uop.rob_idx
invalidate io.bypass[2].bits.uop.csr_addr
invalidate io.bypass[2].bits.uop.imm_packed
invalidate io.bypass[2].bits.uop.taken
invalidate io.bypass[2].bits.uop.pc_lob
invalidate io.bypass[2].bits.uop.edge_inst
invalidate io.bypass[2].bits.uop.ftq_idx
invalidate io.bypass[2].bits.uop.br_tag
invalidate io.bypass[2].bits.uop.br_mask
invalidate io.bypass[2].bits.uop.is_sfb
invalidate io.bypass[2].bits.uop.is_jal
invalidate io.bypass[2].bits.uop.is_jalr
invalidate io.bypass[2].bits.uop.is_br
invalidate io.bypass[2].bits.uop.iw_p2_poisoned
invalidate io.bypass[2].bits.uop.iw_p1_poisoned
invalidate io.bypass[2].bits.uop.iw_state
invalidate io.bypass[2].bits.uop.ctrl.is_std
invalidate io.bypass[2].bits.uop.ctrl.is_sta
invalidate io.bypass[2].bits.uop.ctrl.is_load
invalidate io.bypass[2].bits.uop.ctrl.csr_cmd
invalidate io.bypass[2].bits.uop.ctrl.fcn_dw
invalidate io.bypass[2].bits.uop.ctrl.op_fcn
invalidate io.bypass[2].bits.uop.ctrl.imm_sel
invalidate io.bypass[2].bits.uop.ctrl.op2_sel
invalidate io.bypass[2].bits.uop.ctrl.op1_sel
invalidate io.bypass[2].bits.uop.ctrl.br_type
invalidate io.bypass[2].bits.uop.fu_code
invalidate io.bypass[2].bits.uop.iq_type
invalidate io.bypass[2].bits.uop.debug_pc
invalidate io.bypass[2].bits.uop.is_rvc
invalidate io.bypass[2].bits.uop.debug_inst
invalidate io.bypass[2].bits.uop.inst
invalidate io.bypass[2].bits.uop.uopc
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.sfence.bits.hg
invalidate io.resp.bits.sfence.bits.hv
invalidate io.resp.bits.sfence.bits.asid
invalidate io.resp.bits.sfence.bits.addr
invalidate io.resp.bits.sfence.bits.rs2
invalidate io.resp.bits.sfence.bits.rs1
invalidate io.resp.bits.sfence.valid
invalidate io.resp.bits.mxcpt.bits
invalidate io.resp.bits.mxcpt.valid
invalidate io.resp.bits.addr
invalidate io.resp.bits.fflags.bits.flags
invalidate io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.resp.bits.fflags.bits.uop.fp_single
invalidate io.resp.bits.fflags.bits.uop.fp_val
invalidate io.resp.bits.fflags.bits.uop.frs3_en
invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.resp.bits.fflags.bits.uop.dst_rtype
invalidate io.resp.bits.fflags.bits.uop.ldst_val
invalidate io.resp.bits.fflags.bits.uop.lrs3
invalidate io.resp.bits.fflags.bits.uop.lrs2
invalidate io.resp.bits.fflags.bits.uop.lrs1
invalidate io.resp.bits.fflags.bits.uop.ldst
invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate io.resp.bits.fflags.bits.uop.is_unique
invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.fflags.bits.uop.uses_stq
invalidate io.resp.bits.fflags.bits.uop.uses_ldq
invalidate io.resp.bits.fflags.bits.uop.is_amo
invalidate io.resp.bits.fflags.bits.uop.is_fencei
invalidate io.resp.bits.fflags.bits.uop.is_fence
invalidate io.resp.bits.fflags.bits.uop.mem_signed
invalidate io.resp.bits.fflags.bits.uop.mem_size
invalidate io.resp.bits.fflags.bits.uop.mem_cmd
invalidate io.resp.bits.fflags.bits.uop.bypassable
invalidate io.resp.bits.fflags.bits.uop.exc_cause
invalidate io.resp.bits.fflags.bits.uop.exception
invalidate io.resp.bits.fflags.bits.uop.stale_pdst
invalidate io.resp.bits.fflags.bits.uop.ppred_busy
invalidate io.resp.bits.fflags.bits.uop.prs3_busy
invalidate io.resp.bits.fflags.bits.uop.prs2_busy
invalidate io.resp.bits.fflags.bits.uop.prs1_busy
invalidate io.resp.bits.fflags.bits.uop.ppred
invalidate io.resp.bits.fflags.bits.uop.prs3
invalidate io.resp.bits.fflags.bits.uop.prs2
invalidate io.resp.bits.fflags.bits.uop.prs1
invalidate io.resp.bits.fflags.bits.uop.pdst
invalidate io.resp.bits.fflags.bits.uop.rxq_idx
invalidate io.resp.bits.fflags.bits.uop.stq_idx
invalidate io.resp.bits.fflags.bits.uop.ldq_idx
invalidate io.resp.bits.fflags.bits.uop.rob_idx
invalidate io.resp.bits.fflags.bits.uop.csr_addr
invalidate io.resp.bits.fflags.bits.uop.imm_packed
invalidate io.resp.bits.fflags.bits.uop.taken
invalidate io.resp.bits.fflags.bits.uop.pc_lob
invalidate io.resp.bits.fflags.bits.uop.edge_inst
invalidate io.resp.bits.fflags.bits.uop.ftq_idx
invalidate io.resp.bits.fflags.bits.uop.br_tag
invalidate io.resp.bits.fflags.bits.uop.br_mask
invalidate io.resp.bits.fflags.bits.uop.is_sfb
invalidate io.resp.bits.fflags.bits.uop.is_jal
invalidate io.resp.bits.fflags.bits.uop.is_jalr
invalidate io.resp.bits.fflags.bits.uop.is_br
invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_state
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.resp.bits.fflags.bits.uop.fu_code
invalidate io.resp.bits.fflags.bits.uop.iq_type
invalidate io.resp.bits.fflags.bits.uop.debug_pc
invalidate io.resp.bits.fflags.bits.uop.is_rvc
invalidate io.resp.bits.fflags.bits.uop.debug_inst
invalidate io.resp.bits.fflags.bits.uop.inst
invalidate io.resp.bits.fflags.bits.uop.uopc
invalidate io.resp.bits.fflags.valid
invalidate io.resp.bits.data
invalidate io.resp.bits.predicated
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
invalidate io.get_ftq_pc.ftq_idx
connect io.req.ready, UInt<1>(0h1)
wire _r_valids_WIRE : UInt<1>[3]
connect _r_valids_WIRE[0], UInt<1>(0h0)
connect _r_valids_WIRE[1], UInt<1>(0h0)
connect _r_valids_WIRE[2], UInt<1>(0h0)
regreset r_valids : UInt<1>[3], clock, reset, _r_valids_WIRE
reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], clock
node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0))
node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0))
node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2)
node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0))
node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4)
connect r_valids[0], _r_valids_0_T_5
connect r_uops[0], io.req.bits.uop
node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T)
connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1
node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask)
node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0))
node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0))
node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2)
node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0))
node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4)
connect r_valids[1], _r_valids_1_T_5
connect r_uops[1], r_uops[0]
node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T)
connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1
connect io.bypass[0].bits.uop, r_uops[0]
node _r_valids_2_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask)
node _r_valids_2_T_1 = neq(_r_valids_2_T, UInt<1>(0h0))
node _r_valids_2_T_2 = eq(_r_valids_2_T_1, UInt<1>(0h0))
node _r_valids_2_T_3 = and(r_valids[1], _r_valids_2_T_2)
node _r_valids_2_T_4 = eq(io.req.bits.kill, UInt<1>(0h0))
node _r_valids_2_T_5 = and(_r_valids_2_T_3, _r_valids_2_T_4)
connect r_valids[2], _r_valids_2_T_5
connect r_uops[2], r_uops[1]
node _r_uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uops_2_br_mask_T_1 = and(r_uops[1].br_mask, _r_uops_2_br_mask_T)
connect r_uops[2].br_mask, _r_uops_2_br_mask_T_1
connect io.bypass[1].bits.uop, r_uops[1]
node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[2].br_mask)
node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0))
node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0))
node _io_resp_valid_T_3 = and(r_valids[2], _io_resp_valid_T_2)
connect io.resp.valid, _io_resp_valid_T_3
connect io.resp.bits.predicated, UInt<1>(0h0)
connect io.resp.bits.uop, r_uops[2]
node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[2].br_mask, _io_resp_bits_uop_br_mask_T)
connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1
connect io.bypass[0].bits.uop, io.req.bits.uop
connect io.bypass[1].bits.uop, r_uops[0]
connect io.bypass[2].bits.uop, r_uops[1]
node _imm_xprlen_sign_T = bits(io.req.bits.uop.imm_packed, 19, 19)
node imm_xprlen_sign = asSInt(_imm_xprlen_sign_T)
node _imm_xprlen_i30_20_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h3))
node _imm_xprlen_i30_20_T_1 = bits(io.req.bits.uop.imm_packed, 18, 8)
node _imm_xprlen_i30_20_T_2 = asSInt(_imm_xprlen_i30_20_T_1)
node imm_xprlen_i30_20 = mux(_imm_xprlen_i30_20_T, _imm_xprlen_i30_20_T_2, imm_xprlen_sign)
node _imm_xprlen_i19_12_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h3))
node _imm_xprlen_i19_12_T_1 = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h4))
node _imm_xprlen_i19_12_T_2 = or(_imm_xprlen_i19_12_T, _imm_xprlen_i19_12_T_1)
node _imm_xprlen_i19_12_T_3 = bits(io.req.bits.uop.imm_packed, 7, 0)
node _imm_xprlen_i19_12_T_4 = asSInt(_imm_xprlen_i19_12_T_3)
node imm_xprlen_i19_12 = mux(_imm_xprlen_i19_12_T_2, _imm_xprlen_i19_12_T_4, imm_xprlen_sign)
node _imm_xprlen_i11_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h3))
node _imm_xprlen_i11_T_1 = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h4))
node _imm_xprlen_i11_T_2 = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h2))
node _imm_xprlen_i11_T_3 = or(_imm_xprlen_i11_T_1, _imm_xprlen_i11_T_2)
node _imm_xprlen_i11_T_4 = bits(io.req.bits.uop.imm_packed, 8, 8)
node _imm_xprlen_i11_T_5 = asSInt(_imm_xprlen_i11_T_4)
node _imm_xprlen_i11_T_6 = mux(_imm_xprlen_i11_T_3, _imm_xprlen_i11_T_5, imm_xprlen_sign)
node imm_xprlen_i11 = mux(_imm_xprlen_i11_T, asSInt(UInt<1>(0h0)), _imm_xprlen_i11_T_6)
node _imm_xprlen_i10_5_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h3))
node _imm_xprlen_i10_5_T_1 = bits(io.req.bits.uop.imm_packed, 18, 14)
node _imm_xprlen_i10_5_T_2 = asSInt(_imm_xprlen_i10_5_T_1)
node imm_xprlen_i10_5 = mux(_imm_xprlen_i10_5_T, asSInt(UInt<1>(0h0)), _imm_xprlen_i10_5_T_2)
node _imm_xprlen_i4_1_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h3))
node _imm_xprlen_i4_1_T_1 = bits(io.req.bits.uop.imm_packed, 13, 9)
node _imm_xprlen_i4_1_T_2 = asSInt(_imm_xprlen_i4_1_T_1)
node imm_xprlen_i4_1 = mux(_imm_xprlen_i4_1_T, asSInt(UInt<1>(0h0)), _imm_xprlen_i4_1_T_2)
node _imm_xprlen_i0_T = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h1))
node _imm_xprlen_i0_T_1 = eq(io.req.bits.uop.ctrl.imm_sel, UInt<3>(0h0))
node _imm_xprlen_i0_T_2 = or(_imm_xprlen_i0_T, _imm_xprlen_i0_T_1)
node _imm_xprlen_i0_T_3 = bits(io.req.bits.uop.imm_packed, 8, 8)
node _imm_xprlen_i0_T_4 = asSInt(_imm_xprlen_i0_T_3)
node imm_xprlen_i0 = mux(_imm_xprlen_i0_T_2, _imm_xprlen_i0_T_4, asSInt(UInt<1>(0h0)))
node imm_xprlen_lo_lo = asUInt(imm_xprlen_i0)
node imm_xprlen_lo_hi_lo = asUInt(imm_xprlen_i4_1)
node imm_xprlen_lo_hi_hi = asUInt(imm_xprlen_i10_5)
node imm_xprlen_lo_hi = cat(imm_xprlen_lo_hi_hi, imm_xprlen_lo_hi_lo)
node imm_xprlen_lo = cat(imm_xprlen_lo_hi, imm_xprlen_lo_lo)
node imm_xprlen_hi_lo_lo = asUInt(imm_xprlen_i11)
node imm_xprlen_hi_lo_hi = asUInt(imm_xprlen_i19_12)
node imm_xprlen_hi_lo = cat(imm_xprlen_hi_lo_hi, imm_xprlen_hi_lo_lo)
node imm_xprlen_hi_hi_lo = asUInt(imm_xprlen_i30_20)
node imm_xprlen_hi_hi_hi = asUInt(imm_xprlen_sign)
node imm_xprlen_hi_hi = cat(imm_xprlen_hi_hi_hi, imm_xprlen_hi_hi_lo)
node imm_xprlen_hi = cat(imm_xprlen_hi_hi, imm_xprlen_hi_lo)
node _imm_xprlen_T = cat(imm_xprlen_hi, imm_xprlen_lo)
node imm_xprlen = asSInt(_imm_xprlen_T)
node _block_pc_T = not(io.get_ftq_pc.pc)
node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f))
node block_pc = not(_block_pc_T_1)
node _uop_pc_T = or(block_pc, io.req.bits.uop.pc_lob)
node _uop_pc_T_1 = mux(io.req.bits.uop.edge_inst, UInt<2>(0h2), UInt<1>(0h0))
node _uop_pc_T_2 = sub(_uop_pc_T, _uop_pc_T_1)
node uop_pc = tail(_uop_pc_T_2, 1)
node _T = eq(io.req.bits.uop.ctrl.op1_sel, UInt<2>(0h0))
node _T_1 = eq(io.req.bits.uop.ctrl.op1_sel, UInt<2>(0h2))
node _T_2 = bits(uop_pc, 39, 39)
node _T_3 = mux(_T_2, UInt<24>(0hffffff), UInt<24>(0h0))
node _T_4 = cat(_T_3, uop_pc)
node _T_5 = mux(_T_1, _T_4, UInt<1>(0h0))
node _T_6 = mux(_T, io.req.bits.rs1_data, _T_5)
node _op2_data_T = eq(io.req.bits.uop.ctrl.op2_sel, UInt<3>(0h1))
node _op2_data_T_1 = asUInt(imm_xprlen)
node _op2_data_T_2 = bits(_op2_data_T_1, 31, 31)
node _op2_data_T_3 = mux(_op2_data_T_2, UInt<32>(0hffffffff), UInt<32>(0h0))
node _op2_data_T_4 = cat(_op2_data_T_3, _op2_data_T_1)
node _op2_data_T_5 = eq(io.req.bits.uop.ctrl.op2_sel, UInt<3>(0h4))
node _op2_data_T_6 = bits(io.req.bits.uop.prs1, 4, 0)
node _op2_data_T_7 = eq(io.req.bits.uop.ctrl.op2_sel, UInt<3>(0h0))
node _op2_data_T_8 = eq(io.req.bits.uop.ctrl.op2_sel, UInt<3>(0h3))
node _op2_data_T_9 = mux(io.req.bits.uop.is_rvc, UInt<2>(0h2), UInt<3>(0h4))
node _op2_data_T_10 = mux(_op2_data_T_8, _op2_data_T_9, UInt<1>(0h0))
node _op2_data_T_11 = mux(_op2_data_T_7, io.req.bits.rs2_data, _op2_data_T_10)
node _op2_data_T_12 = mux(_op2_data_T_5, _op2_data_T_6, _op2_data_T_11)
node op2_data = mux(_op2_data_T, _op2_data_T_4, _op2_data_T_12)
inst alu of ALU
connect alu.clock, clock
connect alu.reset, reset
connect alu.io.in1, _T_6
connect alu.io.in2, op2_data
connect alu.io.fn, io.req.bits.uop.ctrl.op_fcn
connect alu.io.dw, io.req.bits.uop.ctrl.fcn_dw
wire killed : UInt<1>
connect killed, UInt<1>(0h0)
node _T_7 = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _T_8 = neq(_T_7, UInt<1>(0h0))
node _T_9 = or(io.req.bits.kill, _T_8)
when _T_9 :
connect killed, UInt<1>(0h1)
node br_eq = eq(io.req.bits.rs1_data, io.req.bits.rs2_data)
node br_ltu = lt(io.req.bits.rs1_data, io.req.bits.rs2_data)
node _br_lt_T = bits(io.req.bits.rs1_data, 63, 63)
node _br_lt_T_1 = bits(io.req.bits.rs2_data, 63, 63)
node _br_lt_T_2 = xor(_br_lt_T, _br_lt_T_1)
node _br_lt_T_3 = not(_br_lt_T_2)
node _br_lt_T_4 = and(_br_lt_T_3, br_ltu)
node _br_lt_T_5 = bits(io.req.bits.rs1_data, 63, 63)
node _br_lt_T_6 = bits(io.req.bits.rs2_data, 63, 63)
node _br_lt_T_7 = not(_br_lt_T_6)
node _br_lt_T_8 = and(_br_lt_T_5, _br_lt_T_7)
node br_lt = or(_br_lt_T_4, _br_lt_T_8)
node _pc_sel_T = eq(br_eq, UInt<1>(0h0))
node _pc_sel_T_1 = mux(_pc_sel_T, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_2 = mux(br_eq, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_3 = eq(br_lt, UInt<1>(0h0))
node _pc_sel_T_4 = mux(_pc_sel_T_3, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_5 = eq(br_ltu, UInt<1>(0h0))
node _pc_sel_T_6 = mux(_pc_sel_T_5, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_7 = mux(br_lt, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_8 = mux(br_ltu, UInt<2>(0h1), UInt<2>(0h0))
node _pc_sel_T_9 = eq(UInt<4>(0h0), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_10 = mux(_pc_sel_T_9, UInt<2>(0h0), UInt<2>(0h0))
node _pc_sel_T_11 = eq(UInt<4>(0h1), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_12 = mux(_pc_sel_T_11, _pc_sel_T_1, _pc_sel_T_10)
node _pc_sel_T_13 = eq(UInt<4>(0h2), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_14 = mux(_pc_sel_T_13, _pc_sel_T_2, _pc_sel_T_12)
node _pc_sel_T_15 = eq(UInt<4>(0h3), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_16 = mux(_pc_sel_T_15, _pc_sel_T_4, _pc_sel_T_14)
node _pc_sel_T_17 = eq(UInt<4>(0h4), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_18 = mux(_pc_sel_T_17, _pc_sel_T_6, _pc_sel_T_16)
node _pc_sel_T_19 = eq(UInt<4>(0h5), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_20 = mux(_pc_sel_T_19, _pc_sel_T_7, _pc_sel_T_18)
node _pc_sel_T_21 = eq(UInt<4>(0h6), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_22 = mux(_pc_sel_T_21, _pc_sel_T_8, _pc_sel_T_20)
node _pc_sel_T_23 = eq(UInt<4>(0h7), io.req.bits.uop.ctrl.br_type)
node _pc_sel_T_24 = mux(_pc_sel_T_23, UInt<2>(0h1), _pc_sel_T_22)
node _pc_sel_T_25 = eq(UInt<4>(0h8), io.req.bits.uop.ctrl.br_type)
node pc_sel = mux(_pc_sel_T_25, UInt<2>(0h2), _pc_sel_T_24)
node _is_taken_T = eq(killed, UInt<1>(0h0))
node _is_taken_T_1 = and(io.req.valid, _is_taken_T)
node _is_taken_T_2 = or(io.req.bits.uop.is_br, io.req.bits.uop.is_jalr)
node _is_taken_T_3 = or(_is_taken_T_2, io.req.bits.uop.is_jal)
node _is_taken_T_4 = and(_is_taken_T_1, _is_taken_T_3)
node _is_taken_T_5 = neq(pc_sel, UInt<2>(0h0))
node is_taken = and(_is_taken_T_4, _is_taken_T_5)
wire mispredict : UInt<1>
connect mispredict, UInt<1>(0h0)
node _is_br_T = eq(killed, UInt<1>(0h0))
node _is_br_T_1 = and(io.req.valid, _is_br_T)
node _is_br_T_2 = and(_is_br_T_1, io.req.bits.uop.is_br)
node _is_br_T_3 = eq(io.req.bits.uop.is_sfb, UInt<1>(0h0))
node is_br = and(_is_br_T_2, _is_br_T_3)
node _is_jal_T = eq(killed, UInt<1>(0h0))
node _is_jal_T_1 = and(io.req.valid, _is_jal_T)
node is_jal = and(_is_jal_T_1, io.req.bits.uop.is_jal)
node _is_jalr_T = eq(killed, UInt<1>(0h0))
node _is_jalr_T_1 = and(io.req.valid, _is_jalr_T)
node is_jalr = and(_is_jalr_T_1, io.req.bits.uop.is_jalr)
node _T_10 = or(is_br, is_jalr)
when _T_10 :
node _T_11 = eq(pc_sel, UInt<2>(0h0))
when _T_11 :
connect mispredict, io.req.bits.uop.taken
node _T_12 = eq(pc_sel, UInt<2>(0h1))
when _T_12 :
node _mispredict_T = eq(io.req.bits.uop.taken, UInt<1>(0h0))
connect mispredict, _mispredict_T
wire brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}
node _brinfo_valid_T = or(is_br, is_jalr)
connect brinfo.valid, _brinfo_valid_T
connect brinfo.mispredict, mispredict
connect brinfo.uop, io.req.bits.uop
node _brinfo_cfi_type_T = mux(is_br, UInt<3>(0h1), UInt<3>(0h0))
node _brinfo_cfi_type_T_1 = mux(is_jalr, UInt<3>(0h3), _brinfo_cfi_type_T)
connect brinfo.cfi_type, _brinfo_cfi_type_T_1
connect brinfo.taken, is_taken
connect brinfo.pc_sel, pc_sel
invalidate brinfo.jalr_target
node _target_offset_T = bits(imm_xprlen, 20, 0)
node target_offset = asSInt(_target_offset_T)
invalidate brinfo.jalr_target
node jalr_target_base = asSInt(io.req.bits.rs1_data)
wire jalr_target_xlen : UInt<64>
node _jalr_target_xlen_T = add(jalr_target_base, target_offset)
node _jalr_target_xlen_T_1 = tail(_jalr_target_xlen_T, 1)
node _jalr_target_xlen_T_2 = asSInt(_jalr_target_xlen_T_1)
node _jalr_target_xlen_T_3 = asUInt(_jalr_target_xlen_T_2)
connect jalr_target_xlen, _jalr_target_xlen_T_3
node _jalr_target_a_T = asSInt(jalr_target_xlen)
node jalr_target_a = shr(_jalr_target_a_T, 39)
node _jalr_target_msb_T = eq(jalr_target_a, asSInt(UInt<1>(0h0)))
node _jalr_target_msb_T_1 = eq(jalr_target_a, asSInt(UInt<1>(0h1)))
node _jalr_target_msb_T_2 = or(_jalr_target_msb_T, _jalr_target_msb_T_1)
node _jalr_target_msb_T_3 = bits(jalr_target_xlen, 39, 39)
node _jalr_target_msb_T_4 = bits(jalr_target_xlen, 38, 38)
node _jalr_target_msb_T_5 = eq(_jalr_target_msb_T_4, UInt<1>(0h0))
node jalr_target_msb = mux(_jalr_target_msb_T_2, _jalr_target_msb_T_3, _jalr_target_msb_T_5)
node _jalr_target_T = bits(jalr_target_xlen, 38, 0)
node _jalr_target_T_1 = cat(jalr_target_msb, _jalr_target_T)
node _jalr_target_T_2 = asSInt(_jalr_target_T_1)
node _jalr_target_T_3 = and(_jalr_target_T_2, asSInt(UInt<2>(0h2)))
node _jalr_target_T_4 = asSInt(_jalr_target_T_3)
node jalr_target = asUInt(_jalr_target_T_4)
connect brinfo.jalr_target, jalr_target
node _cfi_idx_T = eq(io.get_ftq_pc.entry.start_bank, UInt<1>(0h1))
node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3)
node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0))
node _cfi_idx_T_3 = xor(io.req.bits.uop.pc_lob, _cfi_idx_T_2)
node cfi_idx = bits(_cfi_idx_T_3, 2, 1)
node _T_13 = eq(pc_sel, UInt<2>(0h2))
when _T_13 :
node _mispredict_T_1 = eq(io.get_ftq_pc.next_val, UInt<1>(0h0))
node _mispredict_T_2 = neq(io.get_ftq_pc.next_pc, jalr_target)
node _mispredict_T_3 = or(_mispredict_T_1, _mispredict_T_2)
node _mispredict_T_4 = eq(io.get_ftq_pc.entry.cfi_idx.valid, UInt<1>(0h0))
node _mispredict_T_5 = or(_mispredict_T_3, _mispredict_T_4)
node _mispredict_T_6 = neq(io.get_ftq_pc.entry.cfi_idx.bits, cfi_idx)
node _mispredict_T_7 = or(_mispredict_T_5, _mispredict_T_6)
connect mispredict, _mispredict_T_7
connect brinfo.target_offset, target_offset
connect io.brinfo, brinfo
wire _r_val_WIRE : UInt<1>[3]
connect _r_val_WIRE[0], UInt<1>(0h0)
connect _r_val_WIRE[1], UInt<1>(0h0)
connect _r_val_WIRE[2], UInt<1>(0h0)
regreset r_val : UInt<1>[3], clock, reset, _r_val_WIRE
reg r_data : UInt<64>[3], clock
reg r_pred : UInt<1>[3], clock
node _alu_out_T = eq(io.req.bits.uop.is_br, UInt<1>(0h0))
node _alu_out_T_1 = and(_alu_out_T, io.req.bits.uop.is_sfb)
node _alu_out_T_2 = and(_alu_out_T_1, UInt<1>(0h0))
node _alu_out_T_3 = and(_alu_out_T_2, io.req.bits.pred_data)
node _alu_out_T_4 = mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data)
node _alu_out_T_5 = eq(io.req.bits.uop.uopc, UInt<7>(0h6d))
node _alu_out_T_6 = mux(_alu_out_T_5, io.req.bits.rs2_data, alu.io.out)
node alu_out = mux(_alu_out_T_3, _alu_out_T_4, _alu_out_T_6)
connect r_val[0], io.req.valid
node _r_data_0_T = and(io.req.bits.uop.is_br, io.req.bits.uop.is_sfb)
node _r_data_0_T_1 = and(_r_data_0_T, UInt<1>(0h0))
node _r_data_0_T_2 = eq(pc_sel, UInt<2>(0h1))
node _r_data_0_T_3 = mux(_r_data_0_T_1, _r_data_0_T_2, alu_out)
connect r_data[0], _r_data_0_T_3
node _r_pred_0_T = eq(io.req.bits.uop.is_br, UInt<1>(0h0))
node _r_pred_0_T_1 = and(_r_pred_0_T, io.req.bits.uop.is_sfb)
node _r_pred_0_T_2 = and(_r_pred_0_T_1, UInt<1>(0h0))
node _r_pred_0_T_3 = and(_r_pred_0_T_2, io.req.bits.pred_data)
connect r_pred[0], _r_pred_0_T_3
connect r_val[1], r_val[0]
connect r_data[1], r_data[0]
connect r_pred[1], r_pred[0]
connect r_val[2], r_val[1]
connect r_data[2], r_data[1]
connect r_pred[2], r_pred[1]
connect io.resp.bits.data, r_data[2]
connect io.resp.bits.predicated, r_pred[2]
connect io.bypass[0].valid, io.req.valid
node _io_bypass_0_bits_data_T = and(io.req.bits.uop.is_br, io.req.bits.uop.is_sfb)
node _io_bypass_0_bits_data_T_1 = and(_io_bypass_0_bits_data_T, UInt<1>(0h0))
node _io_bypass_0_bits_data_T_2 = eq(pc_sel, UInt<2>(0h1))
node _io_bypass_0_bits_data_T_3 = mux(_io_bypass_0_bits_data_T_1, _io_bypass_0_bits_data_T_2, alu_out)
connect io.bypass[0].bits.data, _io_bypass_0_bits_data_T_3
connect io.bypass[1].valid, r_val[0]
connect io.bypass[1].bits.data, r_data[0]
connect io.bypass[2].valid, r_val[1]
connect io.bypass[2].bits.data, r_data[1]
connect io.resp.bits.fflags.valid, UInt<1>(0h0) | module ALUUnit( // @[functional-unit.scala:290:7]
input clock, // @[functional-unit.scala:290:7]
input reset, // @[functional-unit.scala:290:7]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
output io_bypass_0_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_0_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_0_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_0_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_0_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_bypass_0_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_0_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_0_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_0_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_0_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_0_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_0_bits_data, // @[functional-unit.scala:168:14]
output io_bypass_1_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_1_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_1_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_1_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_1_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_bypass_1_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_1_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_1_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_1_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_1_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_1_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_1_bits_data, // @[functional-unit.scala:168:14]
output io_bypass_2_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_2_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_2_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_2_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_2_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_bypass_2_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_2_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_2_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_2_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_2_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_2_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_2_bits_data, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_brinfo_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_brinfo_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_brinfo_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_brinfo_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_brinfo_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_iw_state, // @[functional-unit.scala:168:14]
output io_brinfo_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_brinfo_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_br, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_jal, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_brinfo_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_brinfo_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_brinfo_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_brinfo_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_brinfo_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_brinfo_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_brinfo_uop_ppred, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_brinfo_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_brinfo_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_mem_size, // @[functional-unit.scala:168:14]
output io_brinfo_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_fence, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_amo, // @[functional-unit.scala:168:14]
output io_brinfo_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_brinfo_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_unique, // @[functional-unit.scala:168:14]
output io_brinfo_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs3, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_brinfo_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_brinfo_uop_fp_val, // @[functional-unit.scala:168:14]
output io_brinfo_uop_fp_single, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output io_brinfo_valid, // @[functional-unit.scala:168:14]
output io_brinfo_mispredict, // @[functional-unit.scala:168:14]
output io_brinfo_taken, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_cfi_type, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_pc_sel, // @[functional-unit.scala:168:14]
output [39:0] io_brinfo_jalr_target, // @[functional-unit.scala:168:14]
output [20:0] io_brinfo_target_offset, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_idx_valid, // @[functional-unit.scala:168:14]
input [1:0] io_get_ftq_pc_entry_cfi_idx_bits, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_taken, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_mispredicted, // @[functional-unit.scala:168:14]
input [2:0] io_get_ftq_pc_entry_cfi_type, // @[functional-unit.scala:168:14]
input [3:0] io_get_ftq_pc_entry_br_mask, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_is_call, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_is_ret, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_cfi_npc_plus4, // @[functional-unit.scala:168:14]
input [39:0] io_get_ftq_pc_entry_ras_top, // @[functional-unit.scala:168:14]
input [4:0] io_get_ftq_pc_entry_ras_idx, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_entry_start_bank, // @[functional-unit.scala:168:14]
input [39:0] io_get_ftq_pc_pc, // @[functional-unit.scala:168:14]
input io_get_ftq_pc_next_val, // @[functional-unit.scala:168:14]
input [39:0] io_get_ftq_pc_next_pc // @[functional-unit.scala:168:14]
);
wire [63:0] _alu_io_out; // @[functional-unit.scala:327:19]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:290:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:290:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:290:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:290:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:290:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:290:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:290:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:290:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:290:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:290:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:290:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:290:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:290:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:290:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:290:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:290:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:290:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:290:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:290:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:290:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:290:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:290:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:290:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:290:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:290:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:290:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_idx_valid_0 = io_get_ftq_pc_entry_cfi_idx_valid; // @[functional-unit.scala:290:7]
wire [1:0] io_get_ftq_pc_entry_cfi_idx_bits_0 = io_get_ftq_pc_entry_cfi_idx_bits; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_taken_0 = io_get_ftq_pc_entry_cfi_taken; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_mispredicted_0 = io_get_ftq_pc_entry_cfi_mispredicted; // @[functional-unit.scala:290:7]
wire [2:0] io_get_ftq_pc_entry_cfi_type_0 = io_get_ftq_pc_entry_cfi_type; // @[functional-unit.scala:290:7]
wire [3:0] io_get_ftq_pc_entry_br_mask_0 = io_get_ftq_pc_entry_br_mask; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_is_call_0 = io_get_ftq_pc_entry_cfi_is_call; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_is_ret_0 = io_get_ftq_pc_entry_cfi_is_ret; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_cfi_npc_plus4_0 = io_get_ftq_pc_entry_cfi_npc_plus4; // @[functional-unit.scala:290:7]
wire [39:0] io_get_ftq_pc_entry_ras_top_0 = io_get_ftq_pc_entry_ras_top; // @[functional-unit.scala:290:7]
wire [4:0] io_get_ftq_pc_entry_ras_idx_0 = io_get_ftq_pc_entry_ras_idx; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_entry_start_bank_0 = io_get_ftq_pc_entry_start_bank; // @[functional-unit.scala:290:7]
wire [39:0] io_get_ftq_pc_pc_0 = io_get_ftq_pc_pc; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_next_val_0 = io_get_ftq_pc_next_val; // @[functional-unit.scala:290:7]
wire [39:0] io_get_ftq_pc_next_pc_0 = io_get_ftq_pc_next_pc; // @[functional-unit.scala:290:7]
wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:422:82]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:290:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [7:0] io_resp_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:290:7]
wire [7:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:290:7]
wire [7:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:290:7]
wire [7:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 8'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_get_ftq_pc_ghist_ras_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:349:53]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ppred = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_get_ftq_pc_ftq_idx = 4'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 3'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_get_ftq_pc_com_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_get_ftq_pc_ghist_old_history = 64'h0; // @[functional-unit.scala:290:7]
wire io_req_ready = 1'h1; // @[functional-unit.scala:290:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_ready = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_get_ftq_pc_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:290:7]
wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_val_WIRE_0 = 1'h0; // @[functional-unit.scala:446:31]
wire _r_val_WIRE_1 = 1'h0; // @[functional-unit.scala:446:31]
wire _r_val_WIRE_2 = 1'h0; // @[functional-unit.scala:446:31]
wire _alu_out_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:449:51]
wire _r_data_0_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire _r_pred_0_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _r_pred_0_T_3 = 1'h0; // @[functional-unit.scala:454:46]
wire _io_bypass_0_bits_data_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire io_bypass_0_valid_0 = io_req_valid_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_uop_uopc_0 = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_uopc = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7, :385:20]
wire [31:0] io_bypass_0_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] brinfo_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire [31:0] io_bypass_0_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] brinfo_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7, :385:20]
wire [39:0] io_bypass_0_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [39:0] brinfo_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_iq_type = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7, :385:20]
wire [9:0] io_bypass_0_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [9:0] brinfo_uop_fu_code = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7, :385:20]
wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [3:0] brinfo_uop_ctrl_br_type = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_ctrl_op1_sel = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_op2_sel = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_imm_sel = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_ctrl_op_fcn = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_fcn_dw = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_csr_cmd = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_load = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_sta = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_std = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_iw_state_0 = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_iw_state = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_iw_p1_poisoned = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_iw_p2_poisoned = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_br_0 = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_br = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_jalr = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_jal_0 = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_jal = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :385:20]
wire [7:0] io_bypass_0_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [7:0] brinfo_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7, :385:20]
wire [3:0] io_bypass_0_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire [3:0] brinfo_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7, :385:20]
wire [19:0] io_bypass_0_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [19:0] brinfo_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7, :385:20]
wire [11:0] io_bypass_0_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [11:0] brinfo_uop_csr_addr = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7, :385:20]
wire [3:0] io_bypass_0_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire [3:0] brinfo_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7, :385:20]
wire [63:0] io_bypass_0_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire [63:0] brinfo_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bypassable_0 = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bypassable = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ldst_val = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_fp_single_0 = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_fp_single = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7, :385:20]
wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:290:7, :416:49]
wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47]
wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [63:0] _io_bypass_0_bits_data_T_3; // @[functional-unit.scala:467:32]
wire brinfo_valid; // @[functional-unit.scala:385:20]
wire brinfo_mispredict; // @[functional-unit.scala:385:20]
wire brinfo_taken; // @[functional-unit.scala:385:20]
wire [2:0] brinfo_cfi_type; // @[functional-unit.scala:385:20]
wire [1:0] brinfo_pc_sel; // @[functional-unit.scala:385:20]
wire [39:0] brinfo_jalr_target; // @[functional-unit.scala:385:20]
wire [20:0] brinfo_target_offset; // @[functional-unit.scala:385:20]
wire _cfi_idx_T = io_get_ftq_pc_entry_start_bank_0; // @[functional-unit.scala:290:7, :422:69]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:290:7]
wire io_resp_valid_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_0_bits_data_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [7:0] io_bypass_1_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_data_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_valid_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [7:0] io_bypass_2_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_data_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_valid_0; // @[functional-unit.scala:290:7]
wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_brinfo_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_brinfo_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_brinfo_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_brinfo_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [7:0] io_brinfo_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [3:0] io_brinfo_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_brinfo_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_brinfo_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [3:0] io_brinfo_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_brinfo_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire io_brinfo_valid_0; // @[functional-unit.scala:290:7]
wire io_brinfo_mispredict_0; // @[functional-unit.scala:290:7]
wire io_brinfo_taken_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_cfi_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_pc_sel_0; // @[functional-unit.scala:290:7]
wire [39:0] io_brinfo_jalr_target_0; // @[functional-unit.scala:290:7]
wire [20:0] io_brinfo_target_offset_0; // @[functional-unit.scala:290:7]
reg r_valids_0; // @[functional-unit.scala:236:27]
reg r_valids_1; // @[functional-unit.scala:236:27]
reg r_valids_2; // @[functional-unit.scala:236:27]
reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uopc_0 = r_uops_0_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_inst_0 = r_uops_0_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_inst_0 = r_uops_0_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_rvc_0 = r_uops_0_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_pc_0 = r_uops_0_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iq_type_0 = r_uops_0_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fu_code_0 = r_uops_0_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_br_type_0 = r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op1_sel_0 = r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op2_sel_0 = r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_imm_sel_0 = r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op_fcn_0 = r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_fcn_dw_0 = r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_csr_cmd_0 = r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_load_0 = r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_sta_0 = r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_std_0 = r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_state_0 = r_uops_0_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_p1_poisoned_0 = r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_p2_poisoned_0 = r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_br; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_br_0 = r_uops_0_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_jalr_0 = r_uops_0_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_jal; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_jal_0 = r_uops_0_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_sfb_0 = r_uops_0_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_br_mask_0 = r_uops_0_br_mask; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_br_tag_0 = r_uops_0_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ftq_idx_0 = r_uops_0_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_edge_inst_0 = r_uops_0_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_pc_lob_0 = r_uops_0_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_taken; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_taken_0 = r_uops_0_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_imm_packed_0 = r_uops_0_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_csr_addr_0 = r_uops_0_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_rob_idx_0 = r_uops_0_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldq_idx_0 = r_uops_0_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_stq_idx_0 = r_uops_0_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_rxq_idx_0 = r_uops_0_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_pdst_0 = r_uops_0_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs1_0 = r_uops_0_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs2_0 = r_uops_0_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs3_0 = r_uops_0_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ppred_0 = r_uops_0_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs1_busy_0 = r_uops_0_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs2_busy_0 = r_uops_0_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs3_busy_0 = r_uops_0_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ppred_busy_0 = r_uops_0_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_stale_pdst_0 = r_uops_0_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_exception; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_exception_0 = r_uops_0_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_exc_cause_0 = r_uops_0_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bypassable; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bypassable_0 = r_uops_0_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_cmd_0 = r_uops_0_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_size_0 = r_uops_0_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_signed_0 = r_uops_0_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_fence; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_fence_0 = r_uops_0_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_fencei_0 = r_uops_0_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_amo; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_amo_0 = r_uops_0_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uses_ldq_0 = r_uops_0_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uses_stq_0 = r_uops_0_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_sys_pc2epc_0 = r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_unique; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_unique_0 = r_uops_0_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_flush_on_commit_0 = r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_is_rs1_0 = r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_0 = r_uops_0_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs1_0 = r_uops_0_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs2_0 = r_uops_0_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs3_0 = r_uops_0_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_val_0 = r_uops_0_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_dst_rtype_0 = r_uops_0_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs1_rtype_0 = r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs2_rtype_0 = r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_frs3_en_0 = r_uops_0_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_fp_val; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fp_val_0 = r_uops_0_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_fp_single; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fp_single_0 = r_uops_0_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_pf_if_0 = r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_ae_if_0 = r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_ma_if_0 = r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bp_debug_if_0 = r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bp_xcpt_if_0 = r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_fsrc_0 = r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_tsrc_0 = r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_br; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_jal; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_br_mask_0 = r_uops_1_br_mask; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_taken; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_exception; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bypassable; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_fence; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_amo; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_unique; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_fp_val; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_fp_single; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uopc_0 = r_uops_2_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_inst_0 = r_uops_2_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_inst_0 = r_uops_2_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_rvc_0 = r_uops_2_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_pc_0 = r_uops_2_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iq_type_0 = r_uops_2_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fu_code_0 = r_uops_2_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_state_0 = r_uops_2_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_br; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_br_0 = r_uops_2_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jalr_0 = r_uops_2_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_jal; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jal_0 = r_uops_2_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sfb_0 = r_uops_2_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [7:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_br_tag_0 = r_uops_2_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ftq_idx_0 = r_uops_2_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_edge_inst_0 = r_uops_2_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pc_lob_0 = r_uops_2_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_taken; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_taken_0 = r_uops_2_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_imm_packed_0 = r_uops_2_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_csr_addr_0 = r_uops_2_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rob_idx_0 = r_uops_2_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldq_idx_0 = r_uops_2_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stq_idx_0 = r_uops_2_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rxq_idx_0 = r_uops_2_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pdst_0 = r_uops_2_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_prs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_0 = r_uops_2_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_prs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_0 = r_uops_2_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_prs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_0 = r_uops_2_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_2_ppred; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_0 = r_uops_2_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_busy_0 = r_uops_2_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_busy_0 = r_uops_2_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_busy_0 = r_uops_2_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_busy_0 = r_uops_2_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stale_pdst_0 = r_uops_2_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_exception; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exception_0 = r_uops_2_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exc_cause_0 = r_uops_2_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bypassable; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bypassable_0 = r_uops_2_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_cmd_0 = r_uops_2_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_size_0 = r_uops_2_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_signed_0 = r_uops_2_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_fence; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fence_0 = r_uops_2_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fencei_0 = r_uops_2_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_amo; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_amo_0 = r_uops_2_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_ldq_0 = r_uops_2_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_stq_0 = r_uops_2_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_unique; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_unique_0 = r_uops_2_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_flush_on_commit_0 = r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_0 = r_uops_2_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_0 = r_uops_2_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_0 = r_uops_2_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs3_0 = r_uops_2_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_val_0 = r_uops_2_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_dst_rtype_0 = r_uops_2_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_frs3_en_0 = r_uops_2_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_fp_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_val_0 = r_uops_2_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_fp_single; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_single_0 = r_uops_2_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_debug_if_0 = r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_fsrc_0 = r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_tsrc_0 = r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}]
wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59]
wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :290:7]
wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :290:7]
wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}]
wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51]
wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}]
wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59]
wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7]
wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51]
wire _r_valids_2_T_1 = |_r_valids_2_T; // @[util.scala:118:{51,59}]
wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59]
wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7]
wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [7:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51]
wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}]
wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59]
assign _io_resp_valid_T_3 = r_valids_2 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}]
assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :290:7]
wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _io_resp_bits_uop_br_mask_T_1 = r_uops_2_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire _imm_xprlen_sign_T = io_req_bits_uop_imm_packed_0[19]; // @[util.scala:273:18]
wire imm_xprlen_sign = _imm_xprlen_sign_T; // @[util.scala:273:{18,37}]
wire imm_xprlen_hi_hi_hi = imm_xprlen_sign; // @[util.scala:273:37, :282:15]
wire _GEN = io_req_bits_uop_ctrl_imm_sel_0 == 3'h3; // @[util.scala:274:27]
wire _imm_xprlen_i30_20_T; // @[util.scala:274:27]
assign _imm_xprlen_i30_20_T = _GEN; // @[util.scala:274:27]
wire _imm_xprlen_i19_12_T; // @[util.scala:275:27]
assign _imm_xprlen_i19_12_T = _GEN; // @[util.scala:274:27, :275:27]
wire _imm_xprlen_i11_T; // @[util.scala:276:27]
assign _imm_xprlen_i11_T = _GEN; // @[util.scala:274:27, :276:27]
wire _imm_xprlen_i10_5_T; // @[util.scala:278:27]
assign _imm_xprlen_i10_5_T = _GEN; // @[util.scala:274:27, :278:27]
wire _imm_xprlen_i4_1_T; // @[util.scala:279:27]
assign _imm_xprlen_i4_1_T = _GEN; // @[util.scala:274:27, :279:27]
wire [10:0] _imm_xprlen_i30_20_T_1 = io_req_bits_uop_imm_packed_0[18:8]; // @[util.scala:274:39]
wire [10:0] _imm_xprlen_i30_20_T_2 = _imm_xprlen_i30_20_T_1; // @[util.scala:274:{39,46}]
wire [10:0] imm_xprlen_i30_20 = _imm_xprlen_i30_20_T ? _imm_xprlen_i30_20_T_2 : {11{imm_xprlen_sign}}; // @[util.scala:273:37, :274:{21,27,46}]
wire [10:0] imm_xprlen_hi_hi_lo = imm_xprlen_i30_20; // @[util.scala:274:21, :282:15]
wire _GEN_0 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h4; // @[util.scala:275:44]
wire _imm_xprlen_i19_12_T_1; // @[util.scala:275:44]
assign _imm_xprlen_i19_12_T_1 = _GEN_0; // @[util.scala:275:44]
wire _imm_xprlen_i11_T_1; // @[util.scala:277:27]
assign _imm_xprlen_i11_T_1 = _GEN_0; // @[util.scala:275:44, :277:27]
wire _imm_xprlen_i19_12_T_2 = _imm_xprlen_i19_12_T | _imm_xprlen_i19_12_T_1; // @[util.scala:275:{27,36,44}]
wire [7:0] _imm_xprlen_i19_12_T_3 = io_req_bits_uop_imm_packed_0[7:0]; // @[util.scala:275:56]
wire [7:0] _imm_xprlen_i19_12_T_4 = _imm_xprlen_i19_12_T_3; // @[util.scala:275:{56,62}]
wire [7:0] imm_xprlen_i19_12 = _imm_xprlen_i19_12_T_2 ? _imm_xprlen_i19_12_T_4 : {8{imm_xprlen_sign}}; // @[util.scala:273:37, :275:{21,36,62}]
wire [7:0] imm_xprlen_hi_lo_hi = imm_xprlen_i19_12; // @[util.scala:275:21, :282:15]
wire _imm_xprlen_i11_T_2 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h2; // @[util.scala:277:44]
wire _imm_xprlen_i11_T_3 = _imm_xprlen_i11_T_1 | _imm_xprlen_i11_T_2; // @[util.scala:277:{27,36,44}]
wire _imm_xprlen_i11_T_4 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56]
wire _imm_xprlen_i0_T_3 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56, :280:56]
wire _imm_xprlen_i11_T_5 = _imm_xprlen_i11_T_4; // @[util.scala:277:{56,60}]
wire _imm_xprlen_i11_T_6 = _imm_xprlen_i11_T_3 ? _imm_xprlen_i11_T_5 : imm_xprlen_sign; // @[util.scala:273:37, :277:{21,36,60}]
wire imm_xprlen_i11 = ~_imm_xprlen_i11_T & _imm_xprlen_i11_T_6; // @[util.scala:276:{21,27}, :277:21]
wire imm_xprlen_hi_lo_lo = imm_xprlen_i11; // @[util.scala:276:21, :282:15]
wire [4:0] _imm_xprlen_i10_5_T_1 = io_req_bits_uop_imm_packed_0[18:14]; // @[util.scala:278:44]
wire [4:0] _imm_xprlen_i10_5_T_2 = _imm_xprlen_i10_5_T_1; // @[util.scala:278:{44,52}]
wire [4:0] imm_xprlen_i10_5 = _imm_xprlen_i10_5_T ? 5'h0 : _imm_xprlen_i10_5_T_2; // @[util.scala:278:{21,27,52}]
wire [4:0] imm_xprlen_lo_hi_hi = imm_xprlen_i10_5; // @[util.scala:278:21, :282:15]
wire [4:0] _imm_xprlen_i4_1_T_1 = io_req_bits_uop_imm_packed_0[13:9]; // @[util.scala:279:44]
wire [4:0] _imm_xprlen_i4_1_T_2 = _imm_xprlen_i4_1_T_1; // @[util.scala:279:{44,51}]
wire [4:0] imm_xprlen_i4_1 = _imm_xprlen_i4_1_T ? 5'h0 : _imm_xprlen_i4_1_T_2; // @[util.scala:279:{21,27,51}]
wire [4:0] imm_xprlen_lo_hi_lo = imm_xprlen_i4_1; // @[util.scala:279:21, :282:15]
wire _imm_xprlen_i0_T = io_req_bits_uop_ctrl_imm_sel_0 == 3'h1; // @[util.scala:280:27]
wire _imm_xprlen_i0_T_1 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h0; // @[util.scala:280:44]
wire _imm_xprlen_i0_T_2 = _imm_xprlen_i0_T | _imm_xprlen_i0_T_1; // @[util.scala:280:{27,36,44}]
wire _imm_xprlen_i0_T_4 = _imm_xprlen_i0_T_3; // @[util.scala:280:{56,60}]
wire imm_xprlen_i0 = _imm_xprlen_i0_T_2 & _imm_xprlen_i0_T_4; // @[util.scala:280:{21,36,60}]
wire imm_xprlen_lo_lo = imm_xprlen_i0; // @[util.scala:280:21, :282:15]
wire [9:0] imm_xprlen_lo_hi = {imm_xprlen_lo_hi_hi, imm_xprlen_lo_hi_lo}; // @[util.scala:282:15]
wire [10:0] imm_xprlen_lo = {imm_xprlen_lo_hi, imm_xprlen_lo_lo}; // @[util.scala:282:15]
wire [8:0] imm_xprlen_hi_lo = {imm_xprlen_hi_lo_hi, imm_xprlen_hi_lo_lo}; // @[util.scala:282:15]
wire [11:0] imm_xprlen_hi_hi = {imm_xprlen_hi_hi_hi, imm_xprlen_hi_hi_lo}; // @[util.scala:282:15]
wire [20:0] imm_xprlen_hi = {imm_xprlen_hi_hi, imm_xprlen_hi_lo}; // @[util.scala:282:15]
wire [31:0] _imm_xprlen_T = {imm_xprlen_hi, imm_xprlen_lo}; // @[util.scala:282:15]
wire [31:0] imm_xprlen = _imm_xprlen_T; // @[util.scala:282:{15,60}]
wire [31:0] _op2_data_T_1 = imm_xprlen; // @[util.scala:282:60]
wire [39:0] _block_pc_T = ~io_get_ftq_pc_pc_0; // @[util.scala:237:7]
wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}]
wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:237:{5,11}]
wire [39:0] _uop_pc_T = {block_pc[39:6], block_pc[5:0] | io_req_bits_uop_pc_lob_0}; // @[util.scala:237:5]
wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:290:7, :310:47]
wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:310:{28,42,47}]
wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:310:42]
wire _op2_data_T = io_req_bits_uop_ctrl_op2_sel_0 == 3'h1; // @[functional-unit.scala:290:7, :321:39]
wire _op2_data_T_2 = _op2_data_T_1[31]; // @[util.scala:261:46]
wire [31:0] _op2_data_T_3 = {32{_op2_data_T_2}}; // @[util.scala:261:{25,46}]
wire [63:0] _op2_data_T_4 = {_op2_data_T_3, _op2_data_T_1}; // @[util.scala:261:{20,25}]
wire _op2_data_T_5 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h4; // @[functional-unit.scala:290:7, :322:39]
wire [4:0] _op2_data_T_6 = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:290:7, :322:73]
wire _op2_data_T_7 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h0; // @[functional-unit.scala:290:7, :323:39]
wire _op2_data_T_8 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h3; // @[functional-unit.scala:290:7, :324:39]
wire [2:0] _op2_data_T_9 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:290:7, :324:56]
wire [2:0] _op2_data_T_10 = _op2_data_T_8 ? _op2_data_T_9 : 3'h0; // @[functional-unit.scala:324:{21,39,56}]
wire [63:0] _op2_data_T_11 = _op2_data_T_7 ? io_req_bits_rs2_data_0 : {61'h0, _op2_data_T_10}; // @[functional-unit.scala:290:7, :323:{21,39}, :324:21]
wire [63:0] _op2_data_T_12 = _op2_data_T_5 ? {59'h0, _op2_data_T_6} : _op2_data_T_11; // @[functional-unit.scala:322:{21,39,73}, :323:21]
wire [63:0] op2_data = _op2_data_T ? _op2_data_T_4 : _op2_data_T_12; // @[util.scala:261:20]
wire killed; // @[functional-unit.scala:337:24]
assign killed = |{io_req_bits_kill_0, _r_valids_0_T}; // @[util.scala:118:{51,59}]
wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :344:21]
wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :345:28]
wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22]
wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22, :347:20]
wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36]
wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36, :347:35]
wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:346:{22,31,36}]
wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:346:{17,31}]
wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:345:28, :346:{17,46}]
wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:347:{31,35}]
wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:347:{20,29,31}]
wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:346:{46,55}, :347:29]
wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:344:21, :351:39]
wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:351:{38,39}]
wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:344:21, :352:38]
wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:346:55, :353:39]
wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:353:{38,39}]
wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:345:28, :354:39]
wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:354:{38,39}]
wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:346:55, :355:38]
wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:345:28, :356:38]
wire _pc_sel_T_9 = io_req_bits_uop_ctrl_br_type_0 == 4'h0; // @[functional-unit.scala:290:7, :349:53]
wire _pc_sel_T_11 = io_req_bits_uop_ctrl_br_type_0 == 4'h1; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:349:53, :351:38]
wire _pc_sel_T_13 = io_req_bits_uop_ctrl_br_type_0 == 4'h2; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:349:53, :352:38]
wire _pc_sel_T_15 = io_req_bits_uop_ctrl_br_type_0 == 4'h3; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:349:53, :353:38]
wire _pc_sel_T_17 = io_req_bits_uop_ctrl_br_type_0 == 4'h4; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:349:53, :354:38]
wire _pc_sel_T_19 = io_req_bits_uop_ctrl_br_type_0 == 4'h5; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:349:53, :355:38]
wire _pc_sel_T_21 = io_req_bits_uop_ctrl_br_type_0 == 4'h6; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:349:53, :356:38]
wire _pc_sel_T_23 = io_req_bits_uop_ctrl_br_type_0 == 4'h7; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:349:53]
wire _pc_sel_T_25 = io_req_bits_uop_ctrl_br_type_0 == 4'h8; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:349:53]
assign brinfo_pc_sel = pc_sel; // @[functional-unit.scala:349:53, :385:20]
wire _is_taken_T = ~killed; // @[functional-unit.scala:337:24, :362:20]
wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:290:7, :361:31, :362:20]
wire _is_taken_T_2 = io_req_bits_uop_is_br_0 | io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :363:31]
wire _is_taken_T_3 = _is_taken_T_2 | io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :363:{31,46}]
wire _is_taken_T_4 = _is_taken_T_1 & _is_taken_T_3; // @[functional-unit.scala:361:31, :362:28, :363:46]
wire _is_taken_T_5 = |pc_sel; // @[functional-unit.scala:349:53, :364:28]
wire is_taken = _is_taken_T_4 & _is_taken_T_5; // @[functional-unit.scala:362:28, :363:61, :364:28]
assign brinfo_taken = is_taken; // @[functional-unit.scala:363:61, :385:20]
wire mispredict; // @[functional-unit.scala:367:28]
assign brinfo_mispredict = mispredict; // @[functional-unit.scala:367:28, :385:20]
wire _is_br_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :369:40]
wire _is_br_T_1 = io_req_valid_0 & _is_br_T; // @[functional-unit.scala:290:7, :369:{37,40}]
wire _is_br_T_2 = _is_br_T_1 & io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :369:{37,48}]
wire _is_br_T_3 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :369:64]
wire is_br = _is_br_T_2 & _is_br_T_3; // @[functional-unit.scala:369:{48,61,64}]
wire _is_jal_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :370:40]
wire _is_jal_T_1 = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:290:7, :370:{37,40}]
wire is_jal = _is_jal_T_1 & io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :370:{37,48}]
wire _is_jalr_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :371:40]
wire _is_jalr_T_1 = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:290:7, :371:{37,40}]
wire is_jalr = _is_jalr_T_1 & io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :371:{37,48}]
wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:369:61, :371:48, :373:15, :388:34]
wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7, :381:21]
assign io_brinfo_uop_uopc_0 = brinfo_uop_uopc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_inst_0 = brinfo_uop_inst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_debug_inst_0 = brinfo_uop_debug_inst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_rvc_0 = brinfo_uop_is_rvc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_debug_pc_0 = brinfo_uop_debug_pc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_iq_type_0 = brinfo_uop_iq_type; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_fu_code_0 = brinfo_uop_fu_code; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_br_type_0 = brinfo_uop_ctrl_br_type; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_op1_sel_0 = brinfo_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_op2_sel_0 = brinfo_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_imm_sel_0 = brinfo_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_op_fcn_0 = brinfo_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_fcn_dw_0 = brinfo_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_csr_cmd_0 = brinfo_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_is_load_0 = brinfo_uop_ctrl_is_load; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_is_sta_0 = brinfo_uop_ctrl_is_sta; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ctrl_is_std_0 = brinfo_uop_ctrl_is_std; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_iw_state_0 = brinfo_uop_iw_state; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_iw_p1_poisoned_0 = brinfo_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_iw_p2_poisoned_0 = brinfo_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_br_0 = brinfo_uop_is_br; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_jalr_0 = brinfo_uop_is_jalr; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_jal_0 = brinfo_uop_is_jal; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_sfb_0 = brinfo_uop_is_sfb; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_br_mask_0 = brinfo_uop_br_mask; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_br_tag_0 = brinfo_uop_br_tag; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ftq_idx_0 = brinfo_uop_ftq_idx; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_edge_inst_0 = brinfo_uop_edge_inst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_pc_lob_0 = brinfo_uop_pc_lob; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_taken_0 = brinfo_uop_taken; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_imm_packed_0 = brinfo_uop_imm_packed; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_csr_addr_0 = brinfo_uop_csr_addr; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_rob_idx_0 = brinfo_uop_rob_idx; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ldq_idx_0 = brinfo_uop_ldq_idx; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_stq_idx_0 = brinfo_uop_stq_idx; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_rxq_idx_0 = brinfo_uop_rxq_idx; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_pdst_0 = brinfo_uop_pdst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs1_0 = brinfo_uop_prs1; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs2_0 = brinfo_uop_prs2; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs3_0 = brinfo_uop_prs3; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ppred_0 = brinfo_uop_ppred; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs1_busy_0 = brinfo_uop_prs1_busy; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs2_busy_0 = brinfo_uop_prs2_busy; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_prs3_busy_0 = brinfo_uop_prs3_busy; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ppred_busy_0 = brinfo_uop_ppred_busy; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_stale_pdst_0 = brinfo_uop_stale_pdst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_exception_0 = brinfo_uop_exception; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_exc_cause_0 = brinfo_uop_exc_cause; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_bypassable_0 = brinfo_uop_bypassable; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_mem_cmd_0 = brinfo_uop_mem_cmd; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_mem_size_0 = brinfo_uop_mem_size; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_mem_signed_0 = brinfo_uop_mem_signed; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_fence_0 = brinfo_uop_is_fence; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_fencei_0 = brinfo_uop_is_fencei; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_amo_0 = brinfo_uop_is_amo; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_uses_ldq_0 = brinfo_uop_uses_ldq; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_uses_stq_0 = brinfo_uop_uses_stq; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_sys_pc2epc_0 = brinfo_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_is_unique_0 = brinfo_uop_is_unique; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_flush_on_commit_0 = brinfo_uop_flush_on_commit; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ldst_is_rs1_0 = brinfo_uop_ldst_is_rs1; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ldst_0 = brinfo_uop_ldst; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_lrs1_0 = brinfo_uop_lrs1; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_lrs2_0 = brinfo_uop_lrs2; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_lrs3_0 = brinfo_uop_lrs3; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_ldst_val_0 = brinfo_uop_ldst_val; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_dst_rtype_0 = brinfo_uop_dst_rtype; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_lrs1_rtype_0 = brinfo_uop_lrs1_rtype; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_lrs2_rtype_0 = brinfo_uop_lrs2_rtype; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_frs3_en_0 = brinfo_uop_frs3_en; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_fp_val_0 = brinfo_uop_fp_val; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_fp_single_0 = brinfo_uop_fp_single; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_xcpt_pf_if_0 = brinfo_uop_xcpt_pf_if; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_xcpt_ae_if_0 = brinfo_uop_xcpt_ae_if; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_xcpt_ma_if_0 = brinfo_uop_xcpt_ma_if; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_bp_debug_if_0 = brinfo_uop_bp_debug_if; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_bp_xcpt_if_0 = brinfo_uop_bp_xcpt_if; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_debug_fsrc_0 = brinfo_uop_debug_fsrc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_uop_debug_tsrc_0 = brinfo_uop_debug_tsrc; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_valid_0 = brinfo_valid; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_mispredict_0 = brinfo_mispredict; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_taken_0 = brinfo_taken; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] _brinfo_cfi_type_T_1; // @[functional-unit.scala:391:31]
assign io_brinfo_cfi_type_0 = brinfo_cfi_type; // @[functional-unit.scala:290:7, :385:20]
assign io_brinfo_pc_sel_0 = brinfo_pc_sel; // @[functional-unit.scala:290:7, :385:20]
wire [39:0] jalr_target; // @[functional-unit.scala:419:96]
assign io_brinfo_jalr_target_0 = brinfo_jalr_target; // @[functional-unit.scala:290:7, :385:20]
wire [20:0] target_offset; // @[functional-unit.scala:402:40]
assign io_brinfo_target_offset_0 = brinfo_target_offset; // @[functional-unit.scala:290:7, :385:20]
assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:385:20, :388:34]
wire [2:0] _brinfo_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:369:61, :392:31]
assign _brinfo_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_cfi_type_T; // @[functional-unit.scala:371:48, :391:31, :392:31]
assign brinfo_cfi_type = _brinfo_cfi_type_T_1; // @[functional-unit.scala:385:20, :391:31]
wire [20:0] _target_offset_T = imm_xprlen[20:0]; // @[util.scala:282:60]
assign target_offset = _target_offset_T; // @[functional-unit.scala:402:{33,40}]
assign brinfo_target_offset = target_offset; // @[functional-unit.scala:385:20, :402:40]
wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:418:60]
wire [63:0] jalr_target_xlen; // @[functional-unit.scala:417:32]
wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:410:18, :417:32]
wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:402:40, :416:49, :418:43]
wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:418:43]
wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:418:43]
assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:418:{43,60}]
assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:417:32, :418:60]
wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:410:{18,25}]
wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:410:25, :411:23]
wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:410:25, :411:36]
wire _jalr_target_msb_T_2 = _jalr_target_msb_T | _jalr_target_msb_T_1; // @[functional-unit.scala:411:{23,31,36}]
wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:411:48, :417:32]
wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:411:64, :417:32]
wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:411:{61,64}]
wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:411:{20,31,48,61}]
wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:412:18, :417:32]
wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:411:20, :412:{10,18}]
wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:412:10, :419:81]
wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:419:{81,88}]
wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:419:88]
assign jalr_target = _jalr_target_T_4; // @[functional-unit.scala:419:{88,96}]
assign brinfo_jalr_target = jalr_target; // @[functional-unit.scala:385:20, :419:96]
wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[functional-unit.scala:422:{37,69}]
wire [5:0] _cfi_idx_T_3 = {io_req_bits_uop_pc_lob_0[5:4], io_req_bits_uop_pc_lob_0[3:0] ^ _cfi_idx_T_2}; // @[functional-unit.scala:290:7, :422:{32,37}]
wire [1:0] cfi_idx = _cfi_idx_T_3[2:1]; // @[functional-unit.scala:422:{32,112}]
wire _mispredict_T_1 = ~io_get_ftq_pc_next_val_0; // @[functional-unit.scala:290:7, :425:21]
wire _mispredict_T_2 = io_get_ftq_pc_next_pc_0 != jalr_target; // @[functional-unit.scala:290:7, :419:96, :426:44]
wire _mispredict_T_3 = _mispredict_T_1 | _mispredict_T_2; // @[functional-unit.scala:425:{21,45}, :426:44]
wire _mispredict_T_4 = ~io_get_ftq_pc_entry_cfi_idx_valid_0; // @[functional-unit.scala:290:7, :427:21]
wire _mispredict_T_5 = _mispredict_T_3 | _mispredict_T_4; // @[functional-unit.scala:425:45, :426:61, :427:21]
wire _mispredict_T_6 = io_get_ftq_pc_entry_cfi_idx_bits_0 != cfi_idx; // @[functional-unit.scala:290:7, :422:112, :428:55]
wire _mispredict_T_7 = _mispredict_T_5 | _mispredict_T_6; // @[functional-unit.scala:426:61, :427:56, :428:55]
assign mispredict = pc_sel == 2'h2 ? _mispredict_T_7 : _brinfo_valid_T & (pc_sel == 2'h1 ? _mispredict_T : ~(|pc_sel) & io_req_bits_uop_taken_0); // @[functional-unit.scala:290:7, :349:53, :364:28, :367:28, :373:27, :377:{18,32}, :378:18, :380:{18,32}, :381:{18,21}, :388:34, :424:{18,31}, :425:18, :427:56]
reg r_val_0; // @[functional-unit.scala:446:23]
assign io_bypass_1_valid_0 = r_val_0; // @[functional-unit.scala:290:7, :446:23]
reg r_val_1; // @[functional-unit.scala:446:23]
assign io_bypass_2_valid_0 = r_val_1; // @[functional-unit.scala:290:7, :446:23]
reg r_val_2; // @[functional-unit.scala:446:23]
reg [63:0] r_data_0; // @[functional-unit.scala:447:19]
assign io_bypass_1_bits_data_0 = r_data_0; // @[functional-unit.scala:290:7, :447:19]
reg [63:0] r_data_1; // @[functional-unit.scala:447:19]
assign io_bypass_2_bits_data_0 = r_data_1; // @[functional-unit.scala:290:7, :447:19]
reg [63:0] r_data_2; // @[functional-unit.scala:447:19]
assign io_resp_bits_data_0 = r_data_2; // @[functional-unit.scala:290:7, :447:19]
wire _alu_out_T = ~io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :450:8]
wire _alu_out_T_5 = io_req_bits_uop_uopc_0 == 7'h6D; // @[functional-unit.scala:290:7, :451:30]
wire [63:0] _alu_out_T_6 = _alu_out_T_5 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:290:7, :327:19, :451:{8,30}]
wire [63:0] alu_out = _alu_out_T_6; // @[functional-unit.scala:449:20, :451:8]
wire [63:0] _r_data_0_T_3 = alu_out; // @[functional-unit.scala:449:20, :453:19]
assign _io_bypass_0_bits_data_T_3 = alu_out; // @[functional-unit.scala:449:20, :467:32]
wire _GEN_1 = io_req_bits_uop_is_br_0 & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire _r_data_0_T; // @[micro-op.scala:109:32]
assign _r_data_0_T = _GEN_1; // @[micro-op.scala:109:32]
wire _io_bypass_0_bits_data_T; // @[micro-op.scala:109:32]
assign _io_bypass_0_bits_data_T = _GEN_1; // @[micro-op.scala:109:32]
wire _GEN_2 = pc_sel == 2'h1; // @[functional-unit.scala:349:53, :453:54]
wire _r_data_0_T_2; // @[functional-unit.scala:453:54]
assign _r_data_0_T_2 = _GEN_2; // @[functional-unit.scala:453:54]
wire _io_bypass_0_bits_data_T_2; // @[functional-unit.scala:467:67]
assign _io_bypass_0_bits_data_T_2 = _GEN_2; // @[functional-unit.scala:453:54, :467:67]
wire _r_pred_0_T = ~io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire _r_pred_0_T_1 = _r_pred_0_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_data_0 = _io_bypass_0_bits_data_T_3; // @[functional-unit.scala:290:7, :467:32]
always @(posedge clock) begin // @[functional-unit.scala:290:7]
if (reset) begin // @[functional-unit.scala:290:7]
r_valids_0 <= 1'h0; // @[functional-unit.scala:236:27]
r_valids_1 <= 1'h0; // @[functional-unit.scala:236:27]
r_valids_2 <= 1'h0; // @[functional-unit.scala:236:27]
r_val_0 <= 1'h0; // @[functional-unit.scala:446:23]
r_val_1 <= 1'h0; // @[functional-unit.scala:446:23]
r_val_2 <= 1'h0; // @[functional-unit.scala:446:23]
end
else begin // @[functional-unit.scala:290:7]
r_valids_0 <= _r_valids_0_T_5; // @[functional-unit.scala:236:27, :240:84]
r_valids_1 <= _r_valids_1_T_5; // @[functional-unit.scala:236:27, :246:83]
r_valids_2 <= _r_valids_2_T_5; // @[functional-unit.scala:236:27, :246:83]
r_val_0 <= io_req_valid_0; // @[functional-unit.scala:290:7, :446:23]
r_val_1 <= r_val_0; // @[functional-unit.scala:446:23]
r_val_2 <= r_val_1; // @[functional-unit.scala:446:23]
end
r_uops_0_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_br_mask <= _r_uops_0_br_mask_T_1; // @[util.scala:85:25]
r_uops_0_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:237:23, :290:7]
r_uops_1_uopc <= r_uops_0_uopc; // @[functional-unit.scala:237:23]
r_uops_1_inst <= r_uops_0_inst; // @[functional-unit.scala:237:23]
r_uops_1_debug_inst <= r_uops_0_debug_inst; // @[functional-unit.scala:237:23]
r_uops_1_is_rvc <= r_uops_0_is_rvc; // @[functional-unit.scala:237:23]
r_uops_1_debug_pc <= r_uops_0_debug_pc; // @[functional-unit.scala:237:23]
r_uops_1_iq_type <= r_uops_0_iq_type; // @[functional-unit.scala:237:23]
r_uops_1_fu_code <= r_uops_0_fu_code; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23]
r_uops_1_iw_state <= r_uops_0_iw_state; // @[functional-unit.scala:237:23]
r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23]
r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23]
r_uops_1_is_br <= r_uops_0_is_br; // @[functional-unit.scala:237:23]
r_uops_1_is_jalr <= r_uops_0_is_jalr; // @[functional-unit.scala:237:23]
r_uops_1_is_jal <= r_uops_0_is_jal; // @[functional-unit.scala:237:23]
r_uops_1_is_sfb <= r_uops_0_is_sfb; // @[functional-unit.scala:237:23]
r_uops_1_br_mask <= _r_uops_1_br_mask_T_1; // @[util.scala:85:25]
r_uops_1_br_tag <= r_uops_0_br_tag; // @[functional-unit.scala:237:23]
r_uops_1_ftq_idx <= r_uops_0_ftq_idx; // @[functional-unit.scala:237:23]
r_uops_1_edge_inst <= r_uops_0_edge_inst; // @[functional-unit.scala:237:23]
r_uops_1_pc_lob <= r_uops_0_pc_lob; // @[functional-unit.scala:237:23]
r_uops_1_taken <= r_uops_0_taken; // @[functional-unit.scala:237:23]
r_uops_1_imm_packed <= r_uops_0_imm_packed; // @[functional-unit.scala:237:23]
r_uops_1_csr_addr <= r_uops_0_csr_addr; // @[functional-unit.scala:237:23]
r_uops_1_rob_idx <= r_uops_0_rob_idx; // @[functional-unit.scala:237:23]
r_uops_1_ldq_idx <= r_uops_0_ldq_idx; // @[functional-unit.scala:237:23]
r_uops_1_stq_idx <= r_uops_0_stq_idx; // @[functional-unit.scala:237:23]
r_uops_1_rxq_idx <= r_uops_0_rxq_idx; // @[functional-unit.scala:237:23]
r_uops_1_pdst <= r_uops_0_pdst; // @[functional-unit.scala:237:23]
r_uops_1_prs1 <= r_uops_0_prs1; // @[functional-unit.scala:237:23]
r_uops_1_prs2 <= r_uops_0_prs2; // @[functional-unit.scala:237:23]
r_uops_1_prs3 <= r_uops_0_prs3; // @[functional-unit.scala:237:23]
r_uops_1_ppred <= r_uops_0_ppred; // @[functional-unit.scala:237:23]
r_uops_1_prs1_busy <= r_uops_0_prs1_busy; // @[functional-unit.scala:237:23]
r_uops_1_prs2_busy <= r_uops_0_prs2_busy; // @[functional-unit.scala:237:23]
r_uops_1_prs3_busy <= r_uops_0_prs3_busy; // @[functional-unit.scala:237:23]
r_uops_1_ppred_busy <= r_uops_0_ppred_busy; // @[functional-unit.scala:237:23]
r_uops_1_stale_pdst <= r_uops_0_stale_pdst; // @[functional-unit.scala:237:23]
r_uops_1_exception <= r_uops_0_exception; // @[functional-unit.scala:237:23]
r_uops_1_exc_cause <= r_uops_0_exc_cause; // @[functional-unit.scala:237:23]
r_uops_1_bypassable <= r_uops_0_bypassable; // @[functional-unit.scala:237:23]
r_uops_1_mem_cmd <= r_uops_0_mem_cmd; // @[functional-unit.scala:237:23]
r_uops_1_mem_size <= r_uops_0_mem_size; // @[functional-unit.scala:237:23]
r_uops_1_mem_signed <= r_uops_0_mem_signed; // @[functional-unit.scala:237:23]
r_uops_1_is_fence <= r_uops_0_is_fence; // @[functional-unit.scala:237:23]
r_uops_1_is_fencei <= r_uops_0_is_fencei; // @[functional-unit.scala:237:23]
r_uops_1_is_amo <= r_uops_0_is_amo; // @[functional-unit.scala:237:23]
r_uops_1_uses_ldq <= r_uops_0_uses_ldq; // @[functional-unit.scala:237:23]
r_uops_1_uses_stq <= r_uops_0_uses_stq; // @[functional-unit.scala:237:23]
r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23]
r_uops_1_is_unique <= r_uops_0_is_unique; // @[functional-unit.scala:237:23]
r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23]
r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23]
r_uops_1_ldst <= r_uops_0_ldst; // @[functional-unit.scala:237:23]
r_uops_1_lrs1 <= r_uops_0_lrs1; // @[functional-unit.scala:237:23]
r_uops_1_lrs2 <= r_uops_0_lrs2; // @[functional-unit.scala:237:23]
r_uops_1_lrs3 <= r_uops_0_lrs3; // @[functional-unit.scala:237:23]
r_uops_1_ldst_val <= r_uops_0_ldst_val; // @[functional-unit.scala:237:23]
r_uops_1_dst_rtype <= r_uops_0_dst_rtype; // @[functional-unit.scala:237:23]
r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23]
r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23]
r_uops_1_frs3_en <= r_uops_0_frs3_en; // @[functional-unit.scala:237:23]
r_uops_1_fp_val <= r_uops_0_fp_val; // @[functional-unit.scala:237:23]
r_uops_1_fp_single <= r_uops_0_fp_single; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23]
r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23]
r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23]
r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23]
r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23]
r_uops_2_uopc <= r_uops_1_uopc; // @[functional-unit.scala:237:23]
r_uops_2_inst <= r_uops_1_inst; // @[functional-unit.scala:237:23]
r_uops_2_debug_inst <= r_uops_1_debug_inst; // @[functional-unit.scala:237:23]
r_uops_2_is_rvc <= r_uops_1_is_rvc; // @[functional-unit.scala:237:23]
r_uops_2_debug_pc <= r_uops_1_debug_pc; // @[functional-unit.scala:237:23]
r_uops_2_iq_type <= r_uops_1_iq_type; // @[functional-unit.scala:237:23]
r_uops_2_fu_code <= r_uops_1_fu_code; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23]
r_uops_2_iw_state <= r_uops_1_iw_state; // @[functional-unit.scala:237:23]
r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23]
r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23]
r_uops_2_is_br <= r_uops_1_is_br; // @[functional-unit.scala:237:23]
r_uops_2_is_jalr <= r_uops_1_is_jalr; // @[functional-unit.scala:237:23]
r_uops_2_is_jal <= r_uops_1_is_jal; // @[functional-unit.scala:237:23]
r_uops_2_is_sfb <= r_uops_1_is_sfb; // @[functional-unit.scala:237:23]
r_uops_2_br_mask <= _r_uops_2_br_mask_T_1; // @[util.scala:85:25]
r_uops_2_br_tag <= r_uops_1_br_tag; // @[functional-unit.scala:237:23]
r_uops_2_ftq_idx <= r_uops_1_ftq_idx; // @[functional-unit.scala:237:23]
r_uops_2_edge_inst <= r_uops_1_edge_inst; // @[functional-unit.scala:237:23]
r_uops_2_pc_lob <= r_uops_1_pc_lob; // @[functional-unit.scala:237:23]
r_uops_2_taken <= r_uops_1_taken; // @[functional-unit.scala:237:23]
r_uops_2_imm_packed <= r_uops_1_imm_packed; // @[functional-unit.scala:237:23]
r_uops_2_csr_addr <= r_uops_1_csr_addr; // @[functional-unit.scala:237:23]
r_uops_2_rob_idx <= r_uops_1_rob_idx; // @[functional-unit.scala:237:23]
r_uops_2_ldq_idx <= r_uops_1_ldq_idx; // @[functional-unit.scala:237:23]
r_uops_2_stq_idx <= r_uops_1_stq_idx; // @[functional-unit.scala:237:23]
r_uops_2_rxq_idx <= r_uops_1_rxq_idx; // @[functional-unit.scala:237:23]
r_uops_2_pdst <= r_uops_1_pdst; // @[functional-unit.scala:237:23]
r_uops_2_prs1 <= r_uops_1_prs1; // @[functional-unit.scala:237:23]
r_uops_2_prs2 <= r_uops_1_prs2; // @[functional-unit.scala:237:23]
r_uops_2_prs3 <= r_uops_1_prs3; // @[functional-unit.scala:237:23]
r_uops_2_ppred <= r_uops_1_ppred; // @[functional-unit.scala:237:23]
r_uops_2_prs1_busy <= r_uops_1_prs1_busy; // @[functional-unit.scala:237:23]
r_uops_2_prs2_busy <= r_uops_1_prs2_busy; // @[functional-unit.scala:237:23]
r_uops_2_prs3_busy <= r_uops_1_prs3_busy; // @[functional-unit.scala:237:23]
r_uops_2_ppred_busy <= r_uops_1_ppred_busy; // @[functional-unit.scala:237:23]
r_uops_2_stale_pdst <= r_uops_1_stale_pdst; // @[functional-unit.scala:237:23]
r_uops_2_exception <= r_uops_1_exception; // @[functional-unit.scala:237:23]
r_uops_2_exc_cause <= r_uops_1_exc_cause; // @[functional-unit.scala:237:23]
r_uops_2_bypassable <= r_uops_1_bypassable; // @[functional-unit.scala:237:23]
r_uops_2_mem_cmd <= r_uops_1_mem_cmd; // @[functional-unit.scala:237:23]
r_uops_2_mem_size <= r_uops_1_mem_size; // @[functional-unit.scala:237:23]
r_uops_2_mem_signed <= r_uops_1_mem_signed; // @[functional-unit.scala:237:23]
r_uops_2_is_fence <= r_uops_1_is_fence; // @[functional-unit.scala:237:23]
r_uops_2_is_fencei <= r_uops_1_is_fencei; // @[functional-unit.scala:237:23]
r_uops_2_is_amo <= r_uops_1_is_amo; // @[functional-unit.scala:237:23]
r_uops_2_uses_ldq <= r_uops_1_uses_ldq; // @[functional-unit.scala:237:23]
r_uops_2_uses_stq <= r_uops_1_uses_stq; // @[functional-unit.scala:237:23]
r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23]
r_uops_2_is_unique <= r_uops_1_is_unique; // @[functional-unit.scala:237:23]
r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23]
r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23]
r_uops_2_ldst <= r_uops_1_ldst; // @[functional-unit.scala:237:23]
r_uops_2_lrs1 <= r_uops_1_lrs1; // @[functional-unit.scala:237:23]
r_uops_2_lrs2 <= r_uops_1_lrs2; // @[functional-unit.scala:237:23]
r_uops_2_lrs3 <= r_uops_1_lrs3; // @[functional-unit.scala:237:23]
r_uops_2_ldst_val <= r_uops_1_ldst_val; // @[functional-unit.scala:237:23]
r_uops_2_dst_rtype <= r_uops_1_dst_rtype; // @[functional-unit.scala:237:23]
r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23]
r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23]
r_uops_2_frs3_en <= r_uops_1_frs3_en; // @[functional-unit.scala:237:23]
r_uops_2_fp_val <= r_uops_1_fp_val; // @[functional-unit.scala:237:23]
r_uops_2_fp_single <= r_uops_1_fp_single; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23]
r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23]
r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23]
r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23]
r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23]
r_data_0 <= _r_data_0_T_3; // @[functional-unit.scala:447:19, :453:19]
r_data_1 <= r_data_0; // @[functional-unit.scala:447:19]
r_data_2 <= r_data_1; // @[functional-unit.scala:447:19]
always @(posedge)
ALU alu ( // @[functional-unit.scala:327:19]
.clock (clock),
.reset (reset),
.io_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:290:7]
.io_fn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:290:7]
.io_in2 (op2_data), // @[functional-unit.scala:321:21]
.io_in1 (io_req_bits_uop_ctrl_op1_sel_0 == 2'h0 ? io_req_bits_rs1_data_0 : io_req_bits_uop_ctrl_op1_sel_0 == 2'h2 ? {{24{uop_pc[39]}}, uop_pc} : 64'h0), // @[util.scala:261:{20,25,46}]
.io_out (_alu_io_out)
); // @[functional-unit.scala:327:19]
assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_valid = io_bypass_0_valid_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_uopc = io_bypass_0_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_inst = io_bypass_0_bits_uop_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_debug_inst = io_bypass_0_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_rvc = io_bypass_0_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_debug_pc = io_bypass_0_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_iq_type = io_bypass_0_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_fu_code = io_bypass_0_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_br_type = io_bypass_0_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_op1_sel = io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_op2_sel = io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_imm_sel = io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_op_fcn = io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_fcn_dw = io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_csr_cmd = io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_is_load = io_bypass_0_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_is_sta = io_bypass_0_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ctrl_is_std = io_bypass_0_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_iw_state = io_bypass_0_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_iw_p1_poisoned = io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_iw_p2_poisoned = io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_br = io_bypass_0_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_jalr = io_bypass_0_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_jal = io_bypass_0_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_sfb = io_bypass_0_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_br_mask = io_bypass_0_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_br_tag = io_bypass_0_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ftq_idx = io_bypass_0_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_edge_inst = io_bypass_0_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_pc_lob = io_bypass_0_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_taken = io_bypass_0_bits_uop_taken_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_imm_packed = io_bypass_0_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_csr_addr = io_bypass_0_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_rob_idx = io_bypass_0_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ldq_idx = io_bypass_0_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_stq_idx = io_bypass_0_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_rxq_idx = io_bypass_0_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_pdst = io_bypass_0_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs1 = io_bypass_0_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs2 = io_bypass_0_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs3 = io_bypass_0_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ppred = io_bypass_0_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs1_busy = io_bypass_0_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs2_busy = io_bypass_0_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_prs3_busy = io_bypass_0_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ppred_busy = io_bypass_0_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_stale_pdst = io_bypass_0_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_exception = io_bypass_0_bits_uop_exception_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_exc_cause = io_bypass_0_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_bypassable = io_bypass_0_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_mem_cmd = io_bypass_0_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_mem_size = io_bypass_0_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_mem_signed = io_bypass_0_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_fence = io_bypass_0_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_fencei = io_bypass_0_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_amo = io_bypass_0_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_uses_ldq = io_bypass_0_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_uses_stq = io_bypass_0_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_sys_pc2epc = io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_is_unique = io_bypass_0_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_flush_on_commit = io_bypass_0_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ldst_is_rs1 = io_bypass_0_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ldst = io_bypass_0_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_lrs1 = io_bypass_0_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_lrs2 = io_bypass_0_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_lrs3 = io_bypass_0_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_ldst_val = io_bypass_0_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_dst_rtype = io_bypass_0_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_lrs1_rtype = io_bypass_0_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_lrs2_rtype = io_bypass_0_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_frs3_en = io_bypass_0_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_fp_val = io_bypass_0_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_fp_single = io_bypass_0_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_xcpt_pf_if = io_bypass_0_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_xcpt_ae_if = io_bypass_0_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_xcpt_ma_if = io_bypass_0_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_bp_debug_if = io_bypass_0_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_bp_xcpt_if = io_bypass_0_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_debug_fsrc = io_bypass_0_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_uop_debug_tsrc = io_bypass_0_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_0_bits_data = io_bypass_0_bits_data_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_valid = io_bypass_1_valid_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_uopc = io_bypass_1_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_inst = io_bypass_1_bits_uop_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_debug_inst = io_bypass_1_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_rvc = io_bypass_1_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_debug_pc = io_bypass_1_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_iq_type = io_bypass_1_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_fu_code = io_bypass_1_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_br_type = io_bypass_1_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_op1_sel = io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_op2_sel = io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_imm_sel = io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_op_fcn = io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_fcn_dw = io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_csr_cmd = io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_is_load = io_bypass_1_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_is_sta = io_bypass_1_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ctrl_is_std = io_bypass_1_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_iw_state = io_bypass_1_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_iw_p1_poisoned = io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_iw_p2_poisoned = io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_br = io_bypass_1_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_jalr = io_bypass_1_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_jal = io_bypass_1_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_sfb = io_bypass_1_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_br_mask = io_bypass_1_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_br_tag = io_bypass_1_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ftq_idx = io_bypass_1_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_edge_inst = io_bypass_1_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_pc_lob = io_bypass_1_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_taken = io_bypass_1_bits_uop_taken_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_imm_packed = io_bypass_1_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_csr_addr = io_bypass_1_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_rob_idx = io_bypass_1_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ldq_idx = io_bypass_1_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_stq_idx = io_bypass_1_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_rxq_idx = io_bypass_1_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_pdst = io_bypass_1_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs1 = io_bypass_1_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs2 = io_bypass_1_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs3 = io_bypass_1_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ppred = io_bypass_1_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs1_busy = io_bypass_1_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs2_busy = io_bypass_1_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_prs3_busy = io_bypass_1_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ppred_busy = io_bypass_1_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_stale_pdst = io_bypass_1_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_exception = io_bypass_1_bits_uop_exception_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_exc_cause = io_bypass_1_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_bypassable = io_bypass_1_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_mem_cmd = io_bypass_1_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_mem_size = io_bypass_1_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_mem_signed = io_bypass_1_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_fence = io_bypass_1_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_fencei = io_bypass_1_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_amo = io_bypass_1_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_uses_ldq = io_bypass_1_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_uses_stq = io_bypass_1_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_sys_pc2epc = io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_is_unique = io_bypass_1_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_flush_on_commit = io_bypass_1_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ldst_is_rs1 = io_bypass_1_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ldst = io_bypass_1_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_lrs1 = io_bypass_1_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_lrs2 = io_bypass_1_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_lrs3 = io_bypass_1_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_ldst_val = io_bypass_1_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_dst_rtype = io_bypass_1_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_lrs1_rtype = io_bypass_1_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_lrs2_rtype = io_bypass_1_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_frs3_en = io_bypass_1_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_fp_val = io_bypass_1_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_fp_single = io_bypass_1_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_xcpt_pf_if = io_bypass_1_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_xcpt_ae_if = io_bypass_1_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_xcpt_ma_if = io_bypass_1_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_bp_debug_if = io_bypass_1_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_bp_xcpt_if = io_bypass_1_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_debug_fsrc = io_bypass_1_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_uop_debug_tsrc = io_bypass_1_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_1_bits_data = io_bypass_1_bits_data_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_valid = io_bypass_2_valid_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_uopc = io_bypass_2_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_inst = io_bypass_2_bits_uop_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_debug_inst = io_bypass_2_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_rvc = io_bypass_2_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_debug_pc = io_bypass_2_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_iq_type = io_bypass_2_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_fu_code = io_bypass_2_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_br_type = io_bypass_2_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_op1_sel = io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_op2_sel = io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_imm_sel = io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_op_fcn = io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_fcn_dw = io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_csr_cmd = io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_is_load = io_bypass_2_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_is_sta = io_bypass_2_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ctrl_is_std = io_bypass_2_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_iw_state = io_bypass_2_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_iw_p1_poisoned = io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_iw_p2_poisoned = io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_br = io_bypass_2_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_jalr = io_bypass_2_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_jal = io_bypass_2_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_sfb = io_bypass_2_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_br_mask = io_bypass_2_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_br_tag = io_bypass_2_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ftq_idx = io_bypass_2_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_edge_inst = io_bypass_2_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_pc_lob = io_bypass_2_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_taken = io_bypass_2_bits_uop_taken_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_imm_packed = io_bypass_2_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_csr_addr = io_bypass_2_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_rob_idx = io_bypass_2_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ldq_idx = io_bypass_2_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_stq_idx = io_bypass_2_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_rxq_idx = io_bypass_2_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_pdst = io_bypass_2_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs1 = io_bypass_2_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs2 = io_bypass_2_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs3 = io_bypass_2_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ppred = io_bypass_2_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs1_busy = io_bypass_2_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs2_busy = io_bypass_2_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_prs3_busy = io_bypass_2_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ppred_busy = io_bypass_2_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_stale_pdst = io_bypass_2_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_exception = io_bypass_2_bits_uop_exception_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_exc_cause = io_bypass_2_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_bypassable = io_bypass_2_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_mem_cmd = io_bypass_2_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_mem_size = io_bypass_2_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_mem_signed = io_bypass_2_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_fence = io_bypass_2_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_fencei = io_bypass_2_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_amo = io_bypass_2_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_uses_ldq = io_bypass_2_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_uses_stq = io_bypass_2_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_sys_pc2epc = io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_is_unique = io_bypass_2_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_flush_on_commit = io_bypass_2_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ldst_is_rs1 = io_bypass_2_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ldst = io_bypass_2_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_lrs1 = io_bypass_2_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_lrs2 = io_bypass_2_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_lrs3 = io_bypass_2_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_ldst_val = io_bypass_2_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_dst_rtype = io_bypass_2_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_lrs1_rtype = io_bypass_2_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_lrs2_rtype = io_bypass_2_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_frs3_en = io_bypass_2_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_fp_val = io_bypass_2_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_fp_single = io_bypass_2_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_xcpt_pf_if = io_bypass_2_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_xcpt_ae_if = io_bypass_2_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_xcpt_ma_if = io_bypass_2_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_bp_debug_if = io_bypass_2_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_bp_xcpt_if = io_bypass_2_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_debug_fsrc = io_bypass_2_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_uop_debug_tsrc = io_bypass_2_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
assign io_bypass_2_bits_data = io_bypass_2_bits_data_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_uopc = io_brinfo_uop_uopc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_inst = io_brinfo_uop_inst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_debug_inst = io_brinfo_uop_debug_inst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_rvc = io_brinfo_uop_is_rvc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_debug_pc = io_brinfo_uop_debug_pc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_iq_type = io_brinfo_uop_iq_type_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_fu_code = io_brinfo_uop_fu_code_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_br_type = io_brinfo_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_op1_sel = io_brinfo_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_op2_sel = io_brinfo_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_imm_sel = io_brinfo_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_op_fcn = io_brinfo_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_fcn_dw = io_brinfo_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_csr_cmd = io_brinfo_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_is_load = io_brinfo_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_is_sta = io_brinfo_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ctrl_is_std = io_brinfo_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_iw_state = io_brinfo_uop_iw_state_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_iw_p1_poisoned = io_brinfo_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_iw_p2_poisoned = io_brinfo_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_br = io_brinfo_uop_is_br_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_jalr = io_brinfo_uop_is_jalr_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_jal = io_brinfo_uop_is_jal_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_sfb = io_brinfo_uop_is_sfb_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_br_mask = io_brinfo_uop_br_mask_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_br_tag = io_brinfo_uop_br_tag_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ftq_idx = io_brinfo_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_edge_inst = io_brinfo_uop_edge_inst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_pc_lob = io_brinfo_uop_pc_lob_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_taken = io_brinfo_uop_taken_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_imm_packed = io_brinfo_uop_imm_packed_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_csr_addr = io_brinfo_uop_csr_addr_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_rob_idx = io_brinfo_uop_rob_idx_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ldq_idx = io_brinfo_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_stq_idx = io_brinfo_uop_stq_idx_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_rxq_idx = io_brinfo_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_pdst = io_brinfo_uop_pdst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs1 = io_brinfo_uop_prs1_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs2 = io_brinfo_uop_prs2_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs3 = io_brinfo_uop_prs3_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ppred = io_brinfo_uop_ppred_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs1_busy = io_brinfo_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs2_busy = io_brinfo_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_prs3_busy = io_brinfo_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ppred_busy = io_brinfo_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_stale_pdst = io_brinfo_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_exception = io_brinfo_uop_exception_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_exc_cause = io_brinfo_uop_exc_cause_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_bypassable = io_brinfo_uop_bypassable_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_mem_cmd = io_brinfo_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_mem_size = io_brinfo_uop_mem_size_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_mem_signed = io_brinfo_uop_mem_signed_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_fence = io_brinfo_uop_is_fence_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_fencei = io_brinfo_uop_is_fencei_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_amo = io_brinfo_uop_is_amo_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_uses_ldq = io_brinfo_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_uses_stq = io_brinfo_uop_uses_stq_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_sys_pc2epc = io_brinfo_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_is_unique = io_brinfo_uop_is_unique_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_flush_on_commit = io_brinfo_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ldst_is_rs1 = io_brinfo_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ldst = io_brinfo_uop_ldst_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_lrs1 = io_brinfo_uop_lrs1_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_lrs2 = io_brinfo_uop_lrs2_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_lrs3 = io_brinfo_uop_lrs3_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_ldst_val = io_brinfo_uop_ldst_val_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_dst_rtype = io_brinfo_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_lrs1_rtype = io_brinfo_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_lrs2_rtype = io_brinfo_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_frs3_en = io_brinfo_uop_frs3_en_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_fp_val = io_brinfo_uop_fp_val_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_fp_single = io_brinfo_uop_fp_single_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_xcpt_pf_if = io_brinfo_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_xcpt_ae_if = io_brinfo_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_xcpt_ma_if = io_brinfo_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_bp_debug_if = io_brinfo_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_bp_xcpt_if = io_brinfo_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_debug_fsrc = io_brinfo_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_uop_debug_tsrc = io_brinfo_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
assign io_brinfo_valid = io_brinfo_valid_0; // @[functional-unit.scala:290:7]
assign io_brinfo_mispredict = io_brinfo_mispredict_0; // @[functional-unit.scala:290:7]
assign io_brinfo_taken = io_brinfo_taken_0; // @[functional-unit.scala:290:7]
assign io_brinfo_cfi_type = io_brinfo_cfi_type_0; // @[functional-unit.scala:290:7]
assign io_brinfo_pc_sel = io_brinfo_pc_sel_0; // @[functional-unit.scala:290:7]
assign io_brinfo_jalr_target = io_brinfo_jalr_target_0; // @[functional-unit.scala:290:7]
assign io_brinfo_target_offset = io_brinfo_target_offset_0; // @[functional-unit.scala:290:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_21 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_21( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ListBuffer_QueuedRequest_q21_e33 :
input clock : Clock
input reset : Reset
output io : { flip push : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<5>, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}}}, valid : UInt<21>, flip pop : { valid : UInt<1>, bits : UInt<5>}, data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}}
regreset valid : UInt<21>, clock, reset, UInt<21>(0h0)
cmem head : UInt<6> [21]
cmem tail : UInt<6> [21]
regreset used : UInt<33>, clock, reset, UInt<33>(0h0)
cmem next : UInt<6> [33]
cmem data : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>} [33]
node _freeOH_T = not(used)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 32, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = shl(_freeOH_T_3, 2)
node _freeOH_T_5 = bits(_freeOH_T_4, 32, 0)
node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5)
node _freeOH_T_7 = shl(_freeOH_T_6, 4)
node _freeOH_T_8 = bits(_freeOH_T_7, 32, 0)
node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8)
node _freeOH_T_10 = shl(_freeOH_T_9, 8)
node _freeOH_T_11 = bits(_freeOH_T_10, 32, 0)
node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11)
node _freeOH_T_13 = shl(_freeOH_T_12, 16)
node _freeOH_T_14 = bits(_freeOH_T_13, 32, 0)
node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14)
node _freeOH_T_16 = shl(_freeOH_T_15, 32)
node _freeOH_T_17 = bits(_freeOH_T_16, 32, 0)
node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17)
node _freeOH_T_19 = bits(_freeOH_T_18, 32, 0)
node _freeOH_T_20 = shl(_freeOH_T_19, 1)
node _freeOH_T_21 = not(_freeOH_T_20)
node _freeOH_T_22 = not(used)
node freeOH = and(_freeOH_T_21, _freeOH_T_22)
node freeIdx_hi = bits(freeOH, 33, 32)
node freeIdx_lo = bits(freeOH, 31, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16)
node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0)
node _freeIdx_T_2 = orr(freeIdx_hi_1)
node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1)
node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8)
node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0)
node _freeIdx_T_4 = orr(freeIdx_hi_2)
node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2)
node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4)
node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0)
node _freeIdx_T_6 = orr(freeIdx_hi_3)
node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3)
node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2)
node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0)
node _freeIdx_T_8 = orr(freeIdx_hi_4)
node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4)
node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1)
node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10)
node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11)
node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12)
node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_14)
wire valid_set : UInt<21>
connect valid_set, UInt<21>(0h0)
wire valid_clr : UInt<21>
connect valid_clr, UInt<21>(0h0)
wire used_set : UInt<33>
connect used_set, UInt<33>(0h0)
wire used_clr : UInt<33>
connect used_clr, UInt<33>(0h0)
read mport push_tail = tail[io.push.bits.index], clock
node _push_valid_T = dshr(valid, io.push.bits.index)
node push_valid = bits(_push_valid_T, 0, 0)
node _io_push_ready_T = andr(used)
node _io_push_ready_T_1 = eq(_io_push_ready_T, UInt<1>(0h0))
connect io.push.ready, _io_push_ready_T_1
node _T = and(io.push.ready, io.push.valid)
when _T :
node valid_set_shiftAmount = bits(io.push.bits.index, 4, 0)
node _valid_set_T = dshl(UInt<1>(0h1), valid_set_shiftAmount)
node _valid_set_T_1 = bits(_valid_set_T, 20, 0)
connect valid_set, _valid_set_T_1
connect used_set, freeOH
write mport MPORT = data[freeIdx], clock
connect MPORT, io.push.bits.data
when push_valid :
write mport MPORT_1 = next[push_tail], clock
connect MPORT_1, freeIdx
else :
write mport MPORT_2 = head[io.push.bits.index], clock
connect MPORT_2, freeIdx
write mport MPORT_3 = tail[io.push.bits.index], clock
connect MPORT_3, freeIdx
read mport pop_head = head[io.pop.bits], clock
node _pop_valid_T = dshr(valid, io.pop.bits)
node pop_valid = bits(_pop_valid_T, 0, 0)
read mport io_data_MPORT = data[pop_head], clock
connect io.data, io_data_MPORT
connect io.valid, valid
node _T_1 = eq(io.pop.valid, UInt<1>(0h0))
node _T_2 = dshr(io.valid, io.pop.bits)
node _T_3 = bits(_T_2, 0, 0)
node _T_4 = or(_T_1, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ListBuffer.scala:86 assert (!io.pop.fire || (io.valid)(io.pop.bits))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
when io.pop.valid :
node used_clr_shiftAmount = bits(pop_head, 5, 0)
node _used_clr_T = dshl(UInt<1>(0h1), used_clr_shiftAmount)
node _used_clr_T_1 = bits(_used_clr_T, 32, 0)
connect used_clr, _used_clr_T_1
read mport MPORT_4 = tail[io.pop.bits], clock
node _T_8 = eq(pop_head, MPORT_4)
when _T_8 :
node valid_clr_shiftAmount = bits(io.pop.bits, 4, 0)
node _valid_clr_T = dshl(UInt<1>(0h1), valid_clr_shiftAmount)
node _valid_clr_T_1 = bits(_valid_clr_T, 20, 0)
connect valid_clr, _valid_clr_T_1
node _T_9 = and(io.push.ready, io.push.valid)
node _T_10 = and(_T_9, push_valid)
node _T_11 = eq(push_tail, pop_head)
node _T_12 = and(_T_10, _T_11)
read mport MPORT_5 = next[pop_head], clock
node _T_13 = mux(_T_12, freeIdx, MPORT_5)
write mport MPORT_6 = head[io.pop.bits], clock
connect MPORT_6, _T_13
node _T_14 = eq(io.pop.valid, UInt<1>(0h0))
node _T_15 = or(UInt<1>(0h1), _T_14)
node _T_16 = or(_T_15, pop_valid)
when _T_16 :
node _used_T = not(used_clr)
node _used_T_1 = and(used, _used_T)
node _used_T_2 = or(_used_T_1, used_set)
connect used, _used_T_2
node _valid_T = not(valid_clr)
node _valid_T_1 = and(valid, _valid_T)
node _valid_T_2 = or(_valid_T_1, valid_set)
connect valid, _valid_T_2 | module ListBuffer_QueuedRequest_q21_e33( // @[ListBuffer.scala:36:7]
input clock, // @[ListBuffer.scala:36:7]
input reset, // @[ListBuffer.scala:36:7]
output io_push_ready, // @[ListBuffer.scala:39:14]
input io_push_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_push_bits_index, // @[ListBuffer.scala:39:14]
input io_push_bits_data_control, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14]
input [12:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14]
output [20:0] io_valid, // @[ListBuffer.scala:39:14]
input io_pop_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_pop_bits, // @[ListBuffer.scala:39:14]
output io_data_prio_0, // @[ListBuffer.scala:39:14]
output io_data_prio_1, // @[ListBuffer.scala:39:14]
output io_data_prio_2, // @[ListBuffer.scala:39:14]
output io_data_control, // @[ListBuffer.scala:39:14]
output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14]
output [2:0] io_data_param, // @[ListBuffer.scala:39:14]
output [2:0] io_data_size, // @[ListBuffer.scala:39:14]
output [5:0] io_data_source, // @[ListBuffer.scala:39:14]
output [12:0] io_data_tag, // @[ListBuffer.scala:39:14]
output [5:0] io_data_offset, // @[ListBuffer.scala:39:14]
output [5:0] io_data_put // @[ListBuffer.scala:39:14]
);
wire [43:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18]
wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18]
wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18]
wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18]
wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18]
wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7]
wire [12:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7]
wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_0 = 1'h1; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_2 = 1'h0; // @[ListBuffer.scala:36:7]
wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20]
wire [4:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49]
wire [4:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49]
wire io_push_ready_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_0_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_1_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_2_0; // @[ListBuffer.scala:36:7]
wire io_data_control_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_source_0; // @[ListBuffer.scala:36:7]
wire [12:0] io_data_tag_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7]
wire [20:0] io_valid_0; // @[ListBuffer.scala:36:7]
reg [20:0] valid; // @[ListBuffer.scala:47:22]
assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22]
reg [32:0] used; // @[ListBuffer.scala:50:22]
assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_source_0 = _data_ext_R0_data[18:13]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_tag_0 = _data_ext_R0_data[31:19]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_offset_0 = _data_ext_R0_data[37:32]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_put_0 = _data_ext_R0_data[43:38]; // @[ListBuffer.scala:36:7, :52:18]
wire [32:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25]
wire [33:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [32:0] _freeOH_T_2 = _freeOH_T_1[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [34:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_5 = _freeOH_T_4[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [36:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_8 = _freeOH_T_7[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [40:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_11 = _freeOH_T_10[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [48:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_14 = _freeOH_T_13[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [64:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_17 = _freeOH_T_16[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}]
wire [32:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17]
wire [33:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17]
wire [33:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}]
wire [32:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}]
wire [33:0] freeOH = {1'h0, _freeOH_T_21[32:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}]
wire [1:0] freeIdx_hi = freeOH[33:32]; // @[OneHot.scala:30:18]
wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _freeIdx_T_1 = {30'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}]
wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}]
wire [20:0] valid_set; // @[ListBuffer.scala:57:30]
wire [20:0] valid_clr; // @[ListBuffer.scala:58:30]
wire [32:0] used_set; // @[ListBuffer.scala:59:30]
wire [32:0] used_clr; // @[ListBuffer.scala:60:30]
wire [20:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25]
wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25]
wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26]
assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}]
assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20]
wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _valid_set_T = 32'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [20:0] _valid_set_T_1 = _valid_set_T[20:0]; // @[OneHot.scala:65:{12,27}]
assign valid_set = data_MPORT_en ? _valid_set_T_1 : 21'h0; // @[OneHot.scala:65:27]
assign used_set = data_MPORT_en ? freeOH[32:0] : 33'h0; // @[Decoupled.scala:51:35]
wire [20:0] _GEN = {16'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24]
wire [20:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24]
wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24] |
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i4_o1_4 :
output auto : { flip anon_in_3 : UInt<1>[1], flip anon_in_2 : UInt<1>[1], flip anon_in_1 : UInt<1>[2], flip anon_in_0 : UInt<1>[1], anon_out : UInt<1>[5]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : UInt<1>[1]
invalidate anonIn[0]
wire anonIn_1 : UInt<1>[2]
invalidate anonIn_1[0]
invalidate anonIn_1[1]
wire anonIn_2 : UInt<1>[1]
invalidate anonIn_2[0]
wire anonIn_3 : UInt<1>[1]
invalidate anonIn_3[0]
wire anonOut : UInt<1>[5]
invalidate anonOut[0]
invalidate anonOut[1]
invalidate anonOut[2]
invalidate anonOut[3]
invalidate anonOut[4]
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
connect anonIn_3, auto.anon_in_3
connect anonOut[0], anonIn[0]
connect anonOut[1], anonIn_1[0]
connect anonOut[2], anonIn_1[1]
connect anonOut[3], anonIn_2[0]
connect anonOut[4], anonIn_3[0] | module IntXbar_i4_o1_4( // @[Xbar.scala:22:9]
input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9]
wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9]
wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire anonOut_1; // @[MixedNode.scala:542:17]
wire anonOut_2; // @[MixedNode.scala:542:17]
wire anonOut_3; // @[MixedNode.scala:542:17]
wire anonOut_4; // @[MixedNode.scala:542:17]
wire auto_anon_out_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_0; // @[Xbar.scala:22:9]
wire auto_anon_out_2_0; // @[Xbar.scala:22:9]
wire auto_anon_out_3_0; // @[Xbar.scala:22:9]
wire auto_anon_out_4_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9]
assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9]
assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9]
assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9]
assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9]
assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9]
assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_152 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_408
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_152( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_408 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MemLoader :
input clock : Clock
input reset : Reset
output io : { l2helperUser : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}}
inst buf_info_queue of Queue16_BufInfoBundle_1
connect buf_info_queue.clock, clock
connect buf_info_queue.reset, reset
inst load_info_queue of Queue256_LoadInfoBundle_1
connect load_info_queue.clock, clock
connect load_info_queue.reset, reset
node base_addr_start_index = and(io.src_info.bits.ip, UInt<5>(0h1f))
node _aligned_loadlen_T = add(io.src_info.bits.isize, base_addr_start_index)
node aligned_loadlen = tail(_aligned_loadlen_T, 1)
node _base_addr_end_index_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_T_1 = tail(_base_addr_end_index_T, 1)
node base_addr_end_index = and(_base_addr_end_index_T_1, UInt<5>(0h1f))
node _base_addr_end_index_inclusive_T = add(io.src_info.bits.isize, base_addr_start_index)
node _base_addr_end_index_inclusive_T_1 = tail(_base_addr_end_index_inclusive_T, 1)
node _base_addr_end_index_inclusive_T_2 = sub(_base_addr_end_index_inclusive_T_1, UInt<1>(0h1))
node _base_addr_end_index_inclusive_T_3 = tail(_base_addr_end_index_inclusive_T_2, 1)
node base_addr_end_index_inclusive = and(_base_addr_end_index_inclusive_T_3, UInt<5>(0h1f))
node _extra_word_T = and(aligned_loadlen, UInt<5>(0h1f))
node extra_word = neq(_extra_word_T, UInt<1>(0h0))
node _base_addr_bytes_aligned_T = dshr(io.src_info.bits.ip, UInt<3>(0h5))
node base_addr_bytes_aligned = dshl(_base_addr_bytes_aligned_T, UInt<3>(0h5))
node _words_to_load_T = dshr(aligned_loadlen, UInt<3>(0h5))
node _words_to_load_T_1 = add(_words_to_load_T, extra_word)
node words_to_load = tail(_words_to_load_T_1, 1)
node _words_to_load_minus_one_T = sub(words_to_load, UInt<1>(0h1))
node words_to_load_minus_one = tail(_words_to_load_minus_one_T, 1)
regreset print_not_done : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(io.src_info.valid, print_not_done)
when _T :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_1
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "base_len: %x\n", io.src_info.bits.isize) : printf_3
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "base_addr_start_index: %x\n", base_addr_start_index) : printf_5
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "aligned_loadlen: %x\n", aligned_loadlen) : printf_7
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "base_addr_end_index: %x\n", base_addr_end_index) : printf_9
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) : printf_11
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "extra_word: %x\n", extra_word) : printf_13
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) : printf_15
regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1))
node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1)
connect loginfo_cycles_8, _loginfo_cycles_T_17
node _T_33 = asUInt(reset)
node _T_34 = eq(_T_33, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "words_to_load: %x\n", words_to_load) : printf_17
regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1))
node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1)
connect loginfo_cycles_9, _loginfo_cycles_T_19
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "words_to_load_minus_one: %x\n", words_to_load_minus_one) : printf_19
when io.src_info.ready :
connect print_not_done, UInt<1>(0h1)
else :
connect print_not_done, UInt<1>(0h0)
connect io.l2helperUser.req.bits.cmd, UInt<1>(0h0)
connect io.l2helperUser.req.bits.size, UInt<3>(0h5)
connect io.l2helperUser.req.bits.data, UInt<1>(0h0)
regreset addrinc : UInt<64>, clock, reset, UInt<64>(0h0)
node _load_info_queue_io_enq_bits_start_byte_T = eq(addrinc, UInt<1>(0h0))
node _load_info_queue_io_enq_bits_start_byte_T_1 = mux(_load_info_queue_io_enq_bits_start_byte_T, base_addr_start_index, UInt<1>(0h0))
connect load_info_queue.io.enq.bits.start_byte, _load_info_queue_io_enq_bits_start_byte_T_1
node _load_info_queue_io_enq_bits_end_byte_T = eq(addrinc, words_to_load_minus_one)
node _load_info_queue_io_enq_bits_end_byte_T_1 = mux(_load_info_queue_io_enq_bits_end_byte_T, base_addr_end_index_inclusive, UInt<5>(0h1f))
connect load_info_queue.io.enq.bits.end_byte, _load_info_queue_io_enq_bits_end_byte_T_1
node _T_41 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_42 = and(_T_41, buf_info_queue.io.enq.ready)
node _T_43 = and(_T_42, load_info_queue.io.enq.ready)
node _T_44 = eq(addrinc, words_to_load_minus_one)
node _T_45 = and(_T_43, _T_44)
when _T_45 :
connect addrinc, UInt<1>(0h0)
else :
node _T_46 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _T_47 = and(_T_46, buf_info_queue.io.enq.ready)
node _T_48 = and(_T_47, load_info_queue.io.enq.ready)
when _T_48 :
node _addrinc_T = add(addrinc, UInt<1>(0h1))
node _addrinc_T_1 = tail(_addrinc_T, 1)
connect addrinc, _addrinc_T_1
node _T_49 = and(io.src_info.ready, io.src_info.valid)
when _T_49 :
regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1))
node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1)
connect loginfo_cycles_10, _loginfo_cycles_T_21
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "COMPLETED INPUT LOAD FOR DECOMPRESSION\n") : printf_21
node _io_src_info_ready_T = eq(addrinc, words_to_load_minus_one)
node _io_src_info_ready_T_1 = and(io.l2helperUser.req.ready, buf_info_queue.io.enq.ready)
node _io_src_info_ready_T_2 = and(_io_src_info_ready_T_1, load_info_queue.io.enq.ready)
node _io_src_info_ready_T_3 = and(_io_src_info_ready_T_2, _io_src_info_ready_T)
connect io.src_info.ready, _io_src_info_ready_T_3
node _buf_info_queue_io_enq_valid_T = eq(addrinc, UInt<1>(0h0))
node _buf_info_queue_io_enq_valid_T_1 = and(io.l2helperUser.req.ready, io.src_info.valid)
node _buf_info_queue_io_enq_valid_T_2 = and(_buf_info_queue_io_enq_valid_T_1, load_info_queue.io.enq.ready)
node _buf_info_queue_io_enq_valid_T_3 = and(_buf_info_queue_io_enq_valid_T_2, _buf_info_queue_io_enq_valid_T)
connect buf_info_queue.io.enq.valid, _buf_info_queue_io_enq_valid_T_3
node _load_info_queue_io_enq_valid_T = and(io.l2helperUser.req.ready, io.src_info.valid)
node _load_info_queue_io_enq_valid_T_1 = and(_load_info_queue_io_enq_valid_T, buf_info_queue.io.enq.ready)
connect load_info_queue.io.enq.valid, _load_info_queue_io_enq_valid_T_1
connect buf_info_queue.io.enq.bits.len_bytes, io.src_info.bits.isize
node _io_l2helperUser_req_bits_addr_T = shl(addrinc, 5)
node _io_l2helperUser_req_bits_addr_T_1 = add(base_addr_bytes_aligned, _io_l2helperUser_req_bits_addr_T)
node _io_l2helperUser_req_bits_addr_T_2 = tail(_io_l2helperUser_req_bits_addr_T_1, 1)
connect io.l2helperUser.req.bits.addr, _io_l2helperUser_req_bits_addr_T_2
node _io_l2helperUser_req_valid_T = and(io.src_info.valid, buf_info_queue.io.enq.ready)
node _io_l2helperUser_req_valid_T_1 = and(_io_l2helperUser_req_valid_T, load_info_queue.io.enq.ready)
connect io.l2helperUser.req.valid, _io_l2helperUser_req_valid_T_1
regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
inst Queue64_UInt8 of Queue64_UInt8_64
connect Queue64_UInt8.clock, clock
connect Queue64_UInt8.reset, reset
inst Queue64_UInt8_1 of Queue64_UInt8_65
connect Queue64_UInt8_1.clock, clock
connect Queue64_UInt8_1.reset, reset
inst Queue64_UInt8_2 of Queue64_UInt8_66
connect Queue64_UInt8_2.clock, clock
connect Queue64_UInt8_2.reset, reset
inst Queue64_UInt8_3 of Queue64_UInt8_67
connect Queue64_UInt8_3.clock, clock
connect Queue64_UInt8_3.reset, reset
inst Queue64_UInt8_4 of Queue64_UInt8_68
connect Queue64_UInt8_4.clock, clock
connect Queue64_UInt8_4.reset, reset
inst Queue64_UInt8_5 of Queue64_UInt8_69
connect Queue64_UInt8_5.clock, clock
connect Queue64_UInt8_5.reset, reset
inst Queue64_UInt8_6 of Queue64_UInt8_70
connect Queue64_UInt8_6.clock, clock
connect Queue64_UInt8_6.reset, reset
inst Queue64_UInt8_7 of Queue64_UInt8_71
connect Queue64_UInt8_7.clock, clock
connect Queue64_UInt8_7.reset, reset
inst Queue64_UInt8_8 of Queue64_UInt8_72
connect Queue64_UInt8_8.clock, clock
connect Queue64_UInt8_8.reset, reset
inst Queue64_UInt8_9 of Queue64_UInt8_73
connect Queue64_UInt8_9.clock, clock
connect Queue64_UInt8_9.reset, reset
inst Queue64_UInt8_10 of Queue64_UInt8_74
connect Queue64_UInt8_10.clock, clock
connect Queue64_UInt8_10.reset, reset
inst Queue64_UInt8_11 of Queue64_UInt8_75
connect Queue64_UInt8_11.clock, clock
connect Queue64_UInt8_11.reset, reset
inst Queue64_UInt8_12 of Queue64_UInt8_76
connect Queue64_UInt8_12.clock, clock
connect Queue64_UInt8_12.reset, reset
inst Queue64_UInt8_13 of Queue64_UInt8_77
connect Queue64_UInt8_13.clock, clock
connect Queue64_UInt8_13.reset, reset
inst Queue64_UInt8_14 of Queue64_UInt8_78
connect Queue64_UInt8_14.clock, clock
connect Queue64_UInt8_14.reset, reset
inst Queue64_UInt8_15 of Queue64_UInt8_79
connect Queue64_UInt8_15.clock, clock
connect Queue64_UInt8_15.reset, reset
inst Queue64_UInt8_16 of Queue64_UInt8_80
connect Queue64_UInt8_16.clock, clock
connect Queue64_UInt8_16.reset, reset
inst Queue64_UInt8_17 of Queue64_UInt8_81
connect Queue64_UInt8_17.clock, clock
connect Queue64_UInt8_17.reset, reset
inst Queue64_UInt8_18 of Queue64_UInt8_82
connect Queue64_UInt8_18.clock, clock
connect Queue64_UInt8_18.reset, reset
inst Queue64_UInt8_19 of Queue64_UInt8_83
connect Queue64_UInt8_19.clock, clock
connect Queue64_UInt8_19.reset, reset
inst Queue64_UInt8_20 of Queue64_UInt8_84
connect Queue64_UInt8_20.clock, clock
connect Queue64_UInt8_20.reset, reset
inst Queue64_UInt8_21 of Queue64_UInt8_85
connect Queue64_UInt8_21.clock, clock
connect Queue64_UInt8_21.reset, reset
inst Queue64_UInt8_22 of Queue64_UInt8_86
connect Queue64_UInt8_22.clock, clock
connect Queue64_UInt8_22.reset, reset
inst Queue64_UInt8_23 of Queue64_UInt8_87
connect Queue64_UInt8_23.clock, clock
connect Queue64_UInt8_23.reset, reset
inst Queue64_UInt8_24 of Queue64_UInt8_88
connect Queue64_UInt8_24.clock, clock
connect Queue64_UInt8_24.reset, reset
inst Queue64_UInt8_25 of Queue64_UInt8_89
connect Queue64_UInt8_25.clock, clock
connect Queue64_UInt8_25.reset, reset
inst Queue64_UInt8_26 of Queue64_UInt8_90
connect Queue64_UInt8_26.clock, clock
connect Queue64_UInt8_26.reset, reset
inst Queue64_UInt8_27 of Queue64_UInt8_91
connect Queue64_UInt8_27.clock, clock
connect Queue64_UInt8_27.reset, reset
inst Queue64_UInt8_28 of Queue64_UInt8_92
connect Queue64_UInt8_28.clock, clock
connect Queue64_UInt8_28.reset, reset
inst Queue64_UInt8_29 of Queue64_UInt8_93
connect Queue64_UInt8_29.clock, clock
connect Queue64_UInt8_29.reset, reset
inst Queue64_UInt8_30 of Queue64_UInt8_94
connect Queue64_UInt8_30.clock, clock
connect Queue64_UInt8_30.reset, reset
inst Queue64_UInt8_31 of Queue64_UInt8_95
connect Queue64_UInt8_31.clock, clock
connect Queue64_UInt8_31.reset, reset
node align_shamt = shl(load_info_queue.io.deq.bits.start_byte, 3)
node memresp_bits_shifted = dshr(io.l2helperUser.resp.bits.data, align_shamt)
connect Queue64_UInt8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_1.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_2.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_3.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_4.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_5.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_6.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_7.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_8.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_9.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_10.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_11.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_12.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_13.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_14.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_15.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_16.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_17.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_18.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_19.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_20.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_21.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_22.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_23.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_24.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_25.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_26.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_27.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_28.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_29.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_30.io.enq.bits, UInt<1>(0h0)
connect Queue64_UInt8_31.io.enq.bits, UInt<1>(0h0)
node _idx_T = add(write_start_index, UInt<1>(0h0))
node idx = rem(_idx_T, UInt<6>(0h20))
node _T_54 = eq(UInt<1>(0h0), idx)
when _T_54 :
node _T_55 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8.io.enq.bits, _T_55
node _T_56 = eq(UInt<1>(0h1), idx)
when _T_56 :
node _T_57 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_1.io.enq.bits, _T_57
node _T_58 = eq(UInt<2>(0h2), idx)
when _T_58 :
node _T_59 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_2.io.enq.bits, _T_59
node _T_60 = eq(UInt<2>(0h3), idx)
when _T_60 :
node _T_61 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_3.io.enq.bits, _T_61
node _T_62 = eq(UInt<3>(0h4), idx)
when _T_62 :
node _T_63 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_4.io.enq.bits, _T_63
node _T_64 = eq(UInt<3>(0h5), idx)
when _T_64 :
node _T_65 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_5.io.enq.bits, _T_65
node _T_66 = eq(UInt<3>(0h6), idx)
when _T_66 :
node _T_67 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_6.io.enq.bits, _T_67
node _T_68 = eq(UInt<3>(0h7), idx)
when _T_68 :
node _T_69 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_7.io.enq.bits, _T_69
node _T_70 = eq(UInt<4>(0h8), idx)
when _T_70 :
node _T_71 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_8.io.enq.bits, _T_71
node _T_72 = eq(UInt<4>(0h9), idx)
when _T_72 :
node _T_73 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_9.io.enq.bits, _T_73
node _T_74 = eq(UInt<4>(0ha), idx)
when _T_74 :
node _T_75 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_10.io.enq.bits, _T_75
node _T_76 = eq(UInt<4>(0hb), idx)
when _T_76 :
node _T_77 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_11.io.enq.bits, _T_77
node _T_78 = eq(UInt<4>(0hc), idx)
when _T_78 :
node _T_79 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_12.io.enq.bits, _T_79
node _T_80 = eq(UInt<4>(0hd), idx)
when _T_80 :
node _T_81 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_13.io.enq.bits, _T_81
node _T_82 = eq(UInt<4>(0he), idx)
when _T_82 :
node _T_83 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_14.io.enq.bits, _T_83
node _T_84 = eq(UInt<4>(0hf), idx)
when _T_84 :
node _T_85 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_15.io.enq.bits, _T_85
node _T_86 = eq(UInt<5>(0h10), idx)
when _T_86 :
node _T_87 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_16.io.enq.bits, _T_87
node _T_88 = eq(UInt<5>(0h11), idx)
when _T_88 :
node _T_89 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_17.io.enq.bits, _T_89
node _T_90 = eq(UInt<5>(0h12), idx)
when _T_90 :
node _T_91 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_18.io.enq.bits, _T_91
node _T_92 = eq(UInt<5>(0h13), idx)
when _T_92 :
node _T_93 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_19.io.enq.bits, _T_93
node _T_94 = eq(UInt<5>(0h14), idx)
when _T_94 :
node _T_95 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_20.io.enq.bits, _T_95
node _T_96 = eq(UInt<5>(0h15), idx)
when _T_96 :
node _T_97 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_21.io.enq.bits, _T_97
node _T_98 = eq(UInt<5>(0h16), idx)
when _T_98 :
node _T_99 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_22.io.enq.bits, _T_99
node _T_100 = eq(UInt<5>(0h17), idx)
when _T_100 :
node _T_101 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_23.io.enq.bits, _T_101
node _T_102 = eq(UInt<5>(0h18), idx)
when _T_102 :
node _T_103 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_24.io.enq.bits, _T_103
node _T_104 = eq(UInt<5>(0h19), idx)
when _T_104 :
node _T_105 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_25.io.enq.bits, _T_105
node _T_106 = eq(UInt<5>(0h1a), idx)
when _T_106 :
node _T_107 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_26.io.enq.bits, _T_107
node _T_108 = eq(UInt<5>(0h1b), idx)
when _T_108 :
node _T_109 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_27.io.enq.bits, _T_109
node _T_110 = eq(UInt<5>(0h1c), idx)
when _T_110 :
node _T_111 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_28.io.enq.bits, _T_111
node _T_112 = eq(UInt<5>(0h1d), idx)
when _T_112 :
node _T_113 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_29.io.enq.bits, _T_113
node _T_114 = eq(UInt<5>(0h1e), idx)
when _T_114 :
node _T_115 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_30.io.enq.bits, _T_115
node _T_116 = eq(UInt<5>(0h1f), idx)
when _T_116 :
node _T_117 = shr(memresp_bits_shifted, 0)
connect Queue64_UInt8_31.io.enq.bits, _T_117
node _idx_T_1 = add(write_start_index, UInt<1>(0h1))
node idx_1 = rem(_idx_T_1, UInt<6>(0h20))
node _T_118 = eq(UInt<1>(0h0), idx_1)
when _T_118 :
node _T_119 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8.io.enq.bits, _T_119
node _T_120 = eq(UInt<1>(0h1), idx_1)
when _T_120 :
node _T_121 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_1.io.enq.bits, _T_121
node _T_122 = eq(UInt<2>(0h2), idx_1)
when _T_122 :
node _T_123 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_2.io.enq.bits, _T_123
node _T_124 = eq(UInt<2>(0h3), idx_1)
when _T_124 :
node _T_125 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_3.io.enq.bits, _T_125
node _T_126 = eq(UInt<3>(0h4), idx_1)
when _T_126 :
node _T_127 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_4.io.enq.bits, _T_127
node _T_128 = eq(UInt<3>(0h5), idx_1)
when _T_128 :
node _T_129 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_5.io.enq.bits, _T_129
node _T_130 = eq(UInt<3>(0h6), idx_1)
when _T_130 :
node _T_131 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_6.io.enq.bits, _T_131
node _T_132 = eq(UInt<3>(0h7), idx_1)
when _T_132 :
node _T_133 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_7.io.enq.bits, _T_133
node _T_134 = eq(UInt<4>(0h8), idx_1)
when _T_134 :
node _T_135 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_8.io.enq.bits, _T_135
node _T_136 = eq(UInt<4>(0h9), idx_1)
when _T_136 :
node _T_137 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_9.io.enq.bits, _T_137
node _T_138 = eq(UInt<4>(0ha), idx_1)
when _T_138 :
node _T_139 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_10.io.enq.bits, _T_139
node _T_140 = eq(UInt<4>(0hb), idx_1)
when _T_140 :
node _T_141 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_11.io.enq.bits, _T_141
node _T_142 = eq(UInt<4>(0hc), idx_1)
when _T_142 :
node _T_143 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_12.io.enq.bits, _T_143
node _T_144 = eq(UInt<4>(0hd), idx_1)
when _T_144 :
node _T_145 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_13.io.enq.bits, _T_145
node _T_146 = eq(UInt<4>(0he), idx_1)
when _T_146 :
node _T_147 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_14.io.enq.bits, _T_147
node _T_148 = eq(UInt<4>(0hf), idx_1)
when _T_148 :
node _T_149 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_15.io.enq.bits, _T_149
node _T_150 = eq(UInt<5>(0h10), idx_1)
when _T_150 :
node _T_151 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_16.io.enq.bits, _T_151
node _T_152 = eq(UInt<5>(0h11), idx_1)
when _T_152 :
node _T_153 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_17.io.enq.bits, _T_153
node _T_154 = eq(UInt<5>(0h12), idx_1)
when _T_154 :
node _T_155 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_18.io.enq.bits, _T_155
node _T_156 = eq(UInt<5>(0h13), idx_1)
when _T_156 :
node _T_157 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_19.io.enq.bits, _T_157
node _T_158 = eq(UInt<5>(0h14), idx_1)
when _T_158 :
node _T_159 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_20.io.enq.bits, _T_159
node _T_160 = eq(UInt<5>(0h15), idx_1)
when _T_160 :
node _T_161 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_21.io.enq.bits, _T_161
node _T_162 = eq(UInt<5>(0h16), idx_1)
when _T_162 :
node _T_163 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_22.io.enq.bits, _T_163
node _T_164 = eq(UInt<5>(0h17), idx_1)
when _T_164 :
node _T_165 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_23.io.enq.bits, _T_165
node _T_166 = eq(UInt<5>(0h18), idx_1)
when _T_166 :
node _T_167 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_24.io.enq.bits, _T_167
node _T_168 = eq(UInt<5>(0h19), idx_1)
when _T_168 :
node _T_169 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_25.io.enq.bits, _T_169
node _T_170 = eq(UInt<5>(0h1a), idx_1)
when _T_170 :
node _T_171 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_26.io.enq.bits, _T_171
node _T_172 = eq(UInt<5>(0h1b), idx_1)
when _T_172 :
node _T_173 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_27.io.enq.bits, _T_173
node _T_174 = eq(UInt<5>(0h1c), idx_1)
when _T_174 :
node _T_175 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_28.io.enq.bits, _T_175
node _T_176 = eq(UInt<5>(0h1d), idx_1)
when _T_176 :
node _T_177 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_29.io.enq.bits, _T_177
node _T_178 = eq(UInt<5>(0h1e), idx_1)
when _T_178 :
node _T_179 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_30.io.enq.bits, _T_179
node _T_180 = eq(UInt<5>(0h1f), idx_1)
when _T_180 :
node _T_181 = shr(memresp_bits_shifted, 8)
connect Queue64_UInt8_31.io.enq.bits, _T_181
node _idx_T_2 = add(write_start_index, UInt<2>(0h2))
node idx_2 = rem(_idx_T_2, UInt<6>(0h20))
node _T_182 = eq(UInt<1>(0h0), idx_2)
when _T_182 :
node _T_183 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8.io.enq.bits, _T_183
node _T_184 = eq(UInt<1>(0h1), idx_2)
when _T_184 :
node _T_185 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_1.io.enq.bits, _T_185
node _T_186 = eq(UInt<2>(0h2), idx_2)
when _T_186 :
node _T_187 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_2.io.enq.bits, _T_187
node _T_188 = eq(UInt<2>(0h3), idx_2)
when _T_188 :
node _T_189 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_3.io.enq.bits, _T_189
node _T_190 = eq(UInt<3>(0h4), idx_2)
when _T_190 :
node _T_191 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_4.io.enq.bits, _T_191
node _T_192 = eq(UInt<3>(0h5), idx_2)
when _T_192 :
node _T_193 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_5.io.enq.bits, _T_193
node _T_194 = eq(UInt<3>(0h6), idx_2)
when _T_194 :
node _T_195 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_6.io.enq.bits, _T_195
node _T_196 = eq(UInt<3>(0h7), idx_2)
when _T_196 :
node _T_197 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_7.io.enq.bits, _T_197
node _T_198 = eq(UInt<4>(0h8), idx_2)
when _T_198 :
node _T_199 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_8.io.enq.bits, _T_199
node _T_200 = eq(UInt<4>(0h9), idx_2)
when _T_200 :
node _T_201 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_9.io.enq.bits, _T_201
node _T_202 = eq(UInt<4>(0ha), idx_2)
when _T_202 :
node _T_203 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_10.io.enq.bits, _T_203
node _T_204 = eq(UInt<4>(0hb), idx_2)
when _T_204 :
node _T_205 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_11.io.enq.bits, _T_205
node _T_206 = eq(UInt<4>(0hc), idx_2)
when _T_206 :
node _T_207 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_12.io.enq.bits, _T_207
node _T_208 = eq(UInt<4>(0hd), idx_2)
when _T_208 :
node _T_209 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_13.io.enq.bits, _T_209
node _T_210 = eq(UInt<4>(0he), idx_2)
when _T_210 :
node _T_211 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_14.io.enq.bits, _T_211
node _T_212 = eq(UInt<4>(0hf), idx_2)
when _T_212 :
node _T_213 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_15.io.enq.bits, _T_213
node _T_214 = eq(UInt<5>(0h10), idx_2)
when _T_214 :
node _T_215 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_16.io.enq.bits, _T_215
node _T_216 = eq(UInt<5>(0h11), idx_2)
when _T_216 :
node _T_217 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_17.io.enq.bits, _T_217
node _T_218 = eq(UInt<5>(0h12), idx_2)
when _T_218 :
node _T_219 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_18.io.enq.bits, _T_219
node _T_220 = eq(UInt<5>(0h13), idx_2)
when _T_220 :
node _T_221 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_19.io.enq.bits, _T_221
node _T_222 = eq(UInt<5>(0h14), idx_2)
when _T_222 :
node _T_223 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_20.io.enq.bits, _T_223
node _T_224 = eq(UInt<5>(0h15), idx_2)
when _T_224 :
node _T_225 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_21.io.enq.bits, _T_225
node _T_226 = eq(UInt<5>(0h16), idx_2)
when _T_226 :
node _T_227 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_22.io.enq.bits, _T_227
node _T_228 = eq(UInt<5>(0h17), idx_2)
when _T_228 :
node _T_229 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_23.io.enq.bits, _T_229
node _T_230 = eq(UInt<5>(0h18), idx_2)
when _T_230 :
node _T_231 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_24.io.enq.bits, _T_231
node _T_232 = eq(UInt<5>(0h19), idx_2)
when _T_232 :
node _T_233 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_25.io.enq.bits, _T_233
node _T_234 = eq(UInt<5>(0h1a), idx_2)
when _T_234 :
node _T_235 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_26.io.enq.bits, _T_235
node _T_236 = eq(UInt<5>(0h1b), idx_2)
when _T_236 :
node _T_237 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_27.io.enq.bits, _T_237
node _T_238 = eq(UInt<5>(0h1c), idx_2)
when _T_238 :
node _T_239 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_28.io.enq.bits, _T_239
node _T_240 = eq(UInt<5>(0h1d), idx_2)
when _T_240 :
node _T_241 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_29.io.enq.bits, _T_241
node _T_242 = eq(UInt<5>(0h1e), idx_2)
when _T_242 :
node _T_243 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_30.io.enq.bits, _T_243
node _T_244 = eq(UInt<5>(0h1f), idx_2)
when _T_244 :
node _T_245 = shr(memresp_bits_shifted, 16)
connect Queue64_UInt8_31.io.enq.bits, _T_245
node _idx_T_3 = add(write_start_index, UInt<2>(0h3))
node idx_3 = rem(_idx_T_3, UInt<6>(0h20))
node _T_246 = eq(UInt<1>(0h0), idx_3)
when _T_246 :
node _T_247 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8.io.enq.bits, _T_247
node _T_248 = eq(UInt<1>(0h1), idx_3)
when _T_248 :
node _T_249 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_1.io.enq.bits, _T_249
node _T_250 = eq(UInt<2>(0h2), idx_3)
when _T_250 :
node _T_251 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_2.io.enq.bits, _T_251
node _T_252 = eq(UInt<2>(0h3), idx_3)
when _T_252 :
node _T_253 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_3.io.enq.bits, _T_253
node _T_254 = eq(UInt<3>(0h4), idx_3)
when _T_254 :
node _T_255 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_4.io.enq.bits, _T_255
node _T_256 = eq(UInt<3>(0h5), idx_3)
when _T_256 :
node _T_257 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_5.io.enq.bits, _T_257
node _T_258 = eq(UInt<3>(0h6), idx_3)
when _T_258 :
node _T_259 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_6.io.enq.bits, _T_259
node _T_260 = eq(UInt<3>(0h7), idx_3)
when _T_260 :
node _T_261 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_7.io.enq.bits, _T_261
node _T_262 = eq(UInt<4>(0h8), idx_3)
when _T_262 :
node _T_263 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_8.io.enq.bits, _T_263
node _T_264 = eq(UInt<4>(0h9), idx_3)
when _T_264 :
node _T_265 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_9.io.enq.bits, _T_265
node _T_266 = eq(UInt<4>(0ha), idx_3)
when _T_266 :
node _T_267 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_10.io.enq.bits, _T_267
node _T_268 = eq(UInt<4>(0hb), idx_3)
when _T_268 :
node _T_269 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_11.io.enq.bits, _T_269
node _T_270 = eq(UInt<4>(0hc), idx_3)
when _T_270 :
node _T_271 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_12.io.enq.bits, _T_271
node _T_272 = eq(UInt<4>(0hd), idx_3)
when _T_272 :
node _T_273 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_13.io.enq.bits, _T_273
node _T_274 = eq(UInt<4>(0he), idx_3)
when _T_274 :
node _T_275 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_14.io.enq.bits, _T_275
node _T_276 = eq(UInt<4>(0hf), idx_3)
when _T_276 :
node _T_277 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_15.io.enq.bits, _T_277
node _T_278 = eq(UInt<5>(0h10), idx_3)
when _T_278 :
node _T_279 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_16.io.enq.bits, _T_279
node _T_280 = eq(UInt<5>(0h11), idx_3)
when _T_280 :
node _T_281 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_17.io.enq.bits, _T_281
node _T_282 = eq(UInt<5>(0h12), idx_3)
when _T_282 :
node _T_283 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_18.io.enq.bits, _T_283
node _T_284 = eq(UInt<5>(0h13), idx_3)
when _T_284 :
node _T_285 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_19.io.enq.bits, _T_285
node _T_286 = eq(UInt<5>(0h14), idx_3)
when _T_286 :
node _T_287 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_20.io.enq.bits, _T_287
node _T_288 = eq(UInt<5>(0h15), idx_3)
when _T_288 :
node _T_289 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_21.io.enq.bits, _T_289
node _T_290 = eq(UInt<5>(0h16), idx_3)
when _T_290 :
node _T_291 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_22.io.enq.bits, _T_291
node _T_292 = eq(UInt<5>(0h17), idx_3)
when _T_292 :
node _T_293 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_23.io.enq.bits, _T_293
node _T_294 = eq(UInt<5>(0h18), idx_3)
when _T_294 :
node _T_295 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_24.io.enq.bits, _T_295
node _T_296 = eq(UInt<5>(0h19), idx_3)
when _T_296 :
node _T_297 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_25.io.enq.bits, _T_297
node _T_298 = eq(UInt<5>(0h1a), idx_3)
when _T_298 :
node _T_299 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_26.io.enq.bits, _T_299
node _T_300 = eq(UInt<5>(0h1b), idx_3)
when _T_300 :
node _T_301 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_27.io.enq.bits, _T_301
node _T_302 = eq(UInt<5>(0h1c), idx_3)
when _T_302 :
node _T_303 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_28.io.enq.bits, _T_303
node _T_304 = eq(UInt<5>(0h1d), idx_3)
when _T_304 :
node _T_305 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_29.io.enq.bits, _T_305
node _T_306 = eq(UInt<5>(0h1e), idx_3)
when _T_306 :
node _T_307 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_30.io.enq.bits, _T_307
node _T_308 = eq(UInt<5>(0h1f), idx_3)
when _T_308 :
node _T_309 = shr(memresp_bits_shifted, 24)
connect Queue64_UInt8_31.io.enq.bits, _T_309
node _idx_T_4 = add(write_start_index, UInt<3>(0h4))
node idx_4 = rem(_idx_T_4, UInt<6>(0h20))
node _T_310 = eq(UInt<1>(0h0), idx_4)
when _T_310 :
node _T_311 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8.io.enq.bits, _T_311
node _T_312 = eq(UInt<1>(0h1), idx_4)
when _T_312 :
node _T_313 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_1.io.enq.bits, _T_313
node _T_314 = eq(UInt<2>(0h2), idx_4)
when _T_314 :
node _T_315 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_2.io.enq.bits, _T_315
node _T_316 = eq(UInt<2>(0h3), idx_4)
when _T_316 :
node _T_317 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_3.io.enq.bits, _T_317
node _T_318 = eq(UInt<3>(0h4), idx_4)
when _T_318 :
node _T_319 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_4.io.enq.bits, _T_319
node _T_320 = eq(UInt<3>(0h5), idx_4)
when _T_320 :
node _T_321 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_5.io.enq.bits, _T_321
node _T_322 = eq(UInt<3>(0h6), idx_4)
when _T_322 :
node _T_323 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_6.io.enq.bits, _T_323
node _T_324 = eq(UInt<3>(0h7), idx_4)
when _T_324 :
node _T_325 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_7.io.enq.bits, _T_325
node _T_326 = eq(UInt<4>(0h8), idx_4)
when _T_326 :
node _T_327 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_8.io.enq.bits, _T_327
node _T_328 = eq(UInt<4>(0h9), idx_4)
when _T_328 :
node _T_329 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_9.io.enq.bits, _T_329
node _T_330 = eq(UInt<4>(0ha), idx_4)
when _T_330 :
node _T_331 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_10.io.enq.bits, _T_331
node _T_332 = eq(UInt<4>(0hb), idx_4)
when _T_332 :
node _T_333 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_11.io.enq.bits, _T_333
node _T_334 = eq(UInt<4>(0hc), idx_4)
when _T_334 :
node _T_335 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_12.io.enq.bits, _T_335
node _T_336 = eq(UInt<4>(0hd), idx_4)
when _T_336 :
node _T_337 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_13.io.enq.bits, _T_337
node _T_338 = eq(UInt<4>(0he), idx_4)
when _T_338 :
node _T_339 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_14.io.enq.bits, _T_339
node _T_340 = eq(UInt<4>(0hf), idx_4)
when _T_340 :
node _T_341 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_15.io.enq.bits, _T_341
node _T_342 = eq(UInt<5>(0h10), idx_4)
when _T_342 :
node _T_343 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_16.io.enq.bits, _T_343
node _T_344 = eq(UInt<5>(0h11), idx_4)
when _T_344 :
node _T_345 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_17.io.enq.bits, _T_345
node _T_346 = eq(UInt<5>(0h12), idx_4)
when _T_346 :
node _T_347 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_18.io.enq.bits, _T_347
node _T_348 = eq(UInt<5>(0h13), idx_4)
when _T_348 :
node _T_349 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_19.io.enq.bits, _T_349
node _T_350 = eq(UInt<5>(0h14), idx_4)
when _T_350 :
node _T_351 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_20.io.enq.bits, _T_351
node _T_352 = eq(UInt<5>(0h15), idx_4)
when _T_352 :
node _T_353 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_21.io.enq.bits, _T_353
node _T_354 = eq(UInt<5>(0h16), idx_4)
when _T_354 :
node _T_355 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_22.io.enq.bits, _T_355
node _T_356 = eq(UInt<5>(0h17), idx_4)
when _T_356 :
node _T_357 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_23.io.enq.bits, _T_357
node _T_358 = eq(UInt<5>(0h18), idx_4)
when _T_358 :
node _T_359 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_24.io.enq.bits, _T_359
node _T_360 = eq(UInt<5>(0h19), idx_4)
when _T_360 :
node _T_361 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_25.io.enq.bits, _T_361
node _T_362 = eq(UInt<5>(0h1a), idx_4)
when _T_362 :
node _T_363 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_26.io.enq.bits, _T_363
node _T_364 = eq(UInt<5>(0h1b), idx_4)
when _T_364 :
node _T_365 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_27.io.enq.bits, _T_365
node _T_366 = eq(UInt<5>(0h1c), idx_4)
when _T_366 :
node _T_367 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_28.io.enq.bits, _T_367
node _T_368 = eq(UInt<5>(0h1d), idx_4)
when _T_368 :
node _T_369 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_29.io.enq.bits, _T_369
node _T_370 = eq(UInt<5>(0h1e), idx_4)
when _T_370 :
node _T_371 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_30.io.enq.bits, _T_371
node _T_372 = eq(UInt<5>(0h1f), idx_4)
when _T_372 :
node _T_373 = shr(memresp_bits_shifted, 32)
connect Queue64_UInt8_31.io.enq.bits, _T_373
node _idx_T_5 = add(write_start_index, UInt<3>(0h5))
node idx_5 = rem(_idx_T_5, UInt<6>(0h20))
node _T_374 = eq(UInt<1>(0h0), idx_5)
when _T_374 :
node _T_375 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8.io.enq.bits, _T_375
node _T_376 = eq(UInt<1>(0h1), idx_5)
when _T_376 :
node _T_377 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_1.io.enq.bits, _T_377
node _T_378 = eq(UInt<2>(0h2), idx_5)
when _T_378 :
node _T_379 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_2.io.enq.bits, _T_379
node _T_380 = eq(UInt<2>(0h3), idx_5)
when _T_380 :
node _T_381 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_3.io.enq.bits, _T_381
node _T_382 = eq(UInt<3>(0h4), idx_5)
when _T_382 :
node _T_383 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_4.io.enq.bits, _T_383
node _T_384 = eq(UInt<3>(0h5), idx_5)
when _T_384 :
node _T_385 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_5.io.enq.bits, _T_385
node _T_386 = eq(UInt<3>(0h6), idx_5)
when _T_386 :
node _T_387 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_6.io.enq.bits, _T_387
node _T_388 = eq(UInt<3>(0h7), idx_5)
when _T_388 :
node _T_389 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_7.io.enq.bits, _T_389
node _T_390 = eq(UInt<4>(0h8), idx_5)
when _T_390 :
node _T_391 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_8.io.enq.bits, _T_391
node _T_392 = eq(UInt<4>(0h9), idx_5)
when _T_392 :
node _T_393 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_9.io.enq.bits, _T_393
node _T_394 = eq(UInt<4>(0ha), idx_5)
when _T_394 :
node _T_395 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_10.io.enq.bits, _T_395
node _T_396 = eq(UInt<4>(0hb), idx_5)
when _T_396 :
node _T_397 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_11.io.enq.bits, _T_397
node _T_398 = eq(UInt<4>(0hc), idx_5)
when _T_398 :
node _T_399 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_12.io.enq.bits, _T_399
node _T_400 = eq(UInt<4>(0hd), idx_5)
when _T_400 :
node _T_401 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_13.io.enq.bits, _T_401
node _T_402 = eq(UInt<4>(0he), idx_5)
when _T_402 :
node _T_403 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_14.io.enq.bits, _T_403
node _T_404 = eq(UInt<4>(0hf), idx_5)
when _T_404 :
node _T_405 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_15.io.enq.bits, _T_405
node _T_406 = eq(UInt<5>(0h10), idx_5)
when _T_406 :
node _T_407 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_16.io.enq.bits, _T_407
node _T_408 = eq(UInt<5>(0h11), idx_5)
when _T_408 :
node _T_409 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_17.io.enq.bits, _T_409
node _T_410 = eq(UInt<5>(0h12), idx_5)
when _T_410 :
node _T_411 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_18.io.enq.bits, _T_411
node _T_412 = eq(UInt<5>(0h13), idx_5)
when _T_412 :
node _T_413 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_19.io.enq.bits, _T_413
node _T_414 = eq(UInt<5>(0h14), idx_5)
when _T_414 :
node _T_415 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_20.io.enq.bits, _T_415
node _T_416 = eq(UInt<5>(0h15), idx_5)
when _T_416 :
node _T_417 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_21.io.enq.bits, _T_417
node _T_418 = eq(UInt<5>(0h16), idx_5)
when _T_418 :
node _T_419 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_22.io.enq.bits, _T_419
node _T_420 = eq(UInt<5>(0h17), idx_5)
when _T_420 :
node _T_421 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_23.io.enq.bits, _T_421
node _T_422 = eq(UInt<5>(0h18), idx_5)
when _T_422 :
node _T_423 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_24.io.enq.bits, _T_423
node _T_424 = eq(UInt<5>(0h19), idx_5)
when _T_424 :
node _T_425 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_25.io.enq.bits, _T_425
node _T_426 = eq(UInt<5>(0h1a), idx_5)
when _T_426 :
node _T_427 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_26.io.enq.bits, _T_427
node _T_428 = eq(UInt<5>(0h1b), idx_5)
when _T_428 :
node _T_429 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_27.io.enq.bits, _T_429
node _T_430 = eq(UInt<5>(0h1c), idx_5)
when _T_430 :
node _T_431 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_28.io.enq.bits, _T_431
node _T_432 = eq(UInt<5>(0h1d), idx_5)
when _T_432 :
node _T_433 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_29.io.enq.bits, _T_433
node _T_434 = eq(UInt<5>(0h1e), idx_5)
when _T_434 :
node _T_435 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_30.io.enq.bits, _T_435
node _T_436 = eq(UInt<5>(0h1f), idx_5)
when _T_436 :
node _T_437 = shr(memresp_bits_shifted, 40)
connect Queue64_UInt8_31.io.enq.bits, _T_437
node _idx_T_6 = add(write_start_index, UInt<3>(0h6))
node idx_6 = rem(_idx_T_6, UInt<6>(0h20))
node _T_438 = eq(UInt<1>(0h0), idx_6)
when _T_438 :
node _T_439 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8.io.enq.bits, _T_439
node _T_440 = eq(UInt<1>(0h1), idx_6)
when _T_440 :
node _T_441 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_1.io.enq.bits, _T_441
node _T_442 = eq(UInt<2>(0h2), idx_6)
when _T_442 :
node _T_443 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_2.io.enq.bits, _T_443
node _T_444 = eq(UInt<2>(0h3), idx_6)
when _T_444 :
node _T_445 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_3.io.enq.bits, _T_445
node _T_446 = eq(UInt<3>(0h4), idx_6)
when _T_446 :
node _T_447 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_4.io.enq.bits, _T_447
node _T_448 = eq(UInt<3>(0h5), idx_6)
when _T_448 :
node _T_449 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_5.io.enq.bits, _T_449
node _T_450 = eq(UInt<3>(0h6), idx_6)
when _T_450 :
node _T_451 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_6.io.enq.bits, _T_451
node _T_452 = eq(UInt<3>(0h7), idx_6)
when _T_452 :
node _T_453 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_7.io.enq.bits, _T_453
node _T_454 = eq(UInt<4>(0h8), idx_6)
when _T_454 :
node _T_455 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_8.io.enq.bits, _T_455
node _T_456 = eq(UInt<4>(0h9), idx_6)
when _T_456 :
node _T_457 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_9.io.enq.bits, _T_457
node _T_458 = eq(UInt<4>(0ha), idx_6)
when _T_458 :
node _T_459 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_10.io.enq.bits, _T_459
node _T_460 = eq(UInt<4>(0hb), idx_6)
when _T_460 :
node _T_461 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_11.io.enq.bits, _T_461
node _T_462 = eq(UInt<4>(0hc), idx_6)
when _T_462 :
node _T_463 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_12.io.enq.bits, _T_463
node _T_464 = eq(UInt<4>(0hd), idx_6)
when _T_464 :
node _T_465 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_13.io.enq.bits, _T_465
node _T_466 = eq(UInt<4>(0he), idx_6)
when _T_466 :
node _T_467 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_14.io.enq.bits, _T_467
node _T_468 = eq(UInt<4>(0hf), idx_6)
when _T_468 :
node _T_469 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_15.io.enq.bits, _T_469
node _T_470 = eq(UInt<5>(0h10), idx_6)
when _T_470 :
node _T_471 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_16.io.enq.bits, _T_471
node _T_472 = eq(UInt<5>(0h11), idx_6)
when _T_472 :
node _T_473 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_17.io.enq.bits, _T_473
node _T_474 = eq(UInt<5>(0h12), idx_6)
when _T_474 :
node _T_475 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_18.io.enq.bits, _T_475
node _T_476 = eq(UInt<5>(0h13), idx_6)
when _T_476 :
node _T_477 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_19.io.enq.bits, _T_477
node _T_478 = eq(UInt<5>(0h14), idx_6)
when _T_478 :
node _T_479 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_20.io.enq.bits, _T_479
node _T_480 = eq(UInt<5>(0h15), idx_6)
when _T_480 :
node _T_481 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_21.io.enq.bits, _T_481
node _T_482 = eq(UInt<5>(0h16), idx_6)
when _T_482 :
node _T_483 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_22.io.enq.bits, _T_483
node _T_484 = eq(UInt<5>(0h17), idx_6)
when _T_484 :
node _T_485 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_23.io.enq.bits, _T_485
node _T_486 = eq(UInt<5>(0h18), idx_6)
when _T_486 :
node _T_487 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_24.io.enq.bits, _T_487
node _T_488 = eq(UInt<5>(0h19), idx_6)
when _T_488 :
node _T_489 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_25.io.enq.bits, _T_489
node _T_490 = eq(UInt<5>(0h1a), idx_6)
when _T_490 :
node _T_491 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_26.io.enq.bits, _T_491
node _T_492 = eq(UInt<5>(0h1b), idx_6)
when _T_492 :
node _T_493 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_27.io.enq.bits, _T_493
node _T_494 = eq(UInt<5>(0h1c), idx_6)
when _T_494 :
node _T_495 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_28.io.enq.bits, _T_495
node _T_496 = eq(UInt<5>(0h1d), idx_6)
when _T_496 :
node _T_497 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_29.io.enq.bits, _T_497
node _T_498 = eq(UInt<5>(0h1e), idx_6)
when _T_498 :
node _T_499 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_30.io.enq.bits, _T_499
node _T_500 = eq(UInt<5>(0h1f), idx_6)
when _T_500 :
node _T_501 = shr(memresp_bits_shifted, 48)
connect Queue64_UInt8_31.io.enq.bits, _T_501
node _idx_T_7 = add(write_start_index, UInt<3>(0h7))
node idx_7 = rem(_idx_T_7, UInt<6>(0h20))
node _T_502 = eq(UInt<1>(0h0), idx_7)
when _T_502 :
node _T_503 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8.io.enq.bits, _T_503
node _T_504 = eq(UInt<1>(0h1), idx_7)
when _T_504 :
node _T_505 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_1.io.enq.bits, _T_505
node _T_506 = eq(UInt<2>(0h2), idx_7)
when _T_506 :
node _T_507 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_2.io.enq.bits, _T_507
node _T_508 = eq(UInt<2>(0h3), idx_7)
when _T_508 :
node _T_509 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_3.io.enq.bits, _T_509
node _T_510 = eq(UInt<3>(0h4), idx_7)
when _T_510 :
node _T_511 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_4.io.enq.bits, _T_511
node _T_512 = eq(UInt<3>(0h5), idx_7)
when _T_512 :
node _T_513 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_5.io.enq.bits, _T_513
node _T_514 = eq(UInt<3>(0h6), idx_7)
when _T_514 :
node _T_515 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_6.io.enq.bits, _T_515
node _T_516 = eq(UInt<3>(0h7), idx_7)
when _T_516 :
node _T_517 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_7.io.enq.bits, _T_517
node _T_518 = eq(UInt<4>(0h8), idx_7)
when _T_518 :
node _T_519 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_8.io.enq.bits, _T_519
node _T_520 = eq(UInt<4>(0h9), idx_7)
when _T_520 :
node _T_521 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_9.io.enq.bits, _T_521
node _T_522 = eq(UInt<4>(0ha), idx_7)
when _T_522 :
node _T_523 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_10.io.enq.bits, _T_523
node _T_524 = eq(UInt<4>(0hb), idx_7)
when _T_524 :
node _T_525 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_11.io.enq.bits, _T_525
node _T_526 = eq(UInt<4>(0hc), idx_7)
when _T_526 :
node _T_527 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_12.io.enq.bits, _T_527
node _T_528 = eq(UInt<4>(0hd), idx_7)
when _T_528 :
node _T_529 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_13.io.enq.bits, _T_529
node _T_530 = eq(UInt<4>(0he), idx_7)
when _T_530 :
node _T_531 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_14.io.enq.bits, _T_531
node _T_532 = eq(UInt<4>(0hf), idx_7)
when _T_532 :
node _T_533 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_15.io.enq.bits, _T_533
node _T_534 = eq(UInt<5>(0h10), idx_7)
when _T_534 :
node _T_535 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_16.io.enq.bits, _T_535
node _T_536 = eq(UInt<5>(0h11), idx_7)
when _T_536 :
node _T_537 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_17.io.enq.bits, _T_537
node _T_538 = eq(UInt<5>(0h12), idx_7)
when _T_538 :
node _T_539 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_18.io.enq.bits, _T_539
node _T_540 = eq(UInt<5>(0h13), idx_7)
when _T_540 :
node _T_541 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_19.io.enq.bits, _T_541
node _T_542 = eq(UInt<5>(0h14), idx_7)
when _T_542 :
node _T_543 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_20.io.enq.bits, _T_543
node _T_544 = eq(UInt<5>(0h15), idx_7)
when _T_544 :
node _T_545 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_21.io.enq.bits, _T_545
node _T_546 = eq(UInt<5>(0h16), idx_7)
when _T_546 :
node _T_547 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_22.io.enq.bits, _T_547
node _T_548 = eq(UInt<5>(0h17), idx_7)
when _T_548 :
node _T_549 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_23.io.enq.bits, _T_549
node _T_550 = eq(UInt<5>(0h18), idx_7)
when _T_550 :
node _T_551 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_24.io.enq.bits, _T_551
node _T_552 = eq(UInt<5>(0h19), idx_7)
when _T_552 :
node _T_553 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_25.io.enq.bits, _T_553
node _T_554 = eq(UInt<5>(0h1a), idx_7)
when _T_554 :
node _T_555 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_26.io.enq.bits, _T_555
node _T_556 = eq(UInt<5>(0h1b), idx_7)
when _T_556 :
node _T_557 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_27.io.enq.bits, _T_557
node _T_558 = eq(UInt<5>(0h1c), idx_7)
when _T_558 :
node _T_559 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_28.io.enq.bits, _T_559
node _T_560 = eq(UInt<5>(0h1d), idx_7)
when _T_560 :
node _T_561 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_29.io.enq.bits, _T_561
node _T_562 = eq(UInt<5>(0h1e), idx_7)
when _T_562 :
node _T_563 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_30.io.enq.bits, _T_563
node _T_564 = eq(UInt<5>(0h1f), idx_7)
when _T_564 :
node _T_565 = shr(memresp_bits_shifted, 56)
connect Queue64_UInt8_31.io.enq.bits, _T_565
node _idx_T_8 = add(write_start_index, UInt<4>(0h8))
node idx_8 = rem(_idx_T_8, UInt<6>(0h20))
node _T_566 = eq(UInt<1>(0h0), idx_8)
when _T_566 :
node _T_567 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8.io.enq.bits, _T_567
node _T_568 = eq(UInt<1>(0h1), idx_8)
when _T_568 :
node _T_569 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_1.io.enq.bits, _T_569
node _T_570 = eq(UInt<2>(0h2), idx_8)
when _T_570 :
node _T_571 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_2.io.enq.bits, _T_571
node _T_572 = eq(UInt<2>(0h3), idx_8)
when _T_572 :
node _T_573 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_3.io.enq.bits, _T_573
node _T_574 = eq(UInt<3>(0h4), idx_8)
when _T_574 :
node _T_575 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_4.io.enq.bits, _T_575
node _T_576 = eq(UInt<3>(0h5), idx_8)
when _T_576 :
node _T_577 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_5.io.enq.bits, _T_577
node _T_578 = eq(UInt<3>(0h6), idx_8)
when _T_578 :
node _T_579 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_6.io.enq.bits, _T_579
node _T_580 = eq(UInt<3>(0h7), idx_8)
when _T_580 :
node _T_581 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_7.io.enq.bits, _T_581
node _T_582 = eq(UInt<4>(0h8), idx_8)
when _T_582 :
node _T_583 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_8.io.enq.bits, _T_583
node _T_584 = eq(UInt<4>(0h9), idx_8)
when _T_584 :
node _T_585 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_9.io.enq.bits, _T_585
node _T_586 = eq(UInt<4>(0ha), idx_8)
when _T_586 :
node _T_587 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_10.io.enq.bits, _T_587
node _T_588 = eq(UInt<4>(0hb), idx_8)
when _T_588 :
node _T_589 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_11.io.enq.bits, _T_589
node _T_590 = eq(UInt<4>(0hc), idx_8)
when _T_590 :
node _T_591 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_12.io.enq.bits, _T_591
node _T_592 = eq(UInt<4>(0hd), idx_8)
when _T_592 :
node _T_593 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_13.io.enq.bits, _T_593
node _T_594 = eq(UInt<4>(0he), idx_8)
when _T_594 :
node _T_595 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_14.io.enq.bits, _T_595
node _T_596 = eq(UInt<4>(0hf), idx_8)
when _T_596 :
node _T_597 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_15.io.enq.bits, _T_597
node _T_598 = eq(UInt<5>(0h10), idx_8)
when _T_598 :
node _T_599 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_16.io.enq.bits, _T_599
node _T_600 = eq(UInt<5>(0h11), idx_8)
when _T_600 :
node _T_601 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_17.io.enq.bits, _T_601
node _T_602 = eq(UInt<5>(0h12), idx_8)
when _T_602 :
node _T_603 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_18.io.enq.bits, _T_603
node _T_604 = eq(UInt<5>(0h13), idx_8)
when _T_604 :
node _T_605 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_19.io.enq.bits, _T_605
node _T_606 = eq(UInt<5>(0h14), idx_8)
when _T_606 :
node _T_607 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_20.io.enq.bits, _T_607
node _T_608 = eq(UInt<5>(0h15), idx_8)
when _T_608 :
node _T_609 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_21.io.enq.bits, _T_609
node _T_610 = eq(UInt<5>(0h16), idx_8)
when _T_610 :
node _T_611 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_22.io.enq.bits, _T_611
node _T_612 = eq(UInt<5>(0h17), idx_8)
when _T_612 :
node _T_613 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_23.io.enq.bits, _T_613
node _T_614 = eq(UInt<5>(0h18), idx_8)
when _T_614 :
node _T_615 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_24.io.enq.bits, _T_615
node _T_616 = eq(UInt<5>(0h19), idx_8)
when _T_616 :
node _T_617 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_25.io.enq.bits, _T_617
node _T_618 = eq(UInt<5>(0h1a), idx_8)
when _T_618 :
node _T_619 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_26.io.enq.bits, _T_619
node _T_620 = eq(UInt<5>(0h1b), idx_8)
when _T_620 :
node _T_621 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_27.io.enq.bits, _T_621
node _T_622 = eq(UInt<5>(0h1c), idx_8)
when _T_622 :
node _T_623 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_28.io.enq.bits, _T_623
node _T_624 = eq(UInt<5>(0h1d), idx_8)
when _T_624 :
node _T_625 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_29.io.enq.bits, _T_625
node _T_626 = eq(UInt<5>(0h1e), idx_8)
when _T_626 :
node _T_627 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_30.io.enq.bits, _T_627
node _T_628 = eq(UInt<5>(0h1f), idx_8)
when _T_628 :
node _T_629 = shr(memresp_bits_shifted, 64)
connect Queue64_UInt8_31.io.enq.bits, _T_629
node _idx_T_9 = add(write_start_index, UInt<4>(0h9))
node idx_9 = rem(_idx_T_9, UInt<6>(0h20))
node _T_630 = eq(UInt<1>(0h0), idx_9)
when _T_630 :
node _T_631 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8.io.enq.bits, _T_631
node _T_632 = eq(UInt<1>(0h1), idx_9)
when _T_632 :
node _T_633 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_1.io.enq.bits, _T_633
node _T_634 = eq(UInt<2>(0h2), idx_9)
when _T_634 :
node _T_635 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_2.io.enq.bits, _T_635
node _T_636 = eq(UInt<2>(0h3), idx_9)
when _T_636 :
node _T_637 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_3.io.enq.bits, _T_637
node _T_638 = eq(UInt<3>(0h4), idx_9)
when _T_638 :
node _T_639 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_4.io.enq.bits, _T_639
node _T_640 = eq(UInt<3>(0h5), idx_9)
when _T_640 :
node _T_641 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_5.io.enq.bits, _T_641
node _T_642 = eq(UInt<3>(0h6), idx_9)
when _T_642 :
node _T_643 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_6.io.enq.bits, _T_643
node _T_644 = eq(UInt<3>(0h7), idx_9)
when _T_644 :
node _T_645 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_7.io.enq.bits, _T_645
node _T_646 = eq(UInt<4>(0h8), idx_9)
when _T_646 :
node _T_647 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_8.io.enq.bits, _T_647
node _T_648 = eq(UInt<4>(0h9), idx_9)
when _T_648 :
node _T_649 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_9.io.enq.bits, _T_649
node _T_650 = eq(UInt<4>(0ha), idx_9)
when _T_650 :
node _T_651 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_10.io.enq.bits, _T_651
node _T_652 = eq(UInt<4>(0hb), idx_9)
when _T_652 :
node _T_653 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_11.io.enq.bits, _T_653
node _T_654 = eq(UInt<4>(0hc), idx_9)
when _T_654 :
node _T_655 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_12.io.enq.bits, _T_655
node _T_656 = eq(UInt<4>(0hd), idx_9)
when _T_656 :
node _T_657 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_13.io.enq.bits, _T_657
node _T_658 = eq(UInt<4>(0he), idx_9)
when _T_658 :
node _T_659 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_14.io.enq.bits, _T_659
node _T_660 = eq(UInt<4>(0hf), idx_9)
when _T_660 :
node _T_661 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_15.io.enq.bits, _T_661
node _T_662 = eq(UInt<5>(0h10), idx_9)
when _T_662 :
node _T_663 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_16.io.enq.bits, _T_663
node _T_664 = eq(UInt<5>(0h11), idx_9)
when _T_664 :
node _T_665 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_17.io.enq.bits, _T_665
node _T_666 = eq(UInt<5>(0h12), idx_9)
when _T_666 :
node _T_667 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_18.io.enq.bits, _T_667
node _T_668 = eq(UInt<5>(0h13), idx_9)
when _T_668 :
node _T_669 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_19.io.enq.bits, _T_669
node _T_670 = eq(UInt<5>(0h14), idx_9)
when _T_670 :
node _T_671 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_20.io.enq.bits, _T_671
node _T_672 = eq(UInt<5>(0h15), idx_9)
when _T_672 :
node _T_673 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_21.io.enq.bits, _T_673
node _T_674 = eq(UInt<5>(0h16), idx_9)
when _T_674 :
node _T_675 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_22.io.enq.bits, _T_675
node _T_676 = eq(UInt<5>(0h17), idx_9)
when _T_676 :
node _T_677 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_23.io.enq.bits, _T_677
node _T_678 = eq(UInt<5>(0h18), idx_9)
when _T_678 :
node _T_679 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_24.io.enq.bits, _T_679
node _T_680 = eq(UInt<5>(0h19), idx_9)
when _T_680 :
node _T_681 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_25.io.enq.bits, _T_681
node _T_682 = eq(UInt<5>(0h1a), idx_9)
when _T_682 :
node _T_683 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_26.io.enq.bits, _T_683
node _T_684 = eq(UInt<5>(0h1b), idx_9)
when _T_684 :
node _T_685 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_27.io.enq.bits, _T_685
node _T_686 = eq(UInt<5>(0h1c), idx_9)
when _T_686 :
node _T_687 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_28.io.enq.bits, _T_687
node _T_688 = eq(UInt<5>(0h1d), idx_9)
when _T_688 :
node _T_689 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_29.io.enq.bits, _T_689
node _T_690 = eq(UInt<5>(0h1e), idx_9)
when _T_690 :
node _T_691 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_30.io.enq.bits, _T_691
node _T_692 = eq(UInt<5>(0h1f), idx_9)
when _T_692 :
node _T_693 = shr(memresp_bits_shifted, 72)
connect Queue64_UInt8_31.io.enq.bits, _T_693
node _idx_T_10 = add(write_start_index, UInt<4>(0ha))
node idx_10 = rem(_idx_T_10, UInt<6>(0h20))
node _T_694 = eq(UInt<1>(0h0), idx_10)
when _T_694 :
node _T_695 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8.io.enq.bits, _T_695
node _T_696 = eq(UInt<1>(0h1), idx_10)
when _T_696 :
node _T_697 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_1.io.enq.bits, _T_697
node _T_698 = eq(UInt<2>(0h2), idx_10)
when _T_698 :
node _T_699 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_2.io.enq.bits, _T_699
node _T_700 = eq(UInt<2>(0h3), idx_10)
when _T_700 :
node _T_701 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_3.io.enq.bits, _T_701
node _T_702 = eq(UInt<3>(0h4), idx_10)
when _T_702 :
node _T_703 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_4.io.enq.bits, _T_703
node _T_704 = eq(UInt<3>(0h5), idx_10)
when _T_704 :
node _T_705 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_5.io.enq.bits, _T_705
node _T_706 = eq(UInt<3>(0h6), idx_10)
when _T_706 :
node _T_707 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_6.io.enq.bits, _T_707
node _T_708 = eq(UInt<3>(0h7), idx_10)
when _T_708 :
node _T_709 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_7.io.enq.bits, _T_709
node _T_710 = eq(UInt<4>(0h8), idx_10)
when _T_710 :
node _T_711 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_8.io.enq.bits, _T_711
node _T_712 = eq(UInt<4>(0h9), idx_10)
when _T_712 :
node _T_713 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_9.io.enq.bits, _T_713
node _T_714 = eq(UInt<4>(0ha), idx_10)
when _T_714 :
node _T_715 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_10.io.enq.bits, _T_715
node _T_716 = eq(UInt<4>(0hb), idx_10)
when _T_716 :
node _T_717 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_11.io.enq.bits, _T_717
node _T_718 = eq(UInt<4>(0hc), idx_10)
when _T_718 :
node _T_719 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_12.io.enq.bits, _T_719
node _T_720 = eq(UInt<4>(0hd), idx_10)
when _T_720 :
node _T_721 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_13.io.enq.bits, _T_721
node _T_722 = eq(UInt<4>(0he), idx_10)
when _T_722 :
node _T_723 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_14.io.enq.bits, _T_723
node _T_724 = eq(UInt<4>(0hf), idx_10)
when _T_724 :
node _T_725 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_15.io.enq.bits, _T_725
node _T_726 = eq(UInt<5>(0h10), idx_10)
when _T_726 :
node _T_727 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_16.io.enq.bits, _T_727
node _T_728 = eq(UInt<5>(0h11), idx_10)
when _T_728 :
node _T_729 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_17.io.enq.bits, _T_729
node _T_730 = eq(UInt<5>(0h12), idx_10)
when _T_730 :
node _T_731 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_18.io.enq.bits, _T_731
node _T_732 = eq(UInt<5>(0h13), idx_10)
when _T_732 :
node _T_733 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_19.io.enq.bits, _T_733
node _T_734 = eq(UInt<5>(0h14), idx_10)
when _T_734 :
node _T_735 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_20.io.enq.bits, _T_735
node _T_736 = eq(UInt<5>(0h15), idx_10)
when _T_736 :
node _T_737 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_21.io.enq.bits, _T_737
node _T_738 = eq(UInt<5>(0h16), idx_10)
when _T_738 :
node _T_739 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_22.io.enq.bits, _T_739
node _T_740 = eq(UInt<5>(0h17), idx_10)
when _T_740 :
node _T_741 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_23.io.enq.bits, _T_741
node _T_742 = eq(UInt<5>(0h18), idx_10)
when _T_742 :
node _T_743 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_24.io.enq.bits, _T_743
node _T_744 = eq(UInt<5>(0h19), idx_10)
when _T_744 :
node _T_745 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_25.io.enq.bits, _T_745
node _T_746 = eq(UInt<5>(0h1a), idx_10)
when _T_746 :
node _T_747 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_26.io.enq.bits, _T_747
node _T_748 = eq(UInt<5>(0h1b), idx_10)
when _T_748 :
node _T_749 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_27.io.enq.bits, _T_749
node _T_750 = eq(UInt<5>(0h1c), idx_10)
when _T_750 :
node _T_751 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_28.io.enq.bits, _T_751
node _T_752 = eq(UInt<5>(0h1d), idx_10)
when _T_752 :
node _T_753 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_29.io.enq.bits, _T_753
node _T_754 = eq(UInt<5>(0h1e), idx_10)
when _T_754 :
node _T_755 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_30.io.enq.bits, _T_755
node _T_756 = eq(UInt<5>(0h1f), idx_10)
when _T_756 :
node _T_757 = shr(memresp_bits_shifted, 80)
connect Queue64_UInt8_31.io.enq.bits, _T_757
node _idx_T_11 = add(write_start_index, UInt<4>(0hb))
node idx_11 = rem(_idx_T_11, UInt<6>(0h20))
node _T_758 = eq(UInt<1>(0h0), idx_11)
when _T_758 :
node _T_759 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8.io.enq.bits, _T_759
node _T_760 = eq(UInt<1>(0h1), idx_11)
when _T_760 :
node _T_761 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_1.io.enq.bits, _T_761
node _T_762 = eq(UInt<2>(0h2), idx_11)
when _T_762 :
node _T_763 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_2.io.enq.bits, _T_763
node _T_764 = eq(UInt<2>(0h3), idx_11)
when _T_764 :
node _T_765 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_3.io.enq.bits, _T_765
node _T_766 = eq(UInt<3>(0h4), idx_11)
when _T_766 :
node _T_767 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_4.io.enq.bits, _T_767
node _T_768 = eq(UInt<3>(0h5), idx_11)
when _T_768 :
node _T_769 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_5.io.enq.bits, _T_769
node _T_770 = eq(UInt<3>(0h6), idx_11)
when _T_770 :
node _T_771 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_6.io.enq.bits, _T_771
node _T_772 = eq(UInt<3>(0h7), idx_11)
when _T_772 :
node _T_773 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_7.io.enq.bits, _T_773
node _T_774 = eq(UInt<4>(0h8), idx_11)
when _T_774 :
node _T_775 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_8.io.enq.bits, _T_775
node _T_776 = eq(UInt<4>(0h9), idx_11)
when _T_776 :
node _T_777 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_9.io.enq.bits, _T_777
node _T_778 = eq(UInt<4>(0ha), idx_11)
when _T_778 :
node _T_779 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_10.io.enq.bits, _T_779
node _T_780 = eq(UInt<4>(0hb), idx_11)
when _T_780 :
node _T_781 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_11.io.enq.bits, _T_781
node _T_782 = eq(UInt<4>(0hc), idx_11)
when _T_782 :
node _T_783 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_12.io.enq.bits, _T_783
node _T_784 = eq(UInt<4>(0hd), idx_11)
when _T_784 :
node _T_785 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_13.io.enq.bits, _T_785
node _T_786 = eq(UInt<4>(0he), idx_11)
when _T_786 :
node _T_787 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_14.io.enq.bits, _T_787
node _T_788 = eq(UInt<4>(0hf), idx_11)
when _T_788 :
node _T_789 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_15.io.enq.bits, _T_789
node _T_790 = eq(UInt<5>(0h10), idx_11)
when _T_790 :
node _T_791 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_16.io.enq.bits, _T_791
node _T_792 = eq(UInt<5>(0h11), idx_11)
when _T_792 :
node _T_793 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_17.io.enq.bits, _T_793
node _T_794 = eq(UInt<5>(0h12), idx_11)
when _T_794 :
node _T_795 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_18.io.enq.bits, _T_795
node _T_796 = eq(UInt<5>(0h13), idx_11)
when _T_796 :
node _T_797 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_19.io.enq.bits, _T_797
node _T_798 = eq(UInt<5>(0h14), idx_11)
when _T_798 :
node _T_799 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_20.io.enq.bits, _T_799
node _T_800 = eq(UInt<5>(0h15), idx_11)
when _T_800 :
node _T_801 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_21.io.enq.bits, _T_801
node _T_802 = eq(UInt<5>(0h16), idx_11)
when _T_802 :
node _T_803 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_22.io.enq.bits, _T_803
node _T_804 = eq(UInt<5>(0h17), idx_11)
when _T_804 :
node _T_805 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_23.io.enq.bits, _T_805
node _T_806 = eq(UInt<5>(0h18), idx_11)
when _T_806 :
node _T_807 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_24.io.enq.bits, _T_807
node _T_808 = eq(UInt<5>(0h19), idx_11)
when _T_808 :
node _T_809 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_25.io.enq.bits, _T_809
node _T_810 = eq(UInt<5>(0h1a), idx_11)
when _T_810 :
node _T_811 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_26.io.enq.bits, _T_811
node _T_812 = eq(UInt<5>(0h1b), idx_11)
when _T_812 :
node _T_813 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_27.io.enq.bits, _T_813
node _T_814 = eq(UInt<5>(0h1c), idx_11)
when _T_814 :
node _T_815 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_28.io.enq.bits, _T_815
node _T_816 = eq(UInt<5>(0h1d), idx_11)
when _T_816 :
node _T_817 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_29.io.enq.bits, _T_817
node _T_818 = eq(UInt<5>(0h1e), idx_11)
when _T_818 :
node _T_819 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_30.io.enq.bits, _T_819
node _T_820 = eq(UInt<5>(0h1f), idx_11)
when _T_820 :
node _T_821 = shr(memresp_bits_shifted, 88)
connect Queue64_UInt8_31.io.enq.bits, _T_821
node _idx_T_12 = add(write_start_index, UInt<4>(0hc))
node idx_12 = rem(_idx_T_12, UInt<6>(0h20))
node _T_822 = eq(UInt<1>(0h0), idx_12)
when _T_822 :
node _T_823 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8.io.enq.bits, _T_823
node _T_824 = eq(UInt<1>(0h1), idx_12)
when _T_824 :
node _T_825 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_1.io.enq.bits, _T_825
node _T_826 = eq(UInt<2>(0h2), idx_12)
when _T_826 :
node _T_827 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_2.io.enq.bits, _T_827
node _T_828 = eq(UInt<2>(0h3), idx_12)
when _T_828 :
node _T_829 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_3.io.enq.bits, _T_829
node _T_830 = eq(UInt<3>(0h4), idx_12)
when _T_830 :
node _T_831 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_4.io.enq.bits, _T_831
node _T_832 = eq(UInt<3>(0h5), idx_12)
when _T_832 :
node _T_833 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_5.io.enq.bits, _T_833
node _T_834 = eq(UInt<3>(0h6), idx_12)
when _T_834 :
node _T_835 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_6.io.enq.bits, _T_835
node _T_836 = eq(UInt<3>(0h7), idx_12)
when _T_836 :
node _T_837 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_7.io.enq.bits, _T_837
node _T_838 = eq(UInt<4>(0h8), idx_12)
when _T_838 :
node _T_839 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_8.io.enq.bits, _T_839
node _T_840 = eq(UInt<4>(0h9), idx_12)
when _T_840 :
node _T_841 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_9.io.enq.bits, _T_841
node _T_842 = eq(UInt<4>(0ha), idx_12)
when _T_842 :
node _T_843 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_10.io.enq.bits, _T_843
node _T_844 = eq(UInt<4>(0hb), idx_12)
when _T_844 :
node _T_845 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_11.io.enq.bits, _T_845
node _T_846 = eq(UInt<4>(0hc), idx_12)
when _T_846 :
node _T_847 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_12.io.enq.bits, _T_847
node _T_848 = eq(UInt<4>(0hd), idx_12)
when _T_848 :
node _T_849 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_13.io.enq.bits, _T_849
node _T_850 = eq(UInt<4>(0he), idx_12)
when _T_850 :
node _T_851 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_14.io.enq.bits, _T_851
node _T_852 = eq(UInt<4>(0hf), idx_12)
when _T_852 :
node _T_853 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_15.io.enq.bits, _T_853
node _T_854 = eq(UInt<5>(0h10), idx_12)
when _T_854 :
node _T_855 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_16.io.enq.bits, _T_855
node _T_856 = eq(UInt<5>(0h11), idx_12)
when _T_856 :
node _T_857 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_17.io.enq.bits, _T_857
node _T_858 = eq(UInt<5>(0h12), idx_12)
when _T_858 :
node _T_859 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_18.io.enq.bits, _T_859
node _T_860 = eq(UInt<5>(0h13), idx_12)
when _T_860 :
node _T_861 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_19.io.enq.bits, _T_861
node _T_862 = eq(UInt<5>(0h14), idx_12)
when _T_862 :
node _T_863 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_20.io.enq.bits, _T_863
node _T_864 = eq(UInt<5>(0h15), idx_12)
when _T_864 :
node _T_865 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_21.io.enq.bits, _T_865
node _T_866 = eq(UInt<5>(0h16), idx_12)
when _T_866 :
node _T_867 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_22.io.enq.bits, _T_867
node _T_868 = eq(UInt<5>(0h17), idx_12)
when _T_868 :
node _T_869 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_23.io.enq.bits, _T_869
node _T_870 = eq(UInt<5>(0h18), idx_12)
when _T_870 :
node _T_871 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_24.io.enq.bits, _T_871
node _T_872 = eq(UInt<5>(0h19), idx_12)
when _T_872 :
node _T_873 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_25.io.enq.bits, _T_873
node _T_874 = eq(UInt<5>(0h1a), idx_12)
when _T_874 :
node _T_875 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_26.io.enq.bits, _T_875
node _T_876 = eq(UInt<5>(0h1b), idx_12)
when _T_876 :
node _T_877 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_27.io.enq.bits, _T_877
node _T_878 = eq(UInt<5>(0h1c), idx_12)
when _T_878 :
node _T_879 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_28.io.enq.bits, _T_879
node _T_880 = eq(UInt<5>(0h1d), idx_12)
when _T_880 :
node _T_881 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_29.io.enq.bits, _T_881
node _T_882 = eq(UInt<5>(0h1e), idx_12)
when _T_882 :
node _T_883 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_30.io.enq.bits, _T_883
node _T_884 = eq(UInt<5>(0h1f), idx_12)
when _T_884 :
node _T_885 = shr(memresp_bits_shifted, 96)
connect Queue64_UInt8_31.io.enq.bits, _T_885
node _idx_T_13 = add(write_start_index, UInt<4>(0hd))
node idx_13 = rem(_idx_T_13, UInt<6>(0h20))
node _T_886 = eq(UInt<1>(0h0), idx_13)
when _T_886 :
node _T_887 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8.io.enq.bits, _T_887
node _T_888 = eq(UInt<1>(0h1), idx_13)
when _T_888 :
node _T_889 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_1.io.enq.bits, _T_889
node _T_890 = eq(UInt<2>(0h2), idx_13)
when _T_890 :
node _T_891 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_2.io.enq.bits, _T_891
node _T_892 = eq(UInt<2>(0h3), idx_13)
when _T_892 :
node _T_893 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_3.io.enq.bits, _T_893
node _T_894 = eq(UInt<3>(0h4), idx_13)
when _T_894 :
node _T_895 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_4.io.enq.bits, _T_895
node _T_896 = eq(UInt<3>(0h5), idx_13)
when _T_896 :
node _T_897 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_5.io.enq.bits, _T_897
node _T_898 = eq(UInt<3>(0h6), idx_13)
when _T_898 :
node _T_899 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_6.io.enq.bits, _T_899
node _T_900 = eq(UInt<3>(0h7), idx_13)
when _T_900 :
node _T_901 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_7.io.enq.bits, _T_901
node _T_902 = eq(UInt<4>(0h8), idx_13)
when _T_902 :
node _T_903 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_8.io.enq.bits, _T_903
node _T_904 = eq(UInt<4>(0h9), idx_13)
when _T_904 :
node _T_905 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_9.io.enq.bits, _T_905
node _T_906 = eq(UInt<4>(0ha), idx_13)
when _T_906 :
node _T_907 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_10.io.enq.bits, _T_907
node _T_908 = eq(UInt<4>(0hb), idx_13)
when _T_908 :
node _T_909 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_11.io.enq.bits, _T_909
node _T_910 = eq(UInt<4>(0hc), idx_13)
when _T_910 :
node _T_911 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_12.io.enq.bits, _T_911
node _T_912 = eq(UInt<4>(0hd), idx_13)
when _T_912 :
node _T_913 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_13.io.enq.bits, _T_913
node _T_914 = eq(UInt<4>(0he), idx_13)
when _T_914 :
node _T_915 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_14.io.enq.bits, _T_915
node _T_916 = eq(UInt<4>(0hf), idx_13)
when _T_916 :
node _T_917 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_15.io.enq.bits, _T_917
node _T_918 = eq(UInt<5>(0h10), idx_13)
when _T_918 :
node _T_919 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_16.io.enq.bits, _T_919
node _T_920 = eq(UInt<5>(0h11), idx_13)
when _T_920 :
node _T_921 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_17.io.enq.bits, _T_921
node _T_922 = eq(UInt<5>(0h12), idx_13)
when _T_922 :
node _T_923 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_18.io.enq.bits, _T_923
node _T_924 = eq(UInt<5>(0h13), idx_13)
when _T_924 :
node _T_925 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_19.io.enq.bits, _T_925
node _T_926 = eq(UInt<5>(0h14), idx_13)
when _T_926 :
node _T_927 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_20.io.enq.bits, _T_927
node _T_928 = eq(UInt<5>(0h15), idx_13)
when _T_928 :
node _T_929 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_21.io.enq.bits, _T_929
node _T_930 = eq(UInt<5>(0h16), idx_13)
when _T_930 :
node _T_931 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_22.io.enq.bits, _T_931
node _T_932 = eq(UInt<5>(0h17), idx_13)
when _T_932 :
node _T_933 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_23.io.enq.bits, _T_933
node _T_934 = eq(UInt<5>(0h18), idx_13)
when _T_934 :
node _T_935 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_24.io.enq.bits, _T_935
node _T_936 = eq(UInt<5>(0h19), idx_13)
when _T_936 :
node _T_937 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_25.io.enq.bits, _T_937
node _T_938 = eq(UInt<5>(0h1a), idx_13)
when _T_938 :
node _T_939 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_26.io.enq.bits, _T_939
node _T_940 = eq(UInt<5>(0h1b), idx_13)
when _T_940 :
node _T_941 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_27.io.enq.bits, _T_941
node _T_942 = eq(UInt<5>(0h1c), idx_13)
when _T_942 :
node _T_943 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_28.io.enq.bits, _T_943
node _T_944 = eq(UInt<5>(0h1d), idx_13)
when _T_944 :
node _T_945 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_29.io.enq.bits, _T_945
node _T_946 = eq(UInt<5>(0h1e), idx_13)
when _T_946 :
node _T_947 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_30.io.enq.bits, _T_947
node _T_948 = eq(UInt<5>(0h1f), idx_13)
when _T_948 :
node _T_949 = shr(memresp_bits_shifted, 104)
connect Queue64_UInt8_31.io.enq.bits, _T_949
node _idx_T_14 = add(write_start_index, UInt<4>(0he))
node idx_14 = rem(_idx_T_14, UInt<6>(0h20))
node _T_950 = eq(UInt<1>(0h0), idx_14)
when _T_950 :
node _T_951 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8.io.enq.bits, _T_951
node _T_952 = eq(UInt<1>(0h1), idx_14)
when _T_952 :
node _T_953 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_1.io.enq.bits, _T_953
node _T_954 = eq(UInt<2>(0h2), idx_14)
when _T_954 :
node _T_955 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_2.io.enq.bits, _T_955
node _T_956 = eq(UInt<2>(0h3), idx_14)
when _T_956 :
node _T_957 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_3.io.enq.bits, _T_957
node _T_958 = eq(UInt<3>(0h4), idx_14)
when _T_958 :
node _T_959 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_4.io.enq.bits, _T_959
node _T_960 = eq(UInt<3>(0h5), idx_14)
when _T_960 :
node _T_961 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_5.io.enq.bits, _T_961
node _T_962 = eq(UInt<3>(0h6), idx_14)
when _T_962 :
node _T_963 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_6.io.enq.bits, _T_963
node _T_964 = eq(UInt<3>(0h7), idx_14)
when _T_964 :
node _T_965 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_7.io.enq.bits, _T_965
node _T_966 = eq(UInt<4>(0h8), idx_14)
when _T_966 :
node _T_967 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_8.io.enq.bits, _T_967
node _T_968 = eq(UInt<4>(0h9), idx_14)
when _T_968 :
node _T_969 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_9.io.enq.bits, _T_969
node _T_970 = eq(UInt<4>(0ha), idx_14)
when _T_970 :
node _T_971 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_10.io.enq.bits, _T_971
node _T_972 = eq(UInt<4>(0hb), idx_14)
when _T_972 :
node _T_973 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_11.io.enq.bits, _T_973
node _T_974 = eq(UInt<4>(0hc), idx_14)
when _T_974 :
node _T_975 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_12.io.enq.bits, _T_975
node _T_976 = eq(UInt<4>(0hd), idx_14)
when _T_976 :
node _T_977 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_13.io.enq.bits, _T_977
node _T_978 = eq(UInt<4>(0he), idx_14)
when _T_978 :
node _T_979 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_14.io.enq.bits, _T_979
node _T_980 = eq(UInt<4>(0hf), idx_14)
when _T_980 :
node _T_981 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_15.io.enq.bits, _T_981
node _T_982 = eq(UInt<5>(0h10), idx_14)
when _T_982 :
node _T_983 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_16.io.enq.bits, _T_983
node _T_984 = eq(UInt<5>(0h11), idx_14)
when _T_984 :
node _T_985 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_17.io.enq.bits, _T_985
node _T_986 = eq(UInt<5>(0h12), idx_14)
when _T_986 :
node _T_987 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_18.io.enq.bits, _T_987
node _T_988 = eq(UInt<5>(0h13), idx_14)
when _T_988 :
node _T_989 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_19.io.enq.bits, _T_989
node _T_990 = eq(UInt<5>(0h14), idx_14)
when _T_990 :
node _T_991 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_20.io.enq.bits, _T_991
node _T_992 = eq(UInt<5>(0h15), idx_14)
when _T_992 :
node _T_993 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_21.io.enq.bits, _T_993
node _T_994 = eq(UInt<5>(0h16), idx_14)
when _T_994 :
node _T_995 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_22.io.enq.bits, _T_995
node _T_996 = eq(UInt<5>(0h17), idx_14)
when _T_996 :
node _T_997 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_23.io.enq.bits, _T_997
node _T_998 = eq(UInt<5>(0h18), idx_14)
when _T_998 :
node _T_999 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_24.io.enq.bits, _T_999
node _T_1000 = eq(UInt<5>(0h19), idx_14)
when _T_1000 :
node _T_1001 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_25.io.enq.bits, _T_1001
node _T_1002 = eq(UInt<5>(0h1a), idx_14)
when _T_1002 :
node _T_1003 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_26.io.enq.bits, _T_1003
node _T_1004 = eq(UInt<5>(0h1b), idx_14)
when _T_1004 :
node _T_1005 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_27.io.enq.bits, _T_1005
node _T_1006 = eq(UInt<5>(0h1c), idx_14)
when _T_1006 :
node _T_1007 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_28.io.enq.bits, _T_1007
node _T_1008 = eq(UInt<5>(0h1d), idx_14)
when _T_1008 :
node _T_1009 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_29.io.enq.bits, _T_1009
node _T_1010 = eq(UInt<5>(0h1e), idx_14)
when _T_1010 :
node _T_1011 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_30.io.enq.bits, _T_1011
node _T_1012 = eq(UInt<5>(0h1f), idx_14)
when _T_1012 :
node _T_1013 = shr(memresp_bits_shifted, 112)
connect Queue64_UInt8_31.io.enq.bits, _T_1013
node _idx_T_15 = add(write_start_index, UInt<4>(0hf))
node idx_15 = rem(_idx_T_15, UInt<6>(0h20))
node _T_1014 = eq(UInt<1>(0h0), idx_15)
when _T_1014 :
node _T_1015 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8.io.enq.bits, _T_1015
node _T_1016 = eq(UInt<1>(0h1), idx_15)
when _T_1016 :
node _T_1017 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_1.io.enq.bits, _T_1017
node _T_1018 = eq(UInt<2>(0h2), idx_15)
when _T_1018 :
node _T_1019 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_2.io.enq.bits, _T_1019
node _T_1020 = eq(UInt<2>(0h3), idx_15)
when _T_1020 :
node _T_1021 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_3.io.enq.bits, _T_1021
node _T_1022 = eq(UInt<3>(0h4), idx_15)
when _T_1022 :
node _T_1023 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_4.io.enq.bits, _T_1023
node _T_1024 = eq(UInt<3>(0h5), idx_15)
when _T_1024 :
node _T_1025 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_5.io.enq.bits, _T_1025
node _T_1026 = eq(UInt<3>(0h6), idx_15)
when _T_1026 :
node _T_1027 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_6.io.enq.bits, _T_1027
node _T_1028 = eq(UInt<3>(0h7), idx_15)
when _T_1028 :
node _T_1029 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_7.io.enq.bits, _T_1029
node _T_1030 = eq(UInt<4>(0h8), idx_15)
when _T_1030 :
node _T_1031 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_8.io.enq.bits, _T_1031
node _T_1032 = eq(UInt<4>(0h9), idx_15)
when _T_1032 :
node _T_1033 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_9.io.enq.bits, _T_1033
node _T_1034 = eq(UInt<4>(0ha), idx_15)
when _T_1034 :
node _T_1035 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_10.io.enq.bits, _T_1035
node _T_1036 = eq(UInt<4>(0hb), idx_15)
when _T_1036 :
node _T_1037 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_11.io.enq.bits, _T_1037
node _T_1038 = eq(UInt<4>(0hc), idx_15)
when _T_1038 :
node _T_1039 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_12.io.enq.bits, _T_1039
node _T_1040 = eq(UInt<4>(0hd), idx_15)
when _T_1040 :
node _T_1041 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_13.io.enq.bits, _T_1041
node _T_1042 = eq(UInt<4>(0he), idx_15)
when _T_1042 :
node _T_1043 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_14.io.enq.bits, _T_1043
node _T_1044 = eq(UInt<4>(0hf), idx_15)
when _T_1044 :
node _T_1045 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_15.io.enq.bits, _T_1045
node _T_1046 = eq(UInt<5>(0h10), idx_15)
when _T_1046 :
node _T_1047 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_16.io.enq.bits, _T_1047
node _T_1048 = eq(UInt<5>(0h11), idx_15)
when _T_1048 :
node _T_1049 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_17.io.enq.bits, _T_1049
node _T_1050 = eq(UInt<5>(0h12), idx_15)
when _T_1050 :
node _T_1051 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_18.io.enq.bits, _T_1051
node _T_1052 = eq(UInt<5>(0h13), idx_15)
when _T_1052 :
node _T_1053 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_19.io.enq.bits, _T_1053
node _T_1054 = eq(UInt<5>(0h14), idx_15)
when _T_1054 :
node _T_1055 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_20.io.enq.bits, _T_1055
node _T_1056 = eq(UInt<5>(0h15), idx_15)
when _T_1056 :
node _T_1057 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_21.io.enq.bits, _T_1057
node _T_1058 = eq(UInt<5>(0h16), idx_15)
when _T_1058 :
node _T_1059 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_22.io.enq.bits, _T_1059
node _T_1060 = eq(UInt<5>(0h17), idx_15)
when _T_1060 :
node _T_1061 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_23.io.enq.bits, _T_1061
node _T_1062 = eq(UInt<5>(0h18), idx_15)
when _T_1062 :
node _T_1063 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_24.io.enq.bits, _T_1063
node _T_1064 = eq(UInt<5>(0h19), idx_15)
when _T_1064 :
node _T_1065 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_25.io.enq.bits, _T_1065
node _T_1066 = eq(UInt<5>(0h1a), idx_15)
when _T_1066 :
node _T_1067 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_26.io.enq.bits, _T_1067
node _T_1068 = eq(UInt<5>(0h1b), idx_15)
when _T_1068 :
node _T_1069 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_27.io.enq.bits, _T_1069
node _T_1070 = eq(UInt<5>(0h1c), idx_15)
when _T_1070 :
node _T_1071 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_28.io.enq.bits, _T_1071
node _T_1072 = eq(UInt<5>(0h1d), idx_15)
when _T_1072 :
node _T_1073 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_29.io.enq.bits, _T_1073
node _T_1074 = eq(UInt<5>(0h1e), idx_15)
when _T_1074 :
node _T_1075 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_30.io.enq.bits, _T_1075
node _T_1076 = eq(UInt<5>(0h1f), idx_15)
when _T_1076 :
node _T_1077 = shr(memresp_bits_shifted, 120)
connect Queue64_UInt8_31.io.enq.bits, _T_1077
node _idx_T_16 = add(write_start_index, UInt<5>(0h10))
node idx_16 = rem(_idx_T_16, UInt<6>(0h20))
node _T_1078 = eq(UInt<1>(0h0), idx_16)
when _T_1078 :
node _T_1079 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8.io.enq.bits, _T_1079
node _T_1080 = eq(UInt<1>(0h1), idx_16)
when _T_1080 :
node _T_1081 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_1.io.enq.bits, _T_1081
node _T_1082 = eq(UInt<2>(0h2), idx_16)
when _T_1082 :
node _T_1083 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_2.io.enq.bits, _T_1083
node _T_1084 = eq(UInt<2>(0h3), idx_16)
when _T_1084 :
node _T_1085 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_3.io.enq.bits, _T_1085
node _T_1086 = eq(UInt<3>(0h4), idx_16)
when _T_1086 :
node _T_1087 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_4.io.enq.bits, _T_1087
node _T_1088 = eq(UInt<3>(0h5), idx_16)
when _T_1088 :
node _T_1089 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_5.io.enq.bits, _T_1089
node _T_1090 = eq(UInt<3>(0h6), idx_16)
when _T_1090 :
node _T_1091 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_6.io.enq.bits, _T_1091
node _T_1092 = eq(UInt<3>(0h7), idx_16)
when _T_1092 :
node _T_1093 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_7.io.enq.bits, _T_1093
node _T_1094 = eq(UInt<4>(0h8), idx_16)
when _T_1094 :
node _T_1095 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_8.io.enq.bits, _T_1095
node _T_1096 = eq(UInt<4>(0h9), idx_16)
when _T_1096 :
node _T_1097 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_9.io.enq.bits, _T_1097
node _T_1098 = eq(UInt<4>(0ha), idx_16)
when _T_1098 :
node _T_1099 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_10.io.enq.bits, _T_1099
node _T_1100 = eq(UInt<4>(0hb), idx_16)
when _T_1100 :
node _T_1101 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_11.io.enq.bits, _T_1101
node _T_1102 = eq(UInt<4>(0hc), idx_16)
when _T_1102 :
node _T_1103 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_12.io.enq.bits, _T_1103
node _T_1104 = eq(UInt<4>(0hd), idx_16)
when _T_1104 :
node _T_1105 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_13.io.enq.bits, _T_1105
node _T_1106 = eq(UInt<4>(0he), idx_16)
when _T_1106 :
node _T_1107 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_14.io.enq.bits, _T_1107
node _T_1108 = eq(UInt<4>(0hf), idx_16)
when _T_1108 :
node _T_1109 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_15.io.enq.bits, _T_1109
node _T_1110 = eq(UInt<5>(0h10), idx_16)
when _T_1110 :
node _T_1111 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_16.io.enq.bits, _T_1111
node _T_1112 = eq(UInt<5>(0h11), idx_16)
when _T_1112 :
node _T_1113 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_17.io.enq.bits, _T_1113
node _T_1114 = eq(UInt<5>(0h12), idx_16)
when _T_1114 :
node _T_1115 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_18.io.enq.bits, _T_1115
node _T_1116 = eq(UInt<5>(0h13), idx_16)
when _T_1116 :
node _T_1117 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_19.io.enq.bits, _T_1117
node _T_1118 = eq(UInt<5>(0h14), idx_16)
when _T_1118 :
node _T_1119 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_20.io.enq.bits, _T_1119
node _T_1120 = eq(UInt<5>(0h15), idx_16)
when _T_1120 :
node _T_1121 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_21.io.enq.bits, _T_1121
node _T_1122 = eq(UInt<5>(0h16), idx_16)
when _T_1122 :
node _T_1123 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_22.io.enq.bits, _T_1123
node _T_1124 = eq(UInt<5>(0h17), idx_16)
when _T_1124 :
node _T_1125 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_23.io.enq.bits, _T_1125
node _T_1126 = eq(UInt<5>(0h18), idx_16)
when _T_1126 :
node _T_1127 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_24.io.enq.bits, _T_1127
node _T_1128 = eq(UInt<5>(0h19), idx_16)
when _T_1128 :
node _T_1129 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_25.io.enq.bits, _T_1129
node _T_1130 = eq(UInt<5>(0h1a), idx_16)
when _T_1130 :
node _T_1131 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_26.io.enq.bits, _T_1131
node _T_1132 = eq(UInt<5>(0h1b), idx_16)
when _T_1132 :
node _T_1133 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_27.io.enq.bits, _T_1133
node _T_1134 = eq(UInt<5>(0h1c), idx_16)
when _T_1134 :
node _T_1135 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_28.io.enq.bits, _T_1135
node _T_1136 = eq(UInt<5>(0h1d), idx_16)
when _T_1136 :
node _T_1137 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_29.io.enq.bits, _T_1137
node _T_1138 = eq(UInt<5>(0h1e), idx_16)
when _T_1138 :
node _T_1139 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_30.io.enq.bits, _T_1139
node _T_1140 = eq(UInt<5>(0h1f), idx_16)
when _T_1140 :
node _T_1141 = shr(memresp_bits_shifted, 128)
connect Queue64_UInt8_31.io.enq.bits, _T_1141
node _idx_T_17 = add(write_start_index, UInt<5>(0h11))
node idx_17 = rem(_idx_T_17, UInt<6>(0h20))
node _T_1142 = eq(UInt<1>(0h0), idx_17)
when _T_1142 :
node _T_1143 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8.io.enq.bits, _T_1143
node _T_1144 = eq(UInt<1>(0h1), idx_17)
when _T_1144 :
node _T_1145 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_1.io.enq.bits, _T_1145
node _T_1146 = eq(UInt<2>(0h2), idx_17)
when _T_1146 :
node _T_1147 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_2.io.enq.bits, _T_1147
node _T_1148 = eq(UInt<2>(0h3), idx_17)
when _T_1148 :
node _T_1149 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_3.io.enq.bits, _T_1149
node _T_1150 = eq(UInt<3>(0h4), idx_17)
when _T_1150 :
node _T_1151 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_4.io.enq.bits, _T_1151
node _T_1152 = eq(UInt<3>(0h5), idx_17)
when _T_1152 :
node _T_1153 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_5.io.enq.bits, _T_1153
node _T_1154 = eq(UInt<3>(0h6), idx_17)
when _T_1154 :
node _T_1155 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_6.io.enq.bits, _T_1155
node _T_1156 = eq(UInt<3>(0h7), idx_17)
when _T_1156 :
node _T_1157 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_7.io.enq.bits, _T_1157
node _T_1158 = eq(UInt<4>(0h8), idx_17)
when _T_1158 :
node _T_1159 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_8.io.enq.bits, _T_1159
node _T_1160 = eq(UInt<4>(0h9), idx_17)
when _T_1160 :
node _T_1161 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_9.io.enq.bits, _T_1161
node _T_1162 = eq(UInt<4>(0ha), idx_17)
when _T_1162 :
node _T_1163 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_10.io.enq.bits, _T_1163
node _T_1164 = eq(UInt<4>(0hb), idx_17)
when _T_1164 :
node _T_1165 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_11.io.enq.bits, _T_1165
node _T_1166 = eq(UInt<4>(0hc), idx_17)
when _T_1166 :
node _T_1167 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_12.io.enq.bits, _T_1167
node _T_1168 = eq(UInt<4>(0hd), idx_17)
when _T_1168 :
node _T_1169 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_13.io.enq.bits, _T_1169
node _T_1170 = eq(UInt<4>(0he), idx_17)
when _T_1170 :
node _T_1171 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_14.io.enq.bits, _T_1171
node _T_1172 = eq(UInt<4>(0hf), idx_17)
when _T_1172 :
node _T_1173 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_15.io.enq.bits, _T_1173
node _T_1174 = eq(UInt<5>(0h10), idx_17)
when _T_1174 :
node _T_1175 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_16.io.enq.bits, _T_1175
node _T_1176 = eq(UInt<5>(0h11), idx_17)
when _T_1176 :
node _T_1177 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_17.io.enq.bits, _T_1177
node _T_1178 = eq(UInt<5>(0h12), idx_17)
when _T_1178 :
node _T_1179 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_18.io.enq.bits, _T_1179
node _T_1180 = eq(UInt<5>(0h13), idx_17)
when _T_1180 :
node _T_1181 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_19.io.enq.bits, _T_1181
node _T_1182 = eq(UInt<5>(0h14), idx_17)
when _T_1182 :
node _T_1183 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_20.io.enq.bits, _T_1183
node _T_1184 = eq(UInt<5>(0h15), idx_17)
when _T_1184 :
node _T_1185 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_21.io.enq.bits, _T_1185
node _T_1186 = eq(UInt<5>(0h16), idx_17)
when _T_1186 :
node _T_1187 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_22.io.enq.bits, _T_1187
node _T_1188 = eq(UInt<5>(0h17), idx_17)
when _T_1188 :
node _T_1189 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_23.io.enq.bits, _T_1189
node _T_1190 = eq(UInt<5>(0h18), idx_17)
when _T_1190 :
node _T_1191 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_24.io.enq.bits, _T_1191
node _T_1192 = eq(UInt<5>(0h19), idx_17)
when _T_1192 :
node _T_1193 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_25.io.enq.bits, _T_1193
node _T_1194 = eq(UInt<5>(0h1a), idx_17)
when _T_1194 :
node _T_1195 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_26.io.enq.bits, _T_1195
node _T_1196 = eq(UInt<5>(0h1b), idx_17)
when _T_1196 :
node _T_1197 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_27.io.enq.bits, _T_1197
node _T_1198 = eq(UInt<5>(0h1c), idx_17)
when _T_1198 :
node _T_1199 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_28.io.enq.bits, _T_1199
node _T_1200 = eq(UInt<5>(0h1d), idx_17)
when _T_1200 :
node _T_1201 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_29.io.enq.bits, _T_1201
node _T_1202 = eq(UInt<5>(0h1e), idx_17)
when _T_1202 :
node _T_1203 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_30.io.enq.bits, _T_1203
node _T_1204 = eq(UInt<5>(0h1f), idx_17)
when _T_1204 :
node _T_1205 = shr(memresp_bits_shifted, 136)
connect Queue64_UInt8_31.io.enq.bits, _T_1205
node _idx_T_18 = add(write_start_index, UInt<5>(0h12))
node idx_18 = rem(_idx_T_18, UInt<6>(0h20))
node _T_1206 = eq(UInt<1>(0h0), idx_18)
when _T_1206 :
node _T_1207 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8.io.enq.bits, _T_1207
node _T_1208 = eq(UInt<1>(0h1), idx_18)
when _T_1208 :
node _T_1209 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_1.io.enq.bits, _T_1209
node _T_1210 = eq(UInt<2>(0h2), idx_18)
when _T_1210 :
node _T_1211 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_2.io.enq.bits, _T_1211
node _T_1212 = eq(UInt<2>(0h3), idx_18)
when _T_1212 :
node _T_1213 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_3.io.enq.bits, _T_1213
node _T_1214 = eq(UInt<3>(0h4), idx_18)
when _T_1214 :
node _T_1215 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_4.io.enq.bits, _T_1215
node _T_1216 = eq(UInt<3>(0h5), idx_18)
when _T_1216 :
node _T_1217 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_5.io.enq.bits, _T_1217
node _T_1218 = eq(UInt<3>(0h6), idx_18)
when _T_1218 :
node _T_1219 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_6.io.enq.bits, _T_1219
node _T_1220 = eq(UInt<3>(0h7), idx_18)
when _T_1220 :
node _T_1221 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_7.io.enq.bits, _T_1221
node _T_1222 = eq(UInt<4>(0h8), idx_18)
when _T_1222 :
node _T_1223 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_8.io.enq.bits, _T_1223
node _T_1224 = eq(UInt<4>(0h9), idx_18)
when _T_1224 :
node _T_1225 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_9.io.enq.bits, _T_1225
node _T_1226 = eq(UInt<4>(0ha), idx_18)
when _T_1226 :
node _T_1227 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_10.io.enq.bits, _T_1227
node _T_1228 = eq(UInt<4>(0hb), idx_18)
when _T_1228 :
node _T_1229 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_11.io.enq.bits, _T_1229
node _T_1230 = eq(UInt<4>(0hc), idx_18)
when _T_1230 :
node _T_1231 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_12.io.enq.bits, _T_1231
node _T_1232 = eq(UInt<4>(0hd), idx_18)
when _T_1232 :
node _T_1233 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_13.io.enq.bits, _T_1233
node _T_1234 = eq(UInt<4>(0he), idx_18)
when _T_1234 :
node _T_1235 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_14.io.enq.bits, _T_1235
node _T_1236 = eq(UInt<4>(0hf), idx_18)
when _T_1236 :
node _T_1237 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_15.io.enq.bits, _T_1237
node _T_1238 = eq(UInt<5>(0h10), idx_18)
when _T_1238 :
node _T_1239 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_16.io.enq.bits, _T_1239
node _T_1240 = eq(UInt<5>(0h11), idx_18)
when _T_1240 :
node _T_1241 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_17.io.enq.bits, _T_1241
node _T_1242 = eq(UInt<5>(0h12), idx_18)
when _T_1242 :
node _T_1243 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_18.io.enq.bits, _T_1243
node _T_1244 = eq(UInt<5>(0h13), idx_18)
when _T_1244 :
node _T_1245 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_19.io.enq.bits, _T_1245
node _T_1246 = eq(UInt<5>(0h14), idx_18)
when _T_1246 :
node _T_1247 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_20.io.enq.bits, _T_1247
node _T_1248 = eq(UInt<5>(0h15), idx_18)
when _T_1248 :
node _T_1249 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_21.io.enq.bits, _T_1249
node _T_1250 = eq(UInt<5>(0h16), idx_18)
when _T_1250 :
node _T_1251 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_22.io.enq.bits, _T_1251
node _T_1252 = eq(UInt<5>(0h17), idx_18)
when _T_1252 :
node _T_1253 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_23.io.enq.bits, _T_1253
node _T_1254 = eq(UInt<5>(0h18), idx_18)
when _T_1254 :
node _T_1255 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_24.io.enq.bits, _T_1255
node _T_1256 = eq(UInt<5>(0h19), idx_18)
when _T_1256 :
node _T_1257 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_25.io.enq.bits, _T_1257
node _T_1258 = eq(UInt<5>(0h1a), idx_18)
when _T_1258 :
node _T_1259 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_26.io.enq.bits, _T_1259
node _T_1260 = eq(UInt<5>(0h1b), idx_18)
when _T_1260 :
node _T_1261 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_27.io.enq.bits, _T_1261
node _T_1262 = eq(UInt<5>(0h1c), idx_18)
when _T_1262 :
node _T_1263 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_28.io.enq.bits, _T_1263
node _T_1264 = eq(UInt<5>(0h1d), idx_18)
when _T_1264 :
node _T_1265 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_29.io.enq.bits, _T_1265
node _T_1266 = eq(UInt<5>(0h1e), idx_18)
when _T_1266 :
node _T_1267 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_30.io.enq.bits, _T_1267
node _T_1268 = eq(UInt<5>(0h1f), idx_18)
when _T_1268 :
node _T_1269 = shr(memresp_bits_shifted, 144)
connect Queue64_UInt8_31.io.enq.bits, _T_1269
node _idx_T_19 = add(write_start_index, UInt<5>(0h13))
node idx_19 = rem(_idx_T_19, UInt<6>(0h20))
node _T_1270 = eq(UInt<1>(0h0), idx_19)
when _T_1270 :
node _T_1271 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8.io.enq.bits, _T_1271
node _T_1272 = eq(UInt<1>(0h1), idx_19)
when _T_1272 :
node _T_1273 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_1.io.enq.bits, _T_1273
node _T_1274 = eq(UInt<2>(0h2), idx_19)
when _T_1274 :
node _T_1275 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_2.io.enq.bits, _T_1275
node _T_1276 = eq(UInt<2>(0h3), idx_19)
when _T_1276 :
node _T_1277 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_3.io.enq.bits, _T_1277
node _T_1278 = eq(UInt<3>(0h4), idx_19)
when _T_1278 :
node _T_1279 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_4.io.enq.bits, _T_1279
node _T_1280 = eq(UInt<3>(0h5), idx_19)
when _T_1280 :
node _T_1281 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_5.io.enq.bits, _T_1281
node _T_1282 = eq(UInt<3>(0h6), idx_19)
when _T_1282 :
node _T_1283 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_6.io.enq.bits, _T_1283
node _T_1284 = eq(UInt<3>(0h7), idx_19)
when _T_1284 :
node _T_1285 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_7.io.enq.bits, _T_1285
node _T_1286 = eq(UInt<4>(0h8), idx_19)
when _T_1286 :
node _T_1287 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_8.io.enq.bits, _T_1287
node _T_1288 = eq(UInt<4>(0h9), idx_19)
when _T_1288 :
node _T_1289 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_9.io.enq.bits, _T_1289
node _T_1290 = eq(UInt<4>(0ha), idx_19)
when _T_1290 :
node _T_1291 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_10.io.enq.bits, _T_1291
node _T_1292 = eq(UInt<4>(0hb), idx_19)
when _T_1292 :
node _T_1293 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_11.io.enq.bits, _T_1293
node _T_1294 = eq(UInt<4>(0hc), idx_19)
when _T_1294 :
node _T_1295 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_12.io.enq.bits, _T_1295
node _T_1296 = eq(UInt<4>(0hd), idx_19)
when _T_1296 :
node _T_1297 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_13.io.enq.bits, _T_1297
node _T_1298 = eq(UInt<4>(0he), idx_19)
when _T_1298 :
node _T_1299 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_14.io.enq.bits, _T_1299
node _T_1300 = eq(UInt<4>(0hf), idx_19)
when _T_1300 :
node _T_1301 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_15.io.enq.bits, _T_1301
node _T_1302 = eq(UInt<5>(0h10), idx_19)
when _T_1302 :
node _T_1303 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_16.io.enq.bits, _T_1303
node _T_1304 = eq(UInt<5>(0h11), idx_19)
when _T_1304 :
node _T_1305 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_17.io.enq.bits, _T_1305
node _T_1306 = eq(UInt<5>(0h12), idx_19)
when _T_1306 :
node _T_1307 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_18.io.enq.bits, _T_1307
node _T_1308 = eq(UInt<5>(0h13), idx_19)
when _T_1308 :
node _T_1309 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_19.io.enq.bits, _T_1309
node _T_1310 = eq(UInt<5>(0h14), idx_19)
when _T_1310 :
node _T_1311 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_20.io.enq.bits, _T_1311
node _T_1312 = eq(UInt<5>(0h15), idx_19)
when _T_1312 :
node _T_1313 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_21.io.enq.bits, _T_1313
node _T_1314 = eq(UInt<5>(0h16), idx_19)
when _T_1314 :
node _T_1315 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_22.io.enq.bits, _T_1315
node _T_1316 = eq(UInt<5>(0h17), idx_19)
when _T_1316 :
node _T_1317 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_23.io.enq.bits, _T_1317
node _T_1318 = eq(UInt<5>(0h18), idx_19)
when _T_1318 :
node _T_1319 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_24.io.enq.bits, _T_1319
node _T_1320 = eq(UInt<5>(0h19), idx_19)
when _T_1320 :
node _T_1321 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_25.io.enq.bits, _T_1321
node _T_1322 = eq(UInt<5>(0h1a), idx_19)
when _T_1322 :
node _T_1323 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_26.io.enq.bits, _T_1323
node _T_1324 = eq(UInt<5>(0h1b), idx_19)
when _T_1324 :
node _T_1325 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_27.io.enq.bits, _T_1325
node _T_1326 = eq(UInt<5>(0h1c), idx_19)
when _T_1326 :
node _T_1327 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_28.io.enq.bits, _T_1327
node _T_1328 = eq(UInt<5>(0h1d), idx_19)
when _T_1328 :
node _T_1329 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_29.io.enq.bits, _T_1329
node _T_1330 = eq(UInt<5>(0h1e), idx_19)
when _T_1330 :
node _T_1331 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_30.io.enq.bits, _T_1331
node _T_1332 = eq(UInt<5>(0h1f), idx_19)
when _T_1332 :
node _T_1333 = shr(memresp_bits_shifted, 152)
connect Queue64_UInt8_31.io.enq.bits, _T_1333
node _idx_T_20 = add(write_start_index, UInt<5>(0h14))
node idx_20 = rem(_idx_T_20, UInt<6>(0h20))
node _T_1334 = eq(UInt<1>(0h0), idx_20)
when _T_1334 :
node _T_1335 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8.io.enq.bits, _T_1335
node _T_1336 = eq(UInt<1>(0h1), idx_20)
when _T_1336 :
node _T_1337 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_1.io.enq.bits, _T_1337
node _T_1338 = eq(UInt<2>(0h2), idx_20)
when _T_1338 :
node _T_1339 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_2.io.enq.bits, _T_1339
node _T_1340 = eq(UInt<2>(0h3), idx_20)
when _T_1340 :
node _T_1341 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_3.io.enq.bits, _T_1341
node _T_1342 = eq(UInt<3>(0h4), idx_20)
when _T_1342 :
node _T_1343 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_4.io.enq.bits, _T_1343
node _T_1344 = eq(UInt<3>(0h5), idx_20)
when _T_1344 :
node _T_1345 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_5.io.enq.bits, _T_1345
node _T_1346 = eq(UInt<3>(0h6), idx_20)
when _T_1346 :
node _T_1347 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_6.io.enq.bits, _T_1347
node _T_1348 = eq(UInt<3>(0h7), idx_20)
when _T_1348 :
node _T_1349 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_7.io.enq.bits, _T_1349
node _T_1350 = eq(UInt<4>(0h8), idx_20)
when _T_1350 :
node _T_1351 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_8.io.enq.bits, _T_1351
node _T_1352 = eq(UInt<4>(0h9), idx_20)
when _T_1352 :
node _T_1353 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_9.io.enq.bits, _T_1353
node _T_1354 = eq(UInt<4>(0ha), idx_20)
when _T_1354 :
node _T_1355 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_10.io.enq.bits, _T_1355
node _T_1356 = eq(UInt<4>(0hb), idx_20)
when _T_1356 :
node _T_1357 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_11.io.enq.bits, _T_1357
node _T_1358 = eq(UInt<4>(0hc), idx_20)
when _T_1358 :
node _T_1359 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_12.io.enq.bits, _T_1359
node _T_1360 = eq(UInt<4>(0hd), idx_20)
when _T_1360 :
node _T_1361 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_13.io.enq.bits, _T_1361
node _T_1362 = eq(UInt<4>(0he), idx_20)
when _T_1362 :
node _T_1363 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_14.io.enq.bits, _T_1363
node _T_1364 = eq(UInt<4>(0hf), idx_20)
when _T_1364 :
node _T_1365 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_15.io.enq.bits, _T_1365
node _T_1366 = eq(UInt<5>(0h10), idx_20)
when _T_1366 :
node _T_1367 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_16.io.enq.bits, _T_1367
node _T_1368 = eq(UInt<5>(0h11), idx_20)
when _T_1368 :
node _T_1369 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_17.io.enq.bits, _T_1369
node _T_1370 = eq(UInt<5>(0h12), idx_20)
when _T_1370 :
node _T_1371 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_18.io.enq.bits, _T_1371
node _T_1372 = eq(UInt<5>(0h13), idx_20)
when _T_1372 :
node _T_1373 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_19.io.enq.bits, _T_1373
node _T_1374 = eq(UInt<5>(0h14), idx_20)
when _T_1374 :
node _T_1375 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_20.io.enq.bits, _T_1375
node _T_1376 = eq(UInt<5>(0h15), idx_20)
when _T_1376 :
node _T_1377 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_21.io.enq.bits, _T_1377
node _T_1378 = eq(UInt<5>(0h16), idx_20)
when _T_1378 :
node _T_1379 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_22.io.enq.bits, _T_1379
node _T_1380 = eq(UInt<5>(0h17), idx_20)
when _T_1380 :
node _T_1381 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_23.io.enq.bits, _T_1381
node _T_1382 = eq(UInt<5>(0h18), idx_20)
when _T_1382 :
node _T_1383 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_24.io.enq.bits, _T_1383
node _T_1384 = eq(UInt<5>(0h19), idx_20)
when _T_1384 :
node _T_1385 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_25.io.enq.bits, _T_1385
node _T_1386 = eq(UInt<5>(0h1a), idx_20)
when _T_1386 :
node _T_1387 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_26.io.enq.bits, _T_1387
node _T_1388 = eq(UInt<5>(0h1b), idx_20)
when _T_1388 :
node _T_1389 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_27.io.enq.bits, _T_1389
node _T_1390 = eq(UInt<5>(0h1c), idx_20)
when _T_1390 :
node _T_1391 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_28.io.enq.bits, _T_1391
node _T_1392 = eq(UInt<5>(0h1d), idx_20)
when _T_1392 :
node _T_1393 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_29.io.enq.bits, _T_1393
node _T_1394 = eq(UInt<5>(0h1e), idx_20)
when _T_1394 :
node _T_1395 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_30.io.enq.bits, _T_1395
node _T_1396 = eq(UInt<5>(0h1f), idx_20)
when _T_1396 :
node _T_1397 = shr(memresp_bits_shifted, 160)
connect Queue64_UInt8_31.io.enq.bits, _T_1397
node _idx_T_21 = add(write_start_index, UInt<5>(0h15))
node idx_21 = rem(_idx_T_21, UInt<6>(0h20))
node _T_1398 = eq(UInt<1>(0h0), idx_21)
when _T_1398 :
node _T_1399 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8.io.enq.bits, _T_1399
node _T_1400 = eq(UInt<1>(0h1), idx_21)
when _T_1400 :
node _T_1401 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_1.io.enq.bits, _T_1401
node _T_1402 = eq(UInt<2>(0h2), idx_21)
when _T_1402 :
node _T_1403 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_2.io.enq.bits, _T_1403
node _T_1404 = eq(UInt<2>(0h3), idx_21)
when _T_1404 :
node _T_1405 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_3.io.enq.bits, _T_1405
node _T_1406 = eq(UInt<3>(0h4), idx_21)
when _T_1406 :
node _T_1407 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_4.io.enq.bits, _T_1407
node _T_1408 = eq(UInt<3>(0h5), idx_21)
when _T_1408 :
node _T_1409 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_5.io.enq.bits, _T_1409
node _T_1410 = eq(UInt<3>(0h6), idx_21)
when _T_1410 :
node _T_1411 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_6.io.enq.bits, _T_1411
node _T_1412 = eq(UInt<3>(0h7), idx_21)
when _T_1412 :
node _T_1413 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_7.io.enq.bits, _T_1413
node _T_1414 = eq(UInt<4>(0h8), idx_21)
when _T_1414 :
node _T_1415 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_8.io.enq.bits, _T_1415
node _T_1416 = eq(UInt<4>(0h9), idx_21)
when _T_1416 :
node _T_1417 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_9.io.enq.bits, _T_1417
node _T_1418 = eq(UInt<4>(0ha), idx_21)
when _T_1418 :
node _T_1419 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_10.io.enq.bits, _T_1419
node _T_1420 = eq(UInt<4>(0hb), idx_21)
when _T_1420 :
node _T_1421 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_11.io.enq.bits, _T_1421
node _T_1422 = eq(UInt<4>(0hc), idx_21)
when _T_1422 :
node _T_1423 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_12.io.enq.bits, _T_1423
node _T_1424 = eq(UInt<4>(0hd), idx_21)
when _T_1424 :
node _T_1425 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_13.io.enq.bits, _T_1425
node _T_1426 = eq(UInt<4>(0he), idx_21)
when _T_1426 :
node _T_1427 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_14.io.enq.bits, _T_1427
node _T_1428 = eq(UInt<4>(0hf), idx_21)
when _T_1428 :
node _T_1429 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_15.io.enq.bits, _T_1429
node _T_1430 = eq(UInt<5>(0h10), idx_21)
when _T_1430 :
node _T_1431 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_16.io.enq.bits, _T_1431
node _T_1432 = eq(UInt<5>(0h11), idx_21)
when _T_1432 :
node _T_1433 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_17.io.enq.bits, _T_1433
node _T_1434 = eq(UInt<5>(0h12), idx_21)
when _T_1434 :
node _T_1435 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_18.io.enq.bits, _T_1435
node _T_1436 = eq(UInt<5>(0h13), idx_21)
when _T_1436 :
node _T_1437 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_19.io.enq.bits, _T_1437
node _T_1438 = eq(UInt<5>(0h14), idx_21)
when _T_1438 :
node _T_1439 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_20.io.enq.bits, _T_1439
node _T_1440 = eq(UInt<5>(0h15), idx_21)
when _T_1440 :
node _T_1441 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_21.io.enq.bits, _T_1441
node _T_1442 = eq(UInt<5>(0h16), idx_21)
when _T_1442 :
node _T_1443 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_22.io.enq.bits, _T_1443
node _T_1444 = eq(UInt<5>(0h17), idx_21)
when _T_1444 :
node _T_1445 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_23.io.enq.bits, _T_1445
node _T_1446 = eq(UInt<5>(0h18), idx_21)
when _T_1446 :
node _T_1447 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_24.io.enq.bits, _T_1447
node _T_1448 = eq(UInt<5>(0h19), idx_21)
when _T_1448 :
node _T_1449 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_25.io.enq.bits, _T_1449
node _T_1450 = eq(UInt<5>(0h1a), idx_21)
when _T_1450 :
node _T_1451 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_26.io.enq.bits, _T_1451
node _T_1452 = eq(UInt<5>(0h1b), idx_21)
when _T_1452 :
node _T_1453 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_27.io.enq.bits, _T_1453
node _T_1454 = eq(UInt<5>(0h1c), idx_21)
when _T_1454 :
node _T_1455 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_28.io.enq.bits, _T_1455
node _T_1456 = eq(UInt<5>(0h1d), idx_21)
when _T_1456 :
node _T_1457 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_29.io.enq.bits, _T_1457
node _T_1458 = eq(UInt<5>(0h1e), idx_21)
when _T_1458 :
node _T_1459 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_30.io.enq.bits, _T_1459
node _T_1460 = eq(UInt<5>(0h1f), idx_21)
when _T_1460 :
node _T_1461 = shr(memresp_bits_shifted, 168)
connect Queue64_UInt8_31.io.enq.bits, _T_1461
node _idx_T_22 = add(write_start_index, UInt<5>(0h16))
node idx_22 = rem(_idx_T_22, UInt<6>(0h20))
node _T_1462 = eq(UInt<1>(0h0), idx_22)
when _T_1462 :
node _T_1463 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8.io.enq.bits, _T_1463
node _T_1464 = eq(UInt<1>(0h1), idx_22)
when _T_1464 :
node _T_1465 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_1.io.enq.bits, _T_1465
node _T_1466 = eq(UInt<2>(0h2), idx_22)
when _T_1466 :
node _T_1467 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_2.io.enq.bits, _T_1467
node _T_1468 = eq(UInt<2>(0h3), idx_22)
when _T_1468 :
node _T_1469 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_3.io.enq.bits, _T_1469
node _T_1470 = eq(UInt<3>(0h4), idx_22)
when _T_1470 :
node _T_1471 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_4.io.enq.bits, _T_1471
node _T_1472 = eq(UInt<3>(0h5), idx_22)
when _T_1472 :
node _T_1473 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_5.io.enq.bits, _T_1473
node _T_1474 = eq(UInt<3>(0h6), idx_22)
when _T_1474 :
node _T_1475 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_6.io.enq.bits, _T_1475
node _T_1476 = eq(UInt<3>(0h7), idx_22)
when _T_1476 :
node _T_1477 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_7.io.enq.bits, _T_1477
node _T_1478 = eq(UInt<4>(0h8), idx_22)
when _T_1478 :
node _T_1479 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_8.io.enq.bits, _T_1479
node _T_1480 = eq(UInt<4>(0h9), idx_22)
when _T_1480 :
node _T_1481 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_9.io.enq.bits, _T_1481
node _T_1482 = eq(UInt<4>(0ha), idx_22)
when _T_1482 :
node _T_1483 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_10.io.enq.bits, _T_1483
node _T_1484 = eq(UInt<4>(0hb), idx_22)
when _T_1484 :
node _T_1485 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_11.io.enq.bits, _T_1485
node _T_1486 = eq(UInt<4>(0hc), idx_22)
when _T_1486 :
node _T_1487 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_12.io.enq.bits, _T_1487
node _T_1488 = eq(UInt<4>(0hd), idx_22)
when _T_1488 :
node _T_1489 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_13.io.enq.bits, _T_1489
node _T_1490 = eq(UInt<4>(0he), idx_22)
when _T_1490 :
node _T_1491 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_14.io.enq.bits, _T_1491
node _T_1492 = eq(UInt<4>(0hf), idx_22)
when _T_1492 :
node _T_1493 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_15.io.enq.bits, _T_1493
node _T_1494 = eq(UInt<5>(0h10), idx_22)
when _T_1494 :
node _T_1495 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_16.io.enq.bits, _T_1495
node _T_1496 = eq(UInt<5>(0h11), idx_22)
when _T_1496 :
node _T_1497 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_17.io.enq.bits, _T_1497
node _T_1498 = eq(UInt<5>(0h12), idx_22)
when _T_1498 :
node _T_1499 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_18.io.enq.bits, _T_1499
node _T_1500 = eq(UInt<5>(0h13), idx_22)
when _T_1500 :
node _T_1501 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_19.io.enq.bits, _T_1501
node _T_1502 = eq(UInt<5>(0h14), idx_22)
when _T_1502 :
node _T_1503 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_20.io.enq.bits, _T_1503
node _T_1504 = eq(UInt<5>(0h15), idx_22)
when _T_1504 :
node _T_1505 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_21.io.enq.bits, _T_1505
node _T_1506 = eq(UInt<5>(0h16), idx_22)
when _T_1506 :
node _T_1507 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_22.io.enq.bits, _T_1507
node _T_1508 = eq(UInt<5>(0h17), idx_22)
when _T_1508 :
node _T_1509 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_23.io.enq.bits, _T_1509
node _T_1510 = eq(UInt<5>(0h18), idx_22)
when _T_1510 :
node _T_1511 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_24.io.enq.bits, _T_1511
node _T_1512 = eq(UInt<5>(0h19), idx_22)
when _T_1512 :
node _T_1513 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_25.io.enq.bits, _T_1513
node _T_1514 = eq(UInt<5>(0h1a), idx_22)
when _T_1514 :
node _T_1515 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_26.io.enq.bits, _T_1515
node _T_1516 = eq(UInt<5>(0h1b), idx_22)
when _T_1516 :
node _T_1517 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_27.io.enq.bits, _T_1517
node _T_1518 = eq(UInt<5>(0h1c), idx_22)
when _T_1518 :
node _T_1519 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_28.io.enq.bits, _T_1519
node _T_1520 = eq(UInt<5>(0h1d), idx_22)
when _T_1520 :
node _T_1521 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_29.io.enq.bits, _T_1521
node _T_1522 = eq(UInt<5>(0h1e), idx_22)
when _T_1522 :
node _T_1523 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_30.io.enq.bits, _T_1523
node _T_1524 = eq(UInt<5>(0h1f), idx_22)
when _T_1524 :
node _T_1525 = shr(memresp_bits_shifted, 176)
connect Queue64_UInt8_31.io.enq.bits, _T_1525
node _idx_T_23 = add(write_start_index, UInt<5>(0h17))
node idx_23 = rem(_idx_T_23, UInt<6>(0h20))
node _T_1526 = eq(UInt<1>(0h0), idx_23)
when _T_1526 :
node _T_1527 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8.io.enq.bits, _T_1527
node _T_1528 = eq(UInt<1>(0h1), idx_23)
when _T_1528 :
node _T_1529 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_1.io.enq.bits, _T_1529
node _T_1530 = eq(UInt<2>(0h2), idx_23)
when _T_1530 :
node _T_1531 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_2.io.enq.bits, _T_1531
node _T_1532 = eq(UInt<2>(0h3), idx_23)
when _T_1532 :
node _T_1533 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_3.io.enq.bits, _T_1533
node _T_1534 = eq(UInt<3>(0h4), idx_23)
when _T_1534 :
node _T_1535 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_4.io.enq.bits, _T_1535
node _T_1536 = eq(UInt<3>(0h5), idx_23)
when _T_1536 :
node _T_1537 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_5.io.enq.bits, _T_1537
node _T_1538 = eq(UInt<3>(0h6), idx_23)
when _T_1538 :
node _T_1539 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_6.io.enq.bits, _T_1539
node _T_1540 = eq(UInt<3>(0h7), idx_23)
when _T_1540 :
node _T_1541 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_7.io.enq.bits, _T_1541
node _T_1542 = eq(UInt<4>(0h8), idx_23)
when _T_1542 :
node _T_1543 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_8.io.enq.bits, _T_1543
node _T_1544 = eq(UInt<4>(0h9), idx_23)
when _T_1544 :
node _T_1545 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_9.io.enq.bits, _T_1545
node _T_1546 = eq(UInt<4>(0ha), idx_23)
when _T_1546 :
node _T_1547 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_10.io.enq.bits, _T_1547
node _T_1548 = eq(UInt<4>(0hb), idx_23)
when _T_1548 :
node _T_1549 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_11.io.enq.bits, _T_1549
node _T_1550 = eq(UInt<4>(0hc), idx_23)
when _T_1550 :
node _T_1551 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_12.io.enq.bits, _T_1551
node _T_1552 = eq(UInt<4>(0hd), idx_23)
when _T_1552 :
node _T_1553 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_13.io.enq.bits, _T_1553
node _T_1554 = eq(UInt<4>(0he), idx_23)
when _T_1554 :
node _T_1555 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_14.io.enq.bits, _T_1555
node _T_1556 = eq(UInt<4>(0hf), idx_23)
when _T_1556 :
node _T_1557 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_15.io.enq.bits, _T_1557
node _T_1558 = eq(UInt<5>(0h10), idx_23)
when _T_1558 :
node _T_1559 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_16.io.enq.bits, _T_1559
node _T_1560 = eq(UInt<5>(0h11), idx_23)
when _T_1560 :
node _T_1561 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_17.io.enq.bits, _T_1561
node _T_1562 = eq(UInt<5>(0h12), idx_23)
when _T_1562 :
node _T_1563 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_18.io.enq.bits, _T_1563
node _T_1564 = eq(UInt<5>(0h13), idx_23)
when _T_1564 :
node _T_1565 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_19.io.enq.bits, _T_1565
node _T_1566 = eq(UInt<5>(0h14), idx_23)
when _T_1566 :
node _T_1567 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_20.io.enq.bits, _T_1567
node _T_1568 = eq(UInt<5>(0h15), idx_23)
when _T_1568 :
node _T_1569 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_21.io.enq.bits, _T_1569
node _T_1570 = eq(UInt<5>(0h16), idx_23)
when _T_1570 :
node _T_1571 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_22.io.enq.bits, _T_1571
node _T_1572 = eq(UInt<5>(0h17), idx_23)
when _T_1572 :
node _T_1573 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_23.io.enq.bits, _T_1573
node _T_1574 = eq(UInt<5>(0h18), idx_23)
when _T_1574 :
node _T_1575 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_24.io.enq.bits, _T_1575
node _T_1576 = eq(UInt<5>(0h19), idx_23)
when _T_1576 :
node _T_1577 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_25.io.enq.bits, _T_1577
node _T_1578 = eq(UInt<5>(0h1a), idx_23)
when _T_1578 :
node _T_1579 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_26.io.enq.bits, _T_1579
node _T_1580 = eq(UInt<5>(0h1b), idx_23)
when _T_1580 :
node _T_1581 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_27.io.enq.bits, _T_1581
node _T_1582 = eq(UInt<5>(0h1c), idx_23)
when _T_1582 :
node _T_1583 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_28.io.enq.bits, _T_1583
node _T_1584 = eq(UInt<5>(0h1d), idx_23)
when _T_1584 :
node _T_1585 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_29.io.enq.bits, _T_1585
node _T_1586 = eq(UInt<5>(0h1e), idx_23)
when _T_1586 :
node _T_1587 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_30.io.enq.bits, _T_1587
node _T_1588 = eq(UInt<5>(0h1f), idx_23)
when _T_1588 :
node _T_1589 = shr(memresp_bits_shifted, 184)
connect Queue64_UInt8_31.io.enq.bits, _T_1589
node _idx_T_24 = add(write_start_index, UInt<5>(0h18))
node idx_24 = rem(_idx_T_24, UInt<6>(0h20))
node _T_1590 = eq(UInt<1>(0h0), idx_24)
when _T_1590 :
node _T_1591 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8.io.enq.bits, _T_1591
node _T_1592 = eq(UInt<1>(0h1), idx_24)
when _T_1592 :
node _T_1593 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_1.io.enq.bits, _T_1593
node _T_1594 = eq(UInt<2>(0h2), idx_24)
when _T_1594 :
node _T_1595 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_2.io.enq.bits, _T_1595
node _T_1596 = eq(UInt<2>(0h3), idx_24)
when _T_1596 :
node _T_1597 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_3.io.enq.bits, _T_1597
node _T_1598 = eq(UInt<3>(0h4), idx_24)
when _T_1598 :
node _T_1599 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_4.io.enq.bits, _T_1599
node _T_1600 = eq(UInt<3>(0h5), idx_24)
when _T_1600 :
node _T_1601 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_5.io.enq.bits, _T_1601
node _T_1602 = eq(UInt<3>(0h6), idx_24)
when _T_1602 :
node _T_1603 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_6.io.enq.bits, _T_1603
node _T_1604 = eq(UInt<3>(0h7), idx_24)
when _T_1604 :
node _T_1605 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_7.io.enq.bits, _T_1605
node _T_1606 = eq(UInt<4>(0h8), idx_24)
when _T_1606 :
node _T_1607 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_8.io.enq.bits, _T_1607
node _T_1608 = eq(UInt<4>(0h9), idx_24)
when _T_1608 :
node _T_1609 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_9.io.enq.bits, _T_1609
node _T_1610 = eq(UInt<4>(0ha), idx_24)
when _T_1610 :
node _T_1611 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_10.io.enq.bits, _T_1611
node _T_1612 = eq(UInt<4>(0hb), idx_24)
when _T_1612 :
node _T_1613 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_11.io.enq.bits, _T_1613
node _T_1614 = eq(UInt<4>(0hc), idx_24)
when _T_1614 :
node _T_1615 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_12.io.enq.bits, _T_1615
node _T_1616 = eq(UInt<4>(0hd), idx_24)
when _T_1616 :
node _T_1617 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_13.io.enq.bits, _T_1617
node _T_1618 = eq(UInt<4>(0he), idx_24)
when _T_1618 :
node _T_1619 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_14.io.enq.bits, _T_1619
node _T_1620 = eq(UInt<4>(0hf), idx_24)
when _T_1620 :
node _T_1621 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_15.io.enq.bits, _T_1621
node _T_1622 = eq(UInt<5>(0h10), idx_24)
when _T_1622 :
node _T_1623 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_16.io.enq.bits, _T_1623
node _T_1624 = eq(UInt<5>(0h11), idx_24)
when _T_1624 :
node _T_1625 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_17.io.enq.bits, _T_1625
node _T_1626 = eq(UInt<5>(0h12), idx_24)
when _T_1626 :
node _T_1627 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_18.io.enq.bits, _T_1627
node _T_1628 = eq(UInt<5>(0h13), idx_24)
when _T_1628 :
node _T_1629 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_19.io.enq.bits, _T_1629
node _T_1630 = eq(UInt<5>(0h14), idx_24)
when _T_1630 :
node _T_1631 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_20.io.enq.bits, _T_1631
node _T_1632 = eq(UInt<5>(0h15), idx_24)
when _T_1632 :
node _T_1633 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_21.io.enq.bits, _T_1633
node _T_1634 = eq(UInt<5>(0h16), idx_24)
when _T_1634 :
node _T_1635 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_22.io.enq.bits, _T_1635
node _T_1636 = eq(UInt<5>(0h17), idx_24)
when _T_1636 :
node _T_1637 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_23.io.enq.bits, _T_1637
node _T_1638 = eq(UInt<5>(0h18), idx_24)
when _T_1638 :
node _T_1639 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_24.io.enq.bits, _T_1639
node _T_1640 = eq(UInt<5>(0h19), idx_24)
when _T_1640 :
node _T_1641 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_25.io.enq.bits, _T_1641
node _T_1642 = eq(UInt<5>(0h1a), idx_24)
when _T_1642 :
node _T_1643 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_26.io.enq.bits, _T_1643
node _T_1644 = eq(UInt<5>(0h1b), idx_24)
when _T_1644 :
node _T_1645 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_27.io.enq.bits, _T_1645
node _T_1646 = eq(UInt<5>(0h1c), idx_24)
when _T_1646 :
node _T_1647 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_28.io.enq.bits, _T_1647
node _T_1648 = eq(UInt<5>(0h1d), idx_24)
when _T_1648 :
node _T_1649 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_29.io.enq.bits, _T_1649
node _T_1650 = eq(UInt<5>(0h1e), idx_24)
when _T_1650 :
node _T_1651 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_30.io.enq.bits, _T_1651
node _T_1652 = eq(UInt<5>(0h1f), idx_24)
when _T_1652 :
node _T_1653 = shr(memresp_bits_shifted, 192)
connect Queue64_UInt8_31.io.enq.bits, _T_1653
node _idx_T_25 = add(write_start_index, UInt<5>(0h19))
node idx_25 = rem(_idx_T_25, UInt<6>(0h20))
node _T_1654 = eq(UInt<1>(0h0), idx_25)
when _T_1654 :
node _T_1655 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8.io.enq.bits, _T_1655
node _T_1656 = eq(UInt<1>(0h1), idx_25)
when _T_1656 :
node _T_1657 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_1.io.enq.bits, _T_1657
node _T_1658 = eq(UInt<2>(0h2), idx_25)
when _T_1658 :
node _T_1659 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_2.io.enq.bits, _T_1659
node _T_1660 = eq(UInt<2>(0h3), idx_25)
when _T_1660 :
node _T_1661 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_3.io.enq.bits, _T_1661
node _T_1662 = eq(UInt<3>(0h4), idx_25)
when _T_1662 :
node _T_1663 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_4.io.enq.bits, _T_1663
node _T_1664 = eq(UInt<3>(0h5), idx_25)
when _T_1664 :
node _T_1665 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_5.io.enq.bits, _T_1665
node _T_1666 = eq(UInt<3>(0h6), idx_25)
when _T_1666 :
node _T_1667 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_6.io.enq.bits, _T_1667
node _T_1668 = eq(UInt<3>(0h7), idx_25)
when _T_1668 :
node _T_1669 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_7.io.enq.bits, _T_1669
node _T_1670 = eq(UInt<4>(0h8), idx_25)
when _T_1670 :
node _T_1671 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_8.io.enq.bits, _T_1671
node _T_1672 = eq(UInt<4>(0h9), idx_25)
when _T_1672 :
node _T_1673 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_9.io.enq.bits, _T_1673
node _T_1674 = eq(UInt<4>(0ha), idx_25)
when _T_1674 :
node _T_1675 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_10.io.enq.bits, _T_1675
node _T_1676 = eq(UInt<4>(0hb), idx_25)
when _T_1676 :
node _T_1677 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_11.io.enq.bits, _T_1677
node _T_1678 = eq(UInt<4>(0hc), idx_25)
when _T_1678 :
node _T_1679 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_12.io.enq.bits, _T_1679
node _T_1680 = eq(UInt<4>(0hd), idx_25)
when _T_1680 :
node _T_1681 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_13.io.enq.bits, _T_1681
node _T_1682 = eq(UInt<4>(0he), idx_25)
when _T_1682 :
node _T_1683 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_14.io.enq.bits, _T_1683
node _T_1684 = eq(UInt<4>(0hf), idx_25)
when _T_1684 :
node _T_1685 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_15.io.enq.bits, _T_1685
node _T_1686 = eq(UInt<5>(0h10), idx_25)
when _T_1686 :
node _T_1687 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_16.io.enq.bits, _T_1687
node _T_1688 = eq(UInt<5>(0h11), idx_25)
when _T_1688 :
node _T_1689 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_17.io.enq.bits, _T_1689
node _T_1690 = eq(UInt<5>(0h12), idx_25)
when _T_1690 :
node _T_1691 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_18.io.enq.bits, _T_1691
node _T_1692 = eq(UInt<5>(0h13), idx_25)
when _T_1692 :
node _T_1693 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_19.io.enq.bits, _T_1693
node _T_1694 = eq(UInt<5>(0h14), idx_25)
when _T_1694 :
node _T_1695 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_20.io.enq.bits, _T_1695
node _T_1696 = eq(UInt<5>(0h15), idx_25)
when _T_1696 :
node _T_1697 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_21.io.enq.bits, _T_1697
node _T_1698 = eq(UInt<5>(0h16), idx_25)
when _T_1698 :
node _T_1699 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_22.io.enq.bits, _T_1699
node _T_1700 = eq(UInt<5>(0h17), idx_25)
when _T_1700 :
node _T_1701 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_23.io.enq.bits, _T_1701
node _T_1702 = eq(UInt<5>(0h18), idx_25)
when _T_1702 :
node _T_1703 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_24.io.enq.bits, _T_1703
node _T_1704 = eq(UInt<5>(0h19), idx_25)
when _T_1704 :
node _T_1705 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_25.io.enq.bits, _T_1705
node _T_1706 = eq(UInt<5>(0h1a), idx_25)
when _T_1706 :
node _T_1707 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_26.io.enq.bits, _T_1707
node _T_1708 = eq(UInt<5>(0h1b), idx_25)
when _T_1708 :
node _T_1709 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_27.io.enq.bits, _T_1709
node _T_1710 = eq(UInt<5>(0h1c), idx_25)
when _T_1710 :
node _T_1711 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_28.io.enq.bits, _T_1711
node _T_1712 = eq(UInt<5>(0h1d), idx_25)
when _T_1712 :
node _T_1713 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_29.io.enq.bits, _T_1713
node _T_1714 = eq(UInt<5>(0h1e), idx_25)
when _T_1714 :
node _T_1715 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_30.io.enq.bits, _T_1715
node _T_1716 = eq(UInt<5>(0h1f), idx_25)
when _T_1716 :
node _T_1717 = shr(memresp_bits_shifted, 200)
connect Queue64_UInt8_31.io.enq.bits, _T_1717
node _idx_T_26 = add(write_start_index, UInt<5>(0h1a))
node idx_26 = rem(_idx_T_26, UInt<6>(0h20))
node _T_1718 = eq(UInt<1>(0h0), idx_26)
when _T_1718 :
node _T_1719 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8.io.enq.bits, _T_1719
node _T_1720 = eq(UInt<1>(0h1), idx_26)
when _T_1720 :
node _T_1721 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_1.io.enq.bits, _T_1721
node _T_1722 = eq(UInt<2>(0h2), idx_26)
when _T_1722 :
node _T_1723 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_2.io.enq.bits, _T_1723
node _T_1724 = eq(UInt<2>(0h3), idx_26)
when _T_1724 :
node _T_1725 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_3.io.enq.bits, _T_1725
node _T_1726 = eq(UInt<3>(0h4), idx_26)
when _T_1726 :
node _T_1727 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_4.io.enq.bits, _T_1727
node _T_1728 = eq(UInt<3>(0h5), idx_26)
when _T_1728 :
node _T_1729 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_5.io.enq.bits, _T_1729
node _T_1730 = eq(UInt<3>(0h6), idx_26)
when _T_1730 :
node _T_1731 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_6.io.enq.bits, _T_1731
node _T_1732 = eq(UInt<3>(0h7), idx_26)
when _T_1732 :
node _T_1733 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_7.io.enq.bits, _T_1733
node _T_1734 = eq(UInt<4>(0h8), idx_26)
when _T_1734 :
node _T_1735 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_8.io.enq.bits, _T_1735
node _T_1736 = eq(UInt<4>(0h9), idx_26)
when _T_1736 :
node _T_1737 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_9.io.enq.bits, _T_1737
node _T_1738 = eq(UInt<4>(0ha), idx_26)
when _T_1738 :
node _T_1739 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_10.io.enq.bits, _T_1739
node _T_1740 = eq(UInt<4>(0hb), idx_26)
when _T_1740 :
node _T_1741 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_11.io.enq.bits, _T_1741
node _T_1742 = eq(UInt<4>(0hc), idx_26)
when _T_1742 :
node _T_1743 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_12.io.enq.bits, _T_1743
node _T_1744 = eq(UInt<4>(0hd), idx_26)
when _T_1744 :
node _T_1745 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_13.io.enq.bits, _T_1745
node _T_1746 = eq(UInt<4>(0he), idx_26)
when _T_1746 :
node _T_1747 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_14.io.enq.bits, _T_1747
node _T_1748 = eq(UInt<4>(0hf), idx_26)
when _T_1748 :
node _T_1749 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_15.io.enq.bits, _T_1749
node _T_1750 = eq(UInt<5>(0h10), idx_26)
when _T_1750 :
node _T_1751 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_16.io.enq.bits, _T_1751
node _T_1752 = eq(UInt<5>(0h11), idx_26)
when _T_1752 :
node _T_1753 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_17.io.enq.bits, _T_1753
node _T_1754 = eq(UInt<5>(0h12), idx_26)
when _T_1754 :
node _T_1755 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_18.io.enq.bits, _T_1755
node _T_1756 = eq(UInt<5>(0h13), idx_26)
when _T_1756 :
node _T_1757 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_19.io.enq.bits, _T_1757
node _T_1758 = eq(UInt<5>(0h14), idx_26)
when _T_1758 :
node _T_1759 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_20.io.enq.bits, _T_1759
node _T_1760 = eq(UInt<5>(0h15), idx_26)
when _T_1760 :
node _T_1761 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_21.io.enq.bits, _T_1761
node _T_1762 = eq(UInt<5>(0h16), idx_26)
when _T_1762 :
node _T_1763 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_22.io.enq.bits, _T_1763
node _T_1764 = eq(UInt<5>(0h17), idx_26)
when _T_1764 :
node _T_1765 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_23.io.enq.bits, _T_1765
node _T_1766 = eq(UInt<5>(0h18), idx_26)
when _T_1766 :
node _T_1767 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_24.io.enq.bits, _T_1767
node _T_1768 = eq(UInt<5>(0h19), idx_26)
when _T_1768 :
node _T_1769 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_25.io.enq.bits, _T_1769
node _T_1770 = eq(UInt<5>(0h1a), idx_26)
when _T_1770 :
node _T_1771 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_26.io.enq.bits, _T_1771
node _T_1772 = eq(UInt<5>(0h1b), idx_26)
when _T_1772 :
node _T_1773 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_27.io.enq.bits, _T_1773
node _T_1774 = eq(UInt<5>(0h1c), idx_26)
when _T_1774 :
node _T_1775 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_28.io.enq.bits, _T_1775
node _T_1776 = eq(UInt<5>(0h1d), idx_26)
when _T_1776 :
node _T_1777 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_29.io.enq.bits, _T_1777
node _T_1778 = eq(UInt<5>(0h1e), idx_26)
when _T_1778 :
node _T_1779 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_30.io.enq.bits, _T_1779
node _T_1780 = eq(UInt<5>(0h1f), idx_26)
when _T_1780 :
node _T_1781 = shr(memresp_bits_shifted, 208)
connect Queue64_UInt8_31.io.enq.bits, _T_1781
node _idx_T_27 = add(write_start_index, UInt<5>(0h1b))
node idx_27 = rem(_idx_T_27, UInt<6>(0h20))
node _T_1782 = eq(UInt<1>(0h0), idx_27)
when _T_1782 :
node _T_1783 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8.io.enq.bits, _T_1783
node _T_1784 = eq(UInt<1>(0h1), idx_27)
when _T_1784 :
node _T_1785 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_1.io.enq.bits, _T_1785
node _T_1786 = eq(UInt<2>(0h2), idx_27)
when _T_1786 :
node _T_1787 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_2.io.enq.bits, _T_1787
node _T_1788 = eq(UInt<2>(0h3), idx_27)
when _T_1788 :
node _T_1789 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_3.io.enq.bits, _T_1789
node _T_1790 = eq(UInt<3>(0h4), idx_27)
when _T_1790 :
node _T_1791 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_4.io.enq.bits, _T_1791
node _T_1792 = eq(UInt<3>(0h5), idx_27)
when _T_1792 :
node _T_1793 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_5.io.enq.bits, _T_1793
node _T_1794 = eq(UInt<3>(0h6), idx_27)
when _T_1794 :
node _T_1795 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_6.io.enq.bits, _T_1795
node _T_1796 = eq(UInt<3>(0h7), idx_27)
when _T_1796 :
node _T_1797 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_7.io.enq.bits, _T_1797
node _T_1798 = eq(UInt<4>(0h8), idx_27)
when _T_1798 :
node _T_1799 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_8.io.enq.bits, _T_1799
node _T_1800 = eq(UInt<4>(0h9), idx_27)
when _T_1800 :
node _T_1801 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_9.io.enq.bits, _T_1801
node _T_1802 = eq(UInt<4>(0ha), idx_27)
when _T_1802 :
node _T_1803 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_10.io.enq.bits, _T_1803
node _T_1804 = eq(UInt<4>(0hb), idx_27)
when _T_1804 :
node _T_1805 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_11.io.enq.bits, _T_1805
node _T_1806 = eq(UInt<4>(0hc), idx_27)
when _T_1806 :
node _T_1807 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_12.io.enq.bits, _T_1807
node _T_1808 = eq(UInt<4>(0hd), idx_27)
when _T_1808 :
node _T_1809 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_13.io.enq.bits, _T_1809
node _T_1810 = eq(UInt<4>(0he), idx_27)
when _T_1810 :
node _T_1811 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_14.io.enq.bits, _T_1811
node _T_1812 = eq(UInt<4>(0hf), idx_27)
when _T_1812 :
node _T_1813 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_15.io.enq.bits, _T_1813
node _T_1814 = eq(UInt<5>(0h10), idx_27)
when _T_1814 :
node _T_1815 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_16.io.enq.bits, _T_1815
node _T_1816 = eq(UInt<5>(0h11), idx_27)
when _T_1816 :
node _T_1817 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_17.io.enq.bits, _T_1817
node _T_1818 = eq(UInt<5>(0h12), idx_27)
when _T_1818 :
node _T_1819 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_18.io.enq.bits, _T_1819
node _T_1820 = eq(UInt<5>(0h13), idx_27)
when _T_1820 :
node _T_1821 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_19.io.enq.bits, _T_1821
node _T_1822 = eq(UInt<5>(0h14), idx_27)
when _T_1822 :
node _T_1823 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_20.io.enq.bits, _T_1823
node _T_1824 = eq(UInt<5>(0h15), idx_27)
when _T_1824 :
node _T_1825 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_21.io.enq.bits, _T_1825
node _T_1826 = eq(UInt<5>(0h16), idx_27)
when _T_1826 :
node _T_1827 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_22.io.enq.bits, _T_1827
node _T_1828 = eq(UInt<5>(0h17), idx_27)
when _T_1828 :
node _T_1829 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_23.io.enq.bits, _T_1829
node _T_1830 = eq(UInt<5>(0h18), idx_27)
when _T_1830 :
node _T_1831 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_24.io.enq.bits, _T_1831
node _T_1832 = eq(UInt<5>(0h19), idx_27)
when _T_1832 :
node _T_1833 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_25.io.enq.bits, _T_1833
node _T_1834 = eq(UInt<5>(0h1a), idx_27)
when _T_1834 :
node _T_1835 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_26.io.enq.bits, _T_1835
node _T_1836 = eq(UInt<5>(0h1b), idx_27)
when _T_1836 :
node _T_1837 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_27.io.enq.bits, _T_1837
node _T_1838 = eq(UInt<5>(0h1c), idx_27)
when _T_1838 :
node _T_1839 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_28.io.enq.bits, _T_1839
node _T_1840 = eq(UInt<5>(0h1d), idx_27)
when _T_1840 :
node _T_1841 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_29.io.enq.bits, _T_1841
node _T_1842 = eq(UInt<5>(0h1e), idx_27)
when _T_1842 :
node _T_1843 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_30.io.enq.bits, _T_1843
node _T_1844 = eq(UInt<5>(0h1f), idx_27)
when _T_1844 :
node _T_1845 = shr(memresp_bits_shifted, 216)
connect Queue64_UInt8_31.io.enq.bits, _T_1845
node _idx_T_28 = add(write_start_index, UInt<5>(0h1c))
node idx_28 = rem(_idx_T_28, UInt<6>(0h20))
node _T_1846 = eq(UInt<1>(0h0), idx_28)
when _T_1846 :
node _T_1847 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8.io.enq.bits, _T_1847
node _T_1848 = eq(UInt<1>(0h1), idx_28)
when _T_1848 :
node _T_1849 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_1.io.enq.bits, _T_1849
node _T_1850 = eq(UInt<2>(0h2), idx_28)
when _T_1850 :
node _T_1851 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_2.io.enq.bits, _T_1851
node _T_1852 = eq(UInt<2>(0h3), idx_28)
when _T_1852 :
node _T_1853 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_3.io.enq.bits, _T_1853
node _T_1854 = eq(UInt<3>(0h4), idx_28)
when _T_1854 :
node _T_1855 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_4.io.enq.bits, _T_1855
node _T_1856 = eq(UInt<3>(0h5), idx_28)
when _T_1856 :
node _T_1857 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_5.io.enq.bits, _T_1857
node _T_1858 = eq(UInt<3>(0h6), idx_28)
when _T_1858 :
node _T_1859 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_6.io.enq.bits, _T_1859
node _T_1860 = eq(UInt<3>(0h7), idx_28)
when _T_1860 :
node _T_1861 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_7.io.enq.bits, _T_1861
node _T_1862 = eq(UInt<4>(0h8), idx_28)
when _T_1862 :
node _T_1863 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_8.io.enq.bits, _T_1863
node _T_1864 = eq(UInt<4>(0h9), idx_28)
when _T_1864 :
node _T_1865 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_9.io.enq.bits, _T_1865
node _T_1866 = eq(UInt<4>(0ha), idx_28)
when _T_1866 :
node _T_1867 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_10.io.enq.bits, _T_1867
node _T_1868 = eq(UInt<4>(0hb), idx_28)
when _T_1868 :
node _T_1869 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_11.io.enq.bits, _T_1869
node _T_1870 = eq(UInt<4>(0hc), idx_28)
when _T_1870 :
node _T_1871 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_12.io.enq.bits, _T_1871
node _T_1872 = eq(UInt<4>(0hd), idx_28)
when _T_1872 :
node _T_1873 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_13.io.enq.bits, _T_1873
node _T_1874 = eq(UInt<4>(0he), idx_28)
when _T_1874 :
node _T_1875 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_14.io.enq.bits, _T_1875
node _T_1876 = eq(UInt<4>(0hf), idx_28)
when _T_1876 :
node _T_1877 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_15.io.enq.bits, _T_1877
node _T_1878 = eq(UInt<5>(0h10), idx_28)
when _T_1878 :
node _T_1879 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_16.io.enq.bits, _T_1879
node _T_1880 = eq(UInt<5>(0h11), idx_28)
when _T_1880 :
node _T_1881 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_17.io.enq.bits, _T_1881
node _T_1882 = eq(UInt<5>(0h12), idx_28)
when _T_1882 :
node _T_1883 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_18.io.enq.bits, _T_1883
node _T_1884 = eq(UInt<5>(0h13), idx_28)
when _T_1884 :
node _T_1885 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_19.io.enq.bits, _T_1885
node _T_1886 = eq(UInt<5>(0h14), idx_28)
when _T_1886 :
node _T_1887 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_20.io.enq.bits, _T_1887
node _T_1888 = eq(UInt<5>(0h15), idx_28)
when _T_1888 :
node _T_1889 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_21.io.enq.bits, _T_1889
node _T_1890 = eq(UInt<5>(0h16), idx_28)
when _T_1890 :
node _T_1891 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_22.io.enq.bits, _T_1891
node _T_1892 = eq(UInt<5>(0h17), idx_28)
when _T_1892 :
node _T_1893 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_23.io.enq.bits, _T_1893
node _T_1894 = eq(UInt<5>(0h18), idx_28)
when _T_1894 :
node _T_1895 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_24.io.enq.bits, _T_1895
node _T_1896 = eq(UInt<5>(0h19), idx_28)
when _T_1896 :
node _T_1897 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_25.io.enq.bits, _T_1897
node _T_1898 = eq(UInt<5>(0h1a), idx_28)
when _T_1898 :
node _T_1899 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_26.io.enq.bits, _T_1899
node _T_1900 = eq(UInt<5>(0h1b), idx_28)
when _T_1900 :
node _T_1901 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_27.io.enq.bits, _T_1901
node _T_1902 = eq(UInt<5>(0h1c), idx_28)
when _T_1902 :
node _T_1903 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_28.io.enq.bits, _T_1903
node _T_1904 = eq(UInt<5>(0h1d), idx_28)
when _T_1904 :
node _T_1905 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_29.io.enq.bits, _T_1905
node _T_1906 = eq(UInt<5>(0h1e), idx_28)
when _T_1906 :
node _T_1907 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_30.io.enq.bits, _T_1907
node _T_1908 = eq(UInt<5>(0h1f), idx_28)
when _T_1908 :
node _T_1909 = shr(memresp_bits_shifted, 224)
connect Queue64_UInt8_31.io.enq.bits, _T_1909
node _idx_T_29 = add(write_start_index, UInt<5>(0h1d))
node idx_29 = rem(_idx_T_29, UInt<6>(0h20))
node _T_1910 = eq(UInt<1>(0h0), idx_29)
when _T_1910 :
node _T_1911 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8.io.enq.bits, _T_1911
node _T_1912 = eq(UInt<1>(0h1), idx_29)
when _T_1912 :
node _T_1913 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_1.io.enq.bits, _T_1913
node _T_1914 = eq(UInt<2>(0h2), idx_29)
when _T_1914 :
node _T_1915 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_2.io.enq.bits, _T_1915
node _T_1916 = eq(UInt<2>(0h3), idx_29)
when _T_1916 :
node _T_1917 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_3.io.enq.bits, _T_1917
node _T_1918 = eq(UInt<3>(0h4), idx_29)
when _T_1918 :
node _T_1919 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_4.io.enq.bits, _T_1919
node _T_1920 = eq(UInt<3>(0h5), idx_29)
when _T_1920 :
node _T_1921 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_5.io.enq.bits, _T_1921
node _T_1922 = eq(UInt<3>(0h6), idx_29)
when _T_1922 :
node _T_1923 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_6.io.enq.bits, _T_1923
node _T_1924 = eq(UInt<3>(0h7), idx_29)
when _T_1924 :
node _T_1925 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_7.io.enq.bits, _T_1925
node _T_1926 = eq(UInt<4>(0h8), idx_29)
when _T_1926 :
node _T_1927 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_8.io.enq.bits, _T_1927
node _T_1928 = eq(UInt<4>(0h9), idx_29)
when _T_1928 :
node _T_1929 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_9.io.enq.bits, _T_1929
node _T_1930 = eq(UInt<4>(0ha), idx_29)
when _T_1930 :
node _T_1931 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_10.io.enq.bits, _T_1931
node _T_1932 = eq(UInt<4>(0hb), idx_29)
when _T_1932 :
node _T_1933 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_11.io.enq.bits, _T_1933
node _T_1934 = eq(UInt<4>(0hc), idx_29)
when _T_1934 :
node _T_1935 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_12.io.enq.bits, _T_1935
node _T_1936 = eq(UInt<4>(0hd), idx_29)
when _T_1936 :
node _T_1937 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_13.io.enq.bits, _T_1937
node _T_1938 = eq(UInt<4>(0he), idx_29)
when _T_1938 :
node _T_1939 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_14.io.enq.bits, _T_1939
node _T_1940 = eq(UInt<4>(0hf), idx_29)
when _T_1940 :
node _T_1941 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_15.io.enq.bits, _T_1941
node _T_1942 = eq(UInt<5>(0h10), idx_29)
when _T_1942 :
node _T_1943 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_16.io.enq.bits, _T_1943
node _T_1944 = eq(UInt<5>(0h11), idx_29)
when _T_1944 :
node _T_1945 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_17.io.enq.bits, _T_1945
node _T_1946 = eq(UInt<5>(0h12), idx_29)
when _T_1946 :
node _T_1947 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_18.io.enq.bits, _T_1947
node _T_1948 = eq(UInt<5>(0h13), idx_29)
when _T_1948 :
node _T_1949 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_19.io.enq.bits, _T_1949
node _T_1950 = eq(UInt<5>(0h14), idx_29)
when _T_1950 :
node _T_1951 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_20.io.enq.bits, _T_1951
node _T_1952 = eq(UInt<5>(0h15), idx_29)
when _T_1952 :
node _T_1953 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_21.io.enq.bits, _T_1953
node _T_1954 = eq(UInt<5>(0h16), idx_29)
when _T_1954 :
node _T_1955 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_22.io.enq.bits, _T_1955
node _T_1956 = eq(UInt<5>(0h17), idx_29)
when _T_1956 :
node _T_1957 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_23.io.enq.bits, _T_1957
node _T_1958 = eq(UInt<5>(0h18), idx_29)
when _T_1958 :
node _T_1959 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_24.io.enq.bits, _T_1959
node _T_1960 = eq(UInt<5>(0h19), idx_29)
when _T_1960 :
node _T_1961 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_25.io.enq.bits, _T_1961
node _T_1962 = eq(UInt<5>(0h1a), idx_29)
when _T_1962 :
node _T_1963 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_26.io.enq.bits, _T_1963
node _T_1964 = eq(UInt<5>(0h1b), idx_29)
when _T_1964 :
node _T_1965 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_27.io.enq.bits, _T_1965
node _T_1966 = eq(UInt<5>(0h1c), idx_29)
when _T_1966 :
node _T_1967 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_28.io.enq.bits, _T_1967
node _T_1968 = eq(UInt<5>(0h1d), idx_29)
when _T_1968 :
node _T_1969 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_29.io.enq.bits, _T_1969
node _T_1970 = eq(UInt<5>(0h1e), idx_29)
when _T_1970 :
node _T_1971 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_30.io.enq.bits, _T_1971
node _T_1972 = eq(UInt<5>(0h1f), idx_29)
when _T_1972 :
node _T_1973 = shr(memresp_bits_shifted, 232)
connect Queue64_UInt8_31.io.enq.bits, _T_1973
node _idx_T_30 = add(write_start_index, UInt<5>(0h1e))
node idx_30 = rem(_idx_T_30, UInt<6>(0h20))
node _T_1974 = eq(UInt<1>(0h0), idx_30)
when _T_1974 :
node _T_1975 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8.io.enq.bits, _T_1975
node _T_1976 = eq(UInt<1>(0h1), idx_30)
when _T_1976 :
node _T_1977 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_1.io.enq.bits, _T_1977
node _T_1978 = eq(UInt<2>(0h2), idx_30)
when _T_1978 :
node _T_1979 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_2.io.enq.bits, _T_1979
node _T_1980 = eq(UInt<2>(0h3), idx_30)
when _T_1980 :
node _T_1981 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_3.io.enq.bits, _T_1981
node _T_1982 = eq(UInt<3>(0h4), idx_30)
when _T_1982 :
node _T_1983 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_4.io.enq.bits, _T_1983
node _T_1984 = eq(UInt<3>(0h5), idx_30)
when _T_1984 :
node _T_1985 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_5.io.enq.bits, _T_1985
node _T_1986 = eq(UInt<3>(0h6), idx_30)
when _T_1986 :
node _T_1987 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_6.io.enq.bits, _T_1987
node _T_1988 = eq(UInt<3>(0h7), idx_30)
when _T_1988 :
node _T_1989 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_7.io.enq.bits, _T_1989
node _T_1990 = eq(UInt<4>(0h8), idx_30)
when _T_1990 :
node _T_1991 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_8.io.enq.bits, _T_1991
node _T_1992 = eq(UInt<4>(0h9), idx_30)
when _T_1992 :
node _T_1993 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_9.io.enq.bits, _T_1993
node _T_1994 = eq(UInt<4>(0ha), idx_30)
when _T_1994 :
node _T_1995 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_10.io.enq.bits, _T_1995
node _T_1996 = eq(UInt<4>(0hb), idx_30)
when _T_1996 :
node _T_1997 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_11.io.enq.bits, _T_1997
node _T_1998 = eq(UInt<4>(0hc), idx_30)
when _T_1998 :
node _T_1999 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_12.io.enq.bits, _T_1999
node _T_2000 = eq(UInt<4>(0hd), idx_30)
when _T_2000 :
node _T_2001 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_13.io.enq.bits, _T_2001
node _T_2002 = eq(UInt<4>(0he), idx_30)
when _T_2002 :
node _T_2003 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_14.io.enq.bits, _T_2003
node _T_2004 = eq(UInt<4>(0hf), idx_30)
when _T_2004 :
node _T_2005 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_15.io.enq.bits, _T_2005
node _T_2006 = eq(UInt<5>(0h10), idx_30)
when _T_2006 :
node _T_2007 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_16.io.enq.bits, _T_2007
node _T_2008 = eq(UInt<5>(0h11), idx_30)
when _T_2008 :
node _T_2009 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_17.io.enq.bits, _T_2009
node _T_2010 = eq(UInt<5>(0h12), idx_30)
when _T_2010 :
node _T_2011 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_18.io.enq.bits, _T_2011
node _T_2012 = eq(UInt<5>(0h13), idx_30)
when _T_2012 :
node _T_2013 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_19.io.enq.bits, _T_2013
node _T_2014 = eq(UInt<5>(0h14), idx_30)
when _T_2014 :
node _T_2015 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_20.io.enq.bits, _T_2015
node _T_2016 = eq(UInt<5>(0h15), idx_30)
when _T_2016 :
node _T_2017 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_21.io.enq.bits, _T_2017
node _T_2018 = eq(UInt<5>(0h16), idx_30)
when _T_2018 :
node _T_2019 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_22.io.enq.bits, _T_2019
node _T_2020 = eq(UInt<5>(0h17), idx_30)
when _T_2020 :
node _T_2021 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_23.io.enq.bits, _T_2021
node _T_2022 = eq(UInt<5>(0h18), idx_30)
when _T_2022 :
node _T_2023 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_24.io.enq.bits, _T_2023
node _T_2024 = eq(UInt<5>(0h19), idx_30)
when _T_2024 :
node _T_2025 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_25.io.enq.bits, _T_2025
node _T_2026 = eq(UInt<5>(0h1a), idx_30)
when _T_2026 :
node _T_2027 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_26.io.enq.bits, _T_2027
node _T_2028 = eq(UInt<5>(0h1b), idx_30)
when _T_2028 :
node _T_2029 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_27.io.enq.bits, _T_2029
node _T_2030 = eq(UInt<5>(0h1c), idx_30)
when _T_2030 :
node _T_2031 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_28.io.enq.bits, _T_2031
node _T_2032 = eq(UInt<5>(0h1d), idx_30)
when _T_2032 :
node _T_2033 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_29.io.enq.bits, _T_2033
node _T_2034 = eq(UInt<5>(0h1e), idx_30)
when _T_2034 :
node _T_2035 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_30.io.enq.bits, _T_2035
node _T_2036 = eq(UInt<5>(0h1f), idx_30)
when _T_2036 :
node _T_2037 = shr(memresp_bits_shifted, 240)
connect Queue64_UInt8_31.io.enq.bits, _T_2037
node _idx_T_31 = add(write_start_index, UInt<5>(0h1f))
node idx_31 = rem(_idx_T_31, UInt<6>(0h20))
node _T_2038 = eq(UInt<1>(0h0), idx_31)
when _T_2038 :
node _T_2039 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8.io.enq.bits, _T_2039
node _T_2040 = eq(UInt<1>(0h1), idx_31)
when _T_2040 :
node _T_2041 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_1.io.enq.bits, _T_2041
node _T_2042 = eq(UInt<2>(0h2), idx_31)
when _T_2042 :
node _T_2043 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_2.io.enq.bits, _T_2043
node _T_2044 = eq(UInt<2>(0h3), idx_31)
when _T_2044 :
node _T_2045 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_3.io.enq.bits, _T_2045
node _T_2046 = eq(UInt<3>(0h4), idx_31)
when _T_2046 :
node _T_2047 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_4.io.enq.bits, _T_2047
node _T_2048 = eq(UInt<3>(0h5), idx_31)
when _T_2048 :
node _T_2049 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_5.io.enq.bits, _T_2049
node _T_2050 = eq(UInt<3>(0h6), idx_31)
when _T_2050 :
node _T_2051 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_6.io.enq.bits, _T_2051
node _T_2052 = eq(UInt<3>(0h7), idx_31)
when _T_2052 :
node _T_2053 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_7.io.enq.bits, _T_2053
node _T_2054 = eq(UInt<4>(0h8), idx_31)
when _T_2054 :
node _T_2055 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_8.io.enq.bits, _T_2055
node _T_2056 = eq(UInt<4>(0h9), idx_31)
when _T_2056 :
node _T_2057 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_9.io.enq.bits, _T_2057
node _T_2058 = eq(UInt<4>(0ha), idx_31)
when _T_2058 :
node _T_2059 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_10.io.enq.bits, _T_2059
node _T_2060 = eq(UInt<4>(0hb), idx_31)
when _T_2060 :
node _T_2061 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_11.io.enq.bits, _T_2061
node _T_2062 = eq(UInt<4>(0hc), idx_31)
when _T_2062 :
node _T_2063 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_12.io.enq.bits, _T_2063
node _T_2064 = eq(UInt<4>(0hd), idx_31)
when _T_2064 :
node _T_2065 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_13.io.enq.bits, _T_2065
node _T_2066 = eq(UInt<4>(0he), idx_31)
when _T_2066 :
node _T_2067 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_14.io.enq.bits, _T_2067
node _T_2068 = eq(UInt<4>(0hf), idx_31)
when _T_2068 :
node _T_2069 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_15.io.enq.bits, _T_2069
node _T_2070 = eq(UInt<5>(0h10), idx_31)
when _T_2070 :
node _T_2071 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_16.io.enq.bits, _T_2071
node _T_2072 = eq(UInt<5>(0h11), idx_31)
when _T_2072 :
node _T_2073 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_17.io.enq.bits, _T_2073
node _T_2074 = eq(UInt<5>(0h12), idx_31)
when _T_2074 :
node _T_2075 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_18.io.enq.bits, _T_2075
node _T_2076 = eq(UInt<5>(0h13), idx_31)
when _T_2076 :
node _T_2077 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_19.io.enq.bits, _T_2077
node _T_2078 = eq(UInt<5>(0h14), idx_31)
when _T_2078 :
node _T_2079 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_20.io.enq.bits, _T_2079
node _T_2080 = eq(UInt<5>(0h15), idx_31)
when _T_2080 :
node _T_2081 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_21.io.enq.bits, _T_2081
node _T_2082 = eq(UInt<5>(0h16), idx_31)
when _T_2082 :
node _T_2083 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_22.io.enq.bits, _T_2083
node _T_2084 = eq(UInt<5>(0h17), idx_31)
when _T_2084 :
node _T_2085 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_23.io.enq.bits, _T_2085
node _T_2086 = eq(UInt<5>(0h18), idx_31)
when _T_2086 :
node _T_2087 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_24.io.enq.bits, _T_2087
node _T_2088 = eq(UInt<5>(0h19), idx_31)
when _T_2088 :
node _T_2089 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_25.io.enq.bits, _T_2089
node _T_2090 = eq(UInt<5>(0h1a), idx_31)
when _T_2090 :
node _T_2091 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_26.io.enq.bits, _T_2091
node _T_2092 = eq(UInt<5>(0h1b), idx_31)
when _T_2092 :
node _T_2093 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_27.io.enq.bits, _T_2093
node _T_2094 = eq(UInt<5>(0h1c), idx_31)
when _T_2094 :
node _T_2095 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_28.io.enq.bits, _T_2095
node _T_2096 = eq(UInt<5>(0h1d), idx_31)
when _T_2096 :
node _T_2097 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_29.io.enq.bits, _T_2097
node _T_2098 = eq(UInt<5>(0h1e), idx_31)
when _T_2098 :
node _T_2099 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_30.io.enq.bits, _T_2099
node _T_2100 = eq(UInt<5>(0h1f), idx_31)
when _T_2100 :
node _T_2101 = shr(memresp_bits_shifted, 248)
connect Queue64_UInt8_31.io.enq.bits, _T_2101
node _len_to_write_T = sub(load_info_queue.io.deq.bits.end_byte, load_info_queue.io.deq.bits.start_byte)
node _len_to_write_T_1 = tail(_len_to_write_T, 1)
node len_to_write = add(_len_to_write_T_1, UInt<1>(0h1))
node wrap_len_index_wide = add(write_start_index, len_to_write)
node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20))
node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20))
when load_info_queue.io.deq.valid :
regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1))
node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1)
connect loginfo_cycles_11, _loginfo_cycles_T_23
node _T_2102 = asUInt(reset)
node _T_2103 = eq(_T_2102, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22
node _T_2104 = asUInt(reset)
node _T_2105 = eq(_T_2104, UInt<1>(0h0))
when _T_2105 :
printf(clock, UInt<1>(0h1), "memloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) : printf_23
node _all_queues_ready_T = and(Queue64_UInt8.io.enq.ready, Queue64_UInt8_1.io.enq.ready)
node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue64_UInt8_2.io.enq.ready)
node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue64_UInt8_3.io.enq.ready)
node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue64_UInt8_4.io.enq.ready)
node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue64_UInt8_5.io.enq.ready)
node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue64_UInt8_6.io.enq.ready)
node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue64_UInt8_7.io.enq.ready)
node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue64_UInt8_8.io.enq.ready)
node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue64_UInt8_9.io.enq.ready)
node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue64_UInt8_10.io.enq.ready)
node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue64_UInt8_11.io.enq.ready)
node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue64_UInt8_12.io.enq.ready)
node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue64_UInt8_13.io.enq.ready)
node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue64_UInt8_14.io.enq.ready)
node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue64_UInt8_15.io.enq.ready)
node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue64_UInt8_16.io.enq.ready)
node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue64_UInt8_17.io.enq.ready)
node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue64_UInt8_18.io.enq.ready)
node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue64_UInt8_19.io.enq.ready)
node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue64_UInt8_20.io.enq.ready)
node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue64_UInt8_21.io.enq.ready)
node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue64_UInt8_22.io.enq.ready)
node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue64_UInt8_23.io.enq.ready)
node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue64_UInt8_24.io.enq.ready)
node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue64_UInt8_25.io.enq.ready)
node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue64_UInt8_26.io.enq.ready)
node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue64_UInt8_27.io.enq.ready)
node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue64_UInt8_28.io.enq.ready)
node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue64_UInt8_29.io.enq.ready)
node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue64_UInt8_30.io.enq.ready)
node all_queues_ready = and(_all_queues_ready_T_29, Queue64_UInt8_31.io.enq.ready)
node _load_info_queue_io_deq_ready_T = and(io.l2helperUser.resp.valid, all_queues_ready)
connect load_info_queue.io.deq.ready, _load_info_queue_io_deq_ready_T
node _io_l2helperUser_resp_ready_T = and(load_info_queue.io.deq.valid, all_queues_ready)
connect io.l2helperUser.resp.ready, _io_l2helperUser_resp_ready_T
node _resp_fire_allqueues_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node resp_fire_allqueues = and(_resp_fire_allqueues_T, all_queues_ready)
when resp_fire_allqueues :
connect write_start_index, wrap_len_index_end
node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1)
node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4)
node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5)
node _T_2106 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2107 = and(_T_2106, use_this_queue)
node _T_2108 = and(_T_2107, all_queues_ready)
connect Queue64_UInt8.io.enq.valid, _T_2108
node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7)
node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10)
node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11)
node _T_2109 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2110 = and(_T_2109, use_this_queue_1)
node _T_2111 = and(_T_2110, all_queues_ready)
connect Queue64_UInt8_1.io.enq.valid, _T_2111
node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13)
node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16)
node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17)
node _T_2112 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2113 = and(_T_2112, use_this_queue_2)
node _T_2114 = and(_T_2113, all_queues_ready)
connect Queue64_UInt8_2.io.enq.valid, _T_2114
node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19)
node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22)
node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23)
node _T_2115 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2116 = and(_T_2115, use_this_queue_3)
node _T_2117 = and(_T_2116, all_queues_ready)
connect Queue64_UInt8_3.io.enq.valid, _T_2117
node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25)
node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28)
node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29)
node _T_2118 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2119 = and(_T_2118, use_this_queue_4)
node _T_2120 = and(_T_2119, all_queues_ready)
connect Queue64_UInt8_4.io.enq.valid, _T_2120
node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31)
node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34)
node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35)
node _T_2121 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2122 = and(_T_2121, use_this_queue_5)
node _T_2123 = and(_T_2122, all_queues_ready)
connect Queue64_UInt8_5.io.enq.valid, _T_2123
node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37)
node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40)
node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41)
node _T_2124 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2125 = and(_T_2124, use_this_queue_6)
node _T_2126 = and(_T_2125, all_queues_ready)
connect Queue64_UInt8_6.io.enq.valid, _T_2126
node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43)
node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46)
node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47)
node _T_2127 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2128 = and(_T_2127, use_this_queue_7)
node _T_2129 = and(_T_2128, all_queues_ready)
connect Queue64_UInt8_7.io.enq.valid, _T_2129
node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49)
node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52)
node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53)
node _T_2130 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2131 = and(_T_2130, use_this_queue_8)
node _T_2132 = and(_T_2131, all_queues_ready)
connect Queue64_UInt8_8.io.enq.valid, _T_2132
node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55)
node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58)
node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59)
node _T_2133 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2134 = and(_T_2133, use_this_queue_9)
node _T_2135 = and(_T_2134, all_queues_ready)
connect Queue64_UInt8_9.io.enq.valid, _T_2135
node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61)
node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64)
node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65)
node _T_2136 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2137 = and(_T_2136, use_this_queue_10)
node _T_2138 = and(_T_2137, all_queues_ready)
connect Queue64_UInt8_10.io.enq.valid, _T_2138
node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67)
node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70)
node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71)
node _T_2139 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2140 = and(_T_2139, use_this_queue_11)
node _T_2141 = and(_T_2140, all_queues_ready)
connect Queue64_UInt8_11.io.enq.valid, _T_2141
node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73)
node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76)
node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77)
node _T_2142 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2143 = and(_T_2142, use_this_queue_12)
node _T_2144 = and(_T_2143, all_queues_ready)
connect Queue64_UInt8_12.io.enq.valid, _T_2144
node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79)
node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82)
node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83)
node _T_2145 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2146 = and(_T_2145, use_this_queue_13)
node _T_2147 = and(_T_2146, all_queues_ready)
connect Queue64_UInt8_13.io.enq.valid, _T_2147
node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85)
node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88)
node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89)
node _T_2148 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2149 = and(_T_2148, use_this_queue_14)
node _T_2150 = and(_T_2149, all_queues_ready)
connect Queue64_UInt8_14.io.enq.valid, _T_2150
node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91)
node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94)
node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95)
node _T_2151 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2152 = and(_T_2151, use_this_queue_15)
node _T_2153 = and(_T_2152, all_queues_ready)
connect Queue64_UInt8_15.io.enq.valid, _T_2153
node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97)
node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100)
node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101)
node _T_2154 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2155 = and(_T_2154, use_this_queue_16)
node _T_2156 = and(_T_2155, all_queues_ready)
connect Queue64_UInt8_16.io.enq.valid, _T_2156
node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103)
node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106)
node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107)
node _T_2157 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2158 = and(_T_2157, use_this_queue_17)
node _T_2159 = and(_T_2158, all_queues_ready)
connect Queue64_UInt8_17.io.enq.valid, _T_2159
node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109)
node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112)
node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113)
node _T_2160 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2161 = and(_T_2160, use_this_queue_18)
node _T_2162 = and(_T_2161, all_queues_ready)
connect Queue64_UInt8_18.io.enq.valid, _T_2162
node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115)
node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118)
node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119)
node _T_2163 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2164 = and(_T_2163, use_this_queue_19)
node _T_2165 = and(_T_2164, all_queues_ready)
connect Queue64_UInt8_19.io.enq.valid, _T_2165
node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121)
node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124)
node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125)
node _T_2166 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2167 = and(_T_2166, use_this_queue_20)
node _T_2168 = and(_T_2167, all_queues_ready)
connect Queue64_UInt8_20.io.enq.valid, _T_2168
node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127)
node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130)
node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131)
node _T_2169 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2170 = and(_T_2169, use_this_queue_21)
node _T_2171 = and(_T_2170, all_queues_ready)
connect Queue64_UInt8_21.io.enq.valid, _T_2171
node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133)
node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136)
node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137)
node _T_2172 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2173 = and(_T_2172, use_this_queue_22)
node _T_2174 = and(_T_2173, all_queues_ready)
connect Queue64_UInt8_22.io.enq.valid, _T_2174
node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139)
node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142)
node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143)
node _T_2175 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2176 = and(_T_2175, use_this_queue_23)
node _T_2177 = and(_T_2176, all_queues_ready)
connect Queue64_UInt8_23.io.enq.valid, _T_2177
node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145)
node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148)
node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149)
node _T_2178 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2179 = and(_T_2178, use_this_queue_24)
node _T_2180 = and(_T_2179, all_queues_ready)
connect Queue64_UInt8_24.io.enq.valid, _T_2180
node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151)
node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154)
node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155)
node _T_2181 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2182 = and(_T_2181, use_this_queue_25)
node _T_2183 = and(_T_2182, all_queues_ready)
connect Queue64_UInt8_25.io.enq.valid, _T_2183
node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157)
node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160)
node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161)
node _T_2184 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2185 = and(_T_2184, use_this_queue_26)
node _T_2186 = and(_T_2185, all_queues_ready)
connect Queue64_UInt8_26.io.enq.valid, _T_2186
node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163)
node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166)
node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167)
node _T_2187 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2188 = and(_T_2187, use_this_queue_27)
node _T_2189 = and(_T_2188, all_queues_ready)
connect Queue64_UInt8_27.io.enq.valid, _T_2189
node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169)
node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172)
node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173)
node _T_2190 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2191 = and(_T_2190, use_this_queue_28)
node _T_2192 = and(_T_2191, all_queues_ready)
connect Queue64_UInt8_28.io.enq.valid, _T_2192
node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175)
node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178)
node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179)
node _T_2193 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2194 = and(_T_2193, use_this_queue_29)
node _T_2195 = and(_T_2194, all_queues_ready)
connect Queue64_UInt8_29.io.enq.valid, _T_2195
node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181)
node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184)
node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185)
node _T_2196 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2197 = and(_T_2196, use_this_queue_30)
node _T_2198 = and(_T_2197, all_queues_ready)
connect Queue64_UInt8_30.io.enq.valid, _T_2198
node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187)
node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190)
node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191)
node _T_2199 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid)
node _T_2200 = and(_T_2199, use_this_queue_31)
node _T_2201 = and(_T_2200, all_queues_ready)
connect Queue64_UInt8_31.io.enq.valid, _T_2201
when Queue64_UInt8.io.deq.valid :
regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1))
node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1)
connect loginfo_cycles_12, _loginfo_cycles_T_25
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24
node _T_2204 = asUInt(reset)
node _T_2205 = eq(_T_2204, UInt<1>(0h0))
when _T_2205 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h0), Queue64_UInt8.io.deq.bits) : printf_25
when Queue64_UInt8_1.io.deq.valid :
regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1))
node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1)
connect loginfo_cycles_13, _loginfo_cycles_T_27
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h1), Queue64_UInt8_1.io.deq.bits) : printf_27
when Queue64_UInt8_2.io.deq.valid :
regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1))
node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1)
connect loginfo_cycles_14, _loginfo_cycles_T_29
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28
node _T_2212 = asUInt(reset)
node _T_2213 = eq(_T_2212, UInt<1>(0h0))
when _T_2213 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h2), Queue64_UInt8_2.io.deq.bits) : printf_29
when Queue64_UInt8_3.io.deq.valid :
regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1))
node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1)
connect loginfo_cycles_15, _loginfo_cycles_T_31
node _T_2214 = asUInt(reset)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30
node _T_2216 = asUInt(reset)
node _T_2217 = eq(_T_2216, UInt<1>(0h0))
when _T_2217 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h3), Queue64_UInt8_3.io.deq.bits) : printf_31
when Queue64_UInt8_4.io.deq.valid :
regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1))
node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1)
connect loginfo_cycles_16, _loginfo_cycles_T_33
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32
node _T_2220 = asUInt(reset)
node _T_2221 = eq(_T_2220, UInt<1>(0h0))
when _T_2221 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h4), Queue64_UInt8_4.io.deq.bits) : printf_33
when Queue64_UInt8_5.io.deq.valid :
regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1))
node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1)
connect loginfo_cycles_17, _loginfo_cycles_T_35
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h5), Queue64_UInt8_5.io.deq.bits) : printf_35
when Queue64_UInt8_6.io.deq.valid :
regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1))
node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1)
connect loginfo_cycles_18, _loginfo_cycles_T_37
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36
node _T_2228 = asUInt(reset)
node _T_2229 = eq(_T_2228, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h6), Queue64_UInt8_6.io.deq.bits) : printf_37
when Queue64_UInt8_7.io.deq.valid :
regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1))
node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1)
connect loginfo_cycles_19, _loginfo_cycles_T_39
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38
node _T_2232 = asUInt(reset)
node _T_2233 = eq(_T_2232, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h7), Queue64_UInt8_7.io.deq.bits) : printf_39
when Queue64_UInt8_8.io.deq.valid :
regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1))
node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1)
connect loginfo_cycles_20, _loginfo_cycles_T_41
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40
node _T_2236 = asUInt(reset)
node _T_2237 = eq(_T_2236, UInt<1>(0h0))
when _T_2237 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h8), Queue64_UInt8_8.io.deq.bits) : printf_41
when Queue64_UInt8_9.io.deq.valid :
regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1))
node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1)
connect loginfo_cycles_21, _loginfo_cycles_T_43
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42
node _T_2240 = asUInt(reset)
node _T_2241 = eq(_T_2240, UInt<1>(0h0))
when _T_2241 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h9), Queue64_UInt8_9.io.deq.bits) : printf_43
when Queue64_UInt8_10.io.deq.valid :
regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1))
node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1)
connect loginfo_cycles_22, _loginfo_cycles_T_45
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44
node _T_2244 = asUInt(reset)
node _T_2245 = eq(_T_2244, UInt<1>(0h0))
when _T_2245 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0ha), Queue64_UInt8_10.io.deq.bits) : printf_45
when Queue64_UInt8_11.io.deq.valid :
regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1))
node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1)
connect loginfo_cycles_23, _loginfo_cycles_T_47
node _T_2246 = asUInt(reset)
node _T_2247 = eq(_T_2246, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46
node _T_2248 = asUInt(reset)
node _T_2249 = eq(_T_2248, UInt<1>(0h0))
when _T_2249 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hb), Queue64_UInt8_11.io.deq.bits) : printf_47
when Queue64_UInt8_12.io.deq.valid :
regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1))
node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1)
connect loginfo_cycles_24, _loginfo_cycles_T_49
node _T_2250 = asUInt(reset)
node _T_2251 = eq(_T_2250, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48
node _T_2252 = asUInt(reset)
node _T_2253 = eq(_T_2252, UInt<1>(0h0))
when _T_2253 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hc), Queue64_UInt8_12.io.deq.bits) : printf_49
when Queue64_UInt8_13.io.deq.valid :
regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1))
node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1)
connect loginfo_cycles_25, _loginfo_cycles_T_51
node _T_2254 = asUInt(reset)
node _T_2255 = eq(_T_2254, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hd), Queue64_UInt8_13.io.deq.bits) : printf_51
when Queue64_UInt8_14.io.deq.valid :
regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1))
node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1)
connect loginfo_cycles_26, _loginfo_cycles_T_53
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52
node _T_2260 = asUInt(reset)
node _T_2261 = eq(_T_2260, UInt<1>(0h0))
when _T_2261 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0he), Queue64_UInt8_14.io.deq.bits) : printf_53
when Queue64_UInt8_15.io.deq.valid :
regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1))
node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1)
connect loginfo_cycles_27, _loginfo_cycles_T_55
node _T_2262 = asUInt(reset)
node _T_2263 = eq(_T_2262, UInt<1>(0h0))
when _T_2263 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54
node _T_2264 = asUInt(reset)
node _T_2265 = eq(_T_2264, UInt<1>(0h0))
when _T_2265 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hf), Queue64_UInt8_15.io.deq.bits) : printf_55
when Queue64_UInt8_16.io.deq.valid :
regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1))
node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1)
connect loginfo_cycles_28, _loginfo_cycles_T_57
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56
node _T_2268 = asUInt(reset)
node _T_2269 = eq(_T_2268, UInt<1>(0h0))
when _T_2269 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h10), Queue64_UInt8_16.io.deq.bits) : printf_57
when Queue64_UInt8_17.io.deq.valid :
regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1))
node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1)
connect loginfo_cycles_29, _loginfo_cycles_T_59
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h11), Queue64_UInt8_17.io.deq.bits) : printf_59
when Queue64_UInt8_18.io.deq.valid :
regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1))
node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1)
connect loginfo_cycles_30, _loginfo_cycles_T_61
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h12), Queue64_UInt8_18.io.deq.bits) : printf_61
when Queue64_UInt8_19.io.deq.valid :
regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1))
node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1)
connect loginfo_cycles_31, _loginfo_cycles_T_63
node _T_2278 = asUInt(reset)
node _T_2279 = eq(_T_2278, UInt<1>(0h0))
when _T_2279 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62
node _T_2280 = asUInt(reset)
node _T_2281 = eq(_T_2280, UInt<1>(0h0))
when _T_2281 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h13), Queue64_UInt8_19.io.deq.bits) : printf_63
when Queue64_UInt8_20.io.deq.valid :
regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1))
node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1)
connect loginfo_cycles_32, _loginfo_cycles_T_65
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h14), Queue64_UInt8_20.io.deq.bits) : printf_65
when Queue64_UInt8_21.io.deq.valid :
regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1))
node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1)
connect loginfo_cycles_33, _loginfo_cycles_T_67
node _T_2286 = asUInt(reset)
node _T_2287 = eq(_T_2286, UInt<1>(0h0))
when _T_2287 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h15), Queue64_UInt8_21.io.deq.bits) : printf_67
when Queue64_UInt8_22.io.deq.valid :
regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1))
node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1)
connect loginfo_cycles_34, _loginfo_cycles_T_69
node _T_2290 = asUInt(reset)
node _T_2291 = eq(_T_2290, UInt<1>(0h0))
when _T_2291 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h16), Queue64_UInt8_22.io.deq.bits) : printf_69
when Queue64_UInt8_23.io.deq.valid :
regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1))
node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1)
connect loginfo_cycles_35, _loginfo_cycles_T_71
node _T_2294 = asUInt(reset)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
when _T_2295 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h17), Queue64_UInt8_23.io.deq.bits) : printf_71
when Queue64_UInt8_24.io.deq.valid :
regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1))
node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1)
connect loginfo_cycles_36, _loginfo_cycles_T_73
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h18), Queue64_UInt8_24.io.deq.bits) : printf_73
when Queue64_UInt8_25.io.deq.valid :
regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1))
node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1)
connect loginfo_cycles_37, _loginfo_cycles_T_75
node _T_2302 = asUInt(reset)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
when _T_2303 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h19), Queue64_UInt8_25.io.deq.bits) : printf_75
when Queue64_UInt8_26.io.deq.valid :
regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1))
node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1)
connect loginfo_cycles_38, _loginfo_cycles_T_77
node _T_2306 = asUInt(reset)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
when _T_2307 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_76
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1a), Queue64_UInt8_26.io.deq.bits) : printf_77
when Queue64_UInt8_27.io.deq.valid :
regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1))
node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1)
connect loginfo_cycles_39, _loginfo_cycles_T_79
node _T_2310 = asUInt(reset)
node _T_2311 = eq(_T_2310, UInt<1>(0h0))
when _T_2311 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_78
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1b), Queue64_UInt8_27.io.deq.bits) : printf_79
when Queue64_UInt8_28.io.deq.valid :
regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1))
node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1)
connect loginfo_cycles_40, _loginfo_cycles_T_81
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_80
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1c), Queue64_UInt8_28.io.deq.bits) : printf_81
when Queue64_UInt8_29.io.deq.valid :
regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1))
node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1)
connect loginfo_cycles_41, _loginfo_cycles_T_83
node _T_2318 = asUInt(reset)
node _T_2319 = eq(_T_2318, UInt<1>(0h0))
when _T_2319 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_82
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1d), Queue64_UInt8_29.io.deq.bits) : printf_83
when Queue64_UInt8_30.io.deq.valid :
regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1))
node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1)
connect loginfo_cycles_42, _loginfo_cycles_T_85
node _T_2322 = asUInt(reset)
node _T_2323 = eq(_T_2322, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_84
node _T_2324 = asUInt(reset)
node _T_2325 = eq(_T_2324, UInt<1>(0h0))
when _T_2325 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1e), Queue64_UInt8_30.io.deq.bits) : printf_85
when Queue64_UInt8_31.io.deq.valid :
regreset loginfo_cycles_43 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_86 = add(loginfo_cycles_43, UInt<1>(0h1))
node _loginfo_cycles_T_87 = tail(_loginfo_cycles_T_86, 1)
connect loginfo_cycles_43, _loginfo_cycles_T_87
node _T_2326 = asUInt(reset)
node _T_2327 = eq(_T_2326, UInt<1>(0h0))
when _T_2327 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_43) : printf_86
node _T_2328 = asUInt(reset)
node _T_2329 = eq(_T_2328, UInt<1>(0h0))
when _T_2329 :
printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1f), Queue64_UInt8_31.io.deq.bits) : printf_87
regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
regreset len_already_consumed : UInt<64>, clock, reset, UInt<64>(0h0)
wire remapVecData : UInt<8>[32]
wire remapVecValids : UInt<1>[32]
wire remapVecReadys : UInt<1>[32]
connect remapVecData[0], UInt<1>(0h0)
connect remapVecValids[0], UInt<1>(0h0)
connect Queue64_UInt8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[1], UInt<1>(0h0)
connect remapVecValids[1], UInt<1>(0h0)
connect Queue64_UInt8_1.io.deq.ready, UInt<1>(0h0)
connect remapVecData[2], UInt<1>(0h0)
connect remapVecValids[2], UInt<1>(0h0)
connect Queue64_UInt8_2.io.deq.ready, UInt<1>(0h0)
connect remapVecData[3], UInt<1>(0h0)
connect remapVecValids[3], UInt<1>(0h0)
connect Queue64_UInt8_3.io.deq.ready, UInt<1>(0h0)
connect remapVecData[4], UInt<1>(0h0)
connect remapVecValids[4], UInt<1>(0h0)
connect Queue64_UInt8_4.io.deq.ready, UInt<1>(0h0)
connect remapVecData[5], UInt<1>(0h0)
connect remapVecValids[5], UInt<1>(0h0)
connect Queue64_UInt8_5.io.deq.ready, UInt<1>(0h0)
connect remapVecData[6], UInt<1>(0h0)
connect remapVecValids[6], UInt<1>(0h0)
connect Queue64_UInt8_6.io.deq.ready, UInt<1>(0h0)
connect remapVecData[7], UInt<1>(0h0)
connect remapVecValids[7], UInt<1>(0h0)
connect Queue64_UInt8_7.io.deq.ready, UInt<1>(0h0)
connect remapVecData[8], UInt<1>(0h0)
connect remapVecValids[8], UInt<1>(0h0)
connect Queue64_UInt8_8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[9], UInt<1>(0h0)
connect remapVecValids[9], UInt<1>(0h0)
connect Queue64_UInt8_9.io.deq.ready, UInt<1>(0h0)
connect remapVecData[10], UInt<1>(0h0)
connect remapVecValids[10], UInt<1>(0h0)
connect Queue64_UInt8_10.io.deq.ready, UInt<1>(0h0)
connect remapVecData[11], UInt<1>(0h0)
connect remapVecValids[11], UInt<1>(0h0)
connect Queue64_UInt8_11.io.deq.ready, UInt<1>(0h0)
connect remapVecData[12], UInt<1>(0h0)
connect remapVecValids[12], UInt<1>(0h0)
connect Queue64_UInt8_12.io.deq.ready, UInt<1>(0h0)
connect remapVecData[13], UInt<1>(0h0)
connect remapVecValids[13], UInt<1>(0h0)
connect Queue64_UInt8_13.io.deq.ready, UInt<1>(0h0)
connect remapVecData[14], UInt<1>(0h0)
connect remapVecValids[14], UInt<1>(0h0)
connect Queue64_UInt8_14.io.deq.ready, UInt<1>(0h0)
connect remapVecData[15], UInt<1>(0h0)
connect remapVecValids[15], UInt<1>(0h0)
connect Queue64_UInt8_15.io.deq.ready, UInt<1>(0h0)
connect remapVecData[16], UInt<1>(0h0)
connect remapVecValids[16], UInt<1>(0h0)
connect Queue64_UInt8_16.io.deq.ready, UInt<1>(0h0)
connect remapVecData[17], UInt<1>(0h0)
connect remapVecValids[17], UInt<1>(0h0)
connect Queue64_UInt8_17.io.deq.ready, UInt<1>(0h0)
connect remapVecData[18], UInt<1>(0h0)
connect remapVecValids[18], UInt<1>(0h0)
connect Queue64_UInt8_18.io.deq.ready, UInt<1>(0h0)
connect remapVecData[19], UInt<1>(0h0)
connect remapVecValids[19], UInt<1>(0h0)
connect Queue64_UInt8_19.io.deq.ready, UInt<1>(0h0)
connect remapVecData[20], UInt<1>(0h0)
connect remapVecValids[20], UInt<1>(0h0)
connect Queue64_UInt8_20.io.deq.ready, UInt<1>(0h0)
connect remapVecData[21], UInt<1>(0h0)
connect remapVecValids[21], UInt<1>(0h0)
connect Queue64_UInt8_21.io.deq.ready, UInt<1>(0h0)
connect remapVecData[22], UInt<1>(0h0)
connect remapVecValids[22], UInt<1>(0h0)
connect Queue64_UInt8_22.io.deq.ready, UInt<1>(0h0)
connect remapVecData[23], UInt<1>(0h0)
connect remapVecValids[23], UInt<1>(0h0)
connect Queue64_UInt8_23.io.deq.ready, UInt<1>(0h0)
connect remapVecData[24], UInt<1>(0h0)
connect remapVecValids[24], UInt<1>(0h0)
connect Queue64_UInt8_24.io.deq.ready, UInt<1>(0h0)
connect remapVecData[25], UInt<1>(0h0)
connect remapVecValids[25], UInt<1>(0h0)
connect Queue64_UInt8_25.io.deq.ready, UInt<1>(0h0)
connect remapVecData[26], UInt<1>(0h0)
connect remapVecValids[26], UInt<1>(0h0)
connect Queue64_UInt8_26.io.deq.ready, UInt<1>(0h0)
connect remapVecData[27], UInt<1>(0h0)
connect remapVecValids[27], UInt<1>(0h0)
connect Queue64_UInt8_27.io.deq.ready, UInt<1>(0h0)
connect remapVecData[28], UInt<1>(0h0)
connect remapVecValids[28], UInt<1>(0h0)
connect Queue64_UInt8_28.io.deq.ready, UInt<1>(0h0)
connect remapVecData[29], UInt<1>(0h0)
connect remapVecValids[29], UInt<1>(0h0)
connect Queue64_UInt8_29.io.deq.ready, UInt<1>(0h0)
connect remapVecData[30], UInt<1>(0h0)
connect remapVecValids[30], UInt<1>(0h0)
connect Queue64_UInt8_30.io.deq.ready, UInt<1>(0h0)
connect remapVecData[31], UInt<1>(0h0)
connect remapVecValids[31], UInt<1>(0h0)
connect Queue64_UInt8_31.io.deq.ready, UInt<1>(0h0)
node _remapindex_T = add(UInt<1>(0h0), read_start_index)
node remapindex = rem(_remapindex_T, UInt<6>(0h20))
node _T_2330 = eq(UInt<1>(0h0), remapindex)
when _T_2330 :
connect remapVecData[0], Queue64_UInt8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[0]
node _T_2331 = eq(UInt<1>(0h1), remapindex)
when _T_2331 :
connect remapVecData[0], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[0]
node _T_2332 = eq(UInt<2>(0h2), remapindex)
when _T_2332 :
connect remapVecData[0], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[0]
node _T_2333 = eq(UInt<2>(0h3), remapindex)
when _T_2333 :
connect remapVecData[0], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[0]
node _T_2334 = eq(UInt<3>(0h4), remapindex)
when _T_2334 :
connect remapVecData[0], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[0]
node _T_2335 = eq(UInt<3>(0h5), remapindex)
when _T_2335 :
connect remapVecData[0], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[0]
node _T_2336 = eq(UInt<3>(0h6), remapindex)
when _T_2336 :
connect remapVecData[0], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[0]
node _T_2337 = eq(UInt<3>(0h7), remapindex)
when _T_2337 :
connect remapVecData[0], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[0]
node _T_2338 = eq(UInt<4>(0h8), remapindex)
when _T_2338 :
connect remapVecData[0], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[0]
node _T_2339 = eq(UInt<4>(0h9), remapindex)
when _T_2339 :
connect remapVecData[0], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[0]
node _T_2340 = eq(UInt<4>(0ha), remapindex)
when _T_2340 :
connect remapVecData[0], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[0]
node _T_2341 = eq(UInt<4>(0hb), remapindex)
when _T_2341 :
connect remapVecData[0], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[0]
node _T_2342 = eq(UInt<4>(0hc), remapindex)
when _T_2342 :
connect remapVecData[0], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[0]
node _T_2343 = eq(UInt<4>(0hd), remapindex)
when _T_2343 :
connect remapVecData[0], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[0]
node _T_2344 = eq(UInt<4>(0he), remapindex)
when _T_2344 :
connect remapVecData[0], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[0]
node _T_2345 = eq(UInt<4>(0hf), remapindex)
when _T_2345 :
connect remapVecData[0], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[0]
node _T_2346 = eq(UInt<5>(0h10), remapindex)
when _T_2346 :
connect remapVecData[0], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[0]
node _T_2347 = eq(UInt<5>(0h11), remapindex)
when _T_2347 :
connect remapVecData[0], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[0]
node _T_2348 = eq(UInt<5>(0h12), remapindex)
when _T_2348 :
connect remapVecData[0], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[0]
node _T_2349 = eq(UInt<5>(0h13), remapindex)
when _T_2349 :
connect remapVecData[0], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[0]
node _T_2350 = eq(UInt<5>(0h14), remapindex)
when _T_2350 :
connect remapVecData[0], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[0]
node _T_2351 = eq(UInt<5>(0h15), remapindex)
when _T_2351 :
connect remapVecData[0], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[0]
node _T_2352 = eq(UInt<5>(0h16), remapindex)
when _T_2352 :
connect remapVecData[0], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[0]
node _T_2353 = eq(UInt<5>(0h17), remapindex)
when _T_2353 :
connect remapVecData[0], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[0]
node _T_2354 = eq(UInt<5>(0h18), remapindex)
when _T_2354 :
connect remapVecData[0], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[0]
node _T_2355 = eq(UInt<5>(0h19), remapindex)
when _T_2355 :
connect remapVecData[0], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[0]
node _T_2356 = eq(UInt<5>(0h1a), remapindex)
when _T_2356 :
connect remapVecData[0], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[0]
node _T_2357 = eq(UInt<5>(0h1b), remapindex)
when _T_2357 :
connect remapVecData[0], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[0]
node _T_2358 = eq(UInt<5>(0h1c), remapindex)
when _T_2358 :
connect remapVecData[0], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[0]
node _T_2359 = eq(UInt<5>(0h1d), remapindex)
when _T_2359 :
connect remapVecData[0], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[0]
node _T_2360 = eq(UInt<5>(0h1e), remapindex)
when _T_2360 :
connect remapVecData[0], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[0]
node _T_2361 = eq(UInt<5>(0h1f), remapindex)
when _T_2361 :
connect remapVecData[0], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[0], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[0]
node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index)
node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20))
node _T_2362 = eq(UInt<1>(0h0), remapindex_1)
when _T_2362 :
connect remapVecData[1], Queue64_UInt8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[1]
node _T_2363 = eq(UInt<1>(0h1), remapindex_1)
when _T_2363 :
connect remapVecData[1], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[1]
node _T_2364 = eq(UInt<2>(0h2), remapindex_1)
when _T_2364 :
connect remapVecData[1], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[1]
node _T_2365 = eq(UInt<2>(0h3), remapindex_1)
when _T_2365 :
connect remapVecData[1], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[1]
node _T_2366 = eq(UInt<3>(0h4), remapindex_1)
when _T_2366 :
connect remapVecData[1], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[1]
node _T_2367 = eq(UInt<3>(0h5), remapindex_1)
when _T_2367 :
connect remapVecData[1], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[1]
node _T_2368 = eq(UInt<3>(0h6), remapindex_1)
when _T_2368 :
connect remapVecData[1], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[1]
node _T_2369 = eq(UInt<3>(0h7), remapindex_1)
when _T_2369 :
connect remapVecData[1], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[1]
node _T_2370 = eq(UInt<4>(0h8), remapindex_1)
when _T_2370 :
connect remapVecData[1], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[1]
node _T_2371 = eq(UInt<4>(0h9), remapindex_1)
when _T_2371 :
connect remapVecData[1], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[1]
node _T_2372 = eq(UInt<4>(0ha), remapindex_1)
when _T_2372 :
connect remapVecData[1], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[1]
node _T_2373 = eq(UInt<4>(0hb), remapindex_1)
when _T_2373 :
connect remapVecData[1], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[1]
node _T_2374 = eq(UInt<4>(0hc), remapindex_1)
when _T_2374 :
connect remapVecData[1], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[1]
node _T_2375 = eq(UInt<4>(0hd), remapindex_1)
when _T_2375 :
connect remapVecData[1], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[1]
node _T_2376 = eq(UInt<4>(0he), remapindex_1)
when _T_2376 :
connect remapVecData[1], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[1]
node _T_2377 = eq(UInt<4>(0hf), remapindex_1)
when _T_2377 :
connect remapVecData[1], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[1]
node _T_2378 = eq(UInt<5>(0h10), remapindex_1)
when _T_2378 :
connect remapVecData[1], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[1]
node _T_2379 = eq(UInt<5>(0h11), remapindex_1)
when _T_2379 :
connect remapVecData[1], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[1]
node _T_2380 = eq(UInt<5>(0h12), remapindex_1)
when _T_2380 :
connect remapVecData[1], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[1]
node _T_2381 = eq(UInt<5>(0h13), remapindex_1)
when _T_2381 :
connect remapVecData[1], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[1]
node _T_2382 = eq(UInt<5>(0h14), remapindex_1)
when _T_2382 :
connect remapVecData[1], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[1]
node _T_2383 = eq(UInt<5>(0h15), remapindex_1)
when _T_2383 :
connect remapVecData[1], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[1]
node _T_2384 = eq(UInt<5>(0h16), remapindex_1)
when _T_2384 :
connect remapVecData[1], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[1]
node _T_2385 = eq(UInt<5>(0h17), remapindex_1)
when _T_2385 :
connect remapVecData[1], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[1]
node _T_2386 = eq(UInt<5>(0h18), remapindex_1)
when _T_2386 :
connect remapVecData[1], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[1]
node _T_2387 = eq(UInt<5>(0h19), remapindex_1)
when _T_2387 :
connect remapVecData[1], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[1]
node _T_2388 = eq(UInt<5>(0h1a), remapindex_1)
when _T_2388 :
connect remapVecData[1], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[1]
node _T_2389 = eq(UInt<5>(0h1b), remapindex_1)
when _T_2389 :
connect remapVecData[1], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[1]
node _T_2390 = eq(UInt<5>(0h1c), remapindex_1)
when _T_2390 :
connect remapVecData[1], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[1]
node _T_2391 = eq(UInt<5>(0h1d), remapindex_1)
when _T_2391 :
connect remapVecData[1], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[1]
node _T_2392 = eq(UInt<5>(0h1e), remapindex_1)
when _T_2392 :
connect remapVecData[1], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[1]
node _T_2393 = eq(UInt<5>(0h1f), remapindex_1)
when _T_2393 :
connect remapVecData[1], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[1], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[1]
node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index)
node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20))
node _T_2394 = eq(UInt<1>(0h0), remapindex_2)
when _T_2394 :
connect remapVecData[2], Queue64_UInt8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[2]
node _T_2395 = eq(UInt<1>(0h1), remapindex_2)
when _T_2395 :
connect remapVecData[2], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[2]
node _T_2396 = eq(UInt<2>(0h2), remapindex_2)
when _T_2396 :
connect remapVecData[2], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[2]
node _T_2397 = eq(UInt<2>(0h3), remapindex_2)
when _T_2397 :
connect remapVecData[2], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[2]
node _T_2398 = eq(UInt<3>(0h4), remapindex_2)
when _T_2398 :
connect remapVecData[2], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[2]
node _T_2399 = eq(UInt<3>(0h5), remapindex_2)
when _T_2399 :
connect remapVecData[2], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[2]
node _T_2400 = eq(UInt<3>(0h6), remapindex_2)
when _T_2400 :
connect remapVecData[2], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[2]
node _T_2401 = eq(UInt<3>(0h7), remapindex_2)
when _T_2401 :
connect remapVecData[2], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[2]
node _T_2402 = eq(UInt<4>(0h8), remapindex_2)
when _T_2402 :
connect remapVecData[2], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[2]
node _T_2403 = eq(UInt<4>(0h9), remapindex_2)
when _T_2403 :
connect remapVecData[2], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[2]
node _T_2404 = eq(UInt<4>(0ha), remapindex_2)
when _T_2404 :
connect remapVecData[2], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[2]
node _T_2405 = eq(UInt<4>(0hb), remapindex_2)
when _T_2405 :
connect remapVecData[2], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[2]
node _T_2406 = eq(UInt<4>(0hc), remapindex_2)
when _T_2406 :
connect remapVecData[2], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[2]
node _T_2407 = eq(UInt<4>(0hd), remapindex_2)
when _T_2407 :
connect remapVecData[2], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[2]
node _T_2408 = eq(UInt<4>(0he), remapindex_2)
when _T_2408 :
connect remapVecData[2], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[2]
node _T_2409 = eq(UInt<4>(0hf), remapindex_2)
when _T_2409 :
connect remapVecData[2], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[2]
node _T_2410 = eq(UInt<5>(0h10), remapindex_2)
when _T_2410 :
connect remapVecData[2], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[2]
node _T_2411 = eq(UInt<5>(0h11), remapindex_2)
when _T_2411 :
connect remapVecData[2], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[2]
node _T_2412 = eq(UInt<5>(0h12), remapindex_2)
when _T_2412 :
connect remapVecData[2], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[2]
node _T_2413 = eq(UInt<5>(0h13), remapindex_2)
when _T_2413 :
connect remapVecData[2], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[2]
node _T_2414 = eq(UInt<5>(0h14), remapindex_2)
when _T_2414 :
connect remapVecData[2], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[2]
node _T_2415 = eq(UInt<5>(0h15), remapindex_2)
when _T_2415 :
connect remapVecData[2], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[2]
node _T_2416 = eq(UInt<5>(0h16), remapindex_2)
when _T_2416 :
connect remapVecData[2], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[2]
node _T_2417 = eq(UInt<5>(0h17), remapindex_2)
when _T_2417 :
connect remapVecData[2], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[2]
node _T_2418 = eq(UInt<5>(0h18), remapindex_2)
when _T_2418 :
connect remapVecData[2], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[2]
node _T_2419 = eq(UInt<5>(0h19), remapindex_2)
when _T_2419 :
connect remapVecData[2], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[2]
node _T_2420 = eq(UInt<5>(0h1a), remapindex_2)
when _T_2420 :
connect remapVecData[2], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[2]
node _T_2421 = eq(UInt<5>(0h1b), remapindex_2)
when _T_2421 :
connect remapVecData[2], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[2]
node _T_2422 = eq(UInt<5>(0h1c), remapindex_2)
when _T_2422 :
connect remapVecData[2], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[2]
node _T_2423 = eq(UInt<5>(0h1d), remapindex_2)
when _T_2423 :
connect remapVecData[2], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[2]
node _T_2424 = eq(UInt<5>(0h1e), remapindex_2)
when _T_2424 :
connect remapVecData[2], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[2]
node _T_2425 = eq(UInt<5>(0h1f), remapindex_2)
when _T_2425 :
connect remapVecData[2], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[2], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[2]
node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index)
node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20))
node _T_2426 = eq(UInt<1>(0h0), remapindex_3)
when _T_2426 :
connect remapVecData[3], Queue64_UInt8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[3]
node _T_2427 = eq(UInt<1>(0h1), remapindex_3)
when _T_2427 :
connect remapVecData[3], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[3]
node _T_2428 = eq(UInt<2>(0h2), remapindex_3)
when _T_2428 :
connect remapVecData[3], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[3]
node _T_2429 = eq(UInt<2>(0h3), remapindex_3)
when _T_2429 :
connect remapVecData[3], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[3]
node _T_2430 = eq(UInt<3>(0h4), remapindex_3)
when _T_2430 :
connect remapVecData[3], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[3]
node _T_2431 = eq(UInt<3>(0h5), remapindex_3)
when _T_2431 :
connect remapVecData[3], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[3]
node _T_2432 = eq(UInt<3>(0h6), remapindex_3)
when _T_2432 :
connect remapVecData[3], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[3]
node _T_2433 = eq(UInt<3>(0h7), remapindex_3)
when _T_2433 :
connect remapVecData[3], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[3]
node _T_2434 = eq(UInt<4>(0h8), remapindex_3)
when _T_2434 :
connect remapVecData[3], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[3]
node _T_2435 = eq(UInt<4>(0h9), remapindex_3)
when _T_2435 :
connect remapVecData[3], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[3]
node _T_2436 = eq(UInt<4>(0ha), remapindex_3)
when _T_2436 :
connect remapVecData[3], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[3]
node _T_2437 = eq(UInt<4>(0hb), remapindex_3)
when _T_2437 :
connect remapVecData[3], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[3]
node _T_2438 = eq(UInt<4>(0hc), remapindex_3)
when _T_2438 :
connect remapVecData[3], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[3]
node _T_2439 = eq(UInt<4>(0hd), remapindex_3)
when _T_2439 :
connect remapVecData[3], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[3]
node _T_2440 = eq(UInt<4>(0he), remapindex_3)
when _T_2440 :
connect remapVecData[3], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[3]
node _T_2441 = eq(UInt<4>(0hf), remapindex_3)
when _T_2441 :
connect remapVecData[3], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[3]
node _T_2442 = eq(UInt<5>(0h10), remapindex_3)
when _T_2442 :
connect remapVecData[3], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[3]
node _T_2443 = eq(UInt<5>(0h11), remapindex_3)
when _T_2443 :
connect remapVecData[3], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[3]
node _T_2444 = eq(UInt<5>(0h12), remapindex_3)
when _T_2444 :
connect remapVecData[3], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[3]
node _T_2445 = eq(UInt<5>(0h13), remapindex_3)
when _T_2445 :
connect remapVecData[3], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[3]
node _T_2446 = eq(UInt<5>(0h14), remapindex_3)
when _T_2446 :
connect remapVecData[3], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[3]
node _T_2447 = eq(UInt<5>(0h15), remapindex_3)
when _T_2447 :
connect remapVecData[3], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[3]
node _T_2448 = eq(UInt<5>(0h16), remapindex_3)
when _T_2448 :
connect remapVecData[3], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[3]
node _T_2449 = eq(UInt<5>(0h17), remapindex_3)
when _T_2449 :
connect remapVecData[3], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[3]
node _T_2450 = eq(UInt<5>(0h18), remapindex_3)
when _T_2450 :
connect remapVecData[3], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[3]
node _T_2451 = eq(UInt<5>(0h19), remapindex_3)
when _T_2451 :
connect remapVecData[3], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[3]
node _T_2452 = eq(UInt<5>(0h1a), remapindex_3)
when _T_2452 :
connect remapVecData[3], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[3]
node _T_2453 = eq(UInt<5>(0h1b), remapindex_3)
when _T_2453 :
connect remapVecData[3], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[3]
node _T_2454 = eq(UInt<5>(0h1c), remapindex_3)
when _T_2454 :
connect remapVecData[3], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[3]
node _T_2455 = eq(UInt<5>(0h1d), remapindex_3)
when _T_2455 :
connect remapVecData[3], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[3]
node _T_2456 = eq(UInt<5>(0h1e), remapindex_3)
when _T_2456 :
connect remapVecData[3], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[3]
node _T_2457 = eq(UInt<5>(0h1f), remapindex_3)
when _T_2457 :
connect remapVecData[3], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[3], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[3]
node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index)
node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20))
node _T_2458 = eq(UInt<1>(0h0), remapindex_4)
when _T_2458 :
connect remapVecData[4], Queue64_UInt8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[4]
node _T_2459 = eq(UInt<1>(0h1), remapindex_4)
when _T_2459 :
connect remapVecData[4], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[4]
node _T_2460 = eq(UInt<2>(0h2), remapindex_4)
when _T_2460 :
connect remapVecData[4], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[4]
node _T_2461 = eq(UInt<2>(0h3), remapindex_4)
when _T_2461 :
connect remapVecData[4], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[4]
node _T_2462 = eq(UInt<3>(0h4), remapindex_4)
when _T_2462 :
connect remapVecData[4], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[4]
node _T_2463 = eq(UInt<3>(0h5), remapindex_4)
when _T_2463 :
connect remapVecData[4], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[4]
node _T_2464 = eq(UInt<3>(0h6), remapindex_4)
when _T_2464 :
connect remapVecData[4], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[4]
node _T_2465 = eq(UInt<3>(0h7), remapindex_4)
when _T_2465 :
connect remapVecData[4], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[4]
node _T_2466 = eq(UInt<4>(0h8), remapindex_4)
when _T_2466 :
connect remapVecData[4], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[4]
node _T_2467 = eq(UInt<4>(0h9), remapindex_4)
when _T_2467 :
connect remapVecData[4], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[4]
node _T_2468 = eq(UInt<4>(0ha), remapindex_4)
when _T_2468 :
connect remapVecData[4], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[4]
node _T_2469 = eq(UInt<4>(0hb), remapindex_4)
when _T_2469 :
connect remapVecData[4], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[4]
node _T_2470 = eq(UInt<4>(0hc), remapindex_4)
when _T_2470 :
connect remapVecData[4], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[4]
node _T_2471 = eq(UInt<4>(0hd), remapindex_4)
when _T_2471 :
connect remapVecData[4], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[4]
node _T_2472 = eq(UInt<4>(0he), remapindex_4)
when _T_2472 :
connect remapVecData[4], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[4]
node _T_2473 = eq(UInt<4>(0hf), remapindex_4)
when _T_2473 :
connect remapVecData[4], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[4]
node _T_2474 = eq(UInt<5>(0h10), remapindex_4)
when _T_2474 :
connect remapVecData[4], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[4]
node _T_2475 = eq(UInt<5>(0h11), remapindex_4)
when _T_2475 :
connect remapVecData[4], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[4]
node _T_2476 = eq(UInt<5>(0h12), remapindex_4)
when _T_2476 :
connect remapVecData[4], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[4]
node _T_2477 = eq(UInt<5>(0h13), remapindex_4)
when _T_2477 :
connect remapVecData[4], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[4]
node _T_2478 = eq(UInt<5>(0h14), remapindex_4)
when _T_2478 :
connect remapVecData[4], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[4]
node _T_2479 = eq(UInt<5>(0h15), remapindex_4)
when _T_2479 :
connect remapVecData[4], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[4]
node _T_2480 = eq(UInt<5>(0h16), remapindex_4)
when _T_2480 :
connect remapVecData[4], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[4]
node _T_2481 = eq(UInt<5>(0h17), remapindex_4)
when _T_2481 :
connect remapVecData[4], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[4]
node _T_2482 = eq(UInt<5>(0h18), remapindex_4)
when _T_2482 :
connect remapVecData[4], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[4]
node _T_2483 = eq(UInt<5>(0h19), remapindex_4)
when _T_2483 :
connect remapVecData[4], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[4]
node _T_2484 = eq(UInt<5>(0h1a), remapindex_4)
when _T_2484 :
connect remapVecData[4], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[4]
node _T_2485 = eq(UInt<5>(0h1b), remapindex_4)
when _T_2485 :
connect remapVecData[4], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[4]
node _T_2486 = eq(UInt<5>(0h1c), remapindex_4)
when _T_2486 :
connect remapVecData[4], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[4]
node _T_2487 = eq(UInt<5>(0h1d), remapindex_4)
when _T_2487 :
connect remapVecData[4], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[4]
node _T_2488 = eq(UInt<5>(0h1e), remapindex_4)
when _T_2488 :
connect remapVecData[4], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[4]
node _T_2489 = eq(UInt<5>(0h1f), remapindex_4)
when _T_2489 :
connect remapVecData[4], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[4], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[4]
node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index)
node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20))
node _T_2490 = eq(UInt<1>(0h0), remapindex_5)
when _T_2490 :
connect remapVecData[5], Queue64_UInt8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[5]
node _T_2491 = eq(UInt<1>(0h1), remapindex_5)
when _T_2491 :
connect remapVecData[5], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[5]
node _T_2492 = eq(UInt<2>(0h2), remapindex_5)
when _T_2492 :
connect remapVecData[5], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[5]
node _T_2493 = eq(UInt<2>(0h3), remapindex_5)
when _T_2493 :
connect remapVecData[5], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[5]
node _T_2494 = eq(UInt<3>(0h4), remapindex_5)
when _T_2494 :
connect remapVecData[5], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[5]
node _T_2495 = eq(UInt<3>(0h5), remapindex_5)
when _T_2495 :
connect remapVecData[5], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[5]
node _T_2496 = eq(UInt<3>(0h6), remapindex_5)
when _T_2496 :
connect remapVecData[5], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[5]
node _T_2497 = eq(UInt<3>(0h7), remapindex_5)
when _T_2497 :
connect remapVecData[5], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[5]
node _T_2498 = eq(UInt<4>(0h8), remapindex_5)
when _T_2498 :
connect remapVecData[5], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[5]
node _T_2499 = eq(UInt<4>(0h9), remapindex_5)
when _T_2499 :
connect remapVecData[5], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[5]
node _T_2500 = eq(UInt<4>(0ha), remapindex_5)
when _T_2500 :
connect remapVecData[5], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[5]
node _T_2501 = eq(UInt<4>(0hb), remapindex_5)
when _T_2501 :
connect remapVecData[5], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[5]
node _T_2502 = eq(UInt<4>(0hc), remapindex_5)
when _T_2502 :
connect remapVecData[5], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[5]
node _T_2503 = eq(UInt<4>(0hd), remapindex_5)
when _T_2503 :
connect remapVecData[5], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[5]
node _T_2504 = eq(UInt<4>(0he), remapindex_5)
when _T_2504 :
connect remapVecData[5], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[5]
node _T_2505 = eq(UInt<4>(0hf), remapindex_5)
when _T_2505 :
connect remapVecData[5], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[5]
node _T_2506 = eq(UInt<5>(0h10), remapindex_5)
when _T_2506 :
connect remapVecData[5], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[5]
node _T_2507 = eq(UInt<5>(0h11), remapindex_5)
when _T_2507 :
connect remapVecData[5], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[5]
node _T_2508 = eq(UInt<5>(0h12), remapindex_5)
when _T_2508 :
connect remapVecData[5], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[5]
node _T_2509 = eq(UInt<5>(0h13), remapindex_5)
when _T_2509 :
connect remapVecData[5], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[5]
node _T_2510 = eq(UInt<5>(0h14), remapindex_5)
when _T_2510 :
connect remapVecData[5], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[5]
node _T_2511 = eq(UInt<5>(0h15), remapindex_5)
when _T_2511 :
connect remapVecData[5], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[5]
node _T_2512 = eq(UInt<5>(0h16), remapindex_5)
when _T_2512 :
connect remapVecData[5], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[5]
node _T_2513 = eq(UInt<5>(0h17), remapindex_5)
when _T_2513 :
connect remapVecData[5], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[5]
node _T_2514 = eq(UInt<5>(0h18), remapindex_5)
when _T_2514 :
connect remapVecData[5], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[5]
node _T_2515 = eq(UInt<5>(0h19), remapindex_5)
when _T_2515 :
connect remapVecData[5], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[5]
node _T_2516 = eq(UInt<5>(0h1a), remapindex_5)
when _T_2516 :
connect remapVecData[5], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[5]
node _T_2517 = eq(UInt<5>(0h1b), remapindex_5)
when _T_2517 :
connect remapVecData[5], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[5]
node _T_2518 = eq(UInt<5>(0h1c), remapindex_5)
when _T_2518 :
connect remapVecData[5], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[5]
node _T_2519 = eq(UInt<5>(0h1d), remapindex_5)
when _T_2519 :
connect remapVecData[5], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[5]
node _T_2520 = eq(UInt<5>(0h1e), remapindex_5)
when _T_2520 :
connect remapVecData[5], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[5]
node _T_2521 = eq(UInt<5>(0h1f), remapindex_5)
when _T_2521 :
connect remapVecData[5], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[5], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[5]
node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index)
node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20))
node _T_2522 = eq(UInt<1>(0h0), remapindex_6)
when _T_2522 :
connect remapVecData[6], Queue64_UInt8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[6]
node _T_2523 = eq(UInt<1>(0h1), remapindex_6)
when _T_2523 :
connect remapVecData[6], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[6]
node _T_2524 = eq(UInt<2>(0h2), remapindex_6)
when _T_2524 :
connect remapVecData[6], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[6]
node _T_2525 = eq(UInt<2>(0h3), remapindex_6)
when _T_2525 :
connect remapVecData[6], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[6]
node _T_2526 = eq(UInt<3>(0h4), remapindex_6)
when _T_2526 :
connect remapVecData[6], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[6]
node _T_2527 = eq(UInt<3>(0h5), remapindex_6)
when _T_2527 :
connect remapVecData[6], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[6]
node _T_2528 = eq(UInt<3>(0h6), remapindex_6)
when _T_2528 :
connect remapVecData[6], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[6]
node _T_2529 = eq(UInt<3>(0h7), remapindex_6)
when _T_2529 :
connect remapVecData[6], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[6]
node _T_2530 = eq(UInt<4>(0h8), remapindex_6)
when _T_2530 :
connect remapVecData[6], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[6]
node _T_2531 = eq(UInt<4>(0h9), remapindex_6)
when _T_2531 :
connect remapVecData[6], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[6]
node _T_2532 = eq(UInt<4>(0ha), remapindex_6)
when _T_2532 :
connect remapVecData[6], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[6]
node _T_2533 = eq(UInt<4>(0hb), remapindex_6)
when _T_2533 :
connect remapVecData[6], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[6]
node _T_2534 = eq(UInt<4>(0hc), remapindex_6)
when _T_2534 :
connect remapVecData[6], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[6]
node _T_2535 = eq(UInt<4>(0hd), remapindex_6)
when _T_2535 :
connect remapVecData[6], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[6]
node _T_2536 = eq(UInt<4>(0he), remapindex_6)
when _T_2536 :
connect remapVecData[6], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[6]
node _T_2537 = eq(UInt<4>(0hf), remapindex_6)
when _T_2537 :
connect remapVecData[6], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[6]
node _T_2538 = eq(UInt<5>(0h10), remapindex_6)
when _T_2538 :
connect remapVecData[6], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[6]
node _T_2539 = eq(UInt<5>(0h11), remapindex_6)
when _T_2539 :
connect remapVecData[6], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[6]
node _T_2540 = eq(UInt<5>(0h12), remapindex_6)
when _T_2540 :
connect remapVecData[6], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[6]
node _T_2541 = eq(UInt<5>(0h13), remapindex_6)
when _T_2541 :
connect remapVecData[6], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[6]
node _T_2542 = eq(UInt<5>(0h14), remapindex_6)
when _T_2542 :
connect remapVecData[6], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[6]
node _T_2543 = eq(UInt<5>(0h15), remapindex_6)
when _T_2543 :
connect remapVecData[6], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[6]
node _T_2544 = eq(UInt<5>(0h16), remapindex_6)
when _T_2544 :
connect remapVecData[6], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[6]
node _T_2545 = eq(UInt<5>(0h17), remapindex_6)
when _T_2545 :
connect remapVecData[6], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[6]
node _T_2546 = eq(UInt<5>(0h18), remapindex_6)
when _T_2546 :
connect remapVecData[6], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[6]
node _T_2547 = eq(UInt<5>(0h19), remapindex_6)
when _T_2547 :
connect remapVecData[6], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[6]
node _T_2548 = eq(UInt<5>(0h1a), remapindex_6)
when _T_2548 :
connect remapVecData[6], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[6]
node _T_2549 = eq(UInt<5>(0h1b), remapindex_6)
when _T_2549 :
connect remapVecData[6], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[6]
node _T_2550 = eq(UInt<5>(0h1c), remapindex_6)
when _T_2550 :
connect remapVecData[6], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[6]
node _T_2551 = eq(UInt<5>(0h1d), remapindex_6)
when _T_2551 :
connect remapVecData[6], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[6]
node _T_2552 = eq(UInt<5>(0h1e), remapindex_6)
when _T_2552 :
connect remapVecData[6], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[6]
node _T_2553 = eq(UInt<5>(0h1f), remapindex_6)
when _T_2553 :
connect remapVecData[6], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[6], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[6]
node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index)
node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20))
node _T_2554 = eq(UInt<1>(0h0), remapindex_7)
when _T_2554 :
connect remapVecData[7], Queue64_UInt8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[7]
node _T_2555 = eq(UInt<1>(0h1), remapindex_7)
when _T_2555 :
connect remapVecData[7], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[7]
node _T_2556 = eq(UInt<2>(0h2), remapindex_7)
when _T_2556 :
connect remapVecData[7], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[7]
node _T_2557 = eq(UInt<2>(0h3), remapindex_7)
when _T_2557 :
connect remapVecData[7], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[7]
node _T_2558 = eq(UInt<3>(0h4), remapindex_7)
when _T_2558 :
connect remapVecData[7], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[7]
node _T_2559 = eq(UInt<3>(0h5), remapindex_7)
when _T_2559 :
connect remapVecData[7], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[7]
node _T_2560 = eq(UInt<3>(0h6), remapindex_7)
when _T_2560 :
connect remapVecData[7], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[7]
node _T_2561 = eq(UInt<3>(0h7), remapindex_7)
when _T_2561 :
connect remapVecData[7], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[7]
node _T_2562 = eq(UInt<4>(0h8), remapindex_7)
when _T_2562 :
connect remapVecData[7], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[7]
node _T_2563 = eq(UInt<4>(0h9), remapindex_7)
when _T_2563 :
connect remapVecData[7], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[7]
node _T_2564 = eq(UInt<4>(0ha), remapindex_7)
when _T_2564 :
connect remapVecData[7], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[7]
node _T_2565 = eq(UInt<4>(0hb), remapindex_7)
when _T_2565 :
connect remapVecData[7], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[7]
node _T_2566 = eq(UInt<4>(0hc), remapindex_7)
when _T_2566 :
connect remapVecData[7], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[7]
node _T_2567 = eq(UInt<4>(0hd), remapindex_7)
when _T_2567 :
connect remapVecData[7], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[7]
node _T_2568 = eq(UInt<4>(0he), remapindex_7)
when _T_2568 :
connect remapVecData[7], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[7]
node _T_2569 = eq(UInt<4>(0hf), remapindex_7)
when _T_2569 :
connect remapVecData[7], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[7]
node _T_2570 = eq(UInt<5>(0h10), remapindex_7)
when _T_2570 :
connect remapVecData[7], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[7]
node _T_2571 = eq(UInt<5>(0h11), remapindex_7)
when _T_2571 :
connect remapVecData[7], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[7]
node _T_2572 = eq(UInt<5>(0h12), remapindex_7)
when _T_2572 :
connect remapVecData[7], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[7]
node _T_2573 = eq(UInt<5>(0h13), remapindex_7)
when _T_2573 :
connect remapVecData[7], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[7]
node _T_2574 = eq(UInt<5>(0h14), remapindex_7)
when _T_2574 :
connect remapVecData[7], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[7]
node _T_2575 = eq(UInt<5>(0h15), remapindex_7)
when _T_2575 :
connect remapVecData[7], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[7]
node _T_2576 = eq(UInt<5>(0h16), remapindex_7)
when _T_2576 :
connect remapVecData[7], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[7]
node _T_2577 = eq(UInt<5>(0h17), remapindex_7)
when _T_2577 :
connect remapVecData[7], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[7]
node _T_2578 = eq(UInt<5>(0h18), remapindex_7)
when _T_2578 :
connect remapVecData[7], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[7]
node _T_2579 = eq(UInt<5>(0h19), remapindex_7)
when _T_2579 :
connect remapVecData[7], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[7]
node _T_2580 = eq(UInt<5>(0h1a), remapindex_7)
when _T_2580 :
connect remapVecData[7], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[7]
node _T_2581 = eq(UInt<5>(0h1b), remapindex_7)
when _T_2581 :
connect remapVecData[7], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[7]
node _T_2582 = eq(UInt<5>(0h1c), remapindex_7)
when _T_2582 :
connect remapVecData[7], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[7]
node _T_2583 = eq(UInt<5>(0h1d), remapindex_7)
when _T_2583 :
connect remapVecData[7], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[7]
node _T_2584 = eq(UInt<5>(0h1e), remapindex_7)
when _T_2584 :
connect remapVecData[7], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[7]
node _T_2585 = eq(UInt<5>(0h1f), remapindex_7)
when _T_2585 :
connect remapVecData[7], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[7], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[7]
node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index)
node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20))
node _T_2586 = eq(UInt<1>(0h0), remapindex_8)
when _T_2586 :
connect remapVecData[8], Queue64_UInt8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[8]
node _T_2587 = eq(UInt<1>(0h1), remapindex_8)
when _T_2587 :
connect remapVecData[8], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[8]
node _T_2588 = eq(UInt<2>(0h2), remapindex_8)
when _T_2588 :
connect remapVecData[8], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[8]
node _T_2589 = eq(UInt<2>(0h3), remapindex_8)
when _T_2589 :
connect remapVecData[8], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[8]
node _T_2590 = eq(UInt<3>(0h4), remapindex_8)
when _T_2590 :
connect remapVecData[8], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[8]
node _T_2591 = eq(UInt<3>(0h5), remapindex_8)
when _T_2591 :
connect remapVecData[8], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[8]
node _T_2592 = eq(UInt<3>(0h6), remapindex_8)
when _T_2592 :
connect remapVecData[8], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[8]
node _T_2593 = eq(UInt<3>(0h7), remapindex_8)
when _T_2593 :
connect remapVecData[8], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[8]
node _T_2594 = eq(UInt<4>(0h8), remapindex_8)
when _T_2594 :
connect remapVecData[8], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[8]
node _T_2595 = eq(UInt<4>(0h9), remapindex_8)
when _T_2595 :
connect remapVecData[8], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[8]
node _T_2596 = eq(UInt<4>(0ha), remapindex_8)
when _T_2596 :
connect remapVecData[8], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[8]
node _T_2597 = eq(UInt<4>(0hb), remapindex_8)
when _T_2597 :
connect remapVecData[8], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[8]
node _T_2598 = eq(UInt<4>(0hc), remapindex_8)
when _T_2598 :
connect remapVecData[8], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[8]
node _T_2599 = eq(UInt<4>(0hd), remapindex_8)
when _T_2599 :
connect remapVecData[8], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[8]
node _T_2600 = eq(UInt<4>(0he), remapindex_8)
when _T_2600 :
connect remapVecData[8], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[8]
node _T_2601 = eq(UInt<4>(0hf), remapindex_8)
when _T_2601 :
connect remapVecData[8], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[8]
node _T_2602 = eq(UInt<5>(0h10), remapindex_8)
when _T_2602 :
connect remapVecData[8], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[8]
node _T_2603 = eq(UInt<5>(0h11), remapindex_8)
when _T_2603 :
connect remapVecData[8], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[8]
node _T_2604 = eq(UInt<5>(0h12), remapindex_8)
when _T_2604 :
connect remapVecData[8], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[8]
node _T_2605 = eq(UInt<5>(0h13), remapindex_8)
when _T_2605 :
connect remapVecData[8], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[8]
node _T_2606 = eq(UInt<5>(0h14), remapindex_8)
when _T_2606 :
connect remapVecData[8], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[8]
node _T_2607 = eq(UInt<5>(0h15), remapindex_8)
when _T_2607 :
connect remapVecData[8], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[8]
node _T_2608 = eq(UInt<5>(0h16), remapindex_8)
when _T_2608 :
connect remapVecData[8], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[8]
node _T_2609 = eq(UInt<5>(0h17), remapindex_8)
when _T_2609 :
connect remapVecData[8], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[8]
node _T_2610 = eq(UInt<5>(0h18), remapindex_8)
when _T_2610 :
connect remapVecData[8], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[8]
node _T_2611 = eq(UInt<5>(0h19), remapindex_8)
when _T_2611 :
connect remapVecData[8], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[8]
node _T_2612 = eq(UInt<5>(0h1a), remapindex_8)
when _T_2612 :
connect remapVecData[8], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[8]
node _T_2613 = eq(UInt<5>(0h1b), remapindex_8)
when _T_2613 :
connect remapVecData[8], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[8]
node _T_2614 = eq(UInt<5>(0h1c), remapindex_8)
when _T_2614 :
connect remapVecData[8], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[8]
node _T_2615 = eq(UInt<5>(0h1d), remapindex_8)
when _T_2615 :
connect remapVecData[8], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[8]
node _T_2616 = eq(UInt<5>(0h1e), remapindex_8)
when _T_2616 :
connect remapVecData[8], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[8]
node _T_2617 = eq(UInt<5>(0h1f), remapindex_8)
when _T_2617 :
connect remapVecData[8], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[8], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[8]
node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index)
node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20))
node _T_2618 = eq(UInt<1>(0h0), remapindex_9)
when _T_2618 :
connect remapVecData[9], Queue64_UInt8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[9]
node _T_2619 = eq(UInt<1>(0h1), remapindex_9)
when _T_2619 :
connect remapVecData[9], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[9]
node _T_2620 = eq(UInt<2>(0h2), remapindex_9)
when _T_2620 :
connect remapVecData[9], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[9]
node _T_2621 = eq(UInt<2>(0h3), remapindex_9)
when _T_2621 :
connect remapVecData[9], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[9]
node _T_2622 = eq(UInt<3>(0h4), remapindex_9)
when _T_2622 :
connect remapVecData[9], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[9]
node _T_2623 = eq(UInt<3>(0h5), remapindex_9)
when _T_2623 :
connect remapVecData[9], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[9]
node _T_2624 = eq(UInt<3>(0h6), remapindex_9)
when _T_2624 :
connect remapVecData[9], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[9]
node _T_2625 = eq(UInt<3>(0h7), remapindex_9)
when _T_2625 :
connect remapVecData[9], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[9]
node _T_2626 = eq(UInt<4>(0h8), remapindex_9)
when _T_2626 :
connect remapVecData[9], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[9]
node _T_2627 = eq(UInt<4>(0h9), remapindex_9)
when _T_2627 :
connect remapVecData[9], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[9]
node _T_2628 = eq(UInt<4>(0ha), remapindex_9)
when _T_2628 :
connect remapVecData[9], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[9]
node _T_2629 = eq(UInt<4>(0hb), remapindex_9)
when _T_2629 :
connect remapVecData[9], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[9]
node _T_2630 = eq(UInt<4>(0hc), remapindex_9)
when _T_2630 :
connect remapVecData[9], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[9]
node _T_2631 = eq(UInt<4>(0hd), remapindex_9)
when _T_2631 :
connect remapVecData[9], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[9]
node _T_2632 = eq(UInt<4>(0he), remapindex_9)
when _T_2632 :
connect remapVecData[9], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[9]
node _T_2633 = eq(UInt<4>(0hf), remapindex_9)
when _T_2633 :
connect remapVecData[9], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[9]
node _T_2634 = eq(UInt<5>(0h10), remapindex_9)
when _T_2634 :
connect remapVecData[9], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[9]
node _T_2635 = eq(UInt<5>(0h11), remapindex_9)
when _T_2635 :
connect remapVecData[9], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[9]
node _T_2636 = eq(UInt<5>(0h12), remapindex_9)
when _T_2636 :
connect remapVecData[9], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[9]
node _T_2637 = eq(UInt<5>(0h13), remapindex_9)
when _T_2637 :
connect remapVecData[9], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[9]
node _T_2638 = eq(UInt<5>(0h14), remapindex_9)
when _T_2638 :
connect remapVecData[9], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[9]
node _T_2639 = eq(UInt<5>(0h15), remapindex_9)
when _T_2639 :
connect remapVecData[9], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[9]
node _T_2640 = eq(UInt<5>(0h16), remapindex_9)
when _T_2640 :
connect remapVecData[9], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[9]
node _T_2641 = eq(UInt<5>(0h17), remapindex_9)
when _T_2641 :
connect remapVecData[9], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[9]
node _T_2642 = eq(UInt<5>(0h18), remapindex_9)
when _T_2642 :
connect remapVecData[9], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[9]
node _T_2643 = eq(UInt<5>(0h19), remapindex_9)
when _T_2643 :
connect remapVecData[9], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[9]
node _T_2644 = eq(UInt<5>(0h1a), remapindex_9)
when _T_2644 :
connect remapVecData[9], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[9]
node _T_2645 = eq(UInt<5>(0h1b), remapindex_9)
when _T_2645 :
connect remapVecData[9], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[9]
node _T_2646 = eq(UInt<5>(0h1c), remapindex_9)
when _T_2646 :
connect remapVecData[9], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[9]
node _T_2647 = eq(UInt<5>(0h1d), remapindex_9)
when _T_2647 :
connect remapVecData[9], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[9]
node _T_2648 = eq(UInt<5>(0h1e), remapindex_9)
when _T_2648 :
connect remapVecData[9], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[9]
node _T_2649 = eq(UInt<5>(0h1f), remapindex_9)
when _T_2649 :
connect remapVecData[9], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[9], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[9]
node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index)
node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20))
node _T_2650 = eq(UInt<1>(0h0), remapindex_10)
when _T_2650 :
connect remapVecData[10], Queue64_UInt8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[10]
node _T_2651 = eq(UInt<1>(0h1), remapindex_10)
when _T_2651 :
connect remapVecData[10], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[10]
node _T_2652 = eq(UInt<2>(0h2), remapindex_10)
when _T_2652 :
connect remapVecData[10], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[10]
node _T_2653 = eq(UInt<2>(0h3), remapindex_10)
when _T_2653 :
connect remapVecData[10], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[10]
node _T_2654 = eq(UInt<3>(0h4), remapindex_10)
when _T_2654 :
connect remapVecData[10], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[10]
node _T_2655 = eq(UInt<3>(0h5), remapindex_10)
when _T_2655 :
connect remapVecData[10], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[10]
node _T_2656 = eq(UInt<3>(0h6), remapindex_10)
when _T_2656 :
connect remapVecData[10], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[10]
node _T_2657 = eq(UInt<3>(0h7), remapindex_10)
when _T_2657 :
connect remapVecData[10], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[10]
node _T_2658 = eq(UInt<4>(0h8), remapindex_10)
when _T_2658 :
connect remapVecData[10], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[10]
node _T_2659 = eq(UInt<4>(0h9), remapindex_10)
when _T_2659 :
connect remapVecData[10], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[10]
node _T_2660 = eq(UInt<4>(0ha), remapindex_10)
when _T_2660 :
connect remapVecData[10], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[10]
node _T_2661 = eq(UInt<4>(0hb), remapindex_10)
when _T_2661 :
connect remapVecData[10], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[10]
node _T_2662 = eq(UInt<4>(0hc), remapindex_10)
when _T_2662 :
connect remapVecData[10], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[10]
node _T_2663 = eq(UInt<4>(0hd), remapindex_10)
when _T_2663 :
connect remapVecData[10], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[10]
node _T_2664 = eq(UInt<4>(0he), remapindex_10)
when _T_2664 :
connect remapVecData[10], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[10]
node _T_2665 = eq(UInt<4>(0hf), remapindex_10)
when _T_2665 :
connect remapVecData[10], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[10]
node _T_2666 = eq(UInt<5>(0h10), remapindex_10)
when _T_2666 :
connect remapVecData[10], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[10]
node _T_2667 = eq(UInt<5>(0h11), remapindex_10)
when _T_2667 :
connect remapVecData[10], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[10]
node _T_2668 = eq(UInt<5>(0h12), remapindex_10)
when _T_2668 :
connect remapVecData[10], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[10]
node _T_2669 = eq(UInt<5>(0h13), remapindex_10)
when _T_2669 :
connect remapVecData[10], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[10]
node _T_2670 = eq(UInt<5>(0h14), remapindex_10)
when _T_2670 :
connect remapVecData[10], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[10]
node _T_2671 = eq(UInt<5>(0h15), remapindex_10)
when _T_2671 :
connect remapVecData[10], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[10]
node _T_2672 = eq(UInt<5>(0h16), remapindex_10)
when _T_2672 :
connect remapVecData[10], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[10]
node _T_2673 = eq(UInt<5>(0h17), remapindex_10)
when _T_2673 :
connect remapVecData[10], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[10]
node _T_2674 = eq(UInt<5>(0h18), remapindex_10)
when _T_2674 :
connect remapVecData[10], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[10]
node _T_2675 = eq(UInt<5>(0h19), remapindex_10)
when _T_2675 :
connect remapVecData[10], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[10]
node _T_2676 = eq(UInt<5>(0h1a), remapindex_10)
when _T_2676 :
connect remapVecData[10], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[10]
node _T_2677 = eq(UInt<5>(0h1b), remapindex_10)
when _T_2677 :
connect remapVecData[10], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[10]
node _T_2678 = eq(UInt<5>(0h1c), remapindex_10)
when _T_2678 :
connect remapVecData[10], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[10]
node _T_2679 = eq(UInt<5>(0h1d), remapindex_10)
when _T_2679 :
connect remapVecData[10], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[10]
node _T_2680 = eq(UInt<5>(0h1e), remapindex_10)
when _T_2680 :
connect remapVecData[10], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[10]
node _T_2681 = eq(UInt<5>(0h1f), remapindex_10)
when _T_2681 :
connect remapVecData[10], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[10], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[10]
node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index)
node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20))
node _T_2682 = eq(UInt<1>(0h0), remapindex_11)
when _T_2682 :
connect remapVecData[11], Queue64_UInt8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[11]
node _T_2683 = eq(UInt<1>(0h1), remapindex_11)
when _T_2683 :
connect remapVecData[11], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[11]
node _T_2684 = eq(UInt<2>(0h2), remapindex_11)
when _T_2684 :
connect remapVecData[11], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[11]
node _T_2685 = eq(UInt<2>(0h3), remapindex_11)
when _T_2685 :
connect remapVecData[11], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[11]
node _T_2686 = eq(UInt<3>(0h4), remapindex_11)
when _T_2686 :
connect remapVecData[11], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[11]
node _T_2687 = eq(UInt<3>(0h5), remapindex_11)
when _T_2687 :
connect remapVecData[11], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[11]
node _T_2688 = eq(UInt<3>(0h6), remapindex_11)
when _T_2688 :
connect remapVecData[11], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[11]
node _T_2689 = eq(UInt<3>(0h7), remapindex_11)
when _T_2689 :
connect remapVecData[11], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[11]
node _T_2690 = eq(UInt<4>(0h8), remapindex_11)
when _T_2690 :
connect remapVecData[11], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[11]
node _T_2691 = eq(UInt<4>(0h9), remapindex_11)
when _T_2691 :
connect remapVecData[11], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[11]
node _T_2692 = eq(UInt<4>(0ha), remapindex_11)
when _T_2692 :
connect remapVecData[11], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[11]
node _T_2693 = eq(UInt<4>(0hb), remapindex_11)
when _T_2693 :
connect remapVecData[11], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[11]
node _T_2694 = eq(UInt<4>(0hc), remapindex_11)
when _T_2694 :
connect remapVecData[11], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[11]
node _T_2695 = eq(UInt<4>(0hd), remapindex_11)
when _T_2695 :
connect remapVecData[11], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[11]
node _T_2696 = eq(UInt<4>(0he), remapindex_11)
when _T_2696 :
connect remapVecData[11], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[11]
node _T_2697 = eq(UInt<4>(0hf), remapindex_11)
when _T_2697 :
connect remapVecData[11], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[11]
node _T_2698 = eq(UInt<5>(0h10), remapindex_11)
when _T_2698 :
connect remapVecData[11], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[11]
node _T_2699 = eq(UInt<5>(0h11), remapindex_11)
when _T_2699 :
connect remapVecData[11], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[11]
node _T_2700 = eq(UInt<5>(0h12), remapindex_11)
when _T_2700 :
connect remapVecData[11], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[11]
node _T_2701 = eq(UInt<5>(0h13), remapindex_11)
when _T_2701 :
connect remapVecData[11], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[11]
node _T_2702 = eq(UInt<5>(0h14), remapindex_11)
when _T_2702 :
connect remapVecData[11], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[11]
node _T_2703 = eq(UInt<5>(0h15), remapindex_11)
when _T_2703 :
connect remapVecData[11], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[11]
node _T_2704 = eq(UInt<5>(0h16), remapindex_11)
when _T_2704 :
connect remapVecData[11], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[11]
node _T_2705 = eq(UInt<5>(0h17), remapindex_11)
when _T_2705 :
connect remapVecData[11], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[11]
node _T_2706 = eq(UInt<5>(0h18), remapindex_11)
when _T_2706 :
connect remapVecData[11], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[11]
node _T_2707 = eq(UInt<5>(0h19), remapindex_11)
when _T_2707 :
connect remapVecData[11], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[11]
node _T_2708 = eq(UInt<5>(0h1a), remapindex_11)
when _T_2708 :
connect remapVecData[11], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[11]
node _T_2709 = eq(UInt<5>(0h1b), remapindex_11)
when _T_2709 :
connect remapVecData[11], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[11]
node _T_2710 = eq(UInt<5>(0h1c), remapindex_11)
when _T_2710 :
connect remapVecData[11], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[11]
node _T_2711 = eq(UInt<5>(0h1d), remapindex_11)
when _T_2711 :
connect remapVecData[11], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[11]
node _T_2712 = eq(UInt<5>(0h1e), remapindex_11)
when _T_2712 :
connect remapVecData[11], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[11]
node _T_2713 = eq(UInt<5>(0h1f), remapindex_11)
when _T_2713 :
connect remapVecData[11], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[11], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[11]
node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index)
node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20))
node _T_2714 = eq(UInt<1>(0h0), remapindex_12)
when _T_2714 :
connect remapVecData[12], Queue64_UInt8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[12]
node _T_2715 = eq(UInt<1>(0h1), remapindex_12)
when _T_2715 :
connect remapVecData[12], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[12]
node _T_2716 = eq(UInt<2>(0h2), remapindex_12)
when _T_2716 :
connect remapVecData[12], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[12]
node _T_2717 = eq(UInt<2>(0h3), remapindex_12)
when _T_2717 :
connect remapVecData[12], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[12]
node _T_2718 = eq(UInt<3>(0h4), remapindex_12)
when _T_2718 :
connect remapVecData[12], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[12]
node _T_2719 = eq(UInt<3>(0h5), remapindex_12)
when _T_2719 :
connect remapVecData[12], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[12]
node _T_2720 = eq(UInt<3>(0h6), remapindex_12)
when _T_2720 :
connect remapVecData[12], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[12]
node _T_2721 = eq(UInt<3>(0h7), remapindex_12)
when _T_2721 :
connect remapVecData[12], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[12]
node _T_2722 = eq(UInt<4>(0h8), remapindex_12)
when _T_2722 :
connect remapVecData[12], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[12]
node _T_2723 = eq(UInt<4>(0h9), remapindex_12)
when _T_2723 :
connect remapVecData[12], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[12]
node _T_2724 = eq(UInt<4>(0ha), remapindex_12)
when _T_2724 :
connect remapVecData[12], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[12]
node _T_2725 = eq(UInt<4>(0hb), remapindex_12)
when _T_2725 :
connect remapVecData[12], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[12]
node _T_2726 = eq(UInt<4>(0hc), remapindex_12)
when _T_2726 :
connect remapVecData[12], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[12]
node _T_2727 = eq(UInt<4>(0hd), remapindex_12)
when _T_2727 :
connect remapVecData[12], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[12]
node _T_2728 = eq(UInt<4>(0he), remapindex_12)
when _T_2728 :
connect remapVecData[12], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[12]
node _T_2729 = eq(UInt<4>(0hf), remapindex_12)
when _T_2729 :
connect remapVecData[12], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[12]
node _T_2730 = eq(UInt<5>(0h10), remapindex_12)
when _T_2730 :
connect remapVecData[12], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[12]
node _T_2731 = eq(UInt<5>(0h11), remapindex_12)
when _T_2731 :
connect remapVecData[12], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[12]
node _T_2732 = eq(UInt<5>(0h12), remapindex_12)
when _T_2732 :
connect remapVecData[12], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[12]
node _T_2733 = eq(UInt<5>(0h13), remapindex_12)
when _T_2733 :
connect remapVecData[12], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[12]
node _T_2734 = eq(UInt<5>(0h14), remapindex_12)
when _T_2734 :
connect remapVecData[12], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[12]
node _T_2735 = eq(UInt<5>(0h15), remapindex_12)
when _T_2735 :
connect remapVecData[12], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[12]
node _T_2736 = eq(UInt<5>(0h16), remapindex_12)
when _T_2736 :
connect remapVecData[12], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[12]
node _T_2737 = eq(UInt<5>(0h17), remapindex_12)
when _T_2737 :
connect remapVecData[12], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[12]
node _T_2738 = eq(UInt<5>(0h18), remapindex_12)
when _T_2738 :
connect remapVecData[12], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[12]
node _T_2739 = eq(UInt<5>(0h19), remapindex_12)
when _T_2739 :
connect remapVecData[12], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[12]
node _T_2740 = eq(UInt<5>(0h1a), remapindex_12)
when _T_2740 :
connect remapVecData[12], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[12]
node _T_2741 = eq(UInt<5>(0h1b), remapindex_12)
when _T_2741 :
connect remapVecData[12], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[12]
node _T_2742 = eq(UInt<5>(0h1c), remapindex_12)
when _T_2742 :
connect remapVecData[12], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[12]
node _T_2743 = eq(UInt<5>(0h1d), remapindex_12)
when _T_2743 :
connect remapVecData[12], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[12]
node _T_2744 = eq(UInt<5>(0h1e), remapindex_12)
when _T_2744 :
connect remapVecData[12], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[12]
node _T_2745 = eq(UInt<5>(0h1f), remapindex_12)
when _T_2745 :
connect remapVecData[12], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[12], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[12]
node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index)
node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20))
node _T_2746 = eq(UInt<1>(0h0), remapindex_13)
when _T_2746 :
connect remapVecData[13], Queue64_UInt8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[13]
node _T_2747 = eq(UInt<1>(0h1), remapindex_13)
when _T_2747 :
connect remapVecData[13], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[13]
node _T_2748 = eq(UInt<2>(0h2), remapindex_13)
when _T_2748 :
connect remapVecData[13], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[13]
node _T_2749 = eq(UInt<2>(0h3), remapindex_13)
when _T_2749 :
connect remapVecData[13], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[13]
node _T_2750 = eq(UInt<3>(0h4), remapindex_13)
when _T_2750 :
connect remapVecData[13], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[13]
node _T_2751 = eq(UInt<3>(0h5), remapindex_13)
when _T_2751 :
connect remapVecData[13], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[13]
node _T_2752 = eq(UInt<3>(0h6), remapindex_13)
when _T_2752 :
connect remapVecData[13], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[13]
node _T_2753 = eq(UInt<3>(0h7), remapindex_13)
when _T_2753 :
connect remapVecData[13], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[13]
node _T_2754 = eq(UInt<4>(0h8), remapindex_13)
when _T_2754 :
connect remapVecData[13], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[13]
node _T_2755 = eq(UInt<4>(0h9), remapindex_13)
when _T_2755 :
connect remapVecData[13], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[13]
node _T_2756 = eq(UInt<4>(0ha), remapindex_13)
when _T_2756 :
connect remapVecData[13], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[13]
node _T_2757 = eq(UInt<4>(0hb), remapindex_13)
when _T_2757 :
connect remapVecData[13], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[13]
node _T_2758 = eq(UInt<4>(0hc), remapindex_13)
when _T_2758 :
connect remapVecData[13], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[13]
node _T_2759 = eq(UInt<4>(0hd), remapindex_13)
when _T_2759 :
connect remapVecData[13], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[13]
node _T_2760 = eq(UInt<4>(0he), remapindex_13)
when _T_2760 :
connect remapVecData[13], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[13]
node _T_2761 = eq(UInt<4>(0hf), remapindex_13)
when _T_2761 :
connect remapVecData[13], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[13]
node _T_2762 = eq(UInt<5>(0h10), remapindex_13)
when _T_2762 :
connect remapVecData[13], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[13]
node _T_2763 = eq(UInt<5>(0h11), remapindex_13)
when _T_2763 :
connect remapVecData[13], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[13]
node _T_2764 = eq(UInt<5>(0h12), remapindex_13)
when _T_2764 :
connect remapVecData[13], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[13]
node _T_2765 = eq(UInt<5>(0h13), remapindex_13)
when _T_2765 :
connect remapVecData[13], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[13]
node _T_2766 = eq(UInt<5>(0h14), remapindex_13)
when _T_2766 :
connect remapVecData[13], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[13]
node _T_2767 = eq(UInt<5>(0h15), remapindex_13)
when _T_2767 :
connect remapVecData[13], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[13]
node _T_2768 = eq(UInt<5>(0h16), remapindex_13)
when _T_2768 :
connect remapVecData[13], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[13]
node _T_2769 = eq(UInt<5>(0h17), remapindex_13)
when _T_2769 :
connect remapVecData[13], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[13]
node _T_2770 = eq(UInt<5>(0h18), remapindex_13)
when _T_2770 :
connect remapVecData[13], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[13]
node _T_2771 = eq(UInt<5>(0h19), remapindex_13)
when _T_2771 :
connect remapVecData[13], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[13]
node _T_2772 = eq(UInt<5>(0h1a), remapindex_13)
when _T_2772 :
connect remapVecData[13], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[13]
node _T_2773 = eq(UInt<5>(0h1b), remapindex_13)
when _T_2773 :
connect remapVecData[13], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[13]
node _T_2774 = eq(UInt<5>(0h1c), remapindex_13)
when _T_2774 :
connect remapVecData[13], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[13]
node _T_2775 = eq(UInt<5>(0h1d), remapindex_13)
when _T_2775 :
connect remapVecData[13], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[13]
node _T_2776 = eq(UInt<5>(0h1e), remapindex_13)
when _T_2776 :
connect remapVecData[13], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[13]
node _T_2777 = eq(UInt<5>(0h1f), remapindex_13)
when _T_2777 :
connect remapVecData[13], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[13], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[13]
node _remapindex_T_14 = add(UInt<4>(0he), read_start_index)
node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20))
node _T_2778 = eq(UInt<1>(0h0), remapindex_14)
when _T_2778 :
connect remapVecData[14], Queue64_UInt8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[14]
node _T_2779 = eq(UInt<1>(0h1), remapindex_14)
when _T_2779 :
connect remapVecData[14], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[14]
node _T_2780 = eq(UInt<2>(0h2), remapindex_14)
when _T_2780 :
connect remapVecData[14], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[14]
node _T_2781 = eq(UInt<2>(0h3), remapindex_14)
when _T_2781 :
connect remapVecData[14], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[14]
node _T_2782 = eq(UInt<3>(0h4), remapindex_14)
when _T_2782 :
connect remapVecData[14], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[14]
node _T_2783 = eq(UInt<3>(0h5), remapindex_14)
when _T_2783 :
connect remapVecData[14], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[14]
node _T_2784 = eq(UInt<3>(0h6), remapindex_14)
when _T_2784 :
connect remapVecData[14], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[14]
node _T_2785 = eq(UInt<3>(0h7), remapindex_14)
when _T_2785 :
connect remapVecData[14], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[14]
node _T_2786 = eq(UInt<4>(0h8), remapindex_14)
when _T_2786 :
connect remapVecData[14], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[14]
node _T_2787 = eq(UInt<4>(0h9), remapindex_14)
when _T_2787 :
connect remapVecData[14], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[14]
node _T_2788 = eq(UInt<4>(0ha), remapindex_14)
when _T_2788 :
connect remapVecData[14], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[14]
node _T_2789 = eq(UInt<4>(0hb), remapindex_14)
when _T_2789 :
connect remapVecData[14], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[14]
node _T_2790 = eq(UInt<4>(0hc), remapindex_14)
when _T_2790 :
connect remapVecData[14], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[14]
node _T_2791 = eq(UInt<4>(0hd), remapindex_14)
when _T_2791 :
connect remapVecData[14], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[14]
node _T_2792 = eq(UInt<4>(0he), remapindex_14)
when _T_2792 :
connect remapVecData[14], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[14]
node _T_2793 = eq(UInt<4>(0hf), remapindex_14)
when _T_2793 :
connect remapVecData[14], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[14]
node _T_2794 = eq(UInt<5>(0h10), remapindex_14)
when _T_2794 :
connect remapVecData[14], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[14]
node _T_2795 = eq(UInt<5>(0h11), remapindex_14)
when _T_2795 :
connect remapVecData[14], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[14]
node _T_2796 = eq(UInt<5>(0h12), remapindex_14)
when _T_2796 :
connect remapVecData[14], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[14]
node _T_2797 = eq(UInt<5>(0h13), remapindex_14)
when _T_2797 :
connect remapVecData[14], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[14]
node _T_2798 = eq(UInt<5>(0h14), remapindex_14)
when _T_2798 :
connect remapVecData[14], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[14]
node _T_2799 = eq(UInt<5>(0h15), remapindex_14)
when _T_2799 :
connect remapVecData[14], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[14]
node _T_2800 = eq(UInt<5>(0h16), remapindex_14)
when _T_2800 :
connect remapVecData[14], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[14]
node _T_2801 = eq(UInt<5>(0h17), remapindex_14)
when _T_2801 :
connect remapVecData[14], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[14]
node _T_2802 = eq(UInt<5>(0h18), remapindex_14)
when _T_2802 :
connect remapVecData[14], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[14]
node _T_2803 = eq(UInt<5>(0h19), remapindex_14)
when _T_2803 :
connect remapVecData[14], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[14]
node _T_2804 = eq(UInt<5>(0h1a), remapindex_14)
when _T_2804 :
connect remapVecData[14], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[14]
node _T_2805 = eq(UInt<5>(0h1b), remapindex_14)
when _T_2805 :
connect remapVecData[14], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[14]
node _T_2806 = eq(UInt<5>(0h1c), remapindex_14)
when _T_2806 :
connect remapVecData[14], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[14]
node _T_2807 = eq(UInt<5>(0h1d), remapindex_14)
when _T_2807 :
connect remapVecData[14], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[14]
node _T_2808 = eq(UInt<5>(0h1e), remapindex_14)
when _T_2808 :
connect remapVecData[14], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[14]
node _T_2809 = eq(UInt<5>(0h1f), remapindex_14)
when _T_2809 :
connect remapVecData[14], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[14], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[14]
node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index)
node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20))
node _T_2810 = eq(UInt<1>(0h0), remapindex_15)
when _T_2810 :
connect remapVecData[15], Queue64_UInt8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[15]
node _T_2811 = eq(UInt<1>(0h1), remapindex_15)
when _T_2811 :
connect remapVecData[15], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[15]
node _T_2812 = eq(UInt<2>(0h2), remapindex_15)
when _T_2812 :
connect remapVecData[15], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[15]
node _T_2813 = eq(UInt<2>(0h3), remapindex_15)
when _T_2813 :
connect remapVecData[15], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[15]
node _T_2814 = eq(UInt<3>(0h4), remapindex_15)
when _T_2814 :
connect remapVecData[15], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[15]
node _T_2815 = eq(UInt<3>(0h5), remapindex_15)
when _T_2815 :
connect remapVecData[15], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[15]
node _T_2816 = eq(UInt<3>(0h6), remapindex_15)
when _T_2816 :
connect remapVecData[15], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[15]
node _T_2817 = eq(UInt<3>(0h7), remapindex_15)
when _T_2817 :
connect remapVecData[15], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[15]
node _T_2818 = eq(UInt<4>(0h8), remapindex_15)
when _T_2818 :
connect remapVecData[15], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[15]
node _T_2819 = eq(UInt<4>(0h9), remapindex_15)
when _T_2819 :
connect remapVecData[15], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[15]
node _T_2820 = eq(UInt<4>(0ha), remapindex_15)
when _T_2820 :
connect remapVecData[15], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[15]
node _T_2821 = eq(UInt<4>(0hb), remapindex_15)
when _T_2821 :
connect remapVecData[15], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[15]
node _T_2822 = eq(UInt<4>(0hc), remapindex_15)
when _T_2822 :
connect remapVecData[15], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[15]
node _T_2823 = eq(UInt<4>(0hd), remapindex_15)
when _T_2823 :
connect remapVecData[15], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[15]
node _T_2824 = eq(UInt<4>(0he), remapindex_15)
when _T_2824 :
connect remapVecData[15], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[15]
node _T_2825 = eq(UInt<4>(0hf), remapindex_15)
when _T_2825 :
connect remapVecData[15], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[15]
node _T_2826 = eq(UInt<5>(0h10), remapindex_15)
when _T_2826 :
connect remapVecData[15], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[15]
node _T_2827 = eq(UInt<5>(0h11), remapindex_15)
when _T_2827 :
connect remapVecData[15], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[15]
node _T_2828 = eq(UInt<5>(0h12), remapindex_15)
when _T_2828 :
connect remapVecData[15], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[15]
node _T_2829 = eq(UInt<5>(0h13), remapindex_15)
when _T_2829 :
connect remapVecData[15], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[15]
node _T_2830 = eq(UInt<5>(0h14), remapindex_15)
when _T_2830 :
connect remapVecData[15], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[15]
node _T_2831 = eq(UInt<5>(0h15), remapindex_15)
when _T_2831 :
connect remapVecData[15], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[15]
node _T_2832 = eq(UInt<5>(0h16), remapindex_15)
when _T_2832 :
connect remapVecData[15], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[15]
node _T_2833 = eq(UInt<5>(0h17), remapindex_15)
when _T_2833 :
connect remapVecData[15], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[15]
node _T_2834 = eq(UInt<5>(0h18), remapindex_15)
when _T_2834 :
connect remapVecData[15], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[15]
node _T_2835 = eq(UInt<5>(0h19), remapindex_15)
when _T_2835 :
connect remapVecData[15], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[15]
node _T_2836 = eq(UInt<5>(0h1a), remapindex_15)
when _T_2836 :
connect remapVecData[15], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[15]
node _T_2837 = eq(UInt<5>(0h1b), remapindex_15)
when _T_2837 :
connect remapVecData[15], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[15]
node _T_2838 = eq(UInt<5>(0h1c), remapindex_15)
when _T_2838 :
connect remapVecData[15], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[15]
node _T_2839 = eq(UInt<5>(0h1d), remapindex_15)
when _T_2839 :
connect remapVecData[15], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[15]
node _T_2840 = eq(UInt<5>(0h1e), remapindex_15)
when _T_2840 :
connect remapVecData[15], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[15]
node _T_2841 = eq(UInt<5>(0h1f), remapindex_15)
when _T_2841 :
connect remapVecData[15], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[15], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[15]
node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index)
node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20))
node _T_2842 = eq(UInt<1>(0h0), remapindex_16)
when _T_2842 :
connect remapVecData[16], Queue64_UInt8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[16]
node _T_2843 = eq(UInt<1>(0h1), remapindex_16)
when _T_2843 :
connect remapVecData[16], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[16]
node _T_2844 = eq(UInt<2>(0h2), remapindex_16)
when _T_2844 :
connect remapVecData[16], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[16]
node _T_2845 = eq(UInt<2>(0h3), remapindex_16)
when _T_2845 :
connect remapVecData[16], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[16]
node _T_2846 = eq(UInt<3>(0h4), remapindex_16)
when _T_2846 :
connect remapVecData[16], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[16]
node _T_2847 = eq(UInt<3>(0h5), remapindex_16)
when _T_2847 :
connect remapVecData[16], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[16]
node _T_2848 = eq(UInt<3>(0h6), remapindex_16)
when _T_2848 :
connect remapVecData[16], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[16]
node _T_2849 = eq(UInt<3>(0h7), remapindex_16)
when _T_2849 :
connect remapVecData[16], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[16]
node _T_2850 = eq(UInt<4>(0h8), remapindex_16)
when _T_2850 :
connect remapVecData[16], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[16]
node _T_2851 = eq(UInt<4>(0h9), remapindex_16)
when _T_2851 :
connect remapVecData[16], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[16]
node _T_2852 = eq(UInt<4>(0ha), remapindex_16)
when _T_2852 :
connect remapVecData[16], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[16]
node _T_2853 = eq(UInt<4>(0hb), remapindex_16)
when _T_2853 :
connect remapVecData[16], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[16]
node _T_2854 = eq(UInt<4>(0hc), remapindex_16)
when _T_2854 :
connect remapVecData[16], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[16]
node _T_2855 = eq(UInt<4>(0hd), remapindex_16)
when _T_2855 :
connect remapVecData[16], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[16]
node _T_2856 = eq(UInt<4>(0he), remapindex_16)
when _T_2856 :
connect remapVecData[16], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[16]
node _T_2857 = eq(UInt<4>(0hf), remapindex_16)
when _T_2857 :
connect remapVecData[16], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[16]
node _T_2858 = eq(UInt<5>(0h10), remapindex_16)
when _T_2858 :
connect remapVecData[16], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[16]
node _T_2859 = eq(UInt<5>(0h11), remapindex_16)
when _T_2859 :
connect remapVecData[16], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[16]
node _T_2860 = eq(UInt<5>(0h12), remapindex_16)
when _T_2860 :
connect remapVecData[16], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[16]
node _T_2861 = eq(UInt<5>(0h13), remapindex_16)
when _T_2861 :
connect remapVecData[16], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[16]
node _T_2862 = eq(UInt<5>(0h14), remapindex_16)
when _T_2862 :
connect remapVecData[16], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[16]
node _T_2863 = eq(UInt<5>(0h15), remapindex_16)
when _T_2863 :
connect remapVecData[16], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[16]
node _T_2864 = eq(UInt<5>(0h16), remapindex_16)
when _T_2864 :
connect remapVecData[16], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[16]
node _T_2865 = eq(UInt<5>(0h17), remapindex_16)
when _T_2865 :
connect remapVecData[16], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[16]
node _T_2866 = eq(UInt<5>(0h18), remapindex_16)
when _T_2866 :
connect remapVecData[16], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[16]
node _T_2867 = eq(UInt<5>(0h19), remapindex_16)
when _T_2867 :
connect remapVecData[16], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[16]
node _T_2868 = eq(UInt<5>(0h1a), remapindex_16)
when _T_2868 :
connect remapVecData[16], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[16]
node _T_2869 = eq(UInt<5>(0h1b), remapindex_16)
when _T_2869 :
connect remapVecData[16], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[16]
node _T_2870 = eq(UInt<5>(0h1c), remapindex_16)
when _T_2870 :
connect remapVecData[16], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[16]
node _T_2871 = eq(UInt<5>(0h1d), remapindex_16)
when _T_2871 :
connect remapVecData[16], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[16]
node _T_2872 = eq(UInt<5>(0h1e), remapindex_16)
when _T_2872 :
connect remapVecData[16], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[16]
node _T_2873 = eq(UInt<5>(0h1f), remapindex_16)
when _T_2873 :
connect remapVecData[16], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[16], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[16]
node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index)
node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20))
node _T_2874 = eq(UInt<1>(0h0), remapindex_17)
when _T_2874 :
connect remapVecData[17], Queue64_UInt8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[17]
node _T_2875 = eq(UInt<1>(0h1), remapindex_17)
when _T_2875 :
connect remapVecData[17], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[17]
node _T_2876 = eq(UInt<2>(0h2), remapindex_17)
when _T_2876 :
connect remapVecData[17], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[17]
node _T_2877 = eq(UInt<2>(0h3), remapindex_17)
when _T_2877 :
connect remapVecData[17], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[17]
node _T_2878 = eq(UInt<3>(0h4), remapindex_17)
when _T_2878 :
connect remapVecData[17], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[17]
node _T_2879 = eq(UInt<3>(0h5), remapindex_17)
when _T_2879 :
connect remapVecData[17], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[17]
node _T_2880 = eq(UInt<3>(0h6), remapindex_17)
when _T_2880 :
connect remapVecData[17], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[17]
node _T_2881 = eq(UInt<3>(0h7), remapindex_17)
when _T_2881 :
connect remapVecData[17], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[17]
node _T_2882 = eq(UInt<4>(0h8), remapindex_17)
when _T_2882 :
connect remapVecData[17], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[17]
node _T_2883 = eq(UInt<4>(0h9), remapindex_17)
when _T_2883 :
connect remapVecData[17], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[17]
node _T_2884 = eq(UInt<4>(0ha), remapindex_17)
when _T_2884 :
connect remapVecData[17], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[17]
node _T_2885 = eq(UInt<4>(0hb), remapindex_17)
when _T_2885 :
connect remapVecData[17], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[17]
node _T_2886 = eq(UInt<4>(0hc), remapindex_17)
when _T_2886 :
connect remapVecData[17], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[17]
node _T_2887 = eq(UInt<4>(0hd), remapindex_17)
when _T_2887 :
connect remapVecData[17], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[17]
node _T_2888 = eq(UInt<4>(0he), remapindex_17)
when _T_2888 :
connect remapVecData[17], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[17]
node _T_2889 = eq(UInt<4>(0hf), remapindex_17)
when _T_2889 :
connect remapVecData[17], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[17]
node _T_2890 = eq(UInt<5>(0h10), remapindex_17)
when _T_2890 :
connect remapVecData[17], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[17]
node _T_2891 = eq(UInt<5>(0h11), remapindex_17)
when _T_2891 :
connect remapVecData[17], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[17]
node _T_2892 = eq(UInt<5>(0h12), remapindex_17)
when _T_2892 :
connect remapVecData[17], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[17]
node _T_2893 = eq(UInt<5>(0h13), remapindex_17)
when _T_2893 :
connect remapVecData[17], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[17]
node _T_2894 = eq(UInt<5>(0h14), remapindex_17)
when _T_2894 :
connect remapVecData[17], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[17]
node _T_2895 = eq(UInt<5>(0h15), remapindex_17)
when _T_2895 :
connect remapVecData[17], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[17]
node _T_2896 = eq(UInt<5>(0h16), remapindex_17)
when _T_2896 :
connect remapVecData[17], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[17]
node _T_2897 = eq(UInt<5>(0h17), remapindex_17)
when _T_2897 :
connect remapVecData[17], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[17]
node _T_2898 = eq(UInt<5>(0h18), remapindex_17)
when _T_2898 :
connect remapVecData[17], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[17]
node _T_2899 = eq(UInt<5>(0h19), remapindex_17)
when _T_2899 :
connect remapVecData[17], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[17]
node _T_2900 = eq(UInt<5>(0h1a), remapindex_17)
when _T_2900 :
connect remapVecData[17], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[17]
node _T_2901 = eq(UInt<5>(0h1b), remapindex_17)
when _T_2901 :
connect remapVecData[17], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[17]
node _T_2902 = eq(UInt<5>(0h1c), remapindex_17)
when _T_2902 :
connect remapVecData[17], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[17]
node _T_2903 = eq(UInt<5>(0h1d), remapindex_17)
when _T_2903 :
connect remapVecData[17], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[17]
node _T_2904 = eq(UInt<5>(0h1e), remapindex_17)
when _T_2904 :
connect remapVecData[17], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[17]
node _T_2905 = eq(UInt<5>(0h1f), remapindex_17)
when _T_2905 :
connect remapVecData[17], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[17], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[17]
node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index)
node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20))
node _T_2906 = eq(UInt<1>(0h0), remapindex_18)
when _T_2906 :
connect remapVecData[18], Queue64_UInt8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[18]
node _T_2907 = eq(UInt<1>(0h1), remapindex_18)
when _T_2907 :
connect remapVecData[18], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[18]
node _T_2908 = eq(UInt<2>(0h2), remapindex_18)
when _T_2908 :
connect remapVecData[18], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[18]
node _T_2909 = eq(UInt<2>(0h3), remapindex_18)
when _T_2909 :
connect remapVecData[18], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[18]
node _T_2910 = eq(UInt<3>(0h4), remapindex_18)
when _T_2910 :
connect remapVecData[18], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[18]
node _T_2911 = eq(UInt<3>(0h5), remapindex_18)
when _T_2911 :
connect remapVecData[18], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[18]
node _T_2912 = eq(UInt<3>(0h6), remapindex_18)
when _T_2912 :
connect remapVecData[18], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[18]
node _T_2913 = eq(UInt<3>(0h7), remapindex_18)
when _T_2913 :
connect remapVecData[18], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[18]
node _T_2914 = eq(UInt<4>(0h8), remapindex_18)
when _T_2914 :
connect remapVecData[18], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[18]
node _T_2915 = eq(UInt<4>(0h9), remapindex_18)
when _T_2915 :
connect remapVecData[18], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[18]
node _T_2916 = eq(UInt<4>(0ha), remapindex_18)
when _T_2916 :
connect remapVecData[18], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[18]
node _T_2917 = eq(UInt<4>(0hb), remapindex_18)
when _T_2917 :
connect remapVecData[18], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[18]
node _T_2918 = eq(UInt<4>(0hc), remapindex_18)
when _T_2918 :
connect remapVecData[18], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[18]
node _T_2919 = eq(UInt<4>(0hd), remapindex_18)
when _T_2919 :
connect remapVecData[18], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[18]
node _T_2920 = eq(UInt<4>(0he), remapindex_18)
when _T_2920 :
connect remapVecData[18], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[18]
node _T_2921 = eq(UInt<4>(0hf), remapindex_18)
when _T_2921 :
connect remapVecData[18], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[18]
node _T_2922 = eq(UInt<5>(0h10), remapindex_18)
when _T_2922 :
connect remapVecData[18], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[18]
node _T_2923 = eq(UInt<5>(0h11), remapindex_18)
when _T_2923 :
connect remapVecData[18], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[18]
node _T_2924 = eq(UInt<5>(0h12), remapindex_18)
when _T_2924 :
connect remapVecData[18], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[18]
node _T_2925 = eq(UInt<5>(0h13), remapindex_18)
when _T_2925 :
connect remapVecData[18], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[18]
node _T_2926 = eq(UInt<5>(0h14), remapindex_18)
when _T_2926 :
connect remapVecData[18], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[18]
node _T_2927 = eq(UInt<5>(0h15), remapindex_18)
when _T_2927 :
connect remapVecData[18], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[18]
node _T_2928 = eq(UInt<5>(0h16), remapindex_18)
when _T_2928 :
connect remapVecData[18], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[18]
node _T_2929 = eq(UInt<5>(0h17), remapindex_18)
when _T_2929 :
connect remapVecData[18], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[18]
node _T_2930 = eq(UInt<5>(0h18), remapindex_18)
when _T_2930 :
connect remapVecData[18], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[18]
node _T_2931 = eq(UInt<5>(0h19), remapindex_18)
when _T_2931 :
connect remapVecData[18], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[18]
node _T_2932 = eq(UInt<5>(0h1a), remapindex_18)
when _T_2932 :
connect remapVecData[18], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[18]
node _T_2933 = eq(UInt<5>(0h1b), remapindex_18)
when _T_2933 :
connect remapVecData[18], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[18]
node _T_2934 = eq(UInt<5>(0h1c), remapindex_18)
when _T_2934 :
connect remapVecData[18], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[18]
node _T_2935 = eq(UInt<5>(0h1d), remapindex_18)
when _T_2935 :
connect remapVecData[18], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[18]
node _T_2936 = eq(UInt<5>(0h1e), remapindex_18)
when _T_2936 :
connect remapVecData[18], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[18]
node _T_2937 = eq(UInt<5>(0h1f), remapindex_18)
when _T_2937 :
connect remapVecData[18], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[18], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[18]
node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index)
node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20))
node _T_2938 = eq(UInt<1>(0h0), remapindex_19)
when _T_2938 :
connect remapVecData[19], Queue64_UInt8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[19]
node _T_2939 = eq(UInt<1>(0h1), remapindex_19)
when _T_2939 :
connect remapVecData[19], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[19]
node _T_2940 = eq(UInt<2>(0h2), remapindex_19)
when _T_2940 :
connect remapVecData[19], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[19]
node _T_2941 = eq(UInt<2>(0h3), remapindex_19)
when _T_2941 :
connect remapVecData[19], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[19]
node _T_2942 = eq(UInt<3>(0h4), remapindex_19)
when _T_2942 :
connect remapVecData[19], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[19]
node _T_2943 = eq(UInt<3>(0h5), remapindex_19)
when _T_2943 :
connect remapVecData[19], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[19]
node _T_2944 = eq(UInt<3>(0h6), remapindex_19)
when _T_2944 :
connect remapVecData[19], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[19]
node _T_2945 = eq(UInt<3>(0h7), remapindex_19)
when _T_2945 :
connect remapVecData[19], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[19]
node _T_2946 = eq(UInt<4>(0h8), remapindex_19)
when _T_2946 :
connect remapVecData[19], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[19]
node _T_2947 = eq(UInt<4>(0h9), remapindex_19)
when _T_2947 :
connect remapVecData[19], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[19]
node _T_2948 = eq(UInt<4>(0ha), remapindex_19)
when _T_2948 :
connect remapVecData[19], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[19]
node _T_2949 = eq(UInt<4>(0hb), remapindex_19)
when _T_2949 :
connect remapVecData[19], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[19]
node _T_2950 = eq(UInt<4>(0hc), remapindex_19)
when _T_2950 :
connect remapVecData[19], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[19]
node _T_2951 = eq(UInt<4>(0hd), remapindex_19)
when _T_2951 :
connect remapVecData[19], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[19]
node _T_2952 = eq(UInt<4>(0he), remapindex_19)
when _T_2952 :
connect remapVecData[19], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[19]
node _T_2953 = eq(UInt<4>(0hf), remapindex_19)
when _T_2953 :
connect remapVecData[19], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[19]
node _T_2954 = eq(UInt<5>(0h10), remapindex_19)
when _T_2954 :
connect remapVecData[19], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[19]
node _T_2955 = eq(UInt<5>(0h11), remapindex_19)
when _T_2955 :
connect remapVecData[19], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[19]
node _T_2956 = eq(UInt<5>(0h12), remapindex_19)
when _T_2956 :
connect remapVecData[19], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[19]
node _T_2957 = eq(UInt<5>(0h13), remapindex_19)
when _T_2957 :
connect remapVecData[19], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[19]
node _T_2958 = eq(UInt<5>(0h14), remapindex_19)
when _T_2958 :
connect remapVecData[19], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[19]
node _T_2959 = eq(UInt<5>(0h15), remapindex_19)
when _T_2959 :
connect remapVecData[19], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[19]
node _T_2960 = eq(UInt<5>(0h16), remapindex_19)
when _T_2960 :
connect remapVecData[19], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[19]
node _T_2961 = eq(UInt<5>(0h17), remapindex_19)
when _T_2961 :
connect remapVecData[19], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[19]
node _T_2962 = eq(UInt<5>(0h18), remapindex_19)
when _T_2962 :
connect remapVecData[19], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[19]
node _T_2963 = eq(UInt<5>(0h19), remapindex_19)
when _T_2963 :
connect remapVecData[19], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[19]
node _T_2964 = eq(UInt<5>(0h1a), remapindex_19)
when _T_2964 :
connect remapVecData[19], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[19]
node _T_2965 = eq(UInt<5>(0h1b), remapindex_19)
when _T_2965 :
connect remapVecData[19], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[19]
node _T_2966 = eq(UInt<5>(0h1c), remapindex_19)
when _T_2966 :
connect remapVecData[19], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[19]
node _T_2967 = eq(UInt<5>(0h1d), remapindex_19)
when _T_2967 :
connect remapVecData[19], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[19]
node _T_2968 = eq(UInt<5>(0h1e), remapindex_19)
when _T_2968 :
connect remapVecData[19], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[19]
node _T_2969 = eq(UInt<5>(0h1f), remapindex_19)
when _T_2969 :
connect remapVecData[19], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[19], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[19]
node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index)
node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20))
node _T_2970 = eq(UInt<1>(0h0), remapindex_20)
when _T_2970 :
connect remapVecData[20], Queue64_UInt8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[20]
node _T_2971 = eq(UInt<1>(0h1), remapindex_20)
when _T_2971 :
connect remapVecData[20], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[20]
node _T_2972 = eq(UInt<2>(0h2), remapindex_20)
when _T_2972 :
connect remapVecData[20], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[20]
node _T_2973 = eq(UInt<2>(0h3), remapindex_20)
when _T_2973 :
connect remapVecData[20], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[20]
node _T_2974 = eq(UInt<3>(0h4), remapindex_20)
when _T_2974 :
connect remapVecData[20], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[20]
node _T_2975 = eq(UInt<3>(0h5), remapindex_20)
when _T_2975 :
connect remapVecData[20], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[20]
node _T_2976 = eq(UInt<3>(0h6), remapindex_20)
when _T_2976 :
connect remapVecData[20], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[20]
node _T_2977 = eq(UInt<3>(0h7), remapindex_20)
when _T_2977 :
connect remapVecData[20], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[20]
node _T_2978 = eq(UInt<4>(0h8), remapindex_20)
when _T_2978 :
connect remapVecData[20], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[20]
node _T_2979 = eq(UInt<4>(0h9), remapindex_20)
when _T_2979 :
connect remapVecData[20], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[20]
node _T_2980 = eq(UInt<4>(0ha), remapindex_20)
when _T_2980 :
connect remapVecData[20], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[20]
node _T_2981 = eq(UInt<4>(0hb), remapindex_20)
when _T_2981 :
connect remapVecData[20], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[20]
node _T_2982 = eq(UInt<4>(0hc), remapindex_20)
when _T_2982 :
connect remapVecData[20], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[20]
node _T_2983 = eq(UInt<4>(0hd), remapindex_20)
when _T_2983 :
connect remapVecData[20], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[20]
node _T_2984 = eq(UInt<4>(0he), remapindex_20)
when _T_2984 :
connect remapVecData[20], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[20]
node _T_2985 = eq(UInt<4>(0hf), remapindex_20)
when _T_2985 :
connect remapVecData[20], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[20]
node _T_2986 = eq(UInt<5>(0h10), remapindex_20)
when _T_2986 :
connect remapVecData[20], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[20]
node _T_2987 = eq(UInt<5>(0h11), remapindex_20)
when _T_2987 :
connect remapVecData[20], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[20]
node _T_2988 = eq(UInt<5>(0h12), remapindex_20)
when _T_2988 :
connect remapVecData[20], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[20]
node _T_2989 = eq(UInt<5>(0h13), remapindex_20)
when _T_2989 :
connect remapVecData[20], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[20]
node _T_2990 = eq(UInt<5>(0h14), remapindex_20)
when _T_2990 :
connect remapVecData[20], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[20]
node _T_2991 = eq(UInt<5>(0h15), remapindex_20)
when _T_2991 :
connect remapVecData[20], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[20]
node _T_2992 = eq(UInt<5>(0h16), remapindex_20)
when _T_2992 :
connect remapVecData[20], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[20]
node _T_2993 = eq(UInt<5>(0h17), remapindex_20)
when _T_2993 :
connect remapVecData[20], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[20]
node _T_2994 = eq(UInt<5>(0h18), remapindex_20)
when _T_2994 :
connect remapVecData[20], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[20]
node _T_2995 = eq(UInt<5>(0h19), remapindex_20)
when _T_2995 :
connect remapVecData[20], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[20]
node _T_2996 = eq(UInt<5>(0h1a), remapindex_20)
when _T_2996 :
connect remapVecData[20], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[20]
node _T_2997 = eq(UInt<5>(0h1b), remapindex_20)
when _T_2997 :
connect remapVecData[20], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[20]
node _T_2998 = eq(UInt<5>(0h1c), remapindex_20)
when _T_2998 :
connect remapVecData[20], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[20]
node _T_2999 = eq(UInt<5>(0h1d), remapindex_20)
when _T_2999 :
connect remapVecData[20], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[20]
node _T_3000 = eq(UInt<5>(0h1e), remapindex_20)
when _T_3000 :
connect remapVecData[20], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[20]
node _T_3001 = eq(UInt<5>(0h1f), remapindex_20)
when _T_3001 :
connect remapVecData[20], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[20], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[20]
node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index)
node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20))
node _T_3002 = eq(UInt<1>(0h0), remapindex_21)
when _T_3002 :
connect remapVecData[21], Queue64_UInt8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[21]
node _T_3003 = eq(UInt<1>(0h1), remapindex_21)
when _T_3003 :
connect remapVecData[21], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[21]
node _T_3004 = eq(UInt<2>(0h2), remapindex_21)
when _T_3004 :
connect remapVecData[21], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[21]
node _T_3005 = eq(UInt<2>(0h3), remapindex_21)
when _T_3005 :
connect remapVecData[21], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[21]
node _T_3006 = eq(UInt<3>(0h4), remapindex_21)
when _T_3006 :
connect remapVecData[21], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[21]
node _T_3007 = eq(UInt<3>(0h5), remapindex_21)
when _T_3007 :
connect remapVecData[21], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[21]
node _T_3008 = eq(UInt<3>(0h6), remapindex_21)
when _T_3008 :
connect remapVecData[21], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[21]
node _T_3009 = eq(UInt<3>(0h7), remapindex_21)
when _T_3009 :
connect remapVecData[21], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[21]
node _T_3010 = eq(UInt<4>(0h8), remapindex_21)
when _T_3010 :
connect remapVecData[21], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[21]
node _T_3011 = eq(UInt<4>(0h9), remapindex_21)
when _T_3011 :
connect remapVecData[21], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[21]
node _T_3012 = eq(UInt<4>(0ha), remapindex_21)
when _T_3012 :
connect remapVecData[21], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[21]
node _T_3013 = eq(UInt<4>(0hb), remapindex_21)
when _T_3013 :
connect remapVecData[21], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[21]
node _T_3014 = eq(UInt<4>(0hc), remapindex_21)
when _T_3014 :
connect remapVecData[21], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[21]
node _T_3015 = eq(UInt<4>(0hd), remapindex_21)
when _T_3015 :
connect remapVecData[21], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[21]
node _T_3016 = eq(UInt<4>(0he), remapindex_21)
when _T_3016 :
connect remapVecData[21], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[21]
node _T_3017 = eq(UInt<4>(0hf), remapindex_21)
when _T_3017 :
connect remapVecData[21], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[21]
node _T_3018 = eq(UInt<5>(0h10), remapindex_21)
when _T_3018 :
connect remapVecData[21], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[21]
node _T_3019 = eq(UInt<5>(0h11), remapindex_21)
when _T_3019 :
connect remapVecData[21], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[21]
node _T_3020 = eq(UInt<5>(0h12), remapindex_21)
when _T_3020 :
connect remapVecData[21], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[21]
node _T_3021 = eq(UInt<5>(0h13), remapindex_21)
when _T_3021 :
connect remapVecData[21], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[21]
node _T_3022 = eq(UInt<5>(0h14), remapindex_21)
when _T_3022 :
connect remapVecData[21], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[21]
node _T_3023 = eq(UInt<5>(0h15), remapindex_21)
when _T_3023 :
connect remapVecData[21], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[21]
node _T_3024 = eq(UInt<5>(0h16), remapindex_21)
when _T_3024 :
connect remapVecData[21], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[21]
node _T_3025 = eq(UInt<5>(0h17), remapindex_21)
when _T_3025 :
connect remapVecData[21], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[21]
node _T_3026 = eq(UInt<5>(0h18), remapindex_21)
when _T_3026 :
connect remapVecData[21], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[21]
node _T_3027 = eq(UInt<5>(0h19), remapindex_21)
when _T_3027 :
connect remapVecData[21], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[21]
node _T_3028 = eq(UInt<5>(0h1a), remapindex_21)
when _T_3028 :
connect remapVecData[21], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[21]
node _T_3029 = eq(UInt<5>(0h1b), remapindex_21)
when _T_3029 :
connect remapVecData[21], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[21]
node _T_3030 = eq(UInt<5>(0h1c), remapindex_21)
when _T_3030 :
connect remapVecData[21], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[21]
node _T_3031 = eq(UInt<5>(0h1d), remapindex_21)
when _T_3031 :
connect remapVecData[21], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[21]
node _T_3032 = eq(UInt<5>(0h1e), remapindex_21)
when _T_3032 :
connect remapVecData[21], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[21]
node _T_3033 = eq(UInt<5>(0h1f), remapindex_21)
when _T_3033 :
connect remapVecData[21], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[21], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[21]
node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index)
node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20))
node _T_3034 = eq(UInt<1>(0h0), remapindex_22)
when _T_3034 :
connect remapVecData[22], Queue64_UInt8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[22]
node _T_3035 = eq(UInt<1>(0h1), remapindex_22)
when _T_3035 :
connect remapVecData[22], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[22]
node _T_3036 = eq(UInt<2>(0h2), remapindex_22)
when _T_3036 :
connect remapVecData[22], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[22]
node _T_3037 = eq(UInt<2>(0h3), remapindex_22)
when _T_3037 :
connect remapVecData[22], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[22]
node _T_3038 = eq(UInt<3>(0h4), remapindex_22)
when _T_3038 :
connect remapVecData[22], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[22]
node _T_3039 = eq(UInt<3>(0h5), remapindex_22)
when _T_3039 :
connect remapVecData[22], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[22]
node _T_3040 = eq(UInt<3>(0h6), remapindex_22)
when _T_3040 :
connect remapVecData[22], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[22]
node _T_3041 = eq(UInt<3>(0h7), remapindex_22)
when _T_3041 :
connect remapVecData[22], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[22]
node _T_3042 = eq(UInt<4>(0h8), remapindex_22)
when _T_3042 :
connect remapVecData[22], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[22]
node _T_3043 = eq(UInt<4>(0h9), remapindex_22)
when _T_3043 :
connect remapVecData[22], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[22]
node _T_3044 = eq(UInt<4>(0ha), remapindex_22)
when _T_3044 :
connect remapVecData[22], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[22]
node _T_3045 = eq(UInt<4>(0hb), remapindex_22)
when _T_3045 :
connect remapVecData[22], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[22]
node _T_3046 = eq(UInt<4>(0hc), remapindex_22)
when _T_3046 :
connect remapVecData[22], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[22]
node _T_3047 = eq(UInt<4>(0hd), remapindex_22)
when _T_3047 :
connect remapVecData[22], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[22]
node _T_3048 = eq(UInt<4>(0he), remapindex_22)
when _T_3048 :
connect remapVecData[22], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[22]
node _T_3049 = eq(UInt<4>(0hf), remapindex_22)
when _T_3049 :
connect remapVecData[22], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[22]
node _T_3050 = eq(UInt<5>(0h10), remapindex_22)
when _T_3050 :
connect remapVecData[22], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[22]
node _T_3051 = eq(UInt<5>(0h11), remapindex_22)
when _T_3051 :
connect remapVecData[22], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[22]
node _T_3052 = eq(UInt<5>(0h12), remapindex_22)
when _T_3052 :
connect remapVecData[22], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[22]
node _T_3053 = eq(UInt<5>(0h13), remapindex_22)
when _T_3053 :
connect remapVecData[22], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[22]
node _T_3054 = eq(UInt<5>(0h14), remapindex_22)
when _T_3054 :
connect remapVecData[22], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[22]
node _T_3055 = eq(UInt<5>(0h15), remapindex_22)
when _T_3055 :
connect remapVecData[22], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[22]
node _T_3056 = eq(UInt<5>(0h16), remapindex_22)
when _T_3056 :
connect remapVecData[22], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[22]
node _T_3057 = eq(UInt<5>(0h17), remapindex_22)
when _T_3057 :
connect remapVecData[22], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[22]
node _T_3058 = eq(UInt<5>(0h18), remapindex_22)
when _T_3058 :
connect remapVecData[22], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[22]
node _T_3059 = eq(UInt<5>(0h19), remapindex_22)
when _T_3059 :
connect remapVecData[22], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[22]
node _T_3060 = eq(UInt<5>(0h1a), remapindex_22)
when _T_3060 :
connect remapVecData[22], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[22]
node _T_3061 = eq(UInt<5>(0h1b), remapindex_22)
when _T_3061 :
connect remapVecData[22], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[22]
node _T_3062 = eq(UInt<5>(0h1c), remapindex_22)
when _T_3062 :
connect remapVecData[22], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[22]
node _T_3063 = eq(UInt<5>(0h1d), remapindex_22)
when _T_3063 :
connect remapVecData[22], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[22]
node _T_3064 = eq(UInt<5>(0h1e), remapindex_22)
when _T_3064 :
connect remapVecData[22], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[22]
node _T_3065 = eq(UInt<5>(0h1f), remapindex_22)
when _T_3065 :
connect remapVecData[22], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[22], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[22]
node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index)
node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20))
node _T_3066 = eq(UInt<1>(0h0), remapindex_23)
when _T_3066 :
connect remapVecData[23], Queue64_UInt8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[23]
node _T_3067 = eq(UInt<1>(0h1), remapindex_23)
when _T_3067 :
connect remapVecData[23], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[23]
node _T_3068 = eq(UInt<2>(0h2), remapindex_23)
when _T_3068 :
connect remapVecData[23], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[23]
node _T_3069 = eq(UInt<2>(0h3), remapindex_23)
when _T_3069 :
connect remapVecData[23], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[23]
node _T_3070 = eq(UInt<3>(0h4), remapindex_23)
when _T_3070 :
connect remapVecData[23], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[23]
node _T_3071 = eq(UInt<3>(0h5), remapindex_23)
when _T_3071 :
connect remapVecData[23], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[23]
node _T_3072 = eq(UInt<3>(0h6), remapindex_23)
when _T_3072 :
connect remapVecData[23], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[23]
node _T_3073 = eq(UInt<3>(0h7), remapindex_23)
when _T_3073 :
connect remapVecData[23], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[23]
node _T_3074 = eq(UInt<4>(0h8), remapindex_23)
when _T_3074 :
connect remapVecData[23], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[23]
node _T_3075 = eq(UInt<4>(0h9), remapindex_23)
when _T_3075 :
connect remapVecData[23], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[23]
node _T_3076 = eq(UInt<4>(0ha), remapindex_23)
when _T_3076 :
connect remapVecData[23], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[23]
node _T_3077 = eq(UInt<4>(0hb), remapindex_23)
when _T_3077 :
connect remapVecData[23], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[23]
node _T_3078 = eq(UInt<4>(0hc), remapindex_23)
when _T_3078 :
connect remapVecData[23], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[23]
node _T_3079 = eq(UInt<4>(0hd), remapindex_23)
when _T_3079 :
connect remapVecData[23], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[23]
node _T_3080 = eq(UInt<4>(0he), remapindex_23)
when _T_3080 :
connect remapVecData[23], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[23]
node _T_3081 = eq(UInt<4>(0hf), remapindex_23)
when _T_3081 :
connect remapVecData[23], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[23]
node _T_3082 = eq(UInt<5>(0h10), remapindex_23)
when _T_3082 :
connect remapVecData[23], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[23]
node _T_3083 = eq(UInt<5>(0h11), remapindex_23)
when _T_3083 :
connect remapVecData[23], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[23]
node _T_3084 = eq(UInt<5>(0h12), remapindex_23)
when _T_3084 :
connect remapVecData[23], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[23]
node _T_3085 = eq(UInt<5>(0h13), remapindex_23)
when _T_3085 :
connect remapVecData[23], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[23]
node _T_3086 = eq(UInt<5>(0h14), remapindex_23)
when _T_3086 :
connect remapVecData[23], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[23]
node _T_3087 = eq(UInt<5>(0h15), remapindex_23)
when _T_3087 :
connect remapVecData[23], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[23]
node _T_3088 = eq(UInt<5>(0h16), remapindex_23)
when _T_3088 :
connect remapVecData[23], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[23]
node _T_3089 = eq(UInt<5>(0h17), remapindex_23)
when _T_3089 :
connect remapVecData[23], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[23]
node _T_3090 = eq(UInt<5>(0h18), remapindex_23)
when _T_3090 :
connect remapVecData[23], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[23]
node _T_3091 = eq(UInt<5>(0h19), remapindex_23)
when _T_3091 :
connect remapVecData[23], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[23]
node _T_3092 = eq(UInt<5>(0h1a), remapindex_23)
when _T_3092 :
connect remapVecData[23], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[23]
node _T_3093 = eq(UInt<5>(0h1b), remapindex_23)
when _T_3093 :
connect remapVecData[23], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[23]
node _T_3094 = eq(UInt<5>(0h1c), remapindex_23)
when _T_3094 :
connect remapVecData[23], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[23]
node _T_3095 = eq(UInt<5>(0h1d), remapindex_23)
when _T_3095 :
connect remapVecData[23], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[23]
node _T_3096 = eq(UInt<5>(0h1e), remapindex_23)
when _T_3096 :
connect remapVecData[23], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[23]
node _T_3097 = eq(UInt<5>(0h1f), remapindex_23)
when _T_3097 :
connect remapVecData[23], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[23], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[23]
node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index)
node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20))
node _T_3098 = eq(UInt<1>(0h0), remapindex_24)
when _T_3098 :
connect remapVecData[24], Queue64_UInt8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[24]
node _T_3099 = eq(UInt<1>(0h1), remapindex_24)
when _T_3099 :
connect remapVecData[24], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[24]
node _T_3100 = eq(UInt<2>(0h2), remapindex_24)
when _T_3100 :
connect remapVecData[24], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[24]
node _T_3101 = eq(UInt<2>(0h3), remapindex_24)
when _T_3101 :
connect remapVecData[24], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[24]
node _T_3102 = eq(UInt<3>(0h4), remapindex_24)
when _T_3102 :
connect remapVecData[24], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[24]
node _T_3103 = eq(UInt<3>(0h5), remapindex_24)
when _T_3103 :
connect remapVecData[24], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[24]
node _T_3104 = eq(UInt<3>(0h6), remapindex_24)
when _T_3104 :
connect remapVecData[24], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[24]
node _T_3105 = eq(UInt<3>(0h7), remapindex_24)
when _T_3105 :
connect remapVecData[24], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[24]
node _T_3106 = eq(UInt<4>(0h8), remapindex_24)
when _T_3106 :
connect remapVecData[24], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[24]
node _T_3107 = eq(UInt<4>(0h9), remapindex_24)
when _T_3107 :
connect remapVecData[24], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[24]
node _T_3108 = eq(UInt<4>(0ha), remapindex_24)
when _T_3108 :
connect remapVecData[24], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[24]
node _T_3109 = eq(UInt<4>(0hb), remapindex_24)
when _T_3109 :
connect remapVecData[24], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[24]
node _T_3110 = eq(UInt<4>(0hc), remapindex_24)
when _T_3110 :
connect remapVecData[24], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[24]
node _T_3111 = eq(UInt<4>(0hd), remapindex_24)
when _T_3111 :
connect remapVecData[24], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[24]
node _T_3112 = eq(UInt<4>(0he), remapindex_24)
when _T_3112 :
connect remapVecData[24], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[24]
node _T_3113 = eq(UInt<4>(0hf), remapindex_24)
when _T_3113 :
connect remapVecData[24], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[24]
node _T_3114 = eq(UInt<5>(0h10), remapindex_24)
when _T_3114 :
connect remapVecData[24], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[24]
node _T_3115 = eq(UInt<5>(0h11), remapindex_24)
when _T_3115 :
connect remapVecData[24], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[24]
node _T_3116 = eq(UInt<5>(0h12), remapindex_24)
when _T_3116 :
connect remapVecData[24], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[24]
node _T_3117 = eq(UInt<5>(0h13), remapindex_24)
when _T_3117 :
connect remapVecData[24], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[24]
node _T_3118 = eq(UInt<5>(0h14), remapindex_24)
when _T_3118 :
connect remapVecData[24], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[24]
node _T_3119 = eq(UInt<5>(0h15), remapindex_24)
when _T_3119 :
connect remapVecData[24], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[24]
node _T_3120 = eq(UInt<5>(0h16), remapindex_24)
when _T_3120 :
connect remapVecData[24], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[24]
node _T_3121 = eq(UInt<5>(0h17), remapindex_24)
when _T_3121 :
connect remapVecData[24], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[24]
node _T_3122 = eq(UInt<5>(0h18), remapindex_24)
when _T_3122 :
connect remapVecData[24], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[24]
node _T_3123 = eq(UInt<5>(0h19), remapindex_24)
when _T_3123 :
connect remapVecData[24], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[24]
node _T_3124 = eq(UInt<5>(0h1a), remapindex_24)
when _T_3124 :
connect remapVecData[24], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[24]
node _T_3125 = eq(UInt<5>(0h1b), remapindex_24)
when _T_3125 :
connect remapVecData[24], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[24]
node _T_3126 = eq(UInt<5>(0h1c), remapindex_24)
when _T_3126 :
connect remapVecData[24], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[24]
node _T_3127 = eq(UInt<5>(0h1d), remapindex_24)
when _T_3127 :
connect remapVecData[24], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[24]
node _T_3128 = eq(UInt<5>(0h1e), remapindex_24)
when _T_3128 :
connect remapVecData[24], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[24]
node _T_3129 = eq(UInt<5>(0h1f), remapindex_24)
when _T_3129 :
connect remapVecData[24], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[24], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[24]
node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index)
node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20))
node _T_3130 = eq(UInt<1>(0h0), remapindex_25)
when _T_3130 :
connect remapVecData[25], Queue64_UInt8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[25]
node _T_3131 = eq(UInt<1>(0h1), remapindex_25)
when _T_3131 :
connect remapVecData[25], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[25]
node _T_3132 = eq(UInt<2>(0h2), remapindex_25)
when _T_3132 :
connect remapVecData[25], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[25]
node _T_3133 = eq(UInt<2>(0h3), remapindex_25)
when _T_3133 :
connect remapVecData[25], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[25]
node _T_3134 = eq(UInt<3>(0h4), remapindex_25)
when _T_3134 :
connect remapVecData[25], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[25]
node _T_3135 = eq(UInt<3>(0h5), remapindex_25)
when _T_3135 :
connect remapVecData[25], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[25]
node _T_3136 = eq(UInt<3>(0h6), remapindex_25)
when _T_3136 :
connect remapVecData[25], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[25]
node _T_3137 = eq(UInt<3>(0h7), remapindex_25)
when _T_3137 :
connect remapVecData[25], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[25]
node _T_3138 = eq(UInt<4>(0h8), remapindex_25)
when _T_3138 :
connect remapVecData[25], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[25]
node _T_3139 = eq(UInt<4>(0h9), remapindex_25)
when _T_3139 :
connect remapVecData[25], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[25]
node _T_3140 = eq(UInt<4>(0ha), remapindex_25)
when _T_3140 :
connect remapVecData[25], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[25]
node _T_3141 = eq(UInt<4>(0hb), remapindex_25)
when _T_3141 :
connect remapVecData[25], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[25]
node _T_3142 = eq(UInt<4>(0hc), remapindex_25)
when _T_3142 :
connect remapVecData[25], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[25]
node _T_3143 = eq(UInt<4>(0hd), remapindex_25)
when _T_3143 :
connect remapVecData[25], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[25]
node _T_3144 = eq(UInt<4>(0he), remapindex_25)
when _T_3144 :
connect remapVecData[25], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[25]
node _T_3145 = eq(UInt<4>(0hf), remapindex_25)
when _T_3145 :
connect remapVecData[25], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[25]
node _T_3146 = eq(UInt<5>(0h10), remapindex_25)
when _T_3146 :
connect remapVecData[25], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[25]
node _T_3147 = eq(UInt<5>(0h11), remapindex_25)
when _T_3147 :
connect remapVecData[25], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[25]
node _T_3148 = eq(UInt<5>(0h12), remapindex_25)
when _T_3148 :
connect remapVecData[25], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[25]
node _T_3149 = eq(UInt<5>(0h13), remapindex_25)
when _T_3149 :
connect remapVecData[25], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[25]
node _T_3150 = eq(UInt<5>(0h14), remapindex_25)
when _T_3150 :
connect remapVecData[25], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[25]
node _T_3151 = eq(UInt<5>(0h15), remapindex_25)
when _T_3151 :
connect remapVecData[25], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[25]
node _T_3152 = eq(UInt<5>(0h16), remapindex_25)
when _T_3152 :
connect remapVecData[25], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[25]
node _T_3153 = eq(UInt<5>(0h17), remapindex_25)
when _T_3153 :
connect remapVecData[25], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[25]
node _T_3154 = eq(UInt<5>(0h18), remapindex_25)
when _T_3154 :
connect remapVecData[25], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[25]
node _T_3155 = eq(UInt<5>(0h19), remapindex_25)
when _T_3155 :
connect remapVecData[25], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[25]
node _T_3156 = eq(UInt<5>(0h1a), remapindex_25)
when _T_3156 :
connect remapVecData[25], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[25]
node _T_3157 = eq(UInt<5>(0h1b), remapindex_25)
when _T_3157 :
connect remapVecData[25], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[25]
node _T_3158 = eq(UInt<5>(0h1c), remapindex_25)
when _T_3158 :
connect remapVecData[25], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[25]
node _T_3159 = eq(UInt<5>(0h1d), remapindex_25)
when _T_3159 :
connect remapVecData[25], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[25]
node _T_3160 = eq(UInt<5>(0h1e), remapindex_25)
when _T_3160 :
connect remapVecData[25], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[25]
node _T_3161 = eq(UInt<5>(0h1f), remapindex_25)
when _T_3161 :
connect remapVecData[25], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[25], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[25]
node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index)
node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20))
node _T_3162 = eq(UInt<1>(0h0), remapindex_26)
when _T_3162 :
connect remapVecData[26], Queue64_UInt8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[26]
node _T_3163 = eq(UInt<1>(0h1), remapindex_26)
when _T_3163 :
connect remapVecData[26], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[26]
node _T_3164 = eq(UInt<2>(0h2), remapindex_26)
when _T_3164 :
connect remapVecData[26], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[26]
node _T_3165 = eq(UInt<2>(0h3), remapindex_26)
when _T_3165 :
connect remapVecData[26], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[26]
node _T_3166 = eq(UInt<3>(0h4), remapindex_26)
when _T_3166 :
connect remapVecData[26], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[26]
node _T_3167 = eq(UInt<3>(0h5), remapindex_26)
when _T_3167 :
connect remapVecData[26], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[26]
node _T_3168 = eq(UInt<3>(0h6), remapindex_26)
when _T_3168 :
connect remapVecData[26], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[26]
node _T_3169 = eq(UInt<3>(0h7), remapindex_26)
when _T_3169 :
connect remapVecData[26], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[26]
node _T_3170 = eq(UInt<4>(0h8), remapindex_26)
when _T_3170 :
connect remapVecData[26], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[26]
node _T_3171 = eq(UInt<4>(0h9), remapindex_26)
when _T_3171 :
connect remapVecData[26], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[26]
node _T_3172 = eq(UInt<4>(0ha), remapindex_26)
when _T_3172 :
connect remapVecData[26], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[26]
node _T_3173 = eq(UInt<4>(0hb), remapindex_26)
when _T_3173 :
connect remapVecData[26], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[26]
node _T_3174 = eq(UInt<4>(0hc), remapindex_26)
when _T_3174 :
connect remapVecData[26], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[26]
node _T_3175 = eq(UInt<4>(0hd), remapindex_26)
when _T_3175 :
connect remapVecData[26], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[26]
node _T_3176 = eq(UInt<4>(0he), remapindex_26)
when _T_3176 :
connect remapVecData[26], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[26]
node _T_3177 = eq(UInt<4>(0hf), remapindex_26)
when _T_3177 :
connect remapVecData[26], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[26]
node _T_3178 = eq(UInt<5>(0h10), remapindex_26)
when _T_3178 :
connect remapVecData[26], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[26]
node _T_3179 = eq(UInt<5>(0h11), remapindex_26)
when _T_3179 :
connect remapVecData[26], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[26]
node _T_3180 = eq(UInt<5>(0h12), remapindex_26)
when _T_3180 :
connect remapVecData[26], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[26]
node _T_3181 = eq(UInt<5>(0h13), remapindex_26)
when _T_3181 :
connect remapVecData[26], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[26]
node _T_3182 = eq(UInt<5>(0h14), remapindex_26)
when _T_3182 :
connect remapVecData[26], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[26]
node _T_3183 = eq(UInt<5>(0h15), remapindex_26)
when _T_3183 :
connect remapVecData[26], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[26]
node _T_3184 = eq(UInt<5>(0h16), remapindex_26)
when _T_3184 :
connect remapVecData[26], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[26]
node _T_3185 = eq(UInt<5>(0h17), remapindex_26)
when _T_3185 :
connect remapVecData[26], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[26]
node _T_3186 = eq(UInt<5>(0h18), remapindex_26)
when _T_3186 :
connect remapVecData[26], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[26]
node _T_3187 = eq(UInt<5>(0h19), remapindex_26)
when _T_3187 :
connect remapVecData[26], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[26]
node _T_3188 = eq(UInt<5>(0h1a), remapindex_26)
when _T_3188 :
connect remapVecData[26], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[26]
node _T_3189 = eq(UInt<5>(0h1b), remapindex_26)
when _T_3189 :
connect remapVecData[26], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[26]
node _T_3190 = eq(UInt<5>(0h1c), remapindex_26)
when _T_3190 :
connect remapVecData[26], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[26]
node _T_3191 = eq(UInt<5>(0h1d), remapindex_26)
when _T_3191 :
connect remapVecData[26], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[26]
node _T_3192 = eq(UInt<5>(0h1e), remapindex_26)
when _T_3192 :
connect remapVecData[26], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[26]
node _T_3193 = eq(UInt<5>(0h1f), remapindex_26)
when _T_3193 :
connect remapVecData[26], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[26], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[26]
node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index)
node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20))
node _T_3194 = eq(UInt<1>(0h0), remapindex_27)
when _T_3194 :
connect remapVecData[27], Queue64_UInt8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[27]
node _T_3195 = eq(UInt<1>(0h1), remapindex_27)
when _T_3195 :
connect remapVecData[27], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[27]
node _T_3196 = eq(UInt<2>(0h2), remapindex_27)
when _T_3196 :
connect remapVecData[27], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[27]
node _T_3197 = eq(UInt<2>(0h3), remapindex_27)
when _T_3197 :
connect remapVecData[27], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[27]
node _T_3198 = eq(UInt<3>(0h4), remapindex_27)
when _T_3198 :
connect remapVecData[27], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[27]
node _T_3199 = eq(UInt<3>(0h5), remapindex_27)
when _T_3199 :
connect remapVecData[27], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[27]
node _T_3200 = eq(UInt<3>(0h6), remapindex_27)
when _T_3200 :
connect remapVecData[27], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[27]
node _T_3201 = eq(UInt<3>(0h7), remapindex_27)
when _T_3201 :
connect remapVecData[27], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[27]
node _T_3202 = eq(UInt<4>(0h8), remapindex_27)
when _T_3202 :
connect remapVecData[27], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[27]
node _T_3203 = eq(UInt<4>(0h9), remapindex_27)
when _T_3203 :
connect remapVecData[27], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[27]
node _T_3204 = eq(UInt<4>(0ha), remapindex_27)
when _T_3204 :
connect remapVecData[27], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[27]
node _T_3205 = eq(UInt<4>(0hb), remapindex_27)
when _T_3205 :
connect remapVecData[27], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[27]
node _T_3206 = eq(UInt<4>(0hc), remapindex_27)
when _T_3206 :
connect remapVecData[27], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[27]
node _T_3207 = eq(UInt<4>(0hd), remapindex_27)
when _T_3207 :
connect remapVecData[27], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[27]
node _T_3208 = eq(UInt<4>(0he), remapindex_27)
when _T_3208 :
connect remapVecData[27], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[27]
node _T_3209 = eq(UInt<4>(0hf), remapindex_27)
when _T_3209 :
connect remapVecData[27], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[27]
node _T_3210 = eq(UInt<5>(0h10), remapindex_27)
when _T_3210 :
connect remapVecData[27], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[27]
node _T_3211 = eq(UInt<5>(0h11), remapindex_27)
when _T_3211 :
connect remapVecData[27], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[27]
node _T_3212 = eq(UInt<5>(0h12), remapindex_27)
when _T_3212 :
connect remapVecData[27], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[27]
node _T_3213 = eq(UInt<5>(0h13), remapindex_27)
when _T_3213 :
connect remapVecData[27], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[27]
node _T_3214 = eq(UInt<5>(0h14), remapindex_27)
when _T_3214 :
connect remapVecData[27], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[27]
node _T_3215 = eq(UInt<5>(0h15), remapindex_27)
when _T_3215 :
connect remapVecData[27], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[27]
node _T_3216 = eq(UInt<5>(0h16), remapindex_27)
when _T_3216 :
connect remapVecData[27], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[27]
node _T_3217 = eq(UInt<5>(0h17), remapindex_27)
when _T_3217 :
connect remapVecData[27], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[27]
node _T_3218 = eq(UInt<5>(0h18), remapindex_27)
when _T_3218 :
connect remapVecData[27], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[27]
node _T_3219 = eq(UInt<5>(0h19), remapindex_27)
when _T_3219 :
connect remapVecData[27], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[27]
node _T_3220 = eq(UInt<5>(0h1a), remapindex_27)
when _T_3220 :
connect remapVecData[27], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[27]
node _T_3221 = eq(UInt<5>(0h1b), remapindex_27)
when _T_3221 :
connect remapVecData[27], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[27]
node _T_3222 = eq(UInt<5>(0h1c), remapindex_27)
when _T_3222 :
connect remapVecData[27], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[27]
node _T_3223 = eq(UInt<5>(0h1d), remapindex_27)
when _T_3223 :
connect remapVecData[27], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[27]
node _T_3224 = eq(UInt<5>(0h1e), remapindex_27)
when _T_3224 :
connect remapVecData[27], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[27]
node _T_3225 = eq(UInt<5>(0h1f), remapindex_27)
when _T_3225 :
connect remapVecData[27], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[27], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[27]
node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index)
node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20))
node _T_3226 = eq(UInt<1>(0h0), remapindex_28)
when _T_3226 :
connect remapVecData[28], Queue64_UInt8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[28]
node _T_3227 = eq(UInt<1>(0h1), remapindex_28)
when _T_3227 :
connect remapVecData[28], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[28]
node _T_3228 = eq(UInt<2>(0h2), remapindex_28)
when _T_3228 :
connect remapVecData[28], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[28]
node _T_3229 = eq(UInt<2>(0h3), remapindex_28)
when _T_3229 :
connect remapVecData[28], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[28]
node _T_3230 = eq(UInt<3>(0h4), remapindex_28)
when _T_3230 :
connect remapVecData[28], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[28]
node _T_3231 = eq(UInt<3>(0h5), remapindex_28)
when _T_3231 :
connect remapVecData[28], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[28]
node _T_3232 = eq(UInt<3>(0h6), remapindex_28)
when _T_3232 :
connect remapVecData[28], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[28]
node _T_3233 = eq(UInt<3>(0h7), remapindex_28)
when _T_3233 :
connect remapVecData[28], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[28]
node _T_3234 = eq(UInt<4>(0h8), remapindex_28)
when _T_3234 :
connect remapVecData[28], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[28]
node _T_3235 = eq(UInt<4>(0h9), remapindex_28)
when _T_3235 :
connect remapVecData[28], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[28]
node _T_3236 = eq(UInt<4>(0ha), remapindex_28)
when _T_3236 :
connect remapVecData[28], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[28]
node _T_3237 = eq(UInt<4>(0hb), remapindex_28)
when _T_3237 :
connect remapVecData[28], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[28]
node _T_3238 = eq(UInt<4>(0hc), remapindex_28)
when _T_3238 :
connect remapVecData[28], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[28]
node _T_3239 = eq(UInt<4>(0hd), remapindex_28)
when _T_3239 :
connect remapVecData[28], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[28]
node _T_3240 = eq(UInt<4>(0he), remapindex_28)
when _T_3240 :
connect remapVecData[28], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[28]
node _T_3241 = eq(UInt<4>(0hf), remapindex_28)
when _T_3241 :
connect remapVecData[28], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[28]
node _T_3242 = eq(UInt<5>(0h10), remapindex_28)
when _T_3242 :
connect remapVecData[28], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[28]
node _T_3243 = eq(UInt<5>(0h11), remapindex_28)
when _T_3243 :
connect remapVecData[28], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[28]
node _T_3244 = eq(UInt<5>(0h12), remapindex_28)
when _T_3244 :
connect remapVecData[28], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[28]
node _T_3245 = eq(UInt<5>(0h13), remapindex_28)
when _T_3245 :
connect remapVecData[28], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[28]
node _T_3246 = eq(UInt<5>(0h14), remapindex_28)
when _T_3246 :
connect remapVecData[28], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[28]
node _T_3247 = eq(UInt<5>(0h15), remapindex_28)
when _T_3247 :
connect remapVecData[28], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[28]
node _T_3248 = eq(UInt<5>(0h16), remapindex_28)
when _T_3248 :
connect remapVecData[28], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[28]
node _T_3249 = eq(UInt<5>(0h17), remapindex_28)
when _T_3249 :
connect remapVecData[28], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[28]
node _T_3250 = eq(UInt<5>(0h18), remapindex_28)
when _T_3250 :
connect remapVecData[28], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[28]
node _T_3251 = eq(UInt<5>(0h19), remapindex_28)
when _T_3251 :
connect remapVecData[28], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[28]
node _T_3252 = eq(UInt<5>(0h1a), remapindex_28)
when _T_3252 :
connect remapVecData[28], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[28]
node _T_3253 = eq(UInt<5>(0h1b), remapindex_28)
when _T_3253 :
connect remapVecData[28], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[28]
node _T_3254 = eq(UInt<5>(0h1c), remapindex_28)
when _T_3254 :
connect remapVecData[28], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[28]
node _T_3255 = eq(UInt<5>(0h1d), remapindex_28)
when _T_3255 :
connect remapVecData[28], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[28]
node _T_3256 = eq(UInt<5>(0h1e), remapindex_28)
when _T_3256 :
connect remapVecData[28], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[28]
node _T_3257 = eq(UInt<5>(0h1f), remapindex_28)
when _T_3257 :
connect remapVecData[28], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[28], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[28]
node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index)
node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20))
node _T_3258 = eq(UInt<1>(0h0), remapindex_29)
when _T_3258 :
connect remapVecData[29], Queue64_UInt8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[29]
node _T_3259 = eq(UInt<1>(0h1), remapindex_29)
when _T_3259 :
connect remapVecData[29], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[29]
node _T_3260 = eq(UInt<2>(0h2), remapindex_29)
when _T_3260 :
connect remapVecData[29], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[29]
node _T_3261 = eq(UInt<2>(0h3), remapindex_29)
when _T_3261 :
connect remapVecData[29], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[29]
node _T_3262 = eq(UInt<3>(0h4), remapindex_29)
when _T_3262 :
connect remapVecData[29], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[29]
node _T_3263 = eq(UInt<3>(0h5), remapindex_29)
when _T_3263 :
connect remapVecData[29], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[29]
node _T_3264 = eq(UInt<3>(0h6), remapindex_29)
when _T_3264 :
connect remapVecData[29], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[29]
node _T_3265 = eq(UInt<3>(0h7), remapindex_29)
when _T_3265 :
connect remapVecData[29], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[29]
node _T_3266 = eq(UInt<4>(0h8), remapindex_29)
when _T_3266 :
connect remapVecData[29], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[29]
node _T_3267 = eq(UInt<4>(0h9), remapindex_29)
when _T_3267 :
connect remapVecData[29], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[29]
node _T_3268 = eq(UInt<4>(0ha), remapindex_29)
when _T_3268 :
connect remapVecData[29], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[29]
node _T_3269 = eq(UInt<4>(0hb), remapindex_29)
when _T_3269 :
connect remapVecData[29], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[29]
node _T_3270 = eq(UInt<4>(0hc), remapindex_29)
when _T_3270 :
connect remapVecData[29], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[29]
node _T_3271 = eq(UInt<4>(0hd), remapindex_29)
when _T_3271 :
connect remapVecData[29], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[29]
node _T_3272 = eq(UInt<4>(0he), remapindex_29)
when _T_3272 :
connect remapVecData[29], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[29]
node _T_3273 = eq(UInt<4>(0hf), remapindex_29)
when _T_3273 :
connect remapVecData[29], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[29]
node _T_3274 = eq(UInt<5>(0h10), remapindex_29)
when _T_3274 :
connect remapVecData[29], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[29]
node _T_3275 = eq(UInt<5>(0h11), remapindex_29)
when _T_3275 :
connect remapVecData[29], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[29]
node _T_3276 = eq(UInt<5>(0h12), remapindex_29)
when _T_3276 :
connect remapVecData[29], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[29]
node _T_3277 = eq(UInt<5>(0h13), remapindex_29)
when _T_3277 :
connect remapVecData[29], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[29]
node _T_3278 = eq(UInt<5>(0h14), remapindex_29)
when _T_3278 :
connect remapVecData[29], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[29]
node _T_3279 = eq(UInt<5>(0h15), remapindex_29)
when _T_3279 :
connect remapVecData[29], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[29]
node _T_3280 = eq(UInt<5>(0h16), remapindex_29)
when _T_3280 :
connect remapVecData[29], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[29]
node _T_3281 = eq(UInt<5>(0h17), remapindex_29)
when _T_3281 :
connect remapVecData[29], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[29]
node _T_3282 = eq(UInt<5>(0h18), remapindex_29)
when _T_3282 :
connect remapVecData[29], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[29]
node _T_3283 = eq(UInt<5>(0h19), remapindex_29)
when _T_3283 :
connect remapVecData[29], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[29]
node _T_3284 = eq(UInt<5>(0h1a), remapindex_29)
when _T_3284 :
connect remapVecData[29], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[29]
node _T_3285 = eq(UInt<5>(0h1b), remapindex_29)
when _T_3285 :
connect remapVecData[29], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[29]
node _T_3286 = eq(UInt<5>(0h1c), remapindex_29)
when _T_3286 :
connect remapVecData[29], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[29]
node _T_3287 = eq(UInt<5>(0h1d), remapindex_29)
when _T_3287 :
connect remapVecData[29], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[29]
node _T_3288 = eq(UInt<5>(0h1e), remapindex_29)
when _T_3288 :
connect remapVecData[29], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[29]
node _T_3289 = eq(UInt<5>(0h1f), remapindex_29)
when _T_3289 :
connect remapVecData[29], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[29], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[29]
node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index)
node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20))
node _T_3290 = eq(UInt<1>(0h0), remapindex_30)
when _T_3290 :
connect remapVecData[30], Queue64_UInt8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[30]
node _T_3291 = eq(UInt<1>(0h1), remapindex_30)
when _T_3291 :
connect remapVecData[30], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[30]
node _T_3292 = eq(UInt<2>(0h2), remapindex_30)
when _T_3292 :
connect remapVecData[30], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[30]
node _T_3293 = eq(UInt<2>(0h3), remapindex_30)
when _T_3293 :
connect remapVecData[30], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[30]
node _T_3294 = eq(UInt<3>(0h4), remapindex_30)
when _T_3294 :
connect remapVecData[30], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[30]
node _T_3295 = eq(UInt<3>(0h5), remapindex_30)
when _T_3295 :
connect remapVecData[30], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[30]
node _T_3296 = eq(UInt<3>(0h6), remapindex_30)
when _T_3296 :
connect remapVecData[30], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[30]
node _T_3297 = eq(UInt<3>(0h7), remapindex_30)
when _T_3297 :
connect remapVecData[30], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[30]
node _T_3298 = eq(UInt<4>(0h8), remapindex_30)
when _T_3298 :
connect remapVecData[30], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[30]
node _T_3299 = eq(UInt<4>(0h9), remapindex_30)
when _T_3299 :
connect remapVecData[30], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[30]
node _T_3300 = eq(UInt<4>(0ha), remapindex_30)
when _T_3300 :
connect remapVecData[30], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[30]
node _T_3301 = eq(UInt<4>(0hb), remapindex_30)
when _T_3301 :
connect remapVecData[30], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[30]
node _T_3302 = eq(UInt<4>(0hc), remapindex_30)
when _T_3302 :
connect remapVecData[30], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[30]
node _T_3303 = eq(UInt<4>(0hd), remapindex_30)
when _T_3303 :
connect remapVecData[30], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[30]
node _T_3304 = eq(UInt<4>(0he), remapindex_30)
when _T_3304 :
connect remapVecData[30], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[30]
node _T_3305 = eq(UInt<4>(0hf), remapindex_30)
when _T_3305 :
connect remapVecData[30], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[30]
node _T_3306 = eq(UInt<5>(0h10), remapindex_30)
when _T_3306 :
connect remapVecData[30], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[30]
node _T_3307 = eq(UInt<5>(0h11), remapindex_30)
when _T_3307 :
connect remapVecData[30], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[30]
node _T_3308 = eq(UInt<5>(0h12), remapindex_30)
when _T_3308 :
connect remapVecData[30], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[30]
node _T_3309 = eq(UInt<5>(0h13), remapindex_30)
when _T_3309 :
connect remapVecData[30], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[30]
node _T_3310 = eq(UInt<5>(0h14), remapindex_30)
when _T_3310 :
connect remapVecData[30], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[30]
node _T_3311 = eq(UInt<5>(0h15), remapindex_30)
when _T_3311 :
connect remapVecData[30], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[30]
node _T_3312 = eq(UInt<5>(0h16), remapindex_30)
when _T_3312 :
connect remapVecData[30], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[30]
node _T_3313 = eq(UInt<5>(0h17), remapindex_30)
when _T_3313 :
connect remapVecData[30], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[30]
node _T_3314 = eq(UInt<5>(0h18), remapindex_30)
when _T_3314 :
connect remapVecData[30], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[30]
node _T_3315 = eq(UInt<5>(0h19), remapindex_30)
when _T_3315 :
connect remapVecData[30], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[30]
node _T_3316 = eq(UInt<5>(0h1a), remapindex_30)
when _T_3316 :
connect remapVecData[30], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[30]
node _T_3317 = eq(UInt<5>(0h1b), remapindex_30)
when _T_3317 :
connect remapVecData[30], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[30]
node _T_3318 = eq(UInt<5>(0h1c), remapindex_30)
when _T_3318 :
connect remapVecData[30], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[30]
node _T_3319 = eq(UInt<5>(0h1d), remapindex_30)
when _T_3319 :
connect remapVecData[30], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[30]
node _T_3320 = eq(UInt<5>(0h1e), remapindex_30)
when _T_3320 :
connect remapVecData[30], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[30]
node _T_3321 = eq(UInt<5>(0h1f), remapindex_30)
when _T_3321 :
connect remapVecData[30], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[30], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[30]
node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index)
node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20))
node _T_3322 = eq(UInt<1>(0h0), remapindex_31)
when _T_3322 :
connect remapVecData[31], Queue64_UInt8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8.io.deq.valid
connect Queue64_UInt8.io.deq.ready, remapVecReadys[31]
node _T_3323 = eq(UInt<1>(0h1), remapindex_31)
when _T_3323 :
connect remapVecData[31], Queue64_UInt8_1.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_1.io.deq.valid
connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[31]
node _T_3324 = eq(UInt<2>(0h2), remapindex_31)
when _T_3324 :
connect remapVecData[31], Queue64_UInt8_2.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_2.io.deq.valid
connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[31]
node _T_3325 = eq(UInt<2>(0h3), remapindex_31)
when _T_3325 :
connect remapVecData[31], Queue64_UInt8_3.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_3.io.deq.valid
connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[31]
node _T_3326 = eq(UInt<3>(0h4), remapindex_31)
when _T_3326 :
connect remapVecData[31], Queue64_UInt8_4.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_4.io.deq.valid
connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[31]
node _T_3327 = eq(UInt<3>(0h5), remapindex_31)
when _T_3327 :
connect remapVecData[31], Queue64_UInt8_5.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_5.io.deq.valid
connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[31]
node _T_3328 = eq(UInt<3>(0h6), remapindex_31)
when _T_3328 :
connect remapVecData[31], Queue64_UInt8_6.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_6.io.deq.valid
connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[31]
node _T_3329 = eq(UInt<3>(0h7), remapindex_31)
when _T_3329 :
connect remapVecData[31], Queue64_UInt8_7.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_7.io.deq.valid
connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[31]
node _T_3330 = eq(UInt<4>(0h8), remapindex_31)
when _T_3330 :
connect remapVecData[31], Queue64_UInt8_8.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_8.io.deq.valid
connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[31]
node _T_3331 = eq(UInt<4>(0h9), remapindex_31)
when _T_3331 :
connect remapVecData[31], Queue64_UInt8_9.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_9.io.deq.valid
connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[31]
node _T_3332 = eq(UInt<4>(0ha), remapindex_31)
when _T_3332 :
connect remapVecData[31], Queue64_UInt8_10.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_10.io.deq.valid
connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[31]
node _T_3333 = eq(UInt<4>(0hb), remapindex_31)
when _T_3333 :
connect remapVecData[31], Queue64_UInt8_11.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_11.io.deq.valid
connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[31]
node _T_3334 = eq(UInt<4>(0hc), remapindex_31)
when _T_3334 :
connect remapVecData[31], Queue64_UInt8_12.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_12.io.deq.valid
connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[31]
node _T_3335 = eq(UInt<4>(0hd), remapindex_31)
when _T_3335 :
connect remapVecData[31], Queue64_UInt8_13.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_13.io.deq.valid
connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[31]
node _T_3336 = eq(UInt<4>(0he), remapindex_31)
when _T_3336 :
connect remapVecData[31], Queue64_UInt8_14.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_14.io.deq.valid
connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[31]
node _T_3337 = eq(UInt<4>(0hf), remapindex_31)
when _T_3337 :
connect remapVecData[31], Queue64_UInt8_15.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_15.io.deq.valid
connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[31]
node _T_3338 = eq(UInt<5>(0h10), remapindex_31)
when _T_3338 :
connect remapVecData[31], Queue64_UInt8_16.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_16.io.deq.valid
connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[31]
node _T_3339 = eq(UInt<5>(0h11), remapindex_31)
when _T_3339 :
connect remapVecData[31], Queue64_UInt8_17.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_17.io.deq.valid
connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[31]
node _T_3340 = eq(UInt<5>(0h12), remapindex_31)
when _T_3340 :
connect remapVecData[31], Queue64_UInt8_18.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_18.io.deq.valid
connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[31]
node _T_3341 = eq(UInt<5>(0h13), remapindex_31)
when _T_3341 :
connect remapVecData[31], Queue64_UInt8_19.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_19.io.deq.valid
connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[31]
node _T_3342 = eq(UInt<5>(0h14), remapindex_31)
when _T_3342 :
connect remapVecData[31], Queue64_UInt8_20.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_20.io.deq.valid
connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[31]
node _T_3343 = eq(UInt<5>(0h15), remapindex_31)
when _T_3343 :
connect remapVecData[31], Queue64_UInt8_21.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_21.io.deq.valid
connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[31]
node _T_3344 = eq(UInt<5>(0h16), remapindex_31)
when _T_3344 :
connect remapVecData[31], Queue64_UInt8_22.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_22.io.deq.valid
connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[31]
node _T_3345 = eq(UInt<5>(0h17), remapindex_31)
when _T_3345 :
connect remapVecData[31], Queue64_UInt8_23.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_23.io.deq.valid
connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[31]
node _T_3346 = eq(UInt<5>(0h18), remapindex_31)
when _T_3346 :
connect remapVecData[31], Queue64_UInt8_24.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_24.io.deq.valid
connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[31]
node _T_3347 = eq(UInt<5>(0h19), remapindex_31)
when _T_3347 :
connect remapVecData[31], Queue64_UInt8_25.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_25.io.deq.valid
connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[31]
node _T_3348 = eq(UInt<5>(0h1a), remapindex_31)
when _T_3348 :
connect remapVecData[31], Queue64_UInt8_26.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_26.io.deq.valid
connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[31]
node _T_3349 = eq(UInt<5>(0h1b), remapindex_31)
when _T_3349 :
connect remapVecData[31], Queue64_UInt8_27.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_27.io.deq.valid
connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[31]
node _T_3350 = eq(UInt<5>(0h1c), remapindex_31)
when _T_3350 :
connect remapVecData[31], Queue64_UInt8_28.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_28.io.deq.valid
connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[31]
node _T_3351 = eq(UInt<5>(0h1d), remapindex_31)
when _T_3351 :
connect remapVecData[31], Queue64_UInt8_29.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_29.io.deq.valid
connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[31]
node _T_3352 = eq(UInt<5>(0h1e), remapindex_31)
when _T_3352 :
connect remapVecData[31], Queue64_UInt8_30.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_30.io.deq.valid
connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[31]
node _T_3353 = eq(UInt<5>(0h1f), remapindex_31)
when _T_3353 :
connect remapVecData[31], Queue64_UInt8_31.io.deq.bits
connect remapVecValids[31], Queue64_UInt8_31.io.deq.valid
connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[31]
node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0])
node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2])
node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo)
node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4])
node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6])
node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo)
node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo)
node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8])
node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10])
node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo)
node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12])
node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14])
node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo)
node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo)
node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo)
node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16])
node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18])
node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo)
node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20])
node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22])
node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo)
node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo)
node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24])
node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26])
node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo)
node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28])
node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30])
node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo)
node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo)
node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo)
node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo)
connect io.consumer.output_data, _io_consumer_output_data_T
node _buf_last_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _buf_last_T_1 = tail(_buf_last_T, 1)
node buf_last = eq(_buf_last_T_1, buf_info_queue.io.deq.bits.len_bytes)
node _count_valids_T = add(remapVecValids[0], remapVecValids[1])
node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2])
node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3])
node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4])
node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5])
node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6])
node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7])
node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8])
node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9])
node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10])
node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11])
node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12])
node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13])
node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14])
node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15])
node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16])
node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17])
node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18])
node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19])
node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20])
node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21])
node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22])
node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23])
node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24])
node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25])
node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26])
node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27])
node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28])
node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29])
node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30])
node count_valids = add(_count_valids_T_29, remapVecValids[31])
node _unconsumed_bytes_so_far_T = sub(buf_info_queue.io.deq.bits.len_bytes, len_already_consumed)
node unconsumed_bytes_so_far = tail(_unconsumed_bytes_so_far_T, 1)
node _enough_data_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _enough_data_T_1 = eq(count_valids, UInt<6>(0h20))
node _enough_data_T_2 = geq(count_valids, unconsumed_bytes_so_far)
node enough_data = mux(_enough_data_T, _enough_data_T_1, _enough_data_T_2)
node _io_consumer_available_output_bytes_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20))
node _io_consumer_available_output_bytes_T_1 = mux(_io_consumer_available_output_bytes_T, UInt<6>(0h20), unconsumed_bytes_so_far)
connect io.consumer.available_output_bytes, _io_consumer_available_output_bytes_T_1
node _io_consumer_output_last_chunk_T = leq(unconsumed_bytes_so_far, UInt<6>(0h20))
connect io.consumer.output_last_chunk, _io_consumer_output_last_chunk_T
node _T_3354 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3355 = and(_T_3354, enough_data)
when _T_3355 :
regreset loginfo_cycles_44 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_88 = add(loginfo_cycles_44, UInt<1>(0h1))
node _loginfo_cycles_T_89 = tail(_loginfo_cycles_T_88, 1)
connect loginfo_cycles_44, _loginfo_cycles_T_89
node _T_3356 = asUInt(reset)
node _T_3357 = eq(_T_3356, UInt<1>(0h0))
when _T_3357 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_44) : printf_88
node _T_3358 = asUInt(reset)
node _T_3359 = eq(_T_3358, UInt<1>(0h0))
when _T_3359 :
printf(clock, UInt<1>(0h1), "MEMLOADER READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_89
node _io_consumer_output_valid_T = and(buf_info_queue.io.deq.valid, enough_data)
connect io.consumer.output_valid, _io_consumer_output_valid_T
node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes)
node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, enough_data)
node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_2)
connect remapVecReadys[0], _remapVecReadys_0_T_3
node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes)
node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, enough_data)
node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_2)
connect remapVecReadys[1], _remapVecReadys_1_T_3
node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes)
node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, enough_data)
node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_2)
connect remapVecReadys[2], _remapVecReadys_2_T_3
node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes)
node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, enough_data)
node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_2)
connect remapVecReadys[3], _remapVecReadys_3_T_3
node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes)
node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, enough_data)
node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_2)
connect remapVecReadys[4], _remapVecReadys_4_T_3
node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes)
node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, enough_data)
node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_2)
connect remapVecReadys[5], _remapVecReadys_5_T_3
node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes)
node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, enough_data)
node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_2)
connect remapVecReadys[6], _remapVecReadys_6_T_3
node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes)
node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, enough_data)
node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_2)
connect remapVecReadys[7], _remapVecReadys_7_T_3
node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes)
node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, enough_data)
node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_2)
connect remapVecReadys[8], _remapVecReadys_8_T_3
node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes)
node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, enough_data)
node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_2)
connect remapVecReadys[9], _remapVecReadys_9_T_3
node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes)
node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, enough_data)
node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_2)
connect remapVecReadys[10], _remapVecReadys_10_T_3
node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes)
node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, enough_data)
node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_2)
connect remapVecReadys[11], _remapVecReadys_11_T_3
node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes)
node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, enough_data)
node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_2)
connect remapVecReadys[12], _remapVecReadys_12_T_3
node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes)
node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, enough_data)
node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_2)
connect remapVecReadys[13], _remapVecReadys_13_T_3
node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes)
node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, enough_data)
node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_2)
connect remapVecReadys[14], _remapVecReadys_14_T_3
node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes)
node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, enough_data)
node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_2)
connect remapVecReadys[15], _remapVecReadys_15_T_3
node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes)
node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, enough_data)
node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_2)
connect remapVecReadys[16], _remapVecReadys_16_T_3
node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes)
node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, enough_data)
node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_2)
connect remapVecReadys[17], _remapVecReadys_17_T_3
node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes)
node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, enough_data)
node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_2)
connect remapVecReadys[18], _remapVecReadys_18_T_3
node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes)
node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, enough_data)
node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_2)
connect remapVecReadys[19], _remapVecReadys_19_T_3
node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes)
node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, enough_data)
node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_2)
connect remapVecReadys[20], _remapVecReadys_20_T_3
node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes)
node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, enough_data)
node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_2)
connect remapVecReadys[21], _remapVecReadys_21_T_3
node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes)
node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, enough_data)
node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_2)
connect remapVecReadys[22], _remapVecReadys_22_T_3
node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes)
node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, enough_data)
node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_2)
connect remapVecReadys[23], _remapVecReadys_23_T_3
node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes)
node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, enough_data)
node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_2)
connect remapVecReadys[24], _remapVecReadys_24_T_3
node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes)
node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, enough_data)
node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_2)
connect remapVecReadys[25], _remapVecReadys_25_T_3
node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes)
node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, enough_data)
node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_2)
connect remapVecReadys[26], _remapVecReadys_26_T_3
node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes)
node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, enough_data)
node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_2)
connect remapVecReadys[27], _remapVecReadys_27_T_3
node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes)
node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, enough_data)
node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_2)
connect remapVecReadys[28], _remapVecReadys_28_T_3
node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes)
node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, enough_data)
node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_2)
connect remapVecReadys[29], _remapVecReadys_29_T_3
node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes)
node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, enough_data)
node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_2)
connect remapVecReadys[30], _remapVecReadys_30_T_3
node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes)
node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, enough_data)
node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_2)
connect remapVecReadys[31], _remapVecReadys_31_T_3
node _T_3360 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3361 = and(_T_3360, enough_data)
when _T_3361 :
node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes)
node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20))
connect read_start_index, _read_start_index_T_1
node _buf_info_queue_io_deq_ready_T = and(io.consumer.output_ready, enough_data)
node _buf_info_queue_io_deq_ready_T_1 = and(_buf_info_queue_io_deq_ready_T, buf_last)
connect buf_info_queue.io.deq.ready, _buf_info_queue_io_deq_ready_T_1
node _T_3362 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid)
node _T_3363 = and(_T_3362, enough_data)
when _T_3363 :
when buf_last :
connect len_already_consumed, UInt<1>(0h0)
else :
node _len_already_consumed_T = add(len_already_consumed, io.consumer.user_consumed_bytes)
node _len_already_consumed_T_1 = tail(_len_already_consumed_T, 1)
connect len_already_consumed, _len_already_consumed_T_1 | module MemLoader( // @[MemLoader.scala:15:7]
input clock, // @[MemLoader.scala:15:7]
input reset, // @[MemLoader.scala:15:7]
input io_l2helperUser_req_ready, // @[MemLoader.scala:18:14]
output io_l2helperUser_req_valid, // @[MemLoader.scala:18:14]
output [70:0] io_l2helperUser_req_bits_addr, // @[MemLoader.scala:18:14]
output io_l2helperUser_resp_ready, // @[MemLoader.scala:18:14]
input io_l2helperUser_resp_valid, // @[MemLoader.scala:18:14]
input [255:0] io_l2helperUser_resp_bits_data, // @[MemLoader.scala:18:14]
input io_l2helperUser_no_memops_inflight, // @[MemLoader.scala:18:14]
output io_src_info_ready, // @[MemLoader.scala:18:14]
input io_src_info_valid, // @[MemLoader.scala:18:14]
input [63:0] io_src_info_bits_ip, // @[MemLoader.scala:18:14]
input [63:0] io_src_info_bits_isize, // @[MemLoader.scala:18:14]
input [5:0] io_consumer_user_consumed_bytes, // @[MemLoader.scala:18:14]
output [5:0] io_consumer_available_output_bytes, // @[MemLoader.scala:18:14]
output io_consumer_output_valid, // @[MemLoader.scala:18:14]
input io_consumer_output_ready, // @[MemLoader.scala:18:14]
output [255:0] io_consumer_output_data, // @[MemLoader.scala:18:14]
output io_consumer_output_last_chunk // @[MemLoader.scala:18:14]
);
wire _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_31_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_31_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_30_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_30_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_29_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_29_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_28_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_28_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_27_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_27_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_26_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_26_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_25_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_25_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_24_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_24_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_23_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_23_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_22_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_22_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_21_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_21_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_20_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_20_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_19_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_19_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_18_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_18_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_17_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_17_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_16_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_16_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_15_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_15_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_14_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_14_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_13_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_13_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_12_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_12_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_11_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_11_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_10_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_10_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_9_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_9_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_8_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_8_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_7_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_7_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_6_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_6_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_5_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_5_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_4_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_4_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_3_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_3_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_2_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_2_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_1_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_1_io_deq_bits; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_io_enq_ready; // @[MemLoader.scala:106:52]
wire _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52]
wire [7:0] _Queue64_UInt8_io_deq_bits; // @[MemLoader.scala:106:52]
wire _load_info_queue_io_enq_ready; // @[MemLoader.scala:28:31]
wire _load_info_queue_io_deq_valid; // @[MemLoader.scala:28:31]
wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[MemLoader.scala:28:31]
wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[MemLoader.scala:28:31]
wire _buf_info_queue_io_enq_ready; // @[MemLoader.scala:26:30]
wire _buf_info_queue_io_deq_valid; // @[MemLoader.scala:26:30]
wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30]
wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[MemLoader.scala:15:7]
wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[MemLoader.scala:15:7]
wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[MemLoader.scala:15:7]
wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[MemLoader.scala:15:7]
wire io_src_info_valid_0 = io_src_info_valid; // @[MemLoader.scala:15:7]
wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[MemLoader.scala:15:7]
wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[MemLoader.scala:15:7]
wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[MemLoader.scala:15:7]
wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[MemLoader.scala:15:7]
wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[MemLoader.scala:15:7]
wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_req_bits_cmd = 1'h0; // @[MemLoader.scala:15:7]
wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:100:62]
wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _io_consumer_output_valid_T; // @[Misc.scala:26:53]
wire [255:0] _io_consumer_output_data_T; // @[MemLoader.scala:186:33]
wire _io_consumer_output_last_chunk_T; // @[MemLoader.scala:201:61]
wire [70:0] io_l2helperUser_req_bits_addr_0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_req_valid_0; // @[MemLoader.scala:15:7]
wire io_l2helperUser_resp_ready_0; // @[MemLoader.scala:15:7]
wire io_src_info_ready_0; // @[MemLoader.scala:15:7]
wire [5:0] io_consumer_available_output_bytes_0; // @[MemLoader.scala:15:7]
wire io_consumer_output_valid_0; // @[MemLoader.scala:15:7]
wire [255:0] io_consumer_output_data_0; // @[MemLoader.scala:15:7]
wire io_consumer_output_last_chunk_0; // @[MemLoader.scala:15:7]
wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[MemLoader.scala:15:7, :32:51]
wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0} + {1'h0, base_addr_start_index}; // @[MemLoader.scala:15:7, :32:51, :33:35]
wire [64:0] _aligned_loadlen_T; // @[MemLoader.scala:33:35]
assign _aligned_loadlen_T = _GEN; // @[MemLoader.scala:33:35]
wire [64:0] _base_addr_end_index_T; // @[MemLoader.scala:34:39]
assign _base_addr_end_index_T = _GEN; // @[MemLoader.scala:33:35, :34:39]
wire [64:0] _base_addr_end_index_inclusive_T; // @[MemLoader.scala:35:49]
assign _base_addr_end_index_inclusive_T = _GEN; // @[MemLoader.scala:33:35, :35:49]
wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[MemLoader.scala:33:35]
wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[MemLoader.scala:34:39]
wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[MemLoader.scala:34:{39,64}]
wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[MemLoader.scala:35:49]
wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[MemLoader.scala:35:{49,73}]
wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[MemLoader.scala:35:73]
wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[MemLoader.scala:35:{73,80}]
wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[MemLoader.scala:33:35, :36:38]
wire extra_word = |_extra_word_T; // @[MemLoader.scala:36:{38,48}]
wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[MemLoader.scala:15:7, :38:50]
wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[MemLoader.scala:38:{50,58}]
wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[MemLoader.scala:33:35, :39:40]
wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[MemLoader.scala:36:48, :39:{40,48}]
wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[MemLoader.scala:39:48]
wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[MemLoader.scala:39:48, :40:47]
wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[MemLoader.scala:40:47]
reg print_not_done; // @[MemLoader.scala:43:31]
wire _T = io_src_info_valid_0 & print_not_done; // @[MemLoader.scala:15:7, :43:31, :45:27]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] addrinc; // @[MemLoader.scala:74:24]
wire _GEN_0 = addrinc == 64'h0; // @[MemLoader.scala:74:24, :76:57]
wire _load_info_queue_io_enq_bits_start_byte_T; // @[MemLoader.scala:76:57]
assign _load_info_queue_io_enq_bits_start_byte_T = _GEN_0; // @[MemLoader.scala:76:57]
wire _buf_info_queue_io_enq_valid_T; // @[MemLoader.scala:95:53]
assign _buf_info_queue_io_enq_valid_T = _GEN_0; // @[MemLoader.scala:76:57, :95:53]
wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[MemLoader.scala:32:51, :76:{48,57}]
wire _T_44 = addrinc == words_to_load_minus_one; // @[MemLoader.scala:40:47, :74:24, :77:55]
wire _load_info_queue_io_enq_bits_end_byte_T; // @[MemLoader.scala:77:55]
assign _load_info_queue_io_enq_bits_end_byte_T = _T_44; // @[MemLoader.scala:77:55]
wire _io_src_info_ready_T; // @[MemLoader.scala:92:53]
assign _io_src_info_ready_T = _T_44; // @[MemLoader.scala:77:55, :92:53]
wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[MemLoader.scala:35:80, :77:{46,55}]
wire _T_46 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18]
wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53]
assign _buf_info_queue_io_enq_valid_T_1 = _T_46; // @[Misc.scala:26:53, :29:18]
wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
assign _load_info_queue_io_enq_valid_T = _T_46; // @[Misc.scala:26:53, :29:18]
wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[MemLoader.scala:74:24, :83:24]
wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[MemLoader.scala:83:24]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53]
assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53]
wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[MemLoader.scala:74:24, :100:73]
wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, base_addr_bytes_aligned} + {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[MemLoader.scala:38:58, :100:{62,73}]
assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[MemLoader.scala:100:62]
assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:15:7, :100:62]
wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53]
reg [5:0] write_start_index; // @[MemLoader.scala:105:34]
wire [7:0] align_shamt = {_load_info_queue_io_deq_bits_start_byte, 3'h0}; // @[MemLoader.scala:28:31, :108:61]
wire [255:0] memresp_bits_shifted = io_l2helperUser_resp_bits_data_0 >> align_shamt; // @[MemLoader.scala:15:7, :108:61, :109:61]
wire [6:0] _idx_T = {1'h0, write_start_index}; // @[MemLoader.scala:105:34, :116:34]
wire [6:0] _GEN_1 = _idx_T % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx = _GEN_1[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_2 = _idx_T_1 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_1 = _GEN_2[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_3 = _idx_T_2 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_2 = _GEN_3[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_4 = _idx_T_3 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_3 = _GEN_4[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_5 = _idx_T_4 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_4 = _GEN_5[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_6 = _idx_T_5 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_5 = _GEN_6[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_7 = _idx_T_6 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_6 = _GEN_7[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_8 = _idx_T_7 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_7 = _GEN_8[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_9 = _idx_T_8 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_8 = _GEN_9[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_10 = _idx_T_9 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_9 = _GEN_10[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_11 = _idx_T_10 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_10 = _GEN_11[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_12 = _idx_T_11 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_11 = _GEN_12[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_13 = _idx_T_12 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_12 = _GEN_13[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_14 = _idx_T_13 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_13 = _GEN_14[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_15 = _idx_T_14 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_14 = _GEN_15[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_16 = _idx_T_15 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_15 = _GEN_16[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_17 = _idx_T_16 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_16 = _GEN_17[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_18 = _idx_T_17 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_17 = _GEN_18[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_19 = _idx_T_18 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_18 = _GEN_19[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_20 = _idx_T_19 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_19 = _GEN_20[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_21 = _idx_T_20 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_20 = _GEN_21[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_22 = _idx_T_21 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_21 = _GEN_22[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_23 = _idx_T_22 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_22 = _GEN_23[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_24 = _idx_T_23 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_23 = _GEN_24[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_25 = _idx_T_24 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_24 = _GEN_25[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_26 = _idx_T_25 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_25 = _GEN_26[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_27 = _idx_T_26 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_26 = _GEN_27[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_28 = _idx_T_27 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_27 = _GEN_28[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_29 = _idx_T_28 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_28 = _GEN_29[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_30 = _idx_T_29 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_29 = _GEN_30[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_31 = _idx_T_30 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_30 = _GEN_31[5:0]; // @[MemLoader.scala:116:48]
wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[MemLoader.scala:116:34]
wire [6:0] _GEN_32 = _idx_T_31 % 7'h20; // @[MemLoader.scala:116:{34,48}]
wire [5:0] idx_31 = _GEN_32[5:0]; // @[MemLoader.scala:116:48]
wire [5:0] _len_to_write_T = {1'h0, _load_info_queue_io_deq_bits_end_byte} - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[MemLoader.scala:28:31, :124:60]
wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[MemLoader.scala:124:60]
wire [5:0] len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[MemLoader.scala:124:{60,102}]
wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, len_to_write}; // @[MemLoader.scala:116:34, :124:102, :126:47]
wire [6:0] _GEN_33 = wrap_len_index_wide % 7'h20; // @[MemLoader.scala:126:47, :127:48]
wire [5:0] wrap_len_index_end = _GEN_33[5:0]; // @[MemLoader.scala:127:48]
wire wrapped = |(wrap_len_index_wide[6:5]); // @[MemLoader.scala:126:47, :128:37]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
wire _all_queues_ready_T = _Queue64_UInt8_io_enq_ready & _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire all_queues_ready = _all_queues_ready_T_29 & _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52, :139:68]
wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53]
assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53]
assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53]
wire _resp_fire_allqueues_T = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18]
wire _GEN_34 = write_start_index == 6'h0; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T; // @[MemLoader.scala:151:41]
assign _use_this_queue_T = _GEN_34; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_3; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_3 = _GEN_34; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_1 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_4 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_35 = write_start_index < 6'h2; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_6; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_6 = _GEN_35; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_9; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_9 = _GEN_35; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_36 = write_start_index < 6'h3; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_12; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_12 = _GEN_36; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_15; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_15 = _GEN_36; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_37 = wrap_len_index_end > 6'h2; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_13; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_13 = _GEN_37; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_16; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_16 = _GEN_37; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_38 = write_start_index < 6'h4; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_18; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_18 = _GEN_38; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_21; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_21 = _GEN_38; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_39 = write_start_index < 6'h5; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_24; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_24 = _GEN_39; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_27; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_27 = _GEN_39; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_40 = wrap_len_index_end > 6'h4; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_25; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_25 = _GEN_40; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_28; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_28 = _GEN_40; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_41 = write_start_index < 6'h6; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_30; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_30 = _GEN_41; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_33; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_33 = _GEN_41; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_42 = wrap_len_index_end > 6'h5; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_31; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_31 = _GEN_42; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_34; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_34 = _GEN_42; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_43 = write_start_index < 6'h7; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_36; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_36 = _GEN_43; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_39; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_39 = _GEN_43; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_44 = wrap_len_index_end > 6'h6; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_37; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_37 = _GEN_44; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_40; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_40 = _GEN_44; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_45 = write_start_index < 6'h8; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_42; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_42 = _GEN_45; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_45; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_45 = _GEN_45; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_46 = write_start_index < 6'h9; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_48; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_48 = _GEN_46; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_51; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_51 = _GEN_46; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_47 = wrap_len_index_end > 6'h8; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_49; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_49 = _GEN_47; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_52; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_52 = _GEN_47; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_48 = write_start_index < 6'hA; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_54; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_54 = _GEN_48; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_57; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_57 = _GEN_48; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_49 = wrap_len_index_end > 6'h9; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_55; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_55 = _GEN_49; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_58; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_58 = _GEN_49; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_50 = write_start_index < 6'hB; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_60; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_60 = _GEN_50; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_63; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_63 = _GEN_50; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_51 = wrap_len_index_end > 6'hA; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_61; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_61 = _GEN_51; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_64; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_64 = _GEN_51; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_52 = write_start_index < 6'hC; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_66; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_66 = _GEN_52; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_69; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_69 = _GEN_52; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_53 = wrap_len_index_end > 6'hB; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_67; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_67 = _GEN_53; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_70; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_70 = _GEN_53; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_54 = write_start_index < 6'hD; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_72; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_72 = _GEN_54; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_75; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_75 = _GEN_54; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_55 = wrap_len_index_end > 6'hC; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_73; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_73 = _GEN_55; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_76; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_76 = _GEN_55; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_56 = write_start_index < 6'hE; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_78; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_78 = _GEN_56; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_81; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_81 = _GEN_56; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_57 = wrap_len_index_end > 6'hD; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_79; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_79 = _GEN_57; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_82; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_82 = _GEN_57; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_58 = write_start_index < 6'hF; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_84; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_84 = _GEN_58; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_87; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_87 = _GEN_58; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_59 = wrap_len_index_end > 6'hE; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_85; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_85 = _GEN_59; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_88; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_88 = _GEN_59; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_60 = write_start_index < 6'h10; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_90; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_90 = _GEN_60; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_93; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_93 = _GEN_60; // @[MemLoader.scala:151:41, :152:41]
wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_61 = write_start_index < 6'h11; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_96; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_96 = _GEN_61; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_99; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_99 = _GEN_61; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_62 = wrap_len_index_end > 6'h10; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_97; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_97 = _GEN_62; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_100; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_100 = _GEN_62; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_63 = write_start_index < 6'h12; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_102; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_102 = _GEN_63; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_105; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_105 = _GEN_63; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_64 = wrap_len_index_end > 6'h11; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_103; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_103 = _GEN_64; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_106; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_106 = _GEN_64; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_65 = write_start_index < 6'h13; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_108; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_108 = _GEN_65; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_111; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_111 = _GEN_65; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_66 = wrap_len_index_end > 6'h12; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_109; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_109 = _GEN_66; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_112; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_112 = _GEN_66; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_67 = write_start_index < 6'h14; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_114; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_114 = _GEN_67; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_117; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_117 = _GEN_67; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_68 = wrap_len_index_end > 6'h13; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_115; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_115 = _GEN_68; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_118; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_118 = _GEN_68; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_69 = write_start_index < 6'h15; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_120; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_120 = _GEN_69; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_123; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_123 = _GEN_69; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_70 = wrap_len_index_end > 6'h14; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_121; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_121 = _GEN_70; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_124; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_124 = _GEN_70; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_71 = write_start_index < 6'h16; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_126; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_126 = _GEN_71; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_129; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_129 = _GEN_71; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_72 = wrap_len_index_end > 6'h15; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_127; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_127 = _GEN_72; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_130; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_130 = _GEN_72; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_73 = write_start_index < 6'h17; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_132; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_132 = _GEN_73; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_135; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_135 = _GEN_73; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_74 = wrap_len_index_end > 6'h16; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_133; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_133 = _GEN_74; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_136; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_136 = _GEN_74; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_75 = write_start_index < 6'h18; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_138; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_138 = _GEN_75; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_141; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_141 = _GEN_75; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_76 = wrap_len_index_end > 6'h17; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_139; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_139 = _GEN_76; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_142; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_142 = _GEN_76; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_77 = write_start_index < 6'h19; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_144; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_144 = _GEN_77; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_147; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_147 = _GEN_77; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_78 = wrap_len_index_end > 6'h18; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_145; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_145 = _GEN_78; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_148; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_148 = _GEN_78; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_79 = write_start_index < 6'h1A; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_150; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_150 = _GEN_79; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_153; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_153 = _GEN_79; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_80 = wrap_len_index_end > 6'h19; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_151; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_151 = _GEN_80; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_154; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_154 = _GEN_80; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_81 = write_start_index < 6'h1B; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_156; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_156 = _GEN_81; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_159; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_159 = _GEN_81; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_82 = wrap_len_index_end > 6'h1A; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_157; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_157 = _GEN_82; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_160; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_160 = _GEN_82; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_83 = write_start_index < 6'h1C; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_162; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_162 = _GEN_83; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_165; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_165 = _GEN_83; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_84 = wrap_len_index_end > 6'h1B; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_163; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_163 = _GEN_84; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_166; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_166 = _GEN_84; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_85 = write_start_index < 6'h1D; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_168; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_168 = _GEN_85; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_171; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_171 = _GEN_85; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_86 = wrap_len_index_end > 6'h1C; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_169; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_169 = _GEN_86; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_172; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_172 = _GEN_86; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_87 = write_start_index < 6'h1E; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_174; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_174 = _GEN_87; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_177; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_177 = _GEN_87; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_88 = wrap_len_index_end > 6'h1D; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_175; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_175 = _GEN_88; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_178; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_178 = _GEN_88; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _GEN_89 = write_start_index < 6'h1F; // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_180; // @[MemLoader.scala:151:41]
assign _use_this_queue_T_180 = _GEN_89; // @[MemLoader.scala:151:41]
wire _use_this_queue_T_183; // @[MemLoader.scala:152:41]
assign _use_this_queue_T_183 = _GEN_89; // @[MemLoader.scala:151:41, :152:41]
wire _GEN_90 = wrap_len_index_end > 6'h1E; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_181; // @[MemLoader.scala:151:77]
assign _use_this_queue_T_181 = _GEN_90; // @[MemLoader.scala:151:77]
wire _use_this_queue_T_184; // @[MemLoader.scala:152:77]
assign _use_this_queue_T_184 = _GEN_90; // @[MemLoader.scala:151:77, :152:77]
wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41]
wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77]
wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77, :152:77]
wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[MemLoader.scala:151:{41,63,77}]
wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41, :152:41]
wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[MemLoader.scala:152:{41,63,77}]
wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38]
reg [5:0] read_start_index; // @[MemLoader.scala:163:33]
reg [63:0] len_already_consumed; // @[MemLoader.scala:164:37]
wire [7:0] remapVecData_0; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_1; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_2; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_3; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_4; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_5; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_6; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_7; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_8; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_9; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_10; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_11; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_12; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_13; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_14; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_15; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_16; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_17; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_18; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_19; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_20; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_21; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_22; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_23; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_24; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_25; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_26; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_27; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_28; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_29; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_30; // @[MemLoader.scala:166:26]
wire [7:0] remapVecData_31; // @[MemLoader.scala:166:26]
wire remapVecValids_0; // @[MemLoader.scala:167:28]
wire remapVecValids_1; // @[MemLoader.scala:167:28]
wire remapVecValids_2; // @[MemLoader.scala:167:28]
wire remapVecValids_3; // @[MemLoader.scala:167:28]
wire remapVecValids_4; // @[MemLoader.scala:167:28]
wire remapVecValids_5; // @[MemLoader.scala:167:28]
wire remapVecValids_6; // @[MemLoader.scala:167:28]
wire remapVecValids_7; // @[MemLoader.scala:167:28]
wire remapVecValids_8; // @[MemLoader.scala:167:28]
wire remapVecValids_9; // @[MemLoader.scala:167:28]
wire remapVecValids_10; // @[MemLoader.scala:167:28]
wire remapVecValids_11; // @[MemLoader.scala:167:28]
wire remapVecValids_12; // @[MemLoader.scala:167:28]
wire remapVecValids_13; // @[MemLoader.scala:167:28]
wire remapVecValids_14; // @[MemLoader.scala:167:28]
wire remapVecValids_15; // @[MemLoader.scala:167:28]
wire remapVecValids_16; // @[MemLoader.scala:167:28]
wire remapVecValids_17; // @[MemLoader.scala:167:28]
wire remapVecValids_18; // @[MemLoader.scala:167:28]
wire remapVecValids_19; // @[MemLoader.scala:167:28]
wire remapVecValids_20; // @[MemLoader.scala:167:28]
wire remapVecValids_21; // @[MemLoader.scala:167:28]
wire remapVecValids_22; // @[MemLoader.scala:167:28]
wire remapVecValids_23; // @[MemLoader.scala:167:28]
wire remapVecValids_24; // @[MemLoader.scala:167:28]
wire remapVecValids_25; // @[MemLoader.scala:167:28]
wire remapVecValids_26; // @[MemLoader.scala:167:28]
wire remapVecValids_27; // @[MemLoader.scala:167:28]
wire remapVecValids_28; // @[MemLoader.scala:167:28]
wire remapVecValids_29; // @[MemLoader.scala:167:28]
wire remapVecValids_30; // @[MemLoader.scala:167:28]
wire remapVecValids_31; // @[MemLoader.scala:167:28]
wire _remapVecReadys_0_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_1_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_2_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_3_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_4_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_5_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_6_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_7_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_8_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_9_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_10_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_11_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_12_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_13_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_14_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_15_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_16_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_17_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_18_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_19_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_20_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_21_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_22_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_23_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_24_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_25_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_26_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_27_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_28_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_29_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_30_T_3; // @[MemLoader.scala:217:78]
wire _remapVecReadys_31_T_3; // @[MemLoader.scala:217:78]
wire remapVecReadys_0; // @[MemLoader.scala:168:28]
wire remapVecReadys_1; // @[MemLoader.scala:168:28]
wire remapVecReadys_2; // @[MemLoader.scala:168:28]
wire remapVecReadys_3; // @[MemLoader.scala:168:28]
wire remapVecReadys_4; // @[MemLoader.scala:168:28]
wire remapVecReadys_5; // @[MemLoader.scala:168:28]
wire remapVecReadys_6; // @[MemLoader.scala:168:28]
wire remapVecReadys_7; // @[MemLoader.scala:168:28]
wire remapVecReadys_8; // @[MemLoader.scala:168:28]
wire remapVecReadys_9; // @[MemLoader.scala:168:28]
wire remapVecReadys_10; // @[MemLoader.scala:168:28]
wire remapVecReadys_11; // @[MemLoader.scala:168:28]
wire remapVecReadys_12; // @[MemLoader.scala:168:28]
wire remapVecReadys_13; // @[MemLoader.scala:168:28]
wire remapVecReadys_14; // @[MemLoader.scala:168:28]
wire remapVecReadys_15; // @[MemLoader.scala:168:28]
wire remapVecReadys_16; // @[MemLoader.scala:168:28]
wire remapVecReadys_17; // @[MemLoader.scala:168:28]
wire remapVecReadys_18; // @[MemLoader.scala:168:28]
wire remapVecReadys_19; // @[MemLoader.scala:168:28]
wire remapVecReadys_20; // @[MemLoader.scala:168:28]
wire remapVecReadys_21; // @[MemLoader.scala:168:28]
wire remapVecReadys_22; // @[MemLoader.scala:168:28]
wire remapVecReadys_23; // @[MemLoader.scala:168:28]
wire remapVecReadys_24; // @[MemLoader.scala:168:28]
wire remapVecReadys_25; // @[MemLoader.scala:168:28]
wire remapVecReadys_26; // @[MemLoader.scala:168:28]
wire remapVecReadys_27; // @[MemLoader.scala:168:28]
wire remapVecReadys_28; // @[MemLoader.scala:168:28]
wire remapVecReadys_29; // @[MemLoader.scala:168:28]
wire remapVecReadys_30; // @[MemLoader.scala:168:28]
wire remapVecReadys_31; // @[MemLoader.scala:168:28]
wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[MemLoader.scala:163:33, :177:33]
wire [6:0] _GEN_91 = _remapindex_T % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex = _GEN_91[5:0]; // @[MemLoader.scala:177:54]
wire _T_2330 = remapindex == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2331 = remapindex == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2332 = remapindex == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2333 = remapindex == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2334 = remapindex == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2335 = remapindex == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2336 = remapindex == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2337 = remapindex == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2338 = remapindex == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2339 = remapindex == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2340 = remapindex == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2341 = remapindex == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2342 = remapindex == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2343 = remapindex == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2344 = remapindex == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2345 = remapindex == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2346 = remapindex == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2347 = remapindex == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2348 = remapindex == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2349 = remapindex == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2350 = remapindex == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2351 = remapindex == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2352 = remapindex == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2353 = remapindex == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2354 = remapindex == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2355 = remapindex == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2356 = remapindex == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2357 = remapindex == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2358 = remapindex == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2359 = remapindex == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2360 = remapindex == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2361 = remapindex == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_bits : _T_2360 ? _Queue64_UInt8_30_io_deq_bits : _T_2359 ? _Queue64_UInt8_29_io_deq_bits : _T_2358 ? _Queue64_UInt8_28_io_deq_bits : _T_2357 ? _Queue64_UInt8_27_io_deq_bits : _T_2356 ? _Queue64_UInt8_26_io_deq_bits : _T_2355 ? _Queue64_UInt8_25_io_deq_bits : _T_2354 ? _Queue64_UInt8_24_io_deq_bits : _T_2353 ? _Queue64_UInt8_23_io_deq_bits : _T_2352 ? _Queue64_UInt8_22_io_deq_bits : _T_2351 ? _Queue64_UInt8_21_io_deq_bits : _T_2350 ? _Queue64_UInt8_20_io_deq_bits : _T_2349 ? _Queue64_UInt8_19_io_deq_bits : _T_2348 ? _Queue64_UInt8_18_io_deq_bits : _T_2347 ? _Queue64_UInt8_17_io_deq_bits : _T_2346 ? _Queue64_UInt8_16_io_deq_bits : _T_2345 ? _Queue64_UInt8_15_io_deq_bits : _T_2344 ? _Queue64_UInt8_14_io_deq_bits : _T_2343 ? _Queue64_UInt8_13_io_deq_bits : _T_2342 ? _Queue64_UInt8_12_io_deq_bits : _T_2341 ? _Queue64_UInt8_11_io_deq_bits : _T_2340 ? _Queue64_UInt8_10_io_deq_bits : _T_2339 ? _Queue64_UInt8_9_io_deq_bits : _T_2338 ? _Queue64_UInt8_8_io_deq_bits : _T_2337 ? _Queue64_UInt8_7_io_deq_bits : _T_2336 ? _Queue64_UInt8_6_io_deq_bits : _T_2335 ? _Queue64_UInt8_5_io_deq_bits : _T_2334 ? _Queue64_UInt8_4_io_deq_bits : _T_2333 ? _Queue64_UInt8_3_io_deq_bits : _T_2332 ? _Queue64_UInt8_2_io_deq_bits : _T_2331 ? _Queue64_UInt8_1_io_deq_bits : _T_2330 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_valid : _T_2360 ? _Queue64_UInt8_30_io_deq_valid : _T_2359 ? _Queue64_UInt8_29_io_deq_valid : _T_2358 ? _Queue64_UInt8_28_io_deq_valid : _T_2357 ? _Queue64_UInt8_27_io_deq_valid : _T_2356 ? _Queue64_UInt8_26_io_deq_valid : _T_2355 ? _Queue64_UInt8_25_io_deq_valid : _T_2354 ? _Queue64_UInt8_24_io_deq_valid : _T_2353 ? _Queue64_UInt8_23_io_deq_valid : _T_2352 ? _Queue64_UInt8_22_io_deq_valid : _T_2351 ? _Queue64_UInt8_21_io_deq_valid : _T_2350 ? _Queue64_UInt8_20_io_deq_valid : _T_2349 ? _Queue64_UInt8_19_io_deq_valid : _T_2348 ? _Queue64_UInt8_18_io_deq_valid : _T_2347 ? _Queue64_UInt8_17_io_deq_valid : _T_2346 ? _Queue64_UInt8_16_io_deq_valid : _T_2345 ? _Queue64_UInt8_15_io_deq_valid : _T_2344 ? _Queue64_UInt8_14_io_deq_valid : _T_2343 ? _Queue64_UInt8_13_io_deq_valid : _T_2342 ? _Queue64_UInt8_12_io_deq_valid : _T_2341 ? _Queue64_UInt8_11_io_deq_valid : _T_2340 ? _Queue64_UInt8_10_io_deq_valid : _T_2339 ? _Queue64_UInt8_9_io_deq_valid : _T_2338 ? _Queue64_UInt8_8_io_deq_valid : _T_2337 ? _Queue64_UInt8_7_io_deq_valid : _T_2336 ? _Queue64_UInt8_6_io_deq_valid : _T_2335 ? _Queue64_UInt8_5_io_deq_valid : _T_2334 ? _Queue64_UInt8_4_io_deq_valid : _T_2333 ? _Queue64_UInt8_3_io_deq_valid : _T_2332 ? _Queue64_UInt8_2_io_deq_valid : _T_2331 ? _Queue64_UInt8_1_io_deq_valid : _T_2330 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_92 = _remapindex_T_1 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_1 = _GEN_92[5:0]; // @[MemLoader.scala:177:54]
wire _T_2362 = remapindex_1 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2363 = remapindex_1 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2364 = remapindex_1 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2365 = remapindex_1 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2366 = remapindex_1 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2367 = remapindex_1 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2368 = remapindex_1 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2369 = remapindex_1 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2370 = remapindex_1 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2371 = remapindex_1 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2372 = remapindex_1 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2373 = remapindex_1 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2374 = remapindex_1 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2375 = remapindex_1 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2376 = remapindex_1 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2377 = remapindex_1 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2378 = remapindex_1 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2379 = remapindex_1 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2380 = remapindex_1 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2381 = remapindex_1 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2382 = remapindex_1 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2383 = remapindex_1 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2384 = remapindex_1 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2385 = remapindex_1 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2386 = remapindex_1 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2387 = remapindex_1 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2388 = remapindex_1 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2389 = remapindex_1 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2390 = remapindex_1 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2391 = remapindex_1 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2392 = remapindex_1 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2393 = remapindex_1 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_bits : _T_2392 ? _Queue64_UInt8_30_io_deq_bits : _T_2391 ? _Queue64_UInt8_29_io_deq_bits : _T_2390 ? _Queue64_UInt8_28_io_deq_bits : _T_2389 ? _Queue64_UInt8_27_io_deq_bits : _T_2388 ? _Queue64_UInt8_26_io_deq_bits : _T_2387 ? _Queue64_UInt8_25_io_deq_bits : _T_2386 ? _Queue64_UInt8_24_io_deq_bits : _T_2385 ? _Queue64_UInt8_23_io_deq_bits : _T_2384 ? _Queue64_UInt8_22_io_deq_bits : _T_2383 ? _Queue64_UInt8_21_io_deq_bits : _T_2382 ? _Queue64_UInt8_20_io_deq_bits : _T_2381 ? _Queue64_UInt8_19_io_deq_bits : _T_2380 ? _Queue64_UInt8_18_io_deq_bits : _T_2379 ? _Queue64_UInt8_17_io_deq_bits : _T_2378 ? _Queue64_UInt8_16_io_deq_bits : _T_2377 ? _Queue64_UInt8_15_io_deq_bits : _T_2376 ? _Queue64_UInt8_14_io_deq_bits : _T_2375 ? _Queue64_UInt8_13_io_deq_bits : _T_2374 ? _Queue64_UInt8_12_io_deq_bits : _T_2373 ? _Queue64_UInt8_11_io_deq_bits : _T_2372 ? _Queue64_UInt8_10_io_deq_bits : _T_2371 ? _Queue64_UInt8_9_io_deq_bits : _T_2370 ? _Queue64_UInt8_8_io_deq_bits : _T_2369 ? _Queue64_UInt8_7_io_deq_bits : _T_2368 ? _Queue64_UInt8_6_io_deq_bits : _T_2367 ? _Queue64_UInt8_5_io_deq_bits : _T_2366 ? _Queue64_UInt8_4_io_deq_bits : _T_2365 ? _Queue64_UInt8_3_io_deq_bits : _T_2364 ? _Queue64_UInt8_2_io_deq_bits : _T_2363 ? _Queue64_UInt8_1_io_deq_bits : _T_2362 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_valid : _T_2392 ? _Queue64_UInt8_30_io_deq_valid : _T_2391 ? _Queue64_UInt8_29_io_deq_valid : _T_2390 ? _Queue64_UInt8_28_io_deq_valid : _T_2389 ? _Queue64_UInt8_27_io_deq_valid : _T_2388 ? _Queue64_UInt8_26_io_deq_valid : _T_2387 ? _Queue64_UInt8_25_io_deq_valid : _T_2386 ? _Queue64_UInt8_24_io_deq_valid : _T_2385 ? _Queue64_UInt8_23_io_deq_valid : _T_2384 ? _Queue64_UInt8_22_io_deq_valid : _T_2383 ? _Queue64_UInt8_21_io_deq_valid : _T_2382 ? _Queue64_UInt8_20_io_deq_valid : _T_2381 ? _Queue64_UInt8_19_io_deq_valid : _T_2380 ? _Queue64_UInt8_18_io_deq_valid : _T_2379 ? _Queue64_UInt8_17_io_deq_valid : _T_2378 ? _Queue64_UInt8_16_io_deq_valid : _T_2377 ? _Queue64_UInt8_15_io_deq_valid : _T_2376 ? _Queue64_UInt8_14_io_deq_valid : _T_2375 ? _Queue64_UInt8_13_io_deq_valid : _T_2374 ? _Queue64_UInt8_12_io_deq_valid : _T_2373 ? _Queue64_UInt8_11_io_deq_valid : _T_2372 ? _Queue64_UInt8_10_io_deq_valid : _T_2371 ? _Queue64_UInt8_9_io_deq_valid : _T_2370 ? _Queue64_UInt8_8_io_deq_valid : _T_2369 ? _Queue64_UInt8_7_io_deq_valid : _T_2368 ? _Queue64_UInt8_6_io_deq_valid : _T_2367 ? _Queue64_UInt8_5_io_deq_valid : _T_2366 ? _Queue64_UInt8_4_io_deq_valid : _T_2365 ? _Queue64_UInt8_3_io_deq_valid : _T_2364 ? _Queue64_UInt8_2_io_deq_valid : _T_2363 ? _Queue64_UInt8_1_io_deq_valid : _T_2362 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_93 = _remapindex_T_2 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_2 = _GEN_93[5:0]; // @[MemLoader.scala:177:54]
wire _T_2394 = remapindex_2 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2395 = remapindex_2 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2396 = remapindex_2 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2397 = remapindex_2 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2398 = remapindex_2 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2399 = remapindex_2 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2400 = remapindex_2 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2401 = remapindex_2 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2402 = remapindex_2 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2403 = remapindex_2 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2404 = remapindex_2 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2405 = remapindex_2 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2406 = remapindex_2 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2407 = remapindex_2 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2408 = remapindex_2 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2409 = remapindex_2 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2410 = remapindex_2 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2411 = remapindex_2 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2412 = remapindex_2 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2413 = remapindex_2 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2414 = remapindex_2 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2415 = remapindex_2 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2416 = remapindex_2 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2417 = remapindex_2 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2418 = remapindex_2 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2419 = remapindex_2 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2420 = remapindex_2 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2421 = remapindex_2 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2422 = remapindex_2 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2423 = remapindex_2 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2424 = remapindex_2 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2425 = remapindex_2 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_bits : _T_2424 ? _Queue64_UInt8_30_io_deq_bits : _T_2423 ? _Queue64_UInt8_29_io_deq_bits : _T_2422 ? _Queue64_UInt8_28_io_deq_bits : _T_2421 ? _Queue64_UInt8_27_io_deq_bits : _T_2420 ? _Queue64_UInt8_26_io_deq_bits : _T_2419 ? _Queue64_UInt8_25_io_deq_bits : _T_2418 ? _Queue64_UInt8_24_io_deq_bits : _T_2417 ? _Queue64_UInt8_23_io_deq_bits : _T_2416 ? _Queue64_UInt8_22_io_deq_bits : _T_2415 ? _Queue64_UInt8_21_io_deq_bits : _T_2414 ? _Queue64_UInt8_20_io_deq_bits : _T_2413 ? _Queue64_UInt8_19_io_deq_bits : _T_2412 ? _Queue64_UInt8_18_io_deq_bits : _T_2411 ? _Queue64_UInt8_17_io_deq_bits : _T_2410 ? _Queue64_UInt8_16_io_deq_bits : _T_2409 ? _Queue64_UInt8_15_io_deq_bits : _T_2408 ? _Queue64_UInt8_14_io_deq_bits : _T_2407 ? _Queue64_UInt8_13_io_deq_bits : _T_2406 ? _Queue64_UInt8_12_io_deq_bits : _T_2405 ? _Queue64_UInt8_11_io_deq_bits : _T_2404 ? _Queue64_UInt8_10_io_deq_bits : _T_2403 ? _Queue64_UInt8_9_io_deq_bits : _T_2402 ? _Queue64_UInt8_8_io_deq_bits : _T_2401 ? _Queue64_UInt8_7_io_deq_bits : _T_2400 ? _Queue64_UInt8_6_io_deq_bits : _T_2399 ? _Queue64_UInt8_5_io_deq_bits : _T_2398 ? _Queue64_UInt8_4_io_deq_bits : _T_2397 ? _Queue64_UInt8_3_io_deq_bits : _T_2396 ? _Queue64_UInt8_2_io_deq_bits : _T_2395 ? _Queue64_UInt8_1_io_deq_bits : _T_2394 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_valid : _T_2424 ? _Queue64_UInt8_30_io_deq_valid : _T_2423 ? _Queue64_UInt8_29_io_deq_valid : _T_2422 ? _Queue64_UInt8_28_io_deq_valid : _T_2421 ? _Queue64_UInt8_27_io_deq_valid : _T_2420 ? _Queue64_UInt8_26_io_deq_valid : _T_2419 ? _Queue64_UInt8_25_io_deq_valid : _T_2418 ? _Queue64_UInt8_24_io_deq_valid : _T_2417 ? _Queue64_UInt8_23_io_deq_valid : _T_2416 ? _Queue64_UInt8_22_io_deq_valid : _T_2415 ? _Queue64_UInt8_21_io_deq_valid : _T_2414 ? _Queue64_UInt8_20_io_deq_valid : _T_2413 ? _Queue64_UInt8_19_io_deq_valid : _T_2412 ? _Queue64_UInt8_18_io_deq_valid : _T_2411 ? _Queue64_UInt8_17_io_deq_valid : _T_2410 ? _Queue64_UInt8_16_io_deq_valid : _T_2409 ? _Queue64_UInt8_15_io_deq_valid : _T_2408 ? _Queue64_UInt8_14_io_deq_valid : _T_2407 ? _Queue64_UInt8_13_io_deq_valid : _T_2406 ? _Queue64_UInt8_12_io_deq_valid : _T_2405 ? _Queue64_UInt8_11_io_deq_valid : _T_2404 ? _Queue64_UInt8_10_io_deq_valid : _T_2403 ? _Queue64_UInt8_9_io_deq_valid : _T_2402 ? _Queue64_UInt8_8_io_deq_valid : _T_2401 ? _Queue64_UInt8_7_io_deq_valid : _T_2400 ? _Queue64_UInt8_6_io_deq_valid : _T_2399 ? _Queue64_UInt8_5_io_deq_valid : _T_2398 ? _Queue64_UInt8_4_io_deq_valid : _T_2397 ? _Queue64_UInt8_3_io_deq_valid : _T_2396 ? _Queue64_UInt8_2_io_deq_valid : _T_2395 ? _Queue64_UInt8_1_io_deq_valid : _T_2394 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_94 = _remapindex_T_3 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_3 = _GEN_94[5:0]; // @[MemLoader.scala:177:54]
wire _T_2426 = remapindex_3 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2427 = remapindex_3 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2428 = remapindex_3 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2429 = remapindex_3 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2430 = remapindex_3 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2431 = remapindex_3 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2432 = remapindex_3 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2433 = remapindex_3 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2434 = remapindex_3 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2435 = remapindex_3 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2436 = remapindex_3 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2437 = remapindex_3 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2438 = remapindex_3 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2439 = remapindex_3 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2440 = remapindex_3 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2441 = remapindex_3 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2442 = remapindex_3 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2443 = remapindex_3 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2444 = remapindex_3 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2445 = remapindex_3 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2446 = remapindex_3 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2447 = remapindex_3 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2448 = remapindex_3 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2449 = remapindex_3 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2450 = remapindex_3 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2451 = remapindex_3 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2452 = remapindex_3 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2453 = remapindex_3 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2454 = remapindex_3 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2455 = remapindex_3 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2456 = remapindex_3 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2457 = remapindex_3 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_bits : _T_2456 ? _Queue64_UInt8_30_io_deq_bits : _T_2455 ? _Queue64_UInt8_29_io_deq_bits : _T_2454 ? _Queue64_UInt8_28_io_deq_bits : _T_2453 ? _Queue64_UInt8_27_io_deq_bits : _T_2452 ? _Queue64_UInt8_26_io_deq_bits : _T_2451 ? _Queue64_UInt8_25_io_deq_bits : _T_2450 ? _Queue64_UInt8_24_io_deq_bits : _T_2449 ? _Queue64_UInt8_23_io_deq_bits : _T_2448 ? _Queue64_UInt8_22_io_deq_bits : _T_2447 ? _Queue64_UInt8_21_io_deq_bits : _T_2446 ? _Queue64_UInt8_20_io_deq_bits : _T_2445 ? _Queue64_UInt8_19_io_deq_bits : _T_2444 ? _Queue64_UInt8_18_io_deq_bits : _T_2443 ? _Queue64_UInt8_17_io_deq_bits : _T_2442 ? _Queue64_UInt8_16_io_deq_bits : _T_2441 ? _Queue64_UInt8_15_io_deq_bits : _T_2440 ? _Queue64_UInt8_14_io_deq_bits : _T_2439 ? _Queue64_UInt8_13_io_deq_bits : _T_2438 ? _Queue64_UInt8_12_io_deq_bits : _T_2437 ? _Queue64_UInt8_11_io_deq_bits : _T_2436 ? _Queue64_UInt8_10_io_deq_bits : _T_2435 ? _Queue64_UInt8_9_io_deq_bits : _T_2434 ? _Queue64_UInt8_8_io_deq_bits : _T_2433 ? _Queue64_UInt8_7_io_deq_bits : _T_2432 ? _Queue64_UInt8_6_io_deq_bits : _T_2431 ? _Queue64_UInt8_5_io_deq_bits : _T_2430 ? _Queue64_UInt8_4_io_deq_bits : _T_2429 ? _Queue64_UInt8_3_io_deq_bits : _T_2428 ? _Queue64_UInt8_2_io_deq_bits : _T_2427 ? _Queue64_UInt8_1_io_deq_bits : _T_2426 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_valid : _T_2456 ? _Queue64_UInt8_30_io_deq_valid : _T_2455 ? _Queue64_UInt8_29_io_deq_valid : _T_2454 ? _Queue64_UInt8_28_io_deq_valid : _T_2453 ? _Queue64_UInt8_27_io_deq_valid : _T_2452 ? _Queue64_UInt8_26_io_deq_valid : _T_2451 ? _Queue64_UInt8_25_io_deq_valid : _T_2450 ? _Queue64_UInt8_24_io_deq_valid : _T_2449 ? _Queue64_UInt8_23_io_deq_valid : _T_2448 ? _Queue64_UInt8_22_io_deq_valid : _T_2447 ? _Queue64_UInt8_21_io_deq_valid : _T_2446 ? _Queue64_UInt8_20_io_deq_valid : _T_2445 ? _Queue64_UInt8_19_io_deq_valid : _T_2444 ? _Queue64_UInt8_18_io_deq_valid : _T_2443 ? _Queue64_UInt8_17_io_deq_valid : _T_2442 ? _Queue64_UInt8_16_io_deq_valid : _T_2441 ? _Queue64_UInt8_15_io_deq_valid : _T_2440 ? _Queue64_UInt8_14_io_deq_valid : _T_2439 ? _Queue64_UInt8_13_io_deq_valid : _T_2438 ? _Queue64_UInt8_12_io_deq_valid : _T_2437 ? _Queue64_UInt8_11_io_deq_valid : _T_2436 ? _Queue64_UInt8_10_io_deq_valid : _T_2435 ? _Queue64_UInt8_9_io_deq_valid : _T_2434 ? _Queue64_UInt8_8_io_deq_valid : _T_2433 ? _Queue64_UInt8_7_io_deq_valid : _T_2432 ? _Queue64_UInt8_6_io_deq_valid : _T_2431 ? _Queue64_UInt8_5_io_deq_valid : _T_2430 ? _Queue64_UInt8_4_io_deq_valid : _T_2429 ? _Queue64_UInt8_3_io_deq_valid : _T_2428 ? _Queue64_UInt8_2_io_deq_valid : _T_2427 ? _Queue64_UInt8_1_io_deq_valid : _T_2426 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_95 = _remapindex_T_4 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_4 = _GEN_95[5:0]; // @[MemLoader.scala:177:54]
wire _T_2458 = remapindex_4 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2459 = remapindex_4 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2460 = remapindex_4 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2461 = remapindex_4 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2462 = remapindex_4 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2463 = remapindex_4 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2464 = remapindex_4 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2465 = remapindex_4 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2466 = remapindex_4 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2467 = remapindex_4 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2468 = remapindex_4 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2469 = remapindex_4 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2470 = remapindex_4 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2471 = remapindex_4 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2472 = remapindex_4 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2473 = remapindex_4 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2474 = remapindex_4 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2475 = remapindex_4 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2476 = remapindex_4 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2477 = remapindex_4 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2478 = remapindex_4 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2479 = remapindex_4 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2480 = remapindex_4 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2481 = remapindex_4 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2482 = remapindex_4 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2483 = remapindex_4 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2484 = remapindex_4 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2485 = remapindex_4 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2486 = remapindex_4 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2487 = remapindex_4 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2488 = remapindex_4 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2489 = remapindex_4 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_bits : _T_2488 ? _Queue64_UInt8_30_io_deq_bits : _T_2487 ? _Queue64_UInt8_29_io_deq_bits : _T_2486 ? _Queue64_UInt8_28_io_deq_bits : _T_2485 ? _Queue64_UInt8_27_io_deq_bits : _T_2484 ? _Queue64_UInt8_26_io_deq_bits : _T_2483 ? _Queue64_UInt8_25_io_deq_bits : _T_2482 ? _Queue64_UInt8_24_io_deq_bits : _T_2481 ? _Queue64_UInt8_23_io_deq_bits : _T_2480 ? _Queue64_UInt8_22_io_deq_bits : _T_2479 ? _Queue64_UInt8_21_io_deq_bits : _T_2478 ? _Queue64_UInt8_20_io_deq_bits : _T_2477 ? _Queue64_UInt8_19_io_deq_bits : _T_2476 ? _Queue64_UInt8_18_io_deq_bits : _T_2475 ? _Queue64_UInt8_17_io_deq_bits : _T_2474 ? _Queue64_UInt8_16_io_deq_bits : _T_2473 ? _Queue64_UInt8_15_io_deq_bits : _T_2472 ? _Queue64_UInt8_14_io_deq_bits : _T_2471 ? _Queue64_UInt8_13_io_deq_bits : _T_2470 ? _Queue64_UInt8_12_io_deq_bits : _T_2469 ? _Queue64_UInt8_11_io_deq_bits : _T_2468 ? _Queue64_UInt8_10_io_deq_bits : _T_2467 ? _Queue64_UInt8_9_io_deq_bits : _T_2466 ? _Queue64_UInt8_8_io_deq_bits : _T_2465 ? _Queue64_UInt8_7_io_deq_bits : _T_2464 ? _Queue64_UInt8_6_io_deq_bits : _T_2463 ? _Queue64_UInt8_5_io_deq_bits : _T_2462 ? _Queue64_UInt8_4_io_deq_bits : _T_2461 ? _Queue64_UInt8_3_io_deq_bits : _T_2460 ? _Queue64_UInt8_2_io_deq_bits : _T_2459 ? _Queue64_UInt8_1_io_deq_bits : _T_2458 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_valid : _T_2488 ? _Queue64_UInt8_30_io_deq_valid : _T_2487 ? _Queue64_UInt8_29_io_deq_valid : _T_2486 ? _Queue64_UInt8_28_io_deq_valid : _T_2485 ? _Queue64_UInt8_27_io_deq_valid : _T_2484 ? _Queue64_UInt8_26_io_deq_valid : _T_2483 ? _Queue64_UInt8_25_io_deq_valid : _T_2482 ? _Queue64_UInt8_24_io_deq_valid : _T_2481 ? _Queue64_UInt8_23_io_deq_valid : _T_2480 ? _Queue64_UInt8_22_io_deq_valid : _T_2479 ? _Queue64_UInt8_21_io_deq_valid : _T_2478 ? _Queue64_UInt8_20_io_deq_valid : _T_2477 ? _Queue64_UInt8_19_io_deq_valid : _T_2476 ? _Queue64_UInt8_18_io_deq_valid : _T_2475 ? _Queue64_UInt8_17_io_deq_valid : _T_2474 ? _Queue64_UInt8_16_io_deq_valid : _T_2473 ? _Queue64_UInt8_15_io_deq_valid : _T_2472 ? _Queue64_UInt8_14_io_deq_valid : _T_2471 ? _Queue64_UInt8_13_io_deq_valid : _T_2470 ? _Queue64_UInt8_12_io_deq_valid : _T_2469 ? _Queue64_UInt8_11_io_deq_valid : _T_2468 ? _Queue64_UInt8_10_io_deq_valid : _T_2467 ? _Queue64_UInt8_9_io_deq_valid : _T_2466 ? _Queue64_UInt8_8_io_deq_valid : _T_2465 ? _Queue64_UInt8_7_io_deq_valid : _T_2464 ? _Queue64_UInt8_6_io_deq_valid : _T_2463 ? _Queue64_UInt8_5_io_deq_valid : _T_2462 ? _Queue64_UInt8_4_io_deq_valid : _T_2461 ? _Queue64_UInt8_3_io_deq_valid : _T_2460 ? _Queue64_UInt8_2_io_deq_valid : _T_2459 ? _Queue64_UInt8_1_io_deq_valid : _T_2458 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_96 = _remapindex_T_5 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_5 = _GEN_96[5:0]; // @[MemLoader.scala:177:54]
wire _T_2490 = remapindex_5 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2491 = remapindex_5 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2492 = remapindex_5 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2493 = remapindex_5 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2494 = remapindex_5 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2495 = remapindex_5 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2496 = remapindex_5 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2497 = remapindex_5 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2498 = remapindex_5 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2499 = remapindex_5 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2500 = remapindex_5 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2501 = remapindex_5 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2502 = remapindex_5 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2503 = remapindex_5 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2504 = remapindex_5 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2505 = remapindex_5 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2506 = remapindex_5 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2507 = remapindex_5 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2508 = remapindex_5 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2509 = remapindex_5 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2510 = remapindex_5 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2511 = remapindex_5 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2512 = remapindex_5 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2513 = remapindex_5 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2514 = remapindex_5 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2515 = remapindex_5 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2516 = remapindex_5 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2517 = remapindex_5 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2518 = remapindex_5 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2519 = remapindex_5 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2520 = remapindex_5 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2521 = remapindex_5 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_bits : _T_2520 ? _Queue64_UInt8_30_io_deq_bits : _T_2519 ? _Queue64_UInt8_29_io_deq_bits : _T_2518 ? _Queue64_UInt8_28_io_deq_bits : _T_2517 ? _Queue64_UInt8_27_io_deq_bits : _T_2516 ? _Queue64_UInt8_26_io_deq_bits : _T_2515 ? _Queue64_UInt8_25_io_deq_bits : _T_2514 ? _Queue64_UInt8_24_io_deq_bits : _T_2513 ? _Queue64_UInt8_23_io_deq_bits : _T_2512 ? _Queue64_UInt8_22_io_deq_bits : _T_2511 ? _Queue64_UInt8_21_io_deq_bits : _T_2510 ? _Queue64_UInt8_20_io_deq_bits : _T_2509 ? _Queue64_UInt8_19_io_deq_bits : _T_2508 ? _Queue64_UInt8_18_io_deq_bits : _T_2507 ? _Queue64_UInt8_17_io_deq_bits : _T_2506 ? _Queue64_UInt8_16_io_deq_bits : _T_2505 ? _Queue64_UInt8_15_io_deq_bits : _T_2504 ? _Queue64_UInt8_14_io_deq_bits : _T_2503 ? _Queue64_UInt8_13_io_deq_bits : _T_2502 ? _Queue64_UInt8_12_io_deq_bits : _T_2501 ? _Queue64_UInt8_11_io_deq_bits : _T_2500 ? _Queue64_UInt8_10_io_deq_bits : _T_2499 ? _Queue64_UInt8_9_io_deq_bits : _T_2498 ? _Queue64_UInt8_8_io_deq_bits : _T_2497 ? _Queue64_UInt8_7_io_deq_bits : _T_2496 ? _Queue64_UInt8_6_io_deq_bits : _T_2495 ? _Queue64_UInt8_5_io_deq_bits : _T_2494 ? _Queue64_UInt8_4_io_deq_bits : _T_2493 ? _Queue64_UInt8_3_io_deq_bits : _T_2492 ? _Queue64_UInt8_2_io_deq_bits : _T_2491 ? _Queue64_UInt8_1_io_deq_bits : _T_2490 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_valid : _T_2520 ? _Queue64_UInt8_30_io_deq_valid : _T_2519 ? _Queue64_UInt8_29_io_deq_valid : _T_2518 ? _Queue64_UInt8_28_io_deq_valid : _T_2517 ? _Queue64_UInt8_27_io_deq_valid : _T_2516 ? _Queue64_UInt8_26_io_deq_valid : _T_2515 ? _Queue64_UInt8_25_io_deq_valid : _T_2514 ? _Queue64_UInt8_24_io_deq_valid : _T_2513 ? _Queue64_UInt8_23_io_deq_valid : _T_2512 ? _Queue64_UInt8_22_io_deq_valid : _T_2511 ? _Queue64_UInt8_21_io_deq_valid : _T_2510 ? _Queue64_UInt8_20_io_deq_valid : _T_2509 ? _Queue64_UInt8_19_io_deq_valid : _T_2508 ? _Queue64_UInt8_18_io_deq_valid : _T_2507 ? _Queue64_UInt8_17_io_deq_valid : _T_2506 ? _Queue64_UInt8_16_io_deq_valid : _T_2505 ? _Queue64_UInt8_15_io_deq_valid : _T_2504 ? _Queue64_UInt8_14_io_deq_valid : _T_2503 ? _Queue64_UInt8_13_io_deq_valid : _T_2502 ? _Queue64_UInt8_12_io_deq_valid : _T_2501 ? _Queue64_UInt8_11_io_deq_valid : _T_2500 ? _Queue64_UInt8_10_io_deq_valid : _T_2499 ? _Queue64_UInt8_9_io_deq_valid : _T_2498 ? _Queue64_UInt8_8_io_deq_valid : _T_2497 ? _Queue64_UInt8_7_io_deq_valid : _T_2496 ? _Queue64_UInt8_6_io_deq_valid : _T_2495 ? _Queue64_UInt8_5_io_deq_valid : _T_2494 ? _Queue64_UInt8_4_io_deq_valid : _T_2493 ? _Queue64_UInt8_3_io_deq_valid : _T_2492 ? _Queue64_UInt8_2_io_deq_valid : _T_2491 ? _Queue64_UInt8_1_io_deq_valid : _T_2490 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_97 = _remapindex_T_6 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_6 = _GEN_97[5:0]; // @[MemLoader.scala:177:54]
wire _T_2522 = remapindex_6 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2523 = remapindex_6 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2524 = remapindex_6 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2525 = remapindex_6 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2526 = remapindex_6 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2527 = remapindex_6 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2528 = remapindex_6 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2529 = remapindex_6 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2530 = remapindex_6 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2531 = remapindex_6 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2532 = remapindex_6 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2533 = remapindex_6 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2534 = remapindex_6 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2535 = remapindex_6 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2536 = remapindex_6 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2537 = remapindex_6 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2538 = remapindex_6 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2539 = remapindex_6 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2540 = remapindex_6 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2541 = remapindex_6 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2542 = remapindex_6 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2543 = remapindex_6 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2544 = remapindex_6 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2545 = remapindex_6 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2546 = remapindex_6 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2547 = remapindex_6 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2548 = remapindex_6 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2549 = remapindex_6 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2550 = remapindex_6 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2551 = remapindex_6 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2552 = remapindex_6 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2553 = remapindex_6 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_bits : _T_2552 ? _Queue64_UInt8_30_io_deq_bits : _T_2551 ? _Queue64_UInt8_29_io_deq_bits : _T_2550 ? _Queue64_UInt8_28_io_deq_bits : _T_2549 ? _Queue64_UInt8_27_io_deq_bits : _T_2548 ? _Queue64_UInt8_26_io_deq_bits : _T_2547 ? _Queue64_UInt8_25_io_deq_bits : _T_2546 ? _Queue64_UInt8_24_io_deq_bits : _T_2545 ? _Queue64_UInt8_23_io_deq_bits : _T_2544 ? _Queue64_UInt8_22_io_deq_bits : _T_2543 ? _Queue64_UInt8_21_io_deq_bits : _T_2542 ? _Queue64_UInt8_20_io_deq_bits : _T_2541 ? _Queue64_UInt8_19_io_deq_bits : _T_2540 ? _Queue64_UInt8_18_io_deq_bits : _T_2539 ? _Queue64_UInt8_17_io_deq_bits : _T_2538 ? _Queue64_UInt8_16_io_deq_bits : _T_2537 ? _Queue64_UInt8_15_io_deq_bits : _T_2536 ? _Queue64_UInt8_14_io_deq_bits : _T_2535 ? _Queue64_UInt8_13_io_deq_bits : _T_2534 ? _Queue64_UInt8_12_io_deq_bits : _T_2533 ? _Queue64_UInt8_11_io_deq_bits : _T_2532 ? _Queue64_UInt8_10_io_deq_bits : _T_2531 ? _Queue64_UInt8_9_io_deq_bits : _T_2530 ? _Queue64_UInt8_8_io_deq_bits : _T_2529 ? _Queue64_UInt8_7_io_deq_bits : _T_2528 ? _Queue64_UInt8_6_io_deq_bits : _T_2527 ? _Queue64_UInt8_5_io_deq_bits : _T_2526 ? _Queue64_UInt8_4_io_deq_bits : _T_2525 ? _Queue64_UInt8_3_io_deq_bits : _T_2524 ? _Queue64_UInt8_2_io_deq_bits : _T_2523 ? _Queue64_UInt8_1_io_deq_bits : _T_2522 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_valid : _T_2552 ? _Queue64_UInt8_30_io_deq_valid : _T_2551 ? _Queue64_UInt8_29_io_deq_valid : _T_2550 ? _Queue64_UInt8_28_io_deq_valid : _T_2549 ? _Queue64_UInt8_27_io_deq_valid : _T_2548 ? _Queue64_UInt8_26_io_deq_valid : _T_2547 ? _Queue64_UInt8_25_io_deq_valid : _T_2546 ? _Queue64_UInt8_24_io_deq_valid : _T_2545 ? _Queue64_UInt8_23_io_deq_valid : _T_2544 ? _Queue64_UInt8_22_io_deq_valid : _T_2543 ? _Queue64_UInt8_21_io_deq_valid : _T_2542 ? _Queue64_UInt8_20_io_deq_valid : _T_2541 ? _Queue64_UInt8_19_io_deq_valid : _T_2540 ? _Queue64_UInt8_18_io_deq_valid : _T_2539 ? _Queue64_UInt8_17_io_deq_valid : _T_2538 ? _Queue64_UInt8_16_io_deq_valid : _T_2537 ? _Queue64_UInt8_15_io_deq_valid : _T_2536 ? _Queue64_UInt8_14_io_deq_valid : _T_2535 ? _Queue64_UInt8_13_io_deq_valid : _T_2534 ? _Queue64_UInt8_12_io_deq_valid : _T_2533 ? _Queue64_UInt8_11_io_deq_valid : _T_2532 ? _Queue64_UInt8_10_io_deq_valid : _T_2531 ? _Queue64_UInt8_9_io_deq_valid : _T_2530 ? _Queue64_UInt8_8_io_deq_valid : _T_2529 ? _Queue64_UInt8_7_io_deq_valid : _T_2528 ? _Queue64_UInt8_6_io_deq_valid : _T_2527 ? _Queue64_UInt8_5_io_deq_valid : _T_2526 ? _Queue64_UInt8_4_io_deq_valid : _T_2525 ? _Queue64_UInt8_3_io_deq_valid : _T_2524 ? _Queue64_UInt8_2_io_deq_valid : _T_2523 ? _Queue64_UInt8_1_io_deq_valid : _T_2522 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_98 = _remapindex_T_7 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_7 = _GEN_98[5:0]; // @[MemLoader.scala:177:54]
wire _T_2554 = remapindex_7 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2555 = remapindex_7 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2556 = remapindex_7 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2557 = remapindex_7 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2558 = remapindex_7 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2559 = remapindex_7 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2560 = remapindex_7 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2561 = remapindex_7 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2562 = remapindex_7 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2563 = remapindex_7 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2564 = remapindex_7 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2565 = remapindex_7 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2566 = remapindex_7 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2567 = remapindex_7 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2568 = remapindex_7 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2569 = remapindex_7 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2570 = remapindex_7 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2571 = remapindex_7 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2572 = remapindex_7 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2573 = remapindex_7 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2574 = remapindex_7 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2575 = remapindex_7 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2576 = remapindex_7 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2577 = remapindex_7 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2578 = remapindex_7 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2579 = remapindex_7 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2580 = remapindex_7 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2581 = remapindex_7 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2582 = remapindex_7 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2583 = remapindex_7 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2584 = remapindex_7 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2585 = remapindex_7 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_bits : _T_2584 ? _Queue64_UInt8_30_io_deq_bits : _T_2583 ? _Queue64_UInt8_29_io_deq_bits : _T_2582 ? _Queue64_UInt8_28_io_deq_bits : _T_2581 ? _Queue64_UInt8_27_io_deq_bits : _T_2580 ? _Queue64_UInt8_26_io_deq_bits : _T_2579 ? _Queue64_UInt8_25_io_deq_bits : _T_2578 ? _Queue64_UInt8_24_io_deq_bits : _T_2577 ? _Queue64_UInt8_23_io_deq_bits : _T_2576 ? _Queue64_UInt8_22_io_deq_bits : _T_2575 ? _Queue64_UInt8_21_io_deq_bits : _T_2574 ? _Queue64_UInt8_20_io_deq_bits : _T_2573 ? _Queue64_UInt8_19_io_deq_bits : _T_2572 ? _Queue64_UInt8_18_io_deq_bits : _T_2571 ? _Queue64_UInt8_17_io_deq_bits : _T_2570 ? _Queue64_UInt8_16_io_deq_bits : _T_2569 ? _Queue64_UInt8_15_io_deq_bits : _T_2568 ? _Queue64_UInt8_14_io_deq_bits : _T_2567 ? _Queue64_UInt8_13_io_deq_bits : _T_2566 ? _Queue64_UInt8_12_io_deq_bits : _T_2565 ? _Queue64_UInt8_11_io_deq_bits : _T_2564 ? _Queue64_UInt8_10_io_deq_bits : _T_2563 ? _Queue64_UInt8_9_io_deq_bits : _T_2562 ? _Queue64_UInt8_8_io_deq_bits : _T_2561 ? _Queue64_UInt8_7_io_deq_bits : _T_2560 ? _Queue64_UInt8_6_io_deq_bits : _T_2559 ? _Queue64_UInt8_5_io_deq_bits : _T_2558 ? _Queue64_UInt8_4_io_deq_bits : _T_2557 ? _Queue64_UInt8_3_io_deq_bits : _T_2556 ? _Queue64_UInt8_2_io_deq_bits : _T_2555 ? _Queue64_UInt8_1_io_deq_bits : _T_2554 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_valid : _T_2584 ? _Queue64_UInt8_30_io_deq_valid : _T_2583 ? _Queue64_UInt8_29_io_deq_valid : _T_2582 ? _Queue64_UInt8_28_io_deq_valid : _T_2581 ? _Queue64_UInt8_27_io_deq_valid : _T_2580 ? _Queue64_UInt8_26_io_deq_valid : _T_2579 ? _Queue64_UInt8_25_io_deq_valid : _T_2578 ? _Queue64_UInt8_24_io_deq_valid : _T_2577 ? _Queue64_UInt8_23_io_deq_valid : _T_2576 ? _Queue64_UInt8_22_io_deq_valid : _T_2575 ? _Queue64_UInt8_21_io_deq_valid : _T_2574 ? _Queue64_UInt8_20_io_deq_valid : _T_2573 ? _Queue64_UInt8_19_io_deq_valid : _T_2572 ? _Queue64_UInt8_18_io_deq_valid : _T_2571 ? _Queue64_UInt8_17_io_deq_valid : _T_2570 ? _Queue64_UInt8_16_io_deq_valid : _T_2569 ? _Queue64_UInt8_15_io_deq_valid : _T_2568 ? _Queue64_UInt8_14_io_deq_valid : _T_2567 ? _Queue64_UInt8_13_io_deq_valid : _T_2566 ? _Queue64_UInt8_12_io_deq_valid : _T_2565 ? _Queue64_UInt8_11_io_deq_valid : _T_2564 ? _Queue64_UInt8_10_io_deq_valid : _T_2563 ? _Queue64_UInt8_9_io_deq_valid : _T_2562 ? _Queue64_UInt8_8_io_deq_valid : _T_2561 ? _Queue64_UInt8_7_io_deq_valid : _T_2560 ? _Queue64_UInt8_6_io_deq_valid : _T_2559 ? _Queue64_UInt8_5_io_deq_valid : _T_2558 ? _Queue64_UInt8_4_io_deq_valid : _T_2557 ? _Queue64_UInt8_3_io_deq_valid : _T_2556 ? _Queue64_UInt8_2_io_deq_valid : _T_2555 ? _Queue64_UInt8_1_io_deq_valid : _T_2554 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_99 = _remapindex_T_8 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_8 = _GEN_99[5:0]; // @[MemLoader.scala:177:54]
wire _T_2586 = remapindex_8 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2587 = remapindex_8 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2588 = remapindex_8 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2589 = remapindex_8 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2590 = remapindex_8 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2591 = remapindex_8 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2592 = remapindex_8 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2593 = remapindex_8 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2594 = remapindex_8 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2595 = remapindex_8 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2596 = remapindex_8 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2597 = remapindex_8 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2598 = remapindex_8 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2599 = remapindex_8 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2600 = remapindex_8 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2601 = remapindex_8 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2602 = remapindex_8 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2603 = remapindex_8 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2604 = remapindex_8 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2605 = remapindex_8 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2606 = remapindex_8 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2607 = remapindex_8 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2608 = remapindex_8 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2609 = remapindex_8 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2610 = remapindex_8 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2611 = remapindex_8 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2612 = remapindex_8 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2613 = remapindex_8 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2614 = remapindex_8 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2615 = remapindex_8 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2616 = remapindex_8 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2617 = remapindex_8 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_bits : _T_2616 ? _Queue64_UInt8_30_io_deq_bits : _T_2615 ? _Queue64_UInt8_29_io_deq_bits : _T_2614 ? _Queue64_UInt8_28_io_deq_bits : _T_2613 ? _Queue64_UInt8_27_io_deq_bits : _T_2612 ? _Queue64_UInt8_26_io_deq_bits : _T_2611 ? _Queue64_UInt8_25_io_deq_bits : _T_2610 ? _Queue64_UInt8_24_io_deq_bits : _T_2609 ? _Queue64_UInt8_23_io_deq_bits : _T_2608 ? _Queue64_UInt8_22_io_deq_bits : _T_2607 ? _Queue64_UInt8_21_io_deq_bits : _T_2606 ? _Queue64_UInt8_20_io_deq_bits : _T_2605 ? _Queue64_UInt8_19_io_deq_bits : _T_2604 ? _Queue64_UInt8_18_io_deq_bits : _T_2603 ? _Queue64_UInt8_17_io_deq_bits : _T_2602 ? _Queue64_UInt8_16_io_deq_bits : _T_2601 ? _Queue64_UInt8_15_io_deq_bits : _T_2600 ? _Queue64_UInt8_14_io_deq_bits : _T_2599 ? _Queue64_UInt8_13_io_deq_bits : _T_2598 ? _Queue64_UInt8_12_io_deq_bits : _T_2597 ? _Queue64_UInt8_11_io_deq_bits : _T_2596 ? _Queue64_UInt8_10_io_deq_bits : _T_2595 ? _Queue64_UInt8_9_io_deq_bits : _T_2594 ? _Queue64_UInt8_8_io_deq_bits : _T_2593 ? _Queue64_UInt8_7_io_deq_bits : _T_2592 ? _Queue64_UInt8_6_io_deq_bits : _T_2591 ? _Queue64_UInt8_5_io_deq_bits : _T_2590 ? _Queue64_UInt8_4_io_deq_bits : _T_2589 ? _Queue64_UInt8_3_io_deq_bits : _T_2588 ? _Queue64_UInt8_2_io_deq_bits : _T_2587 ? _Queue64_UInt8_1_io_deq_bits : _T_2586 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_valid : _T_2616 ? _Queue64_UInt8_30_io_deq_valid : _T_2615 ? _Queue64_UInt8_29_io_deq_valid : _T_2614 ? _Queue64_UInt8_28_io_deq_valid : _T_2613 ? _Queue64_UInt8_27_io_deq_valid : _T_2612 ? _Queue64_UInt8_26_io_deq_valid : _T_2611 ? _Queue64_UInt8_25_io_deq_valid : _T_2610 ? _Queue64_UInt8_24_io_deq_valid : _T_2609 ? _Queue64_UInt8_23_io_deq_valid : _T_2608 ? _Queue64_UInt8_22_io_deq_valid : _T_2607 ? _Queue64_UInt8_21_io_deq_valid : _T_2606 ? _Queue64_UInt8_20_io_deq_valid : _T_2605 ? _Queue64_UInt8_19_io_deq_valid : _T_2604 ? _Queue64_UInt8_18_io_deq_valid : _T_2603 ? _Queue64_UInt8_17_io_deq_valid : _T_2602 ? _Queue64_UInt8_16_io_deq_valid : _T_2601 ? _Queue64_UInt8_15_io_deq_valid : _T_2600 ? _Queue64_UInt8_14_io_deq_valid : _T_2599 ? _Queue64_UInt8_13_io_deq_valid : _T_2598 ? _Queue64_UInt8_12_io_deq_valid : _T_2597 ? _Queue64_UInt8_11_io_deq_valid : _T_2596 ? _Queue64_UInt8_10_io_deq_valid : _T_2595 ? _Queue64_UInt8_9_io_deq_valid : _T_2594 ? _Queue64_UInt8_8_io_deq_valid : _T_2593 ? _Queue64_UInt8_7_io_deq_valid : _T_2592 ? _Queue64_UInt8_6_io_deq_valid : _T_2591 ? _Queue64_UInt8_5_io_deq_valid : _T_2590 ? _Queue64_UInt8_4_io_deq_valid : _T_2589 ? _Queue64_UInt8_3_io_deq_valid : _T_2588 ? _Queue64_UInt8_2_io_deq_valid : _T_2587 ? _Queue64_UInt8_1_io_deq_valid : _T_2586 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_100 = _remapindex_T_9 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_9 = _GEN_100[5:0]; // @[MemLoader.scala:177:54]
wire _T_2618 = remapindex_9 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2619 = remapindex_9 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2620 = remapindex_9 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2621 = remapindex_9 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2622 = remapindex_9 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2623 = remapindex_9 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2624 = remapindex_9 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2625 = remapindex_9 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2626 = remapindex_9 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2627 = remapindex_9 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2628 = remapindex_9 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2629 = remapindex_9 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2630 = remapindex_9 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2631 = remapindex_9 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2632 = remapindex_9 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2633 = remapindex_9 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2634 = remapindex_9 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2635 = remapindex_9 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2636 = remapindex_9 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2637 = remapindex_9 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2638 = remapindex_9 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2639 = remapindex_9 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2640 = remapindex_9 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2641 = remapindex_9 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2642 = remapindex_9 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2643 = remapindex_9 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2644 = remapindex_9 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2645 = remapindex_9 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2646 = remapindex_9 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2647 = remapindex_9 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2648 = remapindex_9 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2649 = remapindex_9 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_bits : _T_2648 ? _Queue64_UInt8_30_io_deq_bits : _T_2647 ? _Queue64_UInt8_29_io_deq_bits : _T_2646 ? _Queue64_UInt8_28_io_deq_bits : _T_2645 ? _Queue64_UInt8_27_io_deq_bits : _T_2644 ? _Queue64_UInt8_26_io_deq_bits : _T_2643 ? _Queue64_UInt8_25_io_deq_bits : _T_2642 ? _Queue64_UInt8_24_io_deq_bits : _T_2641 ? _Queue64_UInt8_23_io_deq_bits : _T_2640 ? _Queue64_UInt8_22_io_deq_bits : _T_2639 ? _Queue64_UInt8_21_io_deq_bits : _T_2638 ? _Queue64_UInt8_20_io_deq_bits : _T_2637 ? _Queue64_UInt8_19_io_deq_bits : _T_2636 ? _Queue64_UInt8_18_io_deq_bits : _T_2635 ? _Queue64_UInt8_17_io_deq_bits : _T_2634 ? _Queue64_UInt8_16_io_deq_bits : _T_2633 ? _Queue64_UInt8_15_io_deq_bits : _T_2632 ? _Queue64_UInt8_14_io_deq_bits : _T_2631 ? _Queue64_UInt8_13_io_deq_bits : _T_2630 ? _Queue64_UInt8_12_io_deq_bits : _T_2629 ? _Queue64_UInt8_11_io_deq_bits : _T_2628 ? _Queue64_UInt8_10_io_deq_bits : _T_2627 ? _Queue64_UInt8_9_io_deq_bits : _T_2626 ? _Queue64_UInt8_8_io_deq_bits : _T_2625 ? _Queue64_UInt8_7_io_deq_bits : _T_2624 ? _Queue64_UInt8_6_io_deq_bits : _T_2623 ? _Queue64_UInt8_5_io_deq_bits : _T_2622 ? _Queue64_UInt8_4_io_deq_bits : _T_2621 ? _Queue64_UInt8_3_io_deq_bits : _T_2620 ? _Queue64_UInt8_2_io_deq_bits : _T_2619 ? _Queue64_UInt8_1_io_deq_bits : _T_2618 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_valid : _T_2648 ? _Queue64_UInt8_30_io_deq_valid : _T_2647 ? _Queue64_UInt8_29_io_deq_valid : _T_2646 ? _Queue64_UInt8_28_io_deq_valid : _T_2645 ? _Queue64_UInt8_27_io_deq_valid : _T_2644 ? _Queue64_UInt8_26_io_deq_valid : _T_2643 ? _Queue64_UInt8_25_io_deq_valid : _T_2642 ? _Queue64_UInt8_24_io_deq_valid : _T_2641 ? _Queue64_UInt8_23_io_deq_valid : _T_2640 ? _Queue64_UInt8_22_io_deq_valid : _T_2639 ? _Queue64_UInt8_21_io_deq_valid : _T_2638 ? _Queue64_UInt8_20_io_deq_valid : _T_2637 ? _Queue64_UInt8_19_io_deq_valid : _T_2636 ? _Queue64_UInt8_18_io_deq_valid : _T_2635 ? _Queue64_UInt8_17_io_deq_valid : _T_2634 ? _Queue64_UInt8_16_io_deq_valid : _T_2633 ? _Queue64_UInt8_15_io_deq_valid : _T_2632 ? _Queue64_UInt8_14_io_deq_valid : _T_2631 ? _Queue64_UInt8_13_io_deq_valid : _T_2630 ? _Queue64_UInt8_12_io_deq_valid : _T_2629 ? _Queue64_UInt8_11_io_deq_valid : _T_2628 ? _Queue64_UInt8_10_io_deq_valid : _T_2627 ? _Queue64_UInt8_9_io_deq_valid : _T_2626 ? _Queue64_UInt8_8_io_deq_valid : _T_2625 ? _Queue64_UInt8_7_io_deq_valid : _T_2624 ? _Queue64_UInt8_6_io_deq_valid : _T_2623 ? _Queue64_UInt8_5_io_deq_valid : _T_2622 ? _Queue64_UInt8_4_io_deq_valid : _T_2621 ? _Queue64_UInt8_3_io_deq_valid : _T_2620 ? _Queue64_UInt8_2_io_deq_valid : _T_2619 ? _Queue64_UInt8_1_io_deq_valid : _T_2618 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_101 = _remapindex_T_10 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_10 = _GEN_101[5:0]; // @[MemLoader.scala:177:54]
wire _T_2650 = remapindex_10 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2651 = remapindex_10 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2652 = remapindex_10 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2653 = remapindex_10 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2654 = remapindex_10 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2655 = remapindex_10 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2656 = remapindex_10 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2657 = remapindex_10 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2658 = remapindex_10 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2659 = remapindex_10 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2660 = remapindex_10 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2661 = remapindex_10 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2662 = remapindex_10 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2663 = remapindex_10 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2664 = remapindex_10 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2665 = remapindex_10 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2666 = remapindex_10 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2667 = remapindex_10 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2668 = remapindex_10 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2669 = remapindex_10 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2670 = remapindex_10 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2671 = remapindex_10 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2672 = remapindex_10 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2673 = remapindex_10 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2674 = remapindex_10 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2675 = remapindex_10 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2676 = remapindex_10 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2677 = remapindex_10 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2678 = remapindex_10 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2679 = remapindex_10 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2680 = remapindex_10 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2681 = remapindex_10 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_bits : _T_2680 ? _Queue64_UInt8_30_io_deq_bits : _T_2679 ? _Queue64_UInt8_29_io_deq_bits : _T_2678 ? _Queue64_UInt8_28_io_deq_bits : _T_2677 ? _Queue64_UInt8_27_io_deq_bits : _T_2676 ? _Queue64_UInt8_26_io_deq_bits : _T_2675 ? _Queue64_UInt8_25_io_deq_bits : _T_2674 ? _Queue64_UInt8_24_io_deq_bits : _T_2673 ? _Queue64_UInt8_23_io_deq_bits : _T_2672 ? _Queue64_UInt8_22_io_deq_bits : _T_2671 ? _Queue64_UInt8_21_io_deq_bits : _T_2670 ? _Queue64_UInt8_20_io_deq_bits : _T_2669 ? _Queue64_UInt8_19_io_deq_bits : _T_2668 ? _Queue64_UInt8_18_io_deq_bits : _T_2667 ? _Queue64_UInt8_17_io_deq_bits : _T_2666 ? _Queue64_UInt8_16_io_deq_bits : _T_2665 ? _Queue64_UInt8_15_io_deq_bits : _T_2664 ? _Queue64_UInt8_14_io_deq_bits : _T_2663 ? _Queue64_UInt8_13_io_deq_bits : _T_2662 ? _Queue64_UInt8_12_io_deq_bits : _T_2661 ? _Queue64_UInt8_11_io_deq_bits : _T_2660 ? _Queue64_UInt8_10_io_deq_bits : _T_2659 ? _Queue64_UInt8_9_io_deq_bits : _T_2658 ? _Queue64_UInt8_8_io_deq_bits : _T_2657 ? _Queue64_UInt8_7_io_deq_bits : _T_2656 ? _Queue64_UInt8_6_io_deq_bits : _T_2655 ? _Queue64_UInt8_5_io_deq_bits : _T_2654 ? _Queue64_UInt8_4_io_deq_bits : _T_2653 ? _Queue64_UInt8_3_io_deq_bits : _T_2652 ? _Queue64_UInt8_2_io_deq_bits : _T_2651 ? _Queue64_UInt8_1_io_deq_bits : _T_2650 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_valid : _T_2680 ? _Queue64_UInt8_30_io_deq_valid : _T_2679 ? _Queue64_UInt8_29_io_deq_valid : _T_2678 ? _Queue64_UInt8_28_io_deq_valid : _T_2677 ? _Queue64_UInt8_27_io_deq_valid : _T_2676 ? _Queue64_UInt8_26_io_deq_valid : _T_2675 ? _Queue64_UInt8_25_io_deq_valid : _T_2674 ? _Queue64_UInt8_24_io_deq_valid : _T_2673 ? _Queue64_UInt8_23_io_deq_valid : _T_2672 ? _Queue64_UInt8_22_io_deq_valid : _T_2671 ? _Queue64_UInt8_21_io_deq_valid : _T_2670 ? _Queue64_UInt8_20_io_deq_valid : _T_2669 ? _Queue64_UInt8_19_io_deq_valid : _T_2668 ? _Queue64_UInt8_18_io_deq_valid : _T_2667 ? _Queue64_UInt8_17_io_deq_valid : _T_2666 ? _Queue64_UInt8_16_io_deq_valid : _T_2665 ? _Queue64_UInt8_15_io_deq_valid : _T_2664 ? _Queue64_UInt8_14_io_deq_valid : _T_2663 ? _Queue64_UInt8_13_io_deq_valid : _T_2662 ? _Queue64_UInt8_12_io_deq_valid : _T_2661 ? _Queue64_UInt8_11_io_deq_valid : _T_2660 ? _Queue64_UInt8_10_io_deq_valid : _T_2659 ? _Queue64_UInt8_9_io_deq_valid : _T_2658 ? _Queue64_UInt8_8_io_deq_valid : _T_2657 ? _Queue64_UInt8_7_io_deq_valid : _T_2656 ? _Queue64_UInt8_6_io_deq_valid : _T_2655 ? _Queue64_UInt8_5_io_deq_valid : _T_2654 ? _Queue64_UInt8_4_io_deq_valid : _T_2653 ? _Queue64_UInt8_3_io_deq_valid : _T_2652 ? _Queue64_UInt8_2_io_deq_valid : _T_2651 ? _Queue64_UInt8_1_io_deq_valid : _T_2650 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_102 = _remapindex_T_11 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_11 = _GEN_102[5:0]; // @[MemLoader.scala:177:54]
wire _T_2682 = remapindex_11 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2683 = remapindex_11 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2684 = remapindex_11 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2685 = remapindex_11 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2686 = remapindex_11 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2687 = remapindex_11 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2688 = remapindex_11 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2689 = remapindex_11 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2690 = remapindex_11 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2691 = remapindex_11 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2692 = remapindex_11 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2693 = remapindex_11 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2694 = remapindex_11 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2695 = remapindex_11 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2696 = remapindex_11 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2697 = remapindex_11 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2698 = remapindex_11 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2699 = remapindex_11 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2700 = remapindex_11 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2701 = remapindex_11 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2702 = remapindex_11 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2703 = remapindex_11 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2704 = remapindex_11 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2705 = remapindex_11 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2706 = remapindex_11 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2707 = remapindex_11 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2708 = remapindex_11 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2709 = remapindex_11 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2710 = remapindex_11 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2711 = remapindex_11 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2712 = remapindex_11 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2713 = remapindex_11 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_bits : _T_2712 ? _Queue64_UInt8_30_io_deq_bits : _T_2711 ? _Queue64_UInt8_29_io_deq_bits : _T_2710 ? _Queue64_UInt8_28_io_deq_bits : _T_2709 ? _Queue64_UInt8_27_io_deq_bits : _T_2708 ? _Queue64_UInt8_26_io_deq_bits : _T_2707 ? _Queue64_UInt8_25_io_deq_bits : _T_2706 ? _Queue64_UInt8_24_io_deq_bits : _T_2705 ? _Queue64_UInt8_23_io_deq_bits : _T_2704 ? _Queue64_UInt8_22_io_deq_bits : _T_2703 ? _Queue64_UInt8_21_io_deq_bits : _T_2702 ? _Queue64_UInt8_20_io_deq_bits : _T_2701 ? _Queue64_UInt8_19_io_deq_bits : _T_2700 ? _Queue64_UInt8_18_io_deq_bits : _T_2699 ? _Queue64_UInt8_17_io_deq_bits : _T_2698 ? _Queue64_UInt8_16_io_deq_bits : _T_2697 ? _Queue64_UInt8_15_io_deq_bits : _T_2696 ? _Queue64_UInt8_14_io_deq_bits : _T_2695 ? _Queue64_UInt8_13_io_deq_bits : _T_2694 ? _Queue64_UInt8_12_io_deq_bits : _T_2693 ? _Queue64_UInt8_11_io_deq_bits : _T_2692 ? _Queue64_UInt8_10_io_deq_bits : _T_2691 ? _Queue64_UInt8_9_io_deq_bits : _T_2690 ? _Queue64_UInt8_8_io_deq_bits : _T_2689 ? _Queue64_UInt8_7_io_deq_bits : _T_2688 ? _Queue64_UInt8_6_io_deq_bits : _T_2687 ? _Queue64_UInt8_5_io_deq_bits : _T_2686 ? _Queue64_UInt8_4_io_deq_bits : _T_2685 ? _Queue64_UInt8_3_io_deq_bits : _T_2684 ? _Queue64_UInt8_2_io_deq_bits : _T_2683 ? _Queue64_UInt8_1_io_deq_bits : _T_2682 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_valid : _T_2712 ? _Queue64_UInt8_30_io_deq_valid : _T_2711 ? _Queue64_UInt8_29_io_deq_valid : _T_2710 ? _Queue64_UInt8_28_io_deq_valid : _T_2709 ? _Queue64_UInt8_27_io_deq_valid : _T_2708 ? _Queue64_UInt8_26_io_deq_valid : _T_2707 ? _Queue64_UInt8_25_io_deq_valid : _T_2706 ? _Queue64_UInt8_24_io_deq_valid : _T_2705 ? _Queue64_UInt8_23_io_deq_valid : _T_2704 ? _Queue64_UInt8_22_io_deq_valid : _T_2703 ? _Queue64_UInt8_21_io_deq_valid : _T_2702 ? _Queue64_UInt8_20_io_deq_valid : _T_2701 ? _Queue64_UInt8_19_io_deq_valid : _T_2700 ? _Queue64_UInt8_18_io_deq_valid : _T_2699 ? _Queue64_UInt8_17_io_deq_valid : _T_2698 ? _Queue64_UInt8_16_io_deq_valid : _T_2697 ? _Queue64_UInt8_15_io_deq_valid : _T_2696 ? _Queue64_UInt8_14_io_deq_valid : _T_2695 ? _Queue64_UInt8_13_io_deq_valid : _T_2694 ? _Queue64_UInt8_12_io_deq_valid : _T_2693 ? _Queue64_UInt8_11_io_deq_valid : _T_2692 ? _Queue64_UInt8_10_io_deq_valid : _T_2691 ? _Queue64_UInt8_9_io_deq_valid : _T_2690 ? _Queue64_UInt8_8_io_deq_valid : _T_2689 ? _Queue64_UInt8_7_io_deq_valid : _T_2688 ? _Queue64_UInt8_6_io_deq_valid : _T_2687 ? _Queue64_UInt8_5_io_deq_valid : _T_2686 ? _Queue64_UInt8_4_io_deq_valid : _T_2685 ? _Queue64_UInt8_3_io_deq_valid : _T_2684 ? _Queue64_UInt8_2_io_deq_valid : _T_2683 ? _Queue64_UInt8_1_io_deq_valid : _T_2682 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_103 = _remapindex_T_12 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_12 = _GEN_103[5:0]; // @[MemLoader.scala:177:54]
wire _T_2714 = remapindex_12 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2715 = remapindex_12 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2716 = remapindex_12 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2717 = remapindex_12 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2718 = remapindex_12 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2719 = remapindex_12 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2720 = remapindex_12 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2721 = remapindex_12 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2722 = remapindex_12 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2723 = remapindex_12 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2724 = remapindex_12 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2725 = remapindex_12 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2726 = remapindex_12 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2727 = remapindex_12 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2728 = remapindex_12 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2729 = remapindex_12 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2730 = remapindex_12 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2731 = remapindex_12 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2732 = remapindex_12 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2733 = remapindex_12 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2734 = remapindex_12 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2735 = remapindex_12 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2736 = remapindex_12 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2737 = remapindex_12 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2738 = remapindex_12 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2739 = remapindex_12 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2740 = remapindex_12 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2741 = remapindex_12 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2742 = remapindex_12 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2743 = remapindex_12 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2744 = remapindex_12 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2745 = remapindex_12 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_bits : _T_2744 ? _Queue64_UInt8_30_io_deq_bits : _T_2743 ? _Queue64_UInt8_29_io_deq_bits : _T_2742 ? _Queue64_UInt8_28_io_deq_bits : _T_2741 ? _Queue64_UInt8_27_io_deq_bits : _T_2740 ? _Queue64_UInt8_26_io_deq_bits : _T_2739 ? _Queue64_UInt8_25_io_deq_bits : _T_2738 ? _Queue64_UInt8_24_io_deq_bits : _T_2737 ? _Queue64_UInt8_23_io_deq_bits : _T_2736 ? _Queue64_UInt8_22_io_deq_bits : _T_2735 ? _Queue64_UInt8_21_io_deq_bits : _T_2734 ? _Queue64_UInt8_20_io_deq_bits : _T_2733 ? _Queue64_UInt8_19_io_deq_bits : _T_2732 ? _Queue64_UInt8_18_io_deq_bits : _T_2731 ? _Queue64_UInt8_17_io_deq_bits : _T_2730 ? _Queue64_UInt8_16_io_deq_bits : _T_2729 ? _Queue64_UInt8_15_io_deq_bits : _T_2728 ? _Queue64_UInt8_14_io_deq_bits : _T_2727 ? _Queue64_UInt8_13_io_deq_bits : _T_2726 ? _Queue64_UInt8_12_io_deq_bits : _T_2725 ? _Queue64_UInt8_11_io_deq_bits : _T_2724 ? _Queue64_UInt8_10_io_deq_bits : _T_2723 ? _Queue64_UInt8_9_io_deq_bits : _T_2722 ? _Queue64_UInt8_8_io_deq_bits : _T_2721 ? _Queue64_UInt8_7_io_deq_bits : _T_2720 ? _Queue64_UInt8_6_io_deq_bits : _T_2719 ? _Queue64_UInt8_5_io_deq_bits : _T_2718 ? _Queue64_UInt8_4_io_deq_bits : _T_2717 ? _Queue64_UInt8_3_io_deq_bits : _T_2716 ? _Queue64_UInt8_2_io_deq_bits : _T_2715 ? _Queue64_UInt8_1_io_deq_bits : _T_2714 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_valid : _T_2744 ? _Queue64_UInt8_30_io_deq_valid : _T_2743 ? _Queue64_UInt8_29_io_deq_valid : _T_2742 ? _Queue64_UInt8_28_io_deq_valid : _T_2741 ? _Queue64_UInt8_27_io_deq_valid : _T_2740 ? _Queue64_UInt8_26_io_deq_valid : _T_2739 ? _Queue64_UInt8_25_io_deq_valid : _T_2738 ? _Queue64_UInt8_24_io_deq_valid : _T_2737 ? _Queue64_UInt8_23_io_deq_valid : _T_2736 ? _Queue64_UInt8_22_io_deq_valid : _T_2735 ? _Queue64_UInt8_21_io_deq_valid : _T_2734 ? _Queue64_UInt8_20_io_deq_valid : _T_2733 ? _Queue64_UInt8_19_io_deq_valid : _T_2732 ? _Queue64_UInt8_18_io_deq_valid : _T_2731 ? _Queue64_UInt8_17_io_deq_valid : _T_2730 ? _Queue64_UInt8_16_io_deq_valid : _T_2729 ? _Queue64_UInt8_15_io_deq_valid : _T_2728 ? _Queue64_UInt8_14_io_deq_valid : _T_2727 ? _Queue64_UInt8_13_io_deq_valid : _T_2726 ? _Queue64_UInt8_12_io_deq_valid : _T_2725 ? _Queue64_UInt8_11_io_deq_valid : _T_2724 ? _Queue64_UInt8_10_io_deq_valid : _T_2723 ? _Queue64_UInt8_9_io_deq_valid : _T_2722 ? _Queue64_UInt8_8_io_deq_valid : _T_2721 ? _Queue64_UInt8_7_io_deq_valid : _T_2720 ? _Queue64_UInt8_6_io_deq_valid : _T_2719 ? _Queue64_UInt8_5_io_deq_valid : _T_2718 ? _Queue64_UInt8_4_io_deq_valid : _T_2717 ? _Queue64_UInt8_3_io_deq_valid : _T_2716 ? _Queue64_UInt8_2_io_deq_valid : _T_2715 ? _Queue64_UInt8_1_io_deq_valid : _T_2714 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_104 = _remapindex_T_13 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_13 = _GEN_104[5:0]; // @[MemLoader.scala:177:54]
wire _T_2746 = remapindex_13 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2747 = remapindex_13 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2748 = remapindex_13 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2749 = remapindex_13 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2750 = remapindex_13 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2751 = remapindex_13 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2752 = remapindex_13 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2753 = remapindex_13 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2754 = remapindex_13 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2755 = remapindex_13 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2756 = remapindex_13 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2757 = remapindex_13 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2758 = remapindex_13 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2759 = remapindex_13 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2760 = remapindex_13 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2761 = remapindex_13 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2762 = remapindex_13 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2763 = remapindex_13 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2764 = remapindex_13 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2765 = remapindex_13 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2766 = remapindex_13 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2767 = remapindex_13 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2768 = remapindex_13 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2769 = remapindex_13 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2770 = remapindex_13 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2771 = remapindex_13 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2772 = remapindex_13 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2773 = remapindex_13 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2774 = remapindex_13 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2775 = remapindex_13 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2776 = remapindex_13 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2777 = remapindex_13 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_bits : _T_2776 ? _Queue64_UInt8_30_io_deq_bits : _T_2775 ? _Queue64_UInt8_29_io_deq_bits : _T_2774 ? _Queue64_UInt8_28_io_deq_bits : _T_2773 ? _Queue64_UInt8_27_io_deq_bits : _T_2772 ? _Queue64_UInt8_26_io_deq_bits : _T_2771 ? _Queue64_UInt8_25_io_deq_bits : _T_2770 ? _Queue64_UInt8_24_io_deq_bits : _T_2769 ? _Queue64_UInt8_23_io_deq_bits : _T_2768 ? _Queue64_UInt8_22_io_deq_bits : _T_2767 ? _Queue64_UInt8_21_io_deq_bits : _T_2766 ? _Queue64_UInt8_20_io_deq_bits : _T_2765 ? _Queue64_UInt8_19_io_deq_bits : _T_2764 ? _Queue64_UInt8_18_io_deq_bits : _T_2763 ? _Queue64_UInt8_17_io_deq_bits : _T_2762 ? _Queue64_UInt8_16_io_deq_bits : _T_2761 ? _Queue64_UInt8_15_io_deq_bits : _T_2760 ? _Queue64_UInt8_14_io_deq_bits : _T_2759 ? _Queue64_UInt8_13_io_deq_bits : _T_2758 ? _Queue64_UInt8_12_io_deq_bits : _T_2757 ? _Queue64_UInt8_11_io_deq_bits : _T_2756 ? _Queue64_UInt8_10_io_deq_bits : _T_2755 ? _Queue64_UInt8_9_io_deq_bits : _T_2754 ? _Queue64_UInt8_8_io_deq_bits : _T_2753 ? _Queue64_UInt8_7_io_deq_bits : _T_2752 ? _Queue64_UInt8_6_io_deq_bits : _T_2751 ? _Queue64_UInt8_5_io_deq_bits : _T_2750 ? _Queue64_UInt8_4_io_deq_bits : _T_2749 ? _Queue64_UInt8_3_io_deq_bits : _T_2748 ? _Queue64_UInt8_2_io_deq_bits : _T_2747 ? _Queue64_UInt8_1_io_deq_bits : _T_2746 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_valid : _T_2776 ? _Queue64_UInt8_30_io_deq_valid : _T_2775 ? _Queue64_UInt8_29_io_deq_valid : _T_2774 ? _Queue64_UInt8_28_io_deq_valid : _T_2773 ? _Queue64_UInt8_27_io_deq_valid : _T_2772 ? _Queue64_UInt8_26_io_deq_valid : _T_2771 ? _Queue64_UInt8_25_io_deq_valid : _T_2770 ? _Queue64_UInt8_24_io_deq_valid : _T_2769 ? _Queue64_UInt8_23_io_deq_valid : _T_2768 ? _Queue64_UInt8_22_io_deq_valid : _T_2767 ? _Queue64_UInt8_21_io_deq_valid : _T_2766 ? _Queue64_UInt8_20_io_deq_valid : _T_2765 ? _Queue64_UInt8_19_io_deq_valid : _T_2764 ? _Queue64_UInt8_18_io_deq_valid : _T_2763 ? _Queue64_UInt8_17_io_deq_valid : _T_2762 ? _Queue64_UInt8_16_io_deq_valid : _T_2761 ? _Queue64_UInt8_15_io_deq_valid : _T_2760 ? _Queue64_UInt8_14_io_deq_valid : _T_2759 ? _Queue64_UInt8_13_io_deq_valid : _T_2758 ? _Queue64_UInt8_12_io_deq_valid : _T_2757 ? _Queue64_UInt8_11_io_deq_valid : _T_2756 ? _Queue64_UInt8_10_io_deq_valid : _T_2755 ? _Queue64_UInt8_9_io_deq_valid : _T_2754 ? _Queue64_UInt8_8_io_deq_valid : _T_2753 ? _Queue64_UInt8_7_io_deq_valid : _T_2752 ? _Queue64_UInt8_6_io_deq_valid : _T_2751 ? _Queue64_UInt8_5_io_deq_valid : _T_2750 ? _Queue64_UInt8_4_io_deq_valid : _T_2749 ? _Queue64_UInt8_3_io_deq_valid : _T_2748 ? _Queue64_UInt8_2_io_deq_valid : _T_2747 ? _Queue64_UInt8_1_io_deq_valid : _T_2746 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_105 = _remapindex_T_14 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_14 = _GEN_105[5:0]; // @[MemLoader.scala:177:54]
wire _T_2778 = remapindex_14 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2779 = remapindex_14 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2780 = remapindex_14 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2781 = remapindex_14 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2782 = remapindex_14 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2783 = remapindex_14 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2784 = remapindex_14 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2785 = remapindex_14 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2786 = remapindex_14 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2787 = remapindex_14 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2788 = remapindex_14 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2789 = remapindex_14 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2790 = remapindex_14 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2791 = remapindex_14 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2792 = remapindex_14 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2793 = remapindex_14 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2794 = remapindex_14 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2795 = remapindex_14 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2796 = remapindex_14 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2797 = remapindex_14 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2798 = remapindex_14 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2799 = remapindex_14 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2800 = remapindex_14 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2801 = remapindex_14 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2802 = remapindex_14 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2803 = remapindex_14 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2804 = remapindex_14 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2805 = remapindex_14 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2806 = remapindex_14 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2807 = remapindex_14 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2808 = remapindex_14 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2809 = remapindex_14 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_bits : _T_2808 ? _Queue64_UInt8_30_io_deq_bits : _T_2807 ? _Queue64_UInt8_29_io_deq_bits : _T_2806 ? _Queue64_UInt8_28_io_deq_bits : _T_2805 ? _Queue64_UInt8_27_io_deq_bits : _T_2804 ? _Queue64_UInt8_26_io_deq_bits : _T_2803 ? _Queue64_UInt8_25_io_deq_bits : _T_2802 ? _Queue64_UInt8_24_io_deq_bits : _T_2801 ? _Queue64_UInt8_23_io_deq_bits : _T_2800 ? _Queue64_UInt8_22_io_deq_bits : _T_2799 ? _Queue64_UInt8_21_io_deq_bits : _T_2798 ? _Queue64_UInt8_20_io_deq_bits : _T_2797 ? _Queue64_UInt8_19_io_deq_bits : _T_2796 ? _Queue64_UInt8_18_io_deq_bits : _T_2795 ? _Queue64_UInt8_17_io_deq_bits : _T_2794 ? _Queue64_UInt8_16_io_deq_bits : _T_2793 ? _Queue64_UInt8_15_io_deq_bits : _T_2792 ? _Queue64_UInt8_14_io_deq_bits : _T_2791 ? _Queue64_UInt8_13_io_deq_bits : _T_2790 ? _Queue64_UInt8_12_io_deq_bits : _T_2789 ? _Queue64_UInt8_11_io_deq_bits : _T_2788 ? _Queue64_UInt8_10_io_deq_bits : _T_2787 ? _Queue64_UInt8_9_io_deq_bits : _T_2786 ? _Queue64_UInt8_8_io_deq_bits : _T_2785 ? _Queue64_UInt8_7_io_deq_bits : _T_2784 ? _Queue64_UInt8_6_io_deq_bits : _T_2783 ? _Queue64_UInt8_5_io_deq_bits : _T_2782 ? _Queue64_UInt8_4_io_deq_bits : _T_2781 ? _Queue64_UInt8_3_io_deq_bits : _T_2780 ? _Queue64_UInt8_2_io_deq_bits : _T_2779 ? _Queue64_UInt8_1_io_deq_bits : _T_2778 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_valid : _T_2808 ? _Queue64_UInt8_30_io_deq_valid : _T_2807 ? _Queue64_UInt8_29_io_deq_valid : _T_2806 ? _Queue64_UInt8_28_io_deq_valid : _T_2805 ? _Queue64_UInt8_27_io_deq_valid : _T_2804 ? _Queue64_UInt8_26_io_deq_valid : _T_2803 ? _Queue64_UInt8_25_io_deq_valid : _T_2802 ? _Queue64_UInt8_24_io_deq_valid : _T_2801 ? _Queue64_UInt8_23_io_deq_valid : _T_2800 ? _Queue64_UInt8_22_io_deq_valid : _T_2799 ? _Queue64_UInt8_21_io_deq_valid : _T_2798 ? _Queue64_UInt8_20_io_deq_valid : _T_2797 ? _Queue64_UInt8_19_io_deq_valid : _T_2796 ? _Queue64_UInt8_18_io_deq_valid : _T_2795 ? _Queue64_UInt8_17_io_deq_valid : _T_2794 ? _Queue64_UInt8_16_io_deq_valid : _T_2793 ? _Queue64_UInt8_15_io_deq_valid : _T_2792 ? _Queue64_UInt8_14_io_deq_valid : _T_2791 ? _Queue64_UInt8_13_io_deq_valid : _T_2790 ? _Queue64_UInt8_12_io_deq_valid : _T_2789 ? _Queue64_UInt8_11_io_deq_valid : _T_2788 ? _Queue64_UInt8_10_io_deq_valid : _T_2787 ? _Queue64_UInt8_9_io_deq_valid : _T_2786 ? _Queue64_UInt8_8_io_deq_valid : _T_2785 ? _Queue64_UInt8_7_io_deq_valid : _T_2784 ? _Queue64_UInt8_6_io_deq_valid : _T_2783 ? _Queue64_UInt8_5_io_deq_valid : _T_2782 ? _Queue64_UInt8_4_io_deq_valid : _T_2781 ? _Queue64_UInt8_3_io_deq_valid : _T_2780 ? _Queue64_UInt8_2_io_deq_valid : _T_2779 ? _Queue64_UInt8_1_io_deq_valid : _T_2778 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_106 = _remapindex_T_15 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_15 = _GEN_106[5:0]; // @[MemLoader.scala:177:54]
wire _T_2810 = remapindex_15 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2811 = remapindex_15 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2812 = remapindex_15 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2813 = remapindex_15 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2814 = remapindex_15 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2815 = remapindex_15 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2816 = remapindex_15 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2817 = remapindex_15 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2818 = remapindex_15 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2819 = remapindex_15 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2820 = remapindex_15 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2821 = remapindex_15 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2822 = remapindex_15 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2823 = remapindex_15 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2824 = remapindex_15 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2825 = remapindex_15 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2826 = remapindex_15 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2827 = remapindex_15 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2828 = remapindex_15 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2829 = remapindex_15 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2830 = remapindex_15 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2831 = remapindex_15 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2832 = remapindex_15 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2833 = remapindex_15 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2834 = remapindex_15 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2835 = remapindex_15 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2836 = remapindex_15 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2837 = remapindex_15 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2838 = remapindex_15 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2839 = remapindex_15 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2840 = remapindex_15 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2841 = remapindex_15 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_bits : _T_2840 ? _Queue64_UInt8_30_io_deq_bits : _T_2839 ? _Queue64_UInt8_29_io_deq_bits : _T_2838 ? _Queue64_UInt8_28_io_deq_bits : _T_2837 ? _Queue64_UInt8_27_io_deq_bits : _T_2836 ? _Queue64_UInt8_26_io_deq_bits : _T_2835 ? _Queue64_UInt8_25_io_deq_bits : _T_2834 ? _Queue64_UInt8_24_io_deq_bits : _T_2833 ? _Queue64_UInt8_23_io_deq_bits : _T_2832 ? _Queue64_UInt8_22_io_deq_bits : _T_2831 ? _Queue64_UInt8_21_io_deq_bits : _T_2830 ? _Queue64_UInt8_20_io_deq_bits : _T_2829 ? _Queue64_UInt8_19_io_deq_bits : _T_2828 ? _Queue64_UInt8_18_io_deq_bits : _T_2827 ? _Queue64_UInt8_17_io_deq_bits : _T_2826 ? _Queue64_UInt8_16_io_deq_bits : _T_2825 ? _Queue64_UInt8_15_io_deq_bits : _T_2824 ? _Queue64_UInt8_14_io_deq_bits : _T_2823 ? _Queue64_UInt8_13_io_deq_bits : _T_2822 ? _Queue64_UInt8_12_io_deq_bits : _T_2821 ? _Queue64_UInt8_11_io_deq_bits : _T_2820 ? _Queue64_UInt8_10_io_deq_bits : _T_2819 ? _Queue64_UInt8_9_io_deq_bits : _T_2818 ? _Queue64_UInt8_8_io_deq_bits : _T_2817 ? _Queue64_UInt8_7_io_deq_bits : _T_2816 ? _Queue64_UInt8_6_io_deq_bits : _T_2815 ? _Queue64_UInt8_5_io_deq_bits : _T_2814 ? _Queue64_UInt8_4_io_deq_bits : _T_2813 ? _Queue64_UInt8_3_io_deq_bits : _T_2812 ? _Queue64_UInt8_2_io_deq_bits : _T_2811 ? _Queue64_UInt8_1_io_deq_bits : _T_2810 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_valid : _T_2840 ? _Queue64_UInt8_30_io_deq_valid : _T_2839 ? _Queue64_UInt8_29_io_deq_valid : _T_2838 ? _Queue64_UInt8_28_io_deq_valid : _T_2837 ? _Queue64_UInt8_27_io_deq_valid : _T_2836 ? _Queue64_UInt8_26_io_deq_valid : _T_2835 ? _Queue64_UInt8_25_io_deq_valid : _T_2834 ? _Queue64_UInt8_24_io_deq_valid : _T_2833 ? _Queue64_UInt8_23_io_deq_valid : _T_2832 ? _Queue64_UInt8_22_io_deq_valid : _T_2831 ? _Queue64_UInt8_21_io_deq_valid : _T_2830 ? _Queue64_UInt8_20_io_deq_valid : _T_2829 ? _Queue64_UInt8_19_io_deq_valid : _T_2828 ? _Queue64_UInt8_18_io_deq_valid : _T_2827 ? _Queue64_UInt8_17_io_deq_valid : _T_2826 ? _Queue64_UInt8_16_io_deq_valid : _T_2825 ? _Queue64_UInt8_15_io_deq_valid : _T_2824 ? _Queue64_UInt8_14_io_deq_valid : _T_2823 ? _Queue64_UInt8_13_io_deq_valid : _T_2822 ? _Queue64_UInt8_12_io_deq_valid : _T_2821 ? _Queue64_UInt8_11_io_deq_valid : _T_2820 ? _Queue64_UInt8_10_io_deq_valid : _T_2819 ? _Queue64_UInt8_9_io_deq_valid : _T_2818 ? _Queue64_UInt8_8_io_deq_valid : _T_2817 ? _Queue64_UInt8_7_io_deq_valid : _T_2816 ? _Queue64_UInt8_6_io_deq_valid : _T_2815 ? _Queue64_UInt8_5_io_deq_valid : _T_2814 ? _Queue64_UInt8_4_io_deq_valid : _T_2813 ? _Queue64_UInt8_3_io_deq_valid : _T_2812 ? _Queue64_UInt8_2_io_deq_valid : _T_2811 ? _Queue64_UInt8_1_io_deq_valid : _T_2810 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_107 = _remapindex_T_16 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_16 = _GEN_107[5:0]; // @[MemLoader.scala:177:54]
wire _T_2842 = remapindex_16 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2843 = remapindex_16 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2844 = remapindex_16 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2845 = remapindex_16 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2846 = remapindex_16 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2847 = remapindex_16 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2848 = remapindex_16 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2849 = remapindex_16 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2850 = remapindex_16 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2851 = remapindex_16 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2852 = remapindex_16 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2853 = remapindex_16 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2854 = remapindex_16 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2855 = remapindex_16 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2856 = remapindex_16 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2857 = remapindex_16 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2858 = remapindex_16 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2859 = remapindex_16 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2860 = remapindex_16 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2861 = remapindex_16 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2862 = remapindex_16 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2863 = remapindex_16 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2864 = remapindex_16 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2865 = remapindex_16 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2866 = remapindex_16 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2867 = remapindex_16 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2868 = remapindex_16 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2869 = remapindex_16 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2870 = remapindex_16 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2871 = remapindex_16 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2872 = remapindex_16 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2873 = remapindex_16 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_bits : _T_2872 ? _Queue64_UInt8_30_io_deq_bits : _T_2871 ? _Queue64_UInt8_29_io_deq_bits : _T_2870 ? _Queue64_UInt8_28_io_deq_bits : _T_2869 ? _Queue64_UInt8_27_io_deq_bits : _T_2868 ? _Queue64_UInt8_26_io_deq_bits : _T_2867 ? _Queue64_UInt8_25_io_deq_bits : _T_2866 ? _Queue64_UInt8_24_io_deq_bits : _T_2865 ? _Queue64_UInt8_23_io_deq_bits : _T_2864 ? _Queue64_UInt8_22_io_deq_bits : _T_2863 ? _Queue64_UInt8_21_io_deq_bits : _T_2862 ? _Queue64_UInt8_20_io_deq_bits : _T_2861 ? _Queue64_UInt8_19_io_deq_bits : _T_2860 ? _Queue64_UInt8_18_io_deq_bits : _T_2859 ? _Queue64_UInt8_17_io_deq_bits : _T_2858 ? _Queue64_UInt8_16_io_deq_bits : _T_2857 ? _Queue64_UInt8_15_io_deq_bits : _T_2856 ? _Queue64_UInt8_14_io_deq_bits : _T_2855 ? _Queue64_UInt8_13_io_deq_bits : _T_2854 ? _Queue64_UInt8_12_io_deq_bits : _T_2853 ? _Queue64_UInt8_11_io_deq_bits : _T_2852 ? _Queue64_UInt8_10_io_deq_bits : _T_2851 ? _Queue64_UInt8_9_io_deq_bits : _T_2850 ? _Queue64_UInt8_8_io_deq_bits : _T_2849 ? _Queue64_UInt8_7_io_deq_bits : _T_2848 ? _Queue64_UInt8_6_io_deq_bits : _T_2847 ? _Queue64_UInt8_5_io_deq_bits : _T_2846 ? _Queue64_UInt8_4_io_deq_bits : _T_2845 ? _Queue64_UInt8_3_io_deq_bits : _T_2844 ? _Queue64_UInt8_2_io_deq_bits : _T_2843 ? _Queue64_UInt8_1_io_deq_bits : _T_2842 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_valid : _T_2872 ? _Queue64_UInt8_30_io_deq_valid : _T_2871 ? _Queue64_UInt8_29_io_deq_valid : _T_2870 ? _Queue64_UInt8_28_io_deq_valid : _T_2869 ? _Queue64_UInt8_27_io_deq_valid : _T_2868 ? _Queue64_UInt8_26_io_deq_valid : _T_2867 ? _Queue64_UInt8_25_io_deq_valid : _T_2866 ? _Queue64_UInt8_24_io_deq_valid : _T_2865 ? _Queue64_UInt8_23_io_deq_valid : _T_2864 ? _Queue64_UInt8_22_io_deq_valid : _T_2863 ? _Queue64_UInt8_21_io_deq_valid : _T_2862 ? _Queue64_UInt8_20_io_deq_valid : _T_2861 ? _Queue64_UInt8_19_io_deq_valid : _T_2860 ? _Queue64_UInt8_18_io_deq_valid : _T_2859 ? _Queue64_UInt8_17_io_deq_valid : _T_2858 ? _Queue64_UInt8_16_io_deq_valid : _T_2857 ? _Queue64_UInt8_15_io_deq_valid : _T_2856 ? _Queue64_UInt8_14_io_deq_valid : _T_2855 ? _Queue64_UInt8_13_io_deq_valid : _T_2854 ? _Queue64_UInt8_12_io_deq_valid : _T_2853 ? _Queue64_UInt8_11_io_deq_valid : _T_2852 ? _Queue64_UInt8_10_io_deq_valid : _T_2851 ? _Queue64_UInt8_9_io_deq_valid : _T_2850 ? _Queue64_UInt8_8_io_deq_valid : _T_2849 ? _Queue64_UInt8_7_io_deq_valid : _T_2848 ? _Queue64_UInt8_6_io_deq_valid : _T_2847 ? _Queue64_UInt8_5_io_deq_valid : _T_2846 ? _Queue64_UInt8_4_io_deq_valid : _T_2845 ? _Queue64_UInt8_3_io_deq_valid : _T_2844 ? _Queue64_UInt8_2_io_deq_valid : _T_2843 ? _Queue64_UInt8_1_io_deq_valid : _T_2842 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_108 = _remapindex_T_17 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_17 = _GEN_108[5:0]; // @[MemLoader.scala:177:54]
wire _T_2874 = remapindex_17 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2875 = remapindex_17 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2876 = remapindex_17 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2877 = remapindex_17 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2878 = remapindex_17 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2879 = remapindex_17 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2880 = remapindex_17 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2881 = remapindex_17 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2882 = remapindex_17 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2883 = remapindex_17 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2884 = remapindex_17 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2885 = remapindex_17 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2886 = remapindex_17 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2887 = remapindex_17 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2888 = remapindex_17 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2889 = remapindex_17 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2890 = remapindex_17 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2891 = remapindex_17 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2892 = remapindex_17 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2893 = remapindex_17 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2894 = remapindex_17 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2895 = remapindex_17 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2896 = remapindex_17 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2897 = remapindex_17 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2898 = remapindex_17 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2899 = remapindex_17 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2900 = remapindex_17 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2901 = remapindex_17 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2902 = remapindex_17 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2903 = remapindex_17 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2904 = remapindex_17 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2905 = remapindex_17 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_bits : _T_2904 ? _Queue64_UInt8_30_io_deq_bits : _T_2903 ? _Queue64_UInt8_29_io_deq_bits : _T_2902 ? _Queue64_UInt8_28_io_deq_bits : _T_2901 ? _Queue64_UInt8_27_io_deq_bits : _T_2900 ? _Queue64_UInt8_26_io_deq_bits : _T_2899 ? _Queue64_UInt8_25_io_deq_bits : _T_2898 ? _Queue64_UInt8_24_io_deq_bits : _T_2897 ? _Queue64_UInt8_23_io_deq_bits : _T_2896 ? _Queue64_UInt8_22_io_deq_bits : _T_2895 ? _Queue64_UInt8_21_io_deq_bits : _T_2894 ? _Queue64_UInt8_20_io_deq_bits : _T_2893 ? _Queue64_UInt8_19_io_deq_bits : _T_2892 ? _Queue64_UInt8_18_io_deq_bits : _T_2891 ? _Queue64_UInt8_17_io_deq_bits : _T_2890 ? _Queue64_UInt8_16_io_deq_bits : _T_2889 ? _Queue64_UInt8_15_io_deq_bits : _T_2888 ? _Queue64_UInt8_14_io_deq_bits : _T_2887 ? _Queue64_UInt8_13_io_deq_bits : _T_2886 ? _Queue64_UInt8_12_io_deq_bits : _T_2885 ? _Queue64_UInt8_11_io_deq_bits : _T_2884 ? _Queue64_UInt8_10_io_deq_bits : _T_2883 ? _Queue64_UInt8_9_io_deq_bits : _T_2882 ? _Queue64_UInt8_8_io_deq_bits : _T_2881 ? _Queue64_UInt8_7_io_deq_bits : _T_2880 ? _Queue64_UInt8_6_io_deq_bits : _T_2879 ? _Queue64_UInt8_5_io_deq_bits : _T_2878 ? _Queue64_UInt8_4_io_deq_bits : _T_2877 ? _Queue64_UInt8_3_io_deq_bits : _T_2876 ? _Queue64_UInt8_2_io_deq_bits : _T_2875 ? _Queue64_UInt8_1_io_deq_bits : _T_2874 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_valid : _T_2904 ? _Queue64_UInt8_30_io_deq_valid : _T_2903 ? _Queue64_UInt8_29_io_deq_valid : _T_2902 ? _Queue64_UInt8_28_io_deq_valid : _T_2901 ? _Queue64_UInt8_27_io_deq_valid : _T_2900 ? _Queue64_UInt8_26_io_deq_valid : _T_2899 ? _Queue64_UInt8_25_io_deq_valid : _T_2898 ? _Queue64_UInt8_24_io_deq_valid : _T_2897 ? _Queue64_UInt8_23_io_deq_valid : _T_2896 ? _Queue64_UInt8_22_io_deq_valid : _T_2895 ? _Queue64_UInt8_21_io_deq_valid : _T_2894 ? _Queue64_UInt8_20_io_deq_valid : _T_2893 ? _Queue64_UInt8_19_io_deq_valid : _T_2892 ? _Queue64_UInt8_18_io_deq_valid : _T_2891 ? _Queue64_UInt8_17_io_deq_valid : _T_2890 ? _Queue64_UInt8_16_io_deq_valid : _T_2889 ? _Queue64_UInt8_15_io_deq_valid : _T_2888 ? _Queue64_UInt8_14_io_deq_valid : _T_2887 ? _Queue64_UInt8_13_io_deq_valid : _T_2886 ? _Queue64_UInt8_12_io_deq_valid : _T_2885 ? _Queue64_UInt8_11_io_deq_valid : _T_2884 ? _Queue64_UInt8_10_io_deq_valid : _T_2883 ? _Queue64_UInt8_9_io_deq_valid : _T_2882 ? _Queue64_UInt8_8_io_deq_valid : _T_2881 ? _Queue64_UInt8_7_io_deq_valid : _T_2880 ? _Queue64_UInt8_6_io_deq_valid : _T_2879 ? _Queue64_UInt8_5_io_deq_valid : _T_2878 ? _Queue64_UInt8_4_io_deq_valid : _T_2877 ? _Queue64_UInt8_3_io_deq_valid : _T_2876 ? _Queue64_UInt8_2_io_deq_valid : _T_2875 ? _Queue64_UInt8_1_io_deq_valid : _T_2874 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_109 = _remapindex_T_18 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_18 = _GEN_109[5:0]; // @[MemLoader.scala:177:54]
wire _T_2906 = remapindex_18 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2907 = remapindex_18 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2908 = remapindex_18 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2909 = remapindex_18 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2910 = remapindex_18 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2911 = remapindex_18 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2912 = remapindex_18 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2913 = remapindex_18 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2914 = remapindex_18 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2915 = remapindex_18 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2916 = remapindex_18 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2917 = remapindex_18 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2918 = remapindex_18 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2919 = remapindex_18 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2920 = remapindex_18 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2921 = remapindex_18 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2922 = remapindex_18 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2923 = remapindex_18 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2924 = remapindex_18 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2925 = remapindex_18 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2926 = remapindex_18 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2927 = remapindex_18 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2928 = remapindex_18 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2929 = remapindex_18 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2930 = remapindex_18 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2931 = remapindex_18 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2932 = remapindex_18 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2933 = remapindex_18 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2934 = remapindex_18 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2935 = remapindex_18 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2936 = remapindex_18 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2937 = remapindex_18 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_bits : _T_2936 ? _Queue64_UInt8_30_io_deq_bits : _T_2935 ? _Queue64_UInt8_29_io_deq_bits : _T_2934 ? _Queue64_UInt8_28_io_deq_bits : _T_2933 ? _Queue64_UInt8_27_io_deq_bits : _T_2932 ? _Queue64_UInt8_26_io_deq_bits : _T_2931 ? _Queue64_UInt8_25_io_deq_bits : _T_2930 ? _Queue64_UInt8_24_io_deq_bits : _T_2929 ? _Queue64_UInt8_23_io_deq_bits : _T_2928 ? _Queue64_UInt8_22_io_deq_bits : _T_2927 ? _Queue64_UInt8_21_io_deq_bits : _T_2926 ? _Queue64_UInt8_20_io_deq_bits : _T_2925 ? _Queue64_UInt8_19_io_deq_bits : _T_2924 ? _Queue64_UInt8_18_io_deq_bits : _T_2923 ? _Queue64_UInt8_17_io_deq_bits : _T_2922 ? _Queue64_UInt8_16_io_deq_bits : _T_2921 ? _Queue64_UInt8_15_io_deq_bits : _T_2920 ? _Queue64_UInt8_14_io_deq_bits : _T_2919 ? _Queue64_UInt8_13_io_deq_bits : _T_2918 ? _Queue64_UInt8_12_io_deq_bits : _T_2917 ? _Queue64_UInt8_11_io_deq_bits : _T_2916 ? _Queue64_UInt8_10_io_deq_bits : _T_2915 ? _Queue64_UInt8_9_io_deq_bits : _T_2914 ? _Queue64_UInt8_8_io_deq_bits : _T_2913 ? _Queue64_UInt8_7_io_deq_bits : _T_2912 ? _Queue64_UInt8_6_io_deq_bits : _T_2911 ? _Queue64_UInt8_5_io_deq_bits : _T_2910 ? _Queue64_UInt8_4_io_deq_bits : _T_2909 ? _Queue64_UInt8_3_io_deq_bits : _T_2908 ? _Queue64_UInt8_2_io_deq_bits : _T_2907 ? _Queue64_UInt8_1_io_deq_bits : _T_2906 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_valid : _T_2936 ? _Queue64_UInt8_30_io_deq_valid : _T_2935 ? _Queue64_UInt8_29_io_deq_valid : _T_2934 ? _Queue64_UInt8_28_io_deq_valid : _T_2933 ? _Queue64_UInt8_27_io_deq_valid : _T_2932 ? _Queue64_UInt8_26_io_deq_valid : _T_2931 ? _Queue64_UInt8_25_io_deq_valid : _T_2930 ? _Queue64_UInt8_24_io_deq_valid : _T_2929 ? _Queue64_UInt8_23_io_deq_valid : _T_2928 ? _Queue64_UInt8_22_io_deq_valid : _T_2927 ? _Queue64_UInt8_21_io_deq_valid : _T_2926 ? _Queue64_UInt8_20_io_deq_valid : _T_2925 ? _Queue64_UInt8_19_io_deq_valid : _T_2924 ? _Queue64_UInt8_18_io_deq_valid : _T_2923 ? _Queue64_UInt8_17_io_deq_valid : _T_2922 ? _Queue64_UInt8_16_io_deq_valid : _T_2921 ? _Queue64_UInt8_15_io_deq_valid : _T_2920 ? _Queue64_UInt8_14_io_deq_valid : _T_2919 ? _Queue64_UInt8_13_io_deq_valid : _T_2918 ? _Queue64_UInt8_12_io_deq_valid : _T_2917 ? _Queue64_UInt8_11_io_deq_valid : _T_2916 ? _Queue64_UInt8_10_io_deq_valid : _T_2915 ? _Queue64_UInt8_9_io_deq_valid : _T_2914 ? _Queue64_UInt8_8_io_deq_valid : _T_2913 ? _Queue64_UInt8_7_io_deq_valid : _T_2912 ? _Queue64_UInt8_6_io_deq_valid : _T_2911 ? _Queue64_UInt8_5_io_deq_valid : _T_2910 ? _Queue64_UInt8_4_io_deq_valid : _T_2909 ? _Queue64_UInt8_3_io_deq_valid : _T_2908 ? _Queue64_UInt8_2_io_deq_valid : _T_2907 ? _Queue64_UInt8_1_io_deq_valid : _T_2906 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_110 = _remapindex_T_19 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_19 = _GEN_110[5:0]; // @[MemLoader.scala:177:54]
wire _T_2938 = remapindex_19 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2939 = remapindex_19 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2940 = remapindex_19 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2941 = remapindex_19 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2942 = remapindex_19 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2943 = remapindex_19 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2944 = remapindex_19 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2945 = remapindex_19 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2946 = remapindex_19 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2947 = remapindex_19 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2948 = remapindex_19 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2949 = remapindex_19 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2950 = remapindex_19 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2951 = remapindex_19 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2952 = remapindex_19 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2953 = remapindex_19 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2954 = remapindex_19 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2955 = remapindex_19 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2956 = remapindex_19 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2957 = remapindex_19 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2958 = remapindex_19 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2959 = remapindex_19 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2960 = remapindex_19 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2961 = remapindex_19 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2962 = remapindex_19 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2963 = remapindex_19 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2964 = remapindex_19 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2965 = remapindex_19 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2966 = remapindex_19 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2967 = remapindex_19 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_2968 = remapindex_19 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_2969 = remapindex_19 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_bits : _T_2968 ? _Queue64_UInt8_30_io_deq_bits : _T_2967 ? _Queue64_UInt8_29_io_deq_bits : _T_2966 ? _Queue64_UInt8_28_io_deq_bits : _T_2965 ? _Queue64_UInt8_27_io_deq_bits : _T_2964 ? _Queue64_UInt8_26_io_deq_bits : _T_2963 ? _Queue64_UInt8_25_io_deq_bits : _T_2962 ? _Queue64_UInt8_24_io_deq_bits : _T_2961 ? _Queue64_UInt8_23_io_deq_bits : _T_2960 ? _Queue64_UInt8_22_io_deq_bits : _T_2959 ? _Queue64_UInt8_21_io_deq_bits : _T_2958 ? _Queue64_UInt8_20_io_deq_bits : _T_2957 ? _Queue64_UInt8_19_io_deq_bits : _T_2956 ? _Queue64_UInt8_18_io_deq_bits : _T_2955 ? _Queue64_UInt8_17_io_deq_bits : _T_2954 ? _Queue64_UInt8_16_io_deq_bits : _T_2953 ? _Queue64_UInt8_15_io_deq_bits : _T_2952 ? _Queue64_UInt8_14_io_deq_bits : _T_2951 ? _Queue64_UInt8_13_io_deq_bits : _T_2950 ? _Queue64_UInt8_12_io_deq_bits : _T_2949 ? _Queue64_UInt8_11_io_deq_bits : _T_2948 ? _Queue64_UInt8_10_io_deq_bits : _T_2947 ? _Queue64_UInt8_9_io_deq_bits : _T_2946 ? _Queue64_UInt8_8_io_deq_bits : _T_2945 ? _Queue64_UInt8_7_io_deq_bits : _T_2944 ? _Queue64_UInt8_6_io_deq_bits : _T_2943 ? _Queue64_UInt8_5_io_deq_bits : _T_2942 ? _Queue64_UInt8_4_io_deq_bits : _T_2941 ? _Queue64_UInt8_3_io_deq_bits : _T_2940 ? _Queue64_UInt8_2_io_deq_bits : _T_2939 ? _Queue64_UInt8_1_io_deq_bits : _T_2938 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_valid : _T_2968 ? _Queue64_UInt8_30_io_deq_valid : _T_2967 ? _Queue64_UInt8_29_io_deq_valid : _T_2966 ? _Queue64_UInt8_28_io_deq_valid : _T_2965 ? _Queue64_UInt8_27_io_deq_valid : _T_2964 ? _Queue64_UInt8_26_io_deq_valid : _T_2963 ? _Queue64_UInt8_25_io_deq_valid : _T_2962 ? _Queue64_UInt8_24_io_deq_valid : _T_2961 ? _Queue64_UInt8_23_io_deq_valid : _T_2960 ? _Queue64_UInt8_22_io_deq_valid : _T_2959 ? _Queue64_UInt8_21_io_deq_valid : _T_2958 ? _Queue64_UInt8_20_io_deq_valid : _T_2957 ? _Queue64_UInt8_19_io_deq_valid : _T_2956 ? _Queue64_UInt8_18_io_deq_valid : _T_2955 ? _Queue64_UInt8_17_io_deq_valid : _T_2954 ? _Queue64_UInt8_16_io_deq_valid : _T_2953 ? _Queue64_UInt8_15_io_deq_valid : _T_2952 ? _Queue64_UInt8_14_io_deq_valid : _T_2951 ? _Queue64_UInt8_13_io_deq_valid : _T_2950 ? _Queue64_UInt8_12_io_deq_valid : _T_2949 ? _Queue64_UInt8_11_io_deq_valid : _T_2948 ? _Queue64_UInt8_10_io_deq_valid : _T_2947 ? _Queue64_UInt8_9_io_deq_valid : _T_2946 ? _Queue64_UInt8_8_io_deq_valid : _T_2945 ? _Queue64_UInt8_7_io_deq_valid : _T_2944 ? _Queue64_UInt8_6_io_deq_valid : _T_2943 ? _Queue64_UInt8_5_io_deq_valid : _T_2942 ? _Queue64_UInt8_4_io_deq_valid : _T_2941 ? _Queue64_UInt8_3_io_deq_valid : _T_2940 ? _Queue64_UInt8_2_io_deq_valid : _T_2939 ? _Queue64_UInt8_1_io_deq_valid : _T_2938 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_111 = _remapindex_T_20 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_20 = _GEN_111[5:0]; // @[MemLoader.scala:177:54]
wire _T_2970 = remapindex_20 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_2971 = remapindex_20 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_2972 = remapindex_20 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_2973 = remapindex_20 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_2974 = remapindex_20 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_2975 = remapindex_20 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_2976 = remapindex_20 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_2977 = remapindex_20 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_2978 = remapindex_20 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_2979 = remapindex_20 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_2980 = remapindex_20 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_2981 = remapindex_20 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_2982 = remapindex_20 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_2983 = remapindex_20 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_2984 = remapindex_20 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_2985 = remapindex_20 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_2986 = remapindex_20 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_2987 = remapindex_20 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_2988 = remapindex_20 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_2989 = remapindex_20 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_2990 = remapindex_20 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_2991 = remapindex_20 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_2992 = remapindex_20 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_2993 = remapindex_20 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_2994 = remapindex_20 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_2995 = remapindex_20 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_2996 = remapindex_20 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_2997 = remapindex_20 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_2998 = remapindex_20 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_2999 = remapindex_20 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3000 = remapindex_20 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3001 = remapindex_20 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_bits : _T_3000 ? _Queue64_UInt8_30_io_deq_bits : _T_2999 ? _Queue64_UInt8_29_io_deq_bits : _T_2998 ? _Queue64_UInt8_28_io_deq_bits : _T_2997 ? _Queue64_UInt8_27_io_deq_bits : _T_2996 ? _Queue64_UInt8_26_io_deq_bits : _T_2995 ? _Queue64_UInt8_25_io_deq_bits : _T_2994 ? _Queue64_UInt8_24_io_deq_bits : _T_2993 ? _Queue64_UInt8_23_io_deq_bits : _T_2992 ? _Queue64_UInt8_22_io_deq_bits : _T_2991 ? _Queue64_UInt8_21_io_deq_bits : _T_2990 ? _Queue64_UInt8_20_io_deq_bits : _T_2989 ? _Queue64_UInt8_19_io_deq_bits : _T_2988 ? _Queue64_UInt8_18_io_deq_bits : _T_2987 ? _Queue64_UInt8_17_io_deq_bits : _T_2986 ? _Queue64_UInt8_16_io_deq_bits : _T_2985 ? _Queue64_UInt8_15_io_deq_bits : _T_2984 ? _Queue64_UInt8_14_io_deq_bits : _T_2983 ? _Queue64_UInt8_13_io_deq_bits : _T_2982 ? _Queue64_UInt8_12_io_deq_bits : _T_2981 ? _Queue64_UInt8_11_io_deq_bits : _T_2980 ? _Queue64_UInt8_10_io_deq_bits : _T_2979 ? _Queue64_UInt8_9_io_deq_bits : _T_2978 ? _Queue64_UInt8_8_io_deq_bits : _T_2977 ? _Queue64_UInt8_7_io_deq_bits : _T_2976 ? _Queue64_UInt8_6_io_deq_bits : _T_2975 ? _Queue64_UInt8_5_io_deq_bits : _T_2974 ? _Queue64_UInt8_4_io_deq_bits : _T_2973 ? _Queue64_UInt8_3_io_deq_bits : _T_2972 ? _Queue64_UInt8_2_io_deq_bits : _T_2971 ? _Queue64_UInt8_1_io_deq_bits : _T_2970 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_valid : _T_3000 ? _Queue64_UInt8_30_io_deq_valid : _T_2999 ? _Queue64_UInt8_29_io_deq_valid : _T_2998 ? _Queue64_UInt8_28_io_deq_valid : _T_2997 ? _Queue64_UInt8_27_io_deq_valid : _T_2996 ? _Queue64_UInt8_26_io_deq_valid : _T_2995 ? _Queue64_UInt8_25_io_deq_valid : _T_2994 ? _Queue64_UInt8_24_io_deq_valid : _T_2993 ? _Queue64_UInt8_23_io_deq_valid : _T_2992 ? _Queue64_UInt8_22_io_deq_valid : _T_2991 ? _Queue64_UInt8_21_io_deq_valid : _T_2990 ? _Queue64_UInt8_20_io_deq_valid : _T_2989 ? _Queue64_UInt8_19_io_deq_valid : _T_2988 ? _Queue64_UInt8_18_io_deq_valid : _T_2987 ? _Queue64_UInt8_17_io_deq_valid : _T_2986 ? _Queue64_UInt8_16_io_deq_valid : _T_2985 ? _Queue64_UInt8_15_io_deq_valid : _T_2984 ? _Queue64_UInt8_14_io_deq_valid : _T_2983 ? _Queue64_UInt8_13_io_deq_valid : _T_2982 ? _Queue64_UInt8_12_io_deq_valid : _T_2981 ? _Queue64_UInt8_11_io_deq_valid : _T_2980 ? _Queue64_UInt8_10_io_deq_valid : _T_2979 ? _Queue64_UInt8_9_io_deq_valid : _T_2978 ? _Queue64_UInt8_8_io_deq_valid : _T_2977 ? _Queue64_UInt8_7_io_deq_valid : _T_2976 ? _Queue64_UInt8_6_io_deq_valid : _T_2975 ? _Queue64_UInt8_5_io_deq_valid : _T_2974 ? _Queue64_UInt8_4_io_deq_valid : _T_2973 ? _Queue64_UInt8_3_io_deq_valid : _T_2972 ? _Queue64_UInt8_2_io_deq_valid : _T_2971 ? _Queue64_UInt8_1_io_deq_valid : _T_2970 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_112 = _remapindex_T_21 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_21 = _GEN_112[5:0]; // @[MemLoader.scala:177:54]
wire _T_3002 = remapindex_21 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3003 = remapindex_21 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3004 = remapindex_21 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3005 = remapindex_21 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3006 = remapindex_21 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3007 = remapindex_21 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3008 = remapindex_21 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3009 = remapindex_21 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3010 = remapindex_21 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3011 = remapindex_21 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3012 = remapindex_21 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3013 = remapindex_21 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3014 = remapindex_21 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3015 = remapindex_21 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3016 = remapindex_21 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3017 = remapindex_21 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3018 = remapindex_21 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3019 = remapindex_21 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3020 = remapindex_21 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3021 = remapindex_21 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3022 = remapindex_21 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3023 = remapindex_21 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3024 = remapindex_21 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3025 = remapindex_21 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3026 = remapindex_21 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3027 = remapindex_21 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3028 = remapindex_21 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3029 = remapindex_21 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3030 = remapindex_21 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3031 = remapindex_21 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3032 = remapindex_21 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3033 = remapindex_21 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_bits : _T_3032 ? _Queue64_UInt8_30_io_deq_bits : _T_3031 ? _Queue64_UInt8_29_io_deq_bits : _T_3030 ? _Queue64_UInt8_28_io_deq_bits : _T_3029 ? _Queue64_UInt8_27_io_deq_bits : _T_3028 ? _Queue64_UInt8_26_io_deq_bits : _T_3027 ? _Queue64_UInt8_25_io_deq_bits : _T_3026 ? _Queue64_UInt8_24_io_deq_bits : _T_3025 ? _Queue64_UInt8_23_io_deq_bits : _T_3024 ? _Queue64_UInt8_22_io_deq_bits : _T_3023 ? _Queue64_UInt8_21_io_deq_bits : _T_3022 ? _Queue64_UInt8_20_io_deq_bits : _T_3021 ? _Queue64_UInt8_19_io_deq_bits : _T_3020 ? _Queue64_UInt8_18_io_deq_bits : _T_3019 ? _Queue64_UInt8_17_io_deq_bits : _T_3018 ? _Queue64_UInt8_16_io_deq_bits : _T_3017 ? _Queue64_UInt8_15_io_deq_bits : _T_3016 ? _Queue64_UInt8_14_io_deq_bits : _T_3015 ? _Queue64_UInt8_13_io_deq_bits : _T_3014 ? _Queue64_UInt8_12_io_deq_bits : _T_3013 ? _Queue64_UInt8_11_io_deq_bits : _T_3012 ? _Queue64_UInt8_10_io_deq_bits : _T_3011 ? _Queue64_UInt8_9_io_deq_bits : _T_3010 ? _Queue64_UInt8_8_io_deq_bits : _T_3009 ? _Queue64_UInt8_7_io_deq_bits : _T_3008 ? _Queue64_UInt8_6_io_deq_bits : _T_3007 ? _Queue64_UInt8_5_io_deq_bits : _T_3006 ? _Queue64_UInt8_4_io_deq_bits : _T_3005 ? _Queue64_UInt8_3_io_deq_bits : _T_3004 ? _Queue64_UInt8_2_io_deq_bits : _T_3003 ? _Queue64_UInt8_1_io_deq_bits : _T_3002 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_valid : _T_3032 ? _Queue64_UInt8_30_io_deq_valid : _T_3031 ? _Queue64_UInt8_29_io_deq_valid : _T_3030 ? _Queue64_UInt8_28_io_deq_valid : _T_3029 ? _Queue64_UInt8_27_io_deq_valid : _T_3028 ? _Queue64_UInt8_26_io_deq_valid : _T_3027 ? _Queue64_UInt8_25_io_deq_valid : _T_3026 ? _Queue64_UInt8_24_io_deq_valid : _T_3025 ? _Queue64_UInt8_23_io_deq_valid : _T_3024 ? _Queue64_UInt8_22_io_deq_valid : _T_3023 ? _Queue64_UInt8_21_io_deq_valid : _T_3022 ? _Queue64_UInt8_20_io_deq_valid : _T_3021 ? _Queue64_UInt8_19_io_deq_valid : _T_3020 ? _Queue64_UInt8_18_io_deq_valid : _T_3019 ? _Queue64_UInt8_17_io_deq_valid : _T_3018 ? _Queue64_UInt8_16_io_deq_valid : _T_3017 ? _Queue64_UInt8_15_io_deq_valid : _T_3016 ? _Queue64_UInt8_14_io_deq_valid : _T_3015 ? _Queue64_UInt8_13_io_deq_valid : _T_3014 ? _Queue64_UInt8_12_io_deq_valid : _T_3013 ? _Queue64_UInt8_11_io_deq_valid : _T_3012 ? _Queue64_UInt8_10_io_deq_valid : _T_3011 ? _Queue64_UInt8_9_io_deq_valid : _T_3010 ? _Queue64_UInt8_8_io_deq_valid : _T_3009 ? _Queue64_UInt8_7_io_deq_valid : _T_3008 ? _Queue64_UInt8_6_io_deq_valid : _T_3007 ? _Queue64_UInt8_5_io_deq_valid : _T_3006 ? _Queue64_UInt8_4_io_deq_valid : _T_3005 ? _Queue64_UInt8_3_io_deq_valid : _T_3004 ? _Queue64_UInt8_2_io_deq_valid : _T_3003 ? _Queue64_UInt8_1_io_deq_valid : _T_3002 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_113 = _remapindex_T_22 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_22 = _GEN_113[5:0]; // @[MemLoader.scala:177:54]
wire _T_3034 = remapindex_22 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3035 = remapindex_22 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3036 = remapindex_22 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3037 = remapindex_22 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3038 = remapindex_22 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3039 = remapindex_22 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3040 = remapindex_22 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3041 = remapindex_22 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3042 = remapindex_22 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3043 = remapindex_22 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3044 = remapindex_22 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3045 = remapindex_22 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3046 = remapindex_22 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3047 = remapindex_22 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3048 = remapindex_22 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3049 = remapindex_22 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3050 = remapindex_22 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3051 = remapindex_22 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3052 = remapindex_22 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3053 = remapindex_22 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3054 = remapindex_22 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3055 = remapindex_22 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3056 = remapindex_22 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3057 = remapindex_22 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3058 = remapindex_22 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3059 = remapindex_22 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3060 = remapindex_22 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3061 = remapindex_22 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3062 = remapindex_22 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3063 = remapindex_22 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3064 = remapindex_22 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3065 = remapindex_22 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_bits : _T_3064 ? _Queue64_UInt8_30_io_deq_bits : _T_3063 ? _Queue64_UInt8_29_io_deq_bits : _T_3062 ? _Queue64_UInt8_28_io_deq_bits : _T_3061 ? _Queue64_UInt8_27_io_deq_bits : _T_3060 ? _Queue64_UInt8_26_io_deq_bits : _T_3059 ? _Queue64_UInt8_25_io_deq_bits : _T_3058 ? _Queue64_UInt8_24_io_deq_bits : _T_3057 ? _Queue64_UInt8_23_io_deq_bits : _T_3056 ? _Queue64_UInt8_22_io_deq_bits : _T_3055 ? _Queue64_UInt8_21_io_deq_bits : _T_3054 ? _Queue64_UInt8_20_io_deq_bits : _T_3053 ? _Queue64_UInt8_19_io_deq_bits : _T_3052 ? _Queue64_UInt8_18_io_deq_bits : _T_3051 ? _Queue64_UInt8_17_io_deq_bits : _T_3050 ? _Queue64_UInt8_16_io_deq_bits : _T_3049 ? _Queue64_UInt8_15_io_deq_bits : _T_3048 ? _Queue64_UInt8_14_io_deq_bits : _T_3047 ? _Queue64_UInt8_13_io_deq_bits : _T_3046 ? _Queue64_UInt8_12_io_deq_bits : _T_3045 ? _Queue64_UInt8_11_io_deq_bits : _T_3044 ? _Queue64_UInt8_10_io_deq_bits : _T_3043 ? _Queue64_UInt8_9_io_deq_bits : _T_3042 ? _Queue64_UInt8_8_io_deq_bits : _T_3041 ? _Queue64_UInt8_7_io_deq_bits : _T_3040 ? _Queue64_UInt8_6_io_deq_bits : _T_3039 ? _Queue64_UInt8_5_io_deq_bits : _T_3038 ? _Queue64_UInt8_4_io_deq_bits : _T_3037 ? _Queue64_UInt8_3_io_deq_bits : _T_3036 ? _Queue64_UInt8_2_io_deq_bits : _T_3035 ? _Queue64_UInt8_1_io_deq_bits : _T_3034 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_valid : _T_3064 ? _Queue64_UInt8_30_io_deq_valid : _T_3063 ? _Queue64_UInt8_29_io_deq_valid : _T_3062 ? _Queue64_UInt8_28_io_deq_valid : _T_3061 ? _Queue64_UInt8_27_io_deq_valid : _T_3060 ? _Queue64_UInt8_26_io_deq_valid : _T_3059 ? _Queue64_UInt8_25_io_deq_valid : _T_3058 ? _Queue64_UInt8_24_io_deq_valid : _T_3057 ? _Queue64_UInt8_23_io_deq_valid : _T_3056 ? _Queue64_UInt8_22_io_deq_valid : _T_3055 ? _Queue64_UInt8_21_io_deq_valid : _T_3054 ? _Queue64_UInt8_20_io_deq_valid : _T_3053 ? _Queue64_UInt8_19_io_deq_valid : _T_3052 ? _Queue64_UInt8_18_io_deq_valid : _T_3051 ? _Queue64_UInt8_17_io_deq_valid : _T_3050 ? _Queue64_UInt8_16_io_deq_valid : _T_3049 ? _Queue64_UInt8_15_io_deq_valid : _T_3048 ? _Queue64_UInt8_14_io_deq_valid : _T_3047 ? _Queue64_UInt8_13_io_deq_valid : _T_3046 ? _Queue64_UInt8_12_io_deq_valid : _T_3045 ? _Queue64_UInt8_11_io_deq_valid : _T_3044 ? _Queue64_UInt8_10_io_deq_valid : _T_3043 ? _Queue64_UInt8_9_io_deq_valid : _T_3042 ? _Queue64_UInt8_8_io_deq_valid : _T_3041 ? _Queue64_UInt8_7_io_deq_valid : _T_3040 ? _Queue64_UInt8_6_io_deq_valid : _T_3039 ? _Queue64_UInt8_5_io_deq_valid : _T_3038 ? _Queue64_UInt8_4_io_deq_valid : _T_3037 ? _Queue64_UInt8_3_io_deq_valid : _T_3036 ? _Queue64_UInt8_2_io_deq_valid : _T_3035 ? _Queue64_UInt8_1_io_deq_valid : _T_3034 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_114 = _remapindex_T_23 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_23 = _GEN_114[5:0]; // @[MemLoader.scala:177:54]
wire _T_3066 = remapindex_23 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3067 = remapindex_23 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3068 = remapindex_23 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3069 = remapindex_23 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3070 = remapindex_23 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3071 = remapindex_23 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3072 = remapindex_23 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3073 = remapindex_23 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3074 = remapindex_23 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3075 = remapindex_23 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3076 = remapindex_23 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3077 = remapindex_23 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3078 = remapindex_23 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3079 = remapindex_23 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3080 = remapindex_23 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3081 = remapindex_23 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3082 = remapindex_23 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3083 = remapindex_23 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3084 = remapindex_23 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3085 = remapindex_23 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3086 = remapindex_23 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3087 = remapindex_23 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3088 = remapindex_23 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3089 = remapindex_23 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3090 = remapindex_23 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3091 = remapindex_23 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3092 = remapindex_23 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3093 = remapindex_23 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3094 = remapindex_23 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3095 = remapindex_23 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3096 = remapindex_23 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3097 = remapindex_23 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_bits : _T_3096 ? _Queue64_UInt8_30_io_deq_bits : _T_3095 ? _Queue64_UInt8_29_io_deq_bits : _T_3094 ? _Queue64_UInt8_28_io_deq_bits : _T_3093 ? _Queue64_UInt8_27_io_deq_bits : _T_3092 ? _Queue64_UInt8_26_io_deq_bits : _T_3091 ? _Queue64_UInt8_25_io_deq_bits : _T_3090 ? _Queue64_UInt8_24_io_deq_bits : _T_3089 ? _Queue64_UInt8_23_io_deq_bits : _T_3088 ? _Queue64_UInt8_22_io_deq_bits : _T_3087 ? _Queue64_UInt8_21_io_deq_bits : _T_3086 ? _Queue64_UInt8_20_io_deq_bits : _T_3085 ? _Queue64_UInt8_19_io_deq_bits : _T_3084 ? _Queue64_UInt8_18_io_deq_bits : _T_3083 ? _Queue64_UInt8_17_io_deq_bits : _T_3082 ? _Queue64_UInt8_16_io_deq_bits : _T_3081 ? _Queue64_UInt8_15_io_deq_bits : _T_3080 ? _Queue64_UInt8_14_io_deq_bits : _T_3079 ? _Queue64_UInt8_13_io_deq_bits : _T_3078 ? _Queue64_UInt8_12_io_deq_bits : _T_3077 ? _Queue64_UInt8_11_io_deq_bits : _T_3076 ? _Queue64_UInt8_10_io_deq_bits : _T_3075 ? _Queue64_UInt8_9_io_deq_bits : _T_3074 ? _Queue64_UInt8_8_io_deq_bits : _T_3073 ? _Queue64_UInt8_7_io_deq_bits : _T_3072 ? _Queue64_UInt8_6_io_deq_bits : _T_3071 ? _Queue64_UInt8_5_io_deq_bits : _T_3070 ? _Queue64_UInt8_4_io_deq_bits : _T_3069 ? _Queue64_UInt8_3_io_deq_bits : _T_3068 ? _Queue64_UInt8_2_io_deq_bits : _T_3067 ? _Queue64_UInt8_1_io_deq_bits : _T_3066 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_valid : _T_3096 ? _Queue64_UInt8_30_io_deq_valid : _T_3095 ? _Queue64_UInt8_29_io_deq_valid : _T_3094 ? _Queue64_UInt8_28_io_deq_valid : _T_3093 ? _Queue64_UInt8_27_io_deq_valid : _T_3092 ? _Queue64_UInt8_26_io_deq_valid : _T_3091 ? _Queue64_UInt8_25_io_deq_valid : _T_3090 ? _Queue64_UInt8_24_io_deq_valid : _T_3089 ? _Queue64_UInt8_23_io_deq_valid : _T_3088 ? _Queue64_UInt8_22_io_deq_valid : _T_3087 ? _Queue64_UInt8_21_io_deq_valid : _T_3086 ? _Queue64_UInt8_20_io_deq_valid : _T_3085 ? _Queue64_UInt8_19_io_deq_valid : _T_3084 ? _Queue64_UInt8_18_io_deq_valid : _T_3083 ? _Queue64_UInt8_17_io_deq_valid : _T_3082 ? _Queue64_UInt8_16_io_deq_valid : _T_3081 ? _Queue64_UInt8_15_io_deq_valid : _T_3080 ? _Queue64_UInt8_14_io_deq_valid : _T_3079 ? _Queue64_UInt8_13_io_deq_valid : _T_3078 ? _Queue64_UInt8_12_io_deq_valid : _T_3077 ? _Queue64_UInt8_11_io_deq_valid : _T_3076 ? _Queue64_UInt8_10_io_deq_valid : _T_3075 ? _Queue64_UInt8_9_io_deq_valid : _T_3074 ? _Queue64_UInt8_8_io_deq_valid : _T_3073 ? _Queue64_UInt8_7_io_deq_valid : _T_3072 ? _Queue64_UInt8_6_io_deq_valid : _T_3071 ? _Queue64_UInt8_5_io_deq_valid : _T_3070 ? _Queue64_UInt8_4_io_deq_valid : _T_3069 ? _Queue64_UInt8_3_io_deq_valid : _T_3068 ? _Queue64_UInt8_2_io_deq_valid : _T_3067 ? _Queue64_UInt8_1_io_deq_valid : _T_3066 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_115 = _remapindex_T_24 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_24 = _GEN_115[5:0]; // @[MemLoader.scala:177:54]
wire _T_3098 = remapindex_24 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3099 = remapindex_24 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3100 = remapindex_24 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3101 = remapindex_24 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3102 = remapindex_24 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3103 = remapindex_24 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3104 = remapindex_24 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3105 = remapindex_24 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3106 = remapindex_24 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3107 = remapindex_24 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3108 = remapindex_24 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3109 = remapindex_24 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3110 = remapindex_24 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3111 = remapindex_24 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3112 = remapindex_24 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3113 = remapindex_24 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3114 = remapindex_24 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3115 = remapindex_24 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3116 = remapindex_24 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3117 = remapindex_24 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3118 = remapindex_24 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3119 = remapindex_24 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3120 = remapindex_24 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3121 = remapindex_24 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3122 = remapindex_24 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3123 = remapindex_24 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3124 = remapindex_24 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3125 = remapindex_24 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3126 = remapindex_24 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3127 = remapindex_24 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3128 = remapindex_24 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3129 = remapindex_24 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_bits : _T_3128 ? _Queue64_UInt8_30_io_deq_bits : _T_3127 ? _Queue64_UInt8_29_io_deq_bits : _T_3126 ? _Queue64_UInt8_28_io_deq_bits : _T_3125 ? _Queue64_UInt8_27_io_deq_bits : _T_3124 ? _Queue64_UInt8_26_io_deq_bits : _T_3123 ? _Queue64_UInt8_25_io_deq_bits : _T_3122 ? _Queue64_UInt8_24_io_deq_bits : _T_3121 ? _Queue64_UInt8_23_io_deq_bits : _T_3120 ? _Queue64_UInt8_22_io_deq_bits : _T_3119 ? _Queue64_UInt8_21_io_deq_bits : _T_3118 ? _Queue64_UInt8_20_io_deq_bits : _T_3117 ? _Queue64_UInt8_19_io_deq_bits : _T_3116 ? _Queue64_UInt8_18_io_deq_bits : _T_3115 ? _Queue64_UInt8_17_io_deq_bits : _T_3114 ? _Queue64_UInt8_16_io_deq_bits : _T_3113 ? _Queue64_UInt8_15_io_deq_bits : _T_3112 ? _Queue64_UInt8_14_io_deq_bits : _T_3111 ? _Queue64_UInt8_13_io_deq_bits : _T_3110 ? _Queue64_UInt8_12_io_deq_bits : _T_3109 ? _Queue64_UInt8_11_io_deq_bits : _T_3108 ? _Queue64_UInt8_10_io_deq_bits : _T_3107 ? _Queue64_UInt8_9_io_deq_bits : _T_3106 ? _Queue64_UInt8_8_io_deq_bits : _T_3105 ? _Queue64_UInt8_7_io_deq_bits : _T_3104 ? _Queue64_UInt8_6_io_deq_bits : _T_3103 ? _Queue64_UInt8_5_io_deq_bits : _T_3102 ? _Queue64_UInt8_4_io_deq_bits : _T_3101 ? _Queue64_UInt8_3_io_deq_bits : _T_3100 ? _Queue64_UInt8_2_io_deq_bits : _T_3099 ? _Queue64_UInt8_1_io_deq_bits : _T_3098 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_valid : _T_3128 ? _Queue64_UInt8_30_io_deq_valid : _T_3127 ? _Queue64_UInt8_29_io_deq_valid : _T_3126 ? _Queue64_UInt8_28_io_deq_valid : _T_3125 ? _Queue64_UInt8_27_io_deq_valid : _T_3124 ? _Queue64_UInt8_26_io_deq_valid : _T_3123 ? _Queue64_UInt8_25_io_deq_valid : _T_3122 ? _Queue64_UInt8_24_io_deq_valid : _T_3121 ? _Queue64_UInt8_23_io_deq_valid : _T_3120 ? _Queue64_UInt8_22_io_deq_valid : _T_3119 ? _Queue64_UInt8_21_io_deq_valid : _T_3118 ? _Queue64_UInt8_20_io_deq_valid : _T_3117 ? _Queue64_UInt8_19_io_deq_valid : _T_3116 ? _Queue64_UInt8_18_io_deq_valid : _T_3115 ? _Queue64_UInt8_17_io_deq_valid : _T_3114 ? _Queue64_UInt8_16_io_deq_valid : _T_3113 ? _Queue64_UInt8_15_io_deq_valid : _T_3112 ? _Queue64_UInt8_14_io_deq_valid : _T_3111 ? _Queue64_UInt8_13_io_deq_valid : _T_3110 ? _Queue64_UInt8_12_io_deq_valid : _T_3109 ? _Queue64_UInt8_11_io_deq_valid : _T_3108 ? _Queue64_UInt8_10_io_deq_valid : _T_3107 ? _Queue64_UInt8_9_io_deq_valid : _T_3106 ? _Queue64_UInt8_8_io_deq_valid : _T_3105 ? _Queue64_UInt8_7_io_deq_valid : _T_3104 ? _Queue64_UInt8_6_io_deq_valid : _T_3103 ? _Queue64_UInt8_5_io_deq_valid : _T_3102 ? _Queue64_UInt8_4_io_deq_valid : _T_3101 ? _Queue64_UInt8_3_io_deq_valid : _T_3100 ? _Queue64_UInt8_2_io_deq_valid : _T_3099 ? _Queue64_UInt8_1_io_deq_valid : _T_3098 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_116 = _remapindex_T_25 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_25 = _GEN_116[5:0]; // @[MemLoader.scala:177:54]
wire _T_3130 = remapindex_25 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3131 = remapindex_25 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3132 = remapindex_25 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3133 = remapindex_25 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3134 = remapindex_25 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3135 = remapindex_25 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3136 = remapindex_25 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3137 = remapindex_25 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3138 = remapindex_25 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3139 = remapindex_25 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3140 = remapindex_25 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3141 = remapindex_25 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3142 = remapindex_25 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3143 = remapindex_25 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3144 = remapindex_25 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3145 = remapindex_25 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3146 = remapindex_25 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3147 = remapindex_25 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3148 = remapindex_25 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3149 = remapindex_25 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3150 = remapindex_25 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3151 = remapindex_25 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3152 = remapindex_25 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3153 = remapindex_25 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3154 = remapindex_25 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3155 = remapindex_25 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3156 = remapindex_25 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3157 = remapindex_25 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3158 = remapindex_25 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3159 = remapindex_25 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3160 = remapindex_25 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3161 = remapindex_25 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_bits : _T_3160 ? _Queue64_UInt8_30_io_deq_bits : _T_3159 ? _Queue64_UInt8_29_io_deq_bits : _T_3158 ? _Queue64_UInt8_28_io_deq_bits : _T_3157 ? _Queue64_UInt8_27_io_deq_bits : _T_3156 ? _Queue64_UInt8_26_io_deq_bits : _T_3155 ? _Queue64_UInt8_25_io_deq_bits : _T_3154 ? _Queue64_UInt8_24_io_deq_bits : _T_3153 ? _Queue64_UInt8_23_io_deq_bits : _T_3152 ? _Queue64_UInt8_22_io_deq_bits : _T_3151 ? _Queue64_UInt8_21_io_deq_bits : _T_3150 ? _Queue64_UInt8_20_io_deq_bits : _T_3149 ? _Queue64_UInt8_19_io_deq_bits : _T_3148 ? _Queue64_UInt8_18_io_deq_bits : _T_3147 ? _Queue64_UInt8_17_io_deq_bits : _T_3146 ? _Queue64_UInt8_16_io_deq_bits : _T_3145 ? _Queue64_UInt8_15_io_deq_bits : _T_3144 ? _Queue64_UInt8_14_io_deq_bits : _T_3143 ? _Queue64_UInt8_13_io_deq_bits : _T_3142 ? _Queue64_UInt8_12_io_deq_bits : _T_3141 ? _Queue64_UInt8_11_io_deq_bits : _T_3140 ? _Queue64_UInt8_10_io_deq_bits : _T_3139 ? _Queue64_UInt8_9_io_deq_bits : _T_3138 ? _Queue64_UInt8_8_io_deq_bits : _T_3137 ? _Queue64_UInt8_7_io_deq_bits : _T_3136 ? _Queue64_UInt8_6_io_deq_bits : _T_3135 ? _Queue64_UInt8_5_io_deq_bits : _T_3134 ? _Queue64_UInt8_4_io_deq_bits : _T_3133 ? _Queue64_UInt8_3_io_deq_bits : _T_3132 ? _Queue64_UInt8_2_io_deq_bits : _T_3131 ? _Queue64_UInt8_1_io_deq_bits : _T_3130 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_valid : _T_3160 ? _Queue64_UInt8_30_io_deq_valid : _T_3159 ? _Queue64_UInt8_29_io_deq_valid : _T_3158 ? _Queue64_UInt8_28_io_deq_valid : _T_3157 ? _Queue64_UInt8_27_io_deq_valid : _T_3156 ? _Queue64_UInt8_26_io_deq_valid : _T_3155 ? _Queue64_UInt8_25_io_deq_valid : _T_3154 ? _Queue64_UInt8_24_io_deq_valid : _T_3153 ? _Queue64_UInt8_23_io_deq_valid : _T_3152 ? _Queue64_UInt8_22_io_deq_valid : _T_3151 ? _Queue64_UInt8_21_io_deq_valid : _T_3150 ? _Queue64_UInt8_20_io_deq_valid : _T_3149 ? _Queue64_UInt8_19_io_deq_valid : _T_3148 ? _Queue64_UInt8_18_io_deq_valid : _T_3147 ? _Queue64_UInt8_17_io_deq_valid : _T_3146 ? _Queue64_UInt8_16_io_deq_valid : _T_3145 ? _Queue64_UInt8_15_io_deq_valid : _T_3144 ? _Queue64_UInt8_14_io_deq_valid : _T_3143 ? _Queue64_UInt8_13_io_deq_valid : _T_3142 ? _Queue64_UInt8_12_io_deq_valid : _T_3141 ? _Queue64_UInt8_11_io_deq_valid : _T_3140 ? _Queue64_UInt8_10_io_deq_valid : _T_3139 ? _Queue64_UInt8_9_io_deq_valid : _T_3138 ? _Queue64_UInt8_8_io_deq_valid : _T_3137 ? _Queue64_UInt8_7_io_deq_valid : _T_3136 ? _Queue64_UInt8_6_io_deq_valid : _T_3135 ? _Queue64_UInt8_5_io_deq_valid : _T_3134 ? _Queue64_UInt8_4_io_deq_valid : _T_3133 ? _Queue64_UInt8_3_io_deq_valid : _T_3132 ? _Queue64_UInt8_2_io_deq_valid : _T_3131 ? _Queue64_UInt8_1_io_deq_valid : _T_3130 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_117 = _remapindex_T_26 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_26 = _GEN_117[5:0]; // @[MemLoader.scala:177:54]
wire _T_3162 = remapindex_26 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3163 = remapindex_26 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3164 = remapindex_26 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3165 = remapindex_26 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3166 = remapindex_26 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3167 = remapindex_26 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3168 = remapindex_26 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3169 = remapindex_26 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3170 = remapindex_26 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3171 = remapindex_26 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3172 = remapindex_26 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3173 = remapindex_26 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3174 = remapindex_26 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3175 = remapindex_26 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3176 = remapindex_26 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3177 = remapindex_26 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3178 = remapindex_26 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3179 = remapindex_26 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3180 = remapindex_26 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3181 = remapindex_26 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3182 = remapindex_26 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3183 = remapindex_26 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3184 = remapindex_26 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3185 = remapindex_26 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3186 = remapindex_26 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3187 = remapindex_26 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3188 = remapindex_26 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3189 = remapindex_26 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3190 = remapindex_26 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3191 = remapindex_26 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3192 = remapindex_26 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3193 = remapindex_26 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_bits : _T_3192 ? _Queue64_UInt8_30_io_deq_bits : _T_3191 ? _Queue64_UInt8_29_io_deq_bits : _T_3190 ? _Queue64_UInt8_28_io_deq_bits : _T_3189 ? _Queue64_UInt8_27_io_deq_bits : _T_3188 ? _Queue64_UInt8_26_io_deq_bits : _T_3187 ? _Queue64_UInt8_25_io_deq_bits : _T_3186 ? _Queue64_UInt8_24_io_deq_bits : _T_3185 ? _Queue64_UInt8_23_io_deq_bits : _T_3184 ? _Queue64_UInt8_22_io_deq_bits : _T_3183 ? _Queue64_UInt8_21_io_deq_bits : _T_3182 ? _Queue64_UInt8_20_io_deq_bits : _T_3181 ? _Queue64_UInt8_19_io_deq_bits : _T_3180 ? _Queue64_UInt8_18_io_deq_bits : _T_3179 ? _Queue64_UInt8_17_io_deq_bits : _T_3178 ? _Queue64_UInt8_16_io_deq_bits : _T_3177 ? _Queue64_UInt8_15_io_deq_bits : _T_3176 ? _Queue64_UInt8_14_io_deq_bits : _T_3175 ? _Queue64_UInt8_13_io_deq_bits : _T_3174 ? _Queue64_UInt8_12_io_deq_bits : _T_3173 ? _Queue64_UInt8_11_io_deq_bits : _T_3172 ? _Queue64_UInt8_10_io_deq_bits : _T_3171 ? _Queue64_UInt8_9_io_deq_bits : _T_3170 ? _Queue64_UInt8_8_io_deq_bits : _T_3169 ? _Queue64_UInt8_7_io_deq_bits : _T_3168 ? _Queue64_UInt8_6_io_deq_bits : _T_3167 ? _Queue64_UInt8_5_io_deq_bits : _T_3166 ? _Queue64_UInt8_4_io_deq_bits : _T_3165 ? _Queue64_UInt8_3_io_deq_bits : _T_3164 ? _Queue64_UInt8_2_io_deq_bits : _T_3163 ? _Queue64_UInt8_1_io_deq_bits : _T_3162 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_valid : _T_3192 ? _Queue64_UInt8_30_io_deq_valid : _T_3191 ? _Queue64_UInt8_29_io_deq_valid : _T_3190 ? _Queue64_UInt8_28_io_deq_valid : _T_3189 ? _Queue64_UInt8_27_io_deq_valid : _T_3188 ? _Queue64_UInt8_26_io_deq_valid : _T_3187 ? _Queue64_UInt8_25_io_deq_valid : _T_3186 ? _Queue64_UInt8_24_io_deq_valid : _T_3185 ? _Queue64_UInt8_23_io_deq_valid : _T_3184 ? _Queue64_UInt8_22_io_deq_valid : _T_3183 ? _Queue64_UInt8_21_io_deq_valid : _T_3182 ? _Queue64_UInt8_20_io_deq_valid : _T_3181 ? _Queue64_UInt8_19_io_deq_valid : _T_3180 ? _Queue64_UInt8_18_io_deq_valid : _T_3179 ? _Queue64_UInt8_17_io_deq_valid : _T_3178 ? _Queue64_UInt8_16_io_deq_valid : _T_3177 ? _Queue64_UInt8_15_io_deq_valid : _T_3176 ? _Queue64_UInt8_14_io_deq_valid : _T_3175 ? _Queue64_UInt8_13_io_deq_valid : _T_3174 ? _Queue64_UInt8_12_io_deq_valid : _T_3173 ? _Queue64_UInt8_11_io_deq_valid : _T_3172 ? _Queue64_UInt8_10_io_deq_valid : _T_3171 ? _Queue64_UInt8_9_io_deq_valid : _T_3170 ? _Queue64_UInt8_8_io_deq_valid : _T_3169 ? _Queue64_UInt8_7_io_deq_valid : _T_3168 ? _Queue64_UInt8_6_io_deq_valid : _T_3167 ? _Queue64_UInt8_5_io_deq_valid : _T_3166 ? _Queue64_UInt8_4_io_deq_valid : _T_3165 ? _Queue64_UInt8_3_io_deq_valid : _T_3164 ? _Queue64_UInt8_2_io_deq_valid : _T_3163 ? _Queue64_UInt8_1_io_deq_valid : _T_3162 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_118 = _remapindex_T_27 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_27 = _GEN_118[5:0]; // @[MemLoader.scala:177:54]
wire _T_3194 = remapindex_27 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3195 = remapindex_27 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3196 = remapindex_27 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3197 = remapindex_27 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3198 = remapindex_27 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3199 = remapindex_27 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3200 = remapindex_27 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3201 = remapindex_27 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3202 = remapindex_27 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3203 = remapindex_27 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3204 = remapindex_27 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3205 = remapindex_27 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3206 = remapindex_27 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3207 = remapindex_27 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3208 = remapindex_27 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3209 = remapindex_27 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3210 = remapindex_27 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3211 = remapindex_27 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3212 = remapindex_27 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3213 = remapindex_27 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3214 = remapindex_27 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3215 = remapindex_27 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3216 = remapindex_27 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3217 = remapindex_27 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3218 = remapindex_27 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3219 = remapindex_27 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3220 = remapindex_27 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3221 = remapindex_27 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3222 = remapindex_27 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3223 = remapindex_27 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3224 = remapindex_27 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3225 = remapindex_27 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_bits : _T_3224 ? _Queue64_UInt8_30_io_deq_bits : _T_3223 ? _Queue64_UInt8_29_io_deq_bits : _T_3222 ? _Queue64_UInt8_28_io_deq_bits : _T_3221 ? _Queue64_UInt8_27_io_deq_bits : _T_3220 ? _Queue64_UInt8_26_io_deq_bits : _T_3219 ? _Queue64_UInt8_25_io_deq_bits : _T_3218 ? _Queue64_UInt8_24_io_deq_bits : _T_3217 ? _Queue64_UInt8_23_io_deq_bits : _T_3216 ? _Queue64_UInt8_22_io_deq_bits : _T_3215 ? _Queue64_UInt8_21_io_deq_bits : _T_3214 ? _Queue64_UInt8_20_io_deq_bits : _T_3213 ? _Queue64_UInt8_19_io_deq_bits : _T_3212 ? _Queue64_UInt8_18_io_deq_bits : _T_3211 ? _Queue64_UInt8_17_io_deq_bits : _T_3210 ? _Queue64_UInt8_16_io_deq_bits : _T_3209 ? _Queue64_UInt8_15_io_deq_bits : _T_3208 ? _Queue64_UInt8_14_io_deq_bits : _T_3207 ? _Queue64_UInt8_13_io_deq_bits : _T_3206 ? _Queue64_UInt8_12_io_deq_bits : _T_3205 ? _Queue64_UInt8_11_io_deq_bits : _T_3204 ? _Queue64_UInt8_10_io_deq_bits : _T_3203 ? _Queue64_UInt8_9_io_deq_bits : _T_3202 ? _Queue64_UInt8_8_io_deq_bits : _T_3201 ? _Queue64_UInt8_7_io_deq_bits : _T_3200 ? _Queue64_UInt8_6_io_deq_bits : _T_3199 ? _Queue64_UInt8_5_io_deq_bits : _T_3198 ? _Queue64_UInt8_4_io_deq_bits : _T_3197 ? _Queue64_UInt8_3_io_deq_bits : _T_3196 ? _Queue64_UInt8_2_io_deq_bits : _T_3195 ? _Queue64_UInt8_1_io_deq_bits : _T_3194 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_valid : _T_3224 ? _Queue64_UInt8_30_io_deq_valid : _T_3223 ? _Queue64_UInt8_29_io_deq_valid : _T_3222 ? _Queue64_UInt8_28_io_deq_valid : _T_3221 ? _Queue64_UInt8_27_io_deq_valid : _T_3220 ? _Queue64_UInt8_26_io_deq_valid : _T_3219 ? _Queue64_UInt8_25_io_deq_valid : _T_3218 ? _Queue64_UInt8_24_io_deq_valid : _T_3217 ? _Queue64_UInt8_23_io_deq_valid : _T_3216 ? _Queue64_UInt8_22_io_deq_valid : _T_3215 ? _Queue64_UInt8_21_io_deq_valid : _T_3214 ? _Queue64_UInt8_20_io_deq_valid : _T_3213 ? _Queue64_UInt8_19_io_deq_valid : _T_3212 ? _Queue64_UInt8_18_io_deq_valid : _T_3211 ? _Queue64_UInt8_17_io_deq_valid : _T_3210 ? _Queue64_UInt8_16_io_deq_valid : _T_3209 ? _Queue64_UInt8_15_io_deq_valid : _T_3208 ? _Queue64_UInt8_14_io_deq_valid : _T_3207 ? _Queue64_UInt8_13_io_deq_valid : _T_3206 ? _Queue64_UInt8_12_io_deq_valid : _T_3205 ? _Queue64_UInt8_11_io_deq_valid : _T_3204 ? _Queue64_UInt8_10_io_deq_valid : _T_3203 ? _Queue64_UInt8_9_io_deq_valid : _T_3202 ? _Queue64_UInt8_8_io_deq_valid : _T_3201 ? _Queue64_UInt8_7_io_deq_valid : _T_3200 ? _Queue64_UInt8_6_io_deq_valid : _T_3199 ? _Queue64_UInt8_5_io_deq_valid : _T_3198 ? _Queue64_UInt8_4_io_deq_valid : _T_3197 ? _Queue64_UInt8_3_io_deq_valid : _T_3196 ? _Queue64_UInt8_2_io_deq_valid : _T_3195 ? _Queue64_UInt8_1_io_deq_valid : _T_3194 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_119 = _remapindex_T_28 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_28 = _GEN_119[5:0]; // @[MemLoader.scala:177:54]
wire _T_3226 = remapindex_28 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3227 = remapindex_28 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3228 = remapindex_28 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3229 = remapindex_28 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3230 = remapindex_28 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3231 = remapindex_28 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3232 = remapindex_28 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3233 = remapindex_28 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3234 = remapindex_28 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3235 = remapindex_28 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3236 = remapindex_28 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3237 = remapindex_28 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3238 = remapindex_28 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3239 = remapindex_28 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3240 = remapindex_28 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3241 = remapindex_28 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3242 = remapindex_28 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3243 = remapindex_28 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3244 = remapindex_28 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3245 = remapindex_28 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3246 = remapindex_28 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3247 = remapindex_28 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3248 = remapindex_28 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3249 = remapindex_28 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3250 = remapindex_28 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3251 = remapindex_28 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3252 = remapindex_28 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3253 = remapindex_28 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3254 = remapindex_28 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3255 = remapindex_28 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3256 = remapindex_28 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3257 = remapindex_28 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_bits : _T_3256 ? _Queue64_UInt8_30_io_deq_bits : _T_3255 ? _Queue64_UInt8_29_io_deq_bits : _T_3254 ? _Queue64_UInt8_28_io_deq_bits : _T_3253 ? _Queue64_UInt8_27_io_deq_bits : _T_3252 ? _Queue64_UInt8_26_io_deq_bits : _T_3251 ? _Queue64_UInt8_25_io_deq_bits : _T_3250 ? _Queue64_UInt8_24_io_deq_bits : _T_3249 ? _Queue64_UInt8_23_io_deq_bits : _T_3248 ? _Queue64_UInt8_22_io_deq_bits : _T_3247 ? _Queue64_UInt8_21_io_deq_bits : _T_3246 ? _Queue64_UInt8_20_io_deq_bits : _T_3245 ? _Queue64_UInt8_19_io_deq_bits : _T_3244 ? _Queue64_UInt8_18_io_deq_bits : _T_3243 ? _Queue64_UInt8_17_io_deq_bits : _T_3242 ? _Queue64_UInt8_16_io_deq_bits : _T_3241 ? _Queue64_UInt8_15_io_deq_bits : _T_3240 ? _Queue64_UInt8_14_io_deq_bits : _T_3239 ? _Queue64_UInt8_13_io_deq_bits : _T_3238 ? _Queue64_UInt8_12_io_deq_bits : _T_3237 ? _Queue64_UInt8_11_io_deq_bits : _T_3236 ? _Queue64_UInt8_10_io_deq_bits : _T_3235 ? _Queue64_UInt8_9_io_deq_bits : _T_3234 ? _Queue64_UInt8_8_io_deq_bits : _T_3233 ? _Queue64_UInt8_7_io_deq_bits : _T_3232 ? _Queue64_UInt8_6_io_deq_bits : _T_3231 ? _Queue64_UInt8_5_io_deq_bits : _T_3230 ? _Queue64_UInt8_4_io_deq_bits : _T_3229 ? _Queue64_UInt8_3_io_deq_bits : _T_3228 ? _Queue64_UInt8_2_io_deq_bits : _T_3227 ? _Queue64_UInt8_1_io_deq_bits : _T_3226 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_valid : _T_3256 ? _Queue64_UInt8_30_io_deq_valid : _T_3255 ? _Queue64_UInt8_29_io_deq_valid : _T_3254 ? _Queue64_UInt8_28_io_deq_valid : _T_3253 ? _Queue64_UInt8_27_io_deq_valid : _T_3252 ? _Queue64_UInt8_26_io_deq_valid : _T_3251 ? _Queue64_UInt8_25_io_deq_valid : _T_3250 ? _Queue64_UInt8_24_io_deq_valid : _T_3249 ? _Queue64_UInt8_23_io_deq_valid : _T_3248 ? _Queue64_UInt8_22_io_deq_valid : _T_3247 ? _Queue64_UInt8_21_io_deq_valid : _T_3246 ? _Queue64_UInt8_20_io_deq_valid : _T_3245 ? _Queue64_UInt8_19_io_deq_valid : _T_3244 ? _Queue64_UInt8_18_io_deq_valid : _T_3243 ? _Queue64_UInt8_17_io_deq_valid : _T_3242 ? _Queue64_UInt8_16_io_deq_valid : _T_3241 ? _Queue64_UInt8_15_io_deq_valid : _T_3240 ? _Queue64_UInt8_14_io_deq_valid : _T_3239 ? _Queue64_UInt8_13_io_deq_valid : _T_3238 ? _Queue64_UInt8_12_io_deq_valid : _T_3237 ? _Queue64_UInt8_11_io_deq_valid : _T_3236 ? _Queue64_UInt8_10_io_deq_valid : _T_3235 ? _Queue64_UInt8_9_io_deq_valid : _T_3234 ? _Queue64_UInt8_8_io_deq_valid : _T_3233 ? _Queue64_UInt8_7_io_deq_valid : _T_3232 ? _Queue64_UInt8_6_io_deq_valid : _T_3231 ? _Queue64_UInt8_5_io_deq_valid : _T_3230 ? _Queue64_UInt8_4_io_deq_valid : _T_3229 ? _Queue64_UInt8_3_io_deq_valid : _T_3228 ? _Queue64_UInt8_2_io_deq_valid : _T_3227 ? _Queue64_UInt8_1_io_deq_valid : _T_3226 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_120 = _remapindex_T_29 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_29 = _GEN_120[5:0]; // @[MemLoader.scala:177:54]
wire _T_3258 = remapindex_29 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3259 = remapindex_29 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3260 = remapindex_29 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3261 = remapindex_29 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3262 = remapindex_29 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3263 = remapindex_29 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3264 = remapindex_29 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3265 = remapindex_29 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3266 = remapindex_29 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3267 = remapindex_29 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3268 = remapindex_29 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3269 = remapindex_29 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3270 = remapindex_29 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3271 = remapindex_29 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3272 = remapindex_29 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3273 = remapindex_29 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3274 = remapindex_29 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3275 = remapindex_29 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3276 = remapindex_29 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3277 = remapindex_29 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3278 = remapindex_29 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3279 = remapindex_29 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3280 = remapindex_29 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3281 = remapindex_29 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3282 = remapindex_29 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3283 = remapindex_29 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3284 = remapindex_29 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3285 = remapindex_29 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3286 = remapindex_29 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3287 = remapindex_29 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3288 = remapindex_29 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3289 = remapindex_29 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_bits : _T_3288 ? _Queue64_UInt8_30_io_deq_bits : _T_3287 ? _Queue64_UInt8_29_io_deq_bits : _T_3286 ? _Queue64_UInt8_28_io_deq_bits : _T_3285 ? _Queue64_UInt8_27_io_deq_bits : _T_3284 ? _Queue64_UInt8_26_io_deq_bits : _T_3283 ? _Queue64_UInt8_25_io_deq_bits : _T_3282 ? _Queue64_UInt8_24_io_deq_bits : _T_3281 ? _Queue64_UInt8_23_io_deq_bits : _T_3280 ? _Queue64_UInt8_22_io_deq_bits : _T_3279 ? _Queue64_UInt8_21_io_deq_bits : _T_3278 ? _Queue64_UInt8_20_io_deq_bits : _T_3277 ? _Queue64_UInt8_19_io_deq_bits : _T_3276 ? _Queue64_UInt8_18_io_deq_bits : _T_3275 ? _Queue64_UInt8_17_io_deq_bits : _T_3274 ? _Queue64_UInt8_16_io_deq_bits : _T_3273 ? _Queue64_UInt8_15_io_deq_bits : _T_3272 ? _Queue64_UInt8_14_io_deq_bits : _T_3271 ? _Queue64_UInt8_13_io_deq_bits : _T_3270 ? _Queue64_UInt8_12_io_deq_bits : _T_3269 ? _Queue64_UInt8_11_io_deq_bits : _T_3268 ? _Queue64_UInt8_10_io_deq_bits : _T_3267 ? _Queue64_UInt8_9_io_deq_bits : _T_3266 ? _Queue64_UInt8_8_io_deq_bits : _T_3265 ? _Queue64_UInt8_7_io_deq_bits : _T_3264 ? _Queue64_UInt8_6_io_deq_bits : _T_3263 ? _Queue64_UInt8_5_io_deq_bits : _T_3262 ? _Queue64_UInt8_4_io_deq_bits : _T_3261 ? _Queue64_UInt8_3_io_deq_bits : _T_3260 ? _Queue64_UInt8_2_io_deq_bits : _T_3259 ? _Queue64_UInt8_1_io_deq_bits : _T_3258 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_valid : _T_3288 ? _Queue64_UInt8_30_io_deq_valid : _T_3287 ? _Queue64_UInt8_29_io_deq_valid : _T_3286 ? _Queue64_UInt8_28_io_deq_valid : _T_3285 ? _Queue64_UInt8_27_io_deq_valid : _T_3284 ? _Queue64_UInt8_26_io_deq_valid : _T_3283 ? _Queue64_UInt8_25_io_deq_valid : _T_3282 ? _Queue64_UInt8_24_io_deq_valid : _T_3281 ? _Queue64_UInt8_23_io_deq_valid : _T_3280 ? _Queue64_UInt8_22_io_deq_valid : _T_3279 ? _Queue64_UInt8_21_io_deq_valid : _T_3278 ? _Queue64_UInt8_20_io_deq_valid : _T_3277 ? _Queue64_UInt8_19_io_deq_valid : _T_3276 ? _Queue64_UInt8_18_io_deq_valid : _T_3275 ? _Queue64_UInt8_17_io_deq_valid : _T_3274 ? _Queue64_UInt8_16_io_deq_valid : _T_3273 ? _Queue64_UInt8_15_io_deq_valid : _T_3272 ? _Queue64_UInt8_14_io_deq_valid : _T_3271 ? _Queue64_UInt8_13_io_deq_valid : _T_3270 ? _Queue64_UInt8_12_io_deq_valid : _T_3269 ? _Queue64_UInt8_11_io_deq_valid : _T_3268 ? _Queue64_UInt8_10_io_deq_valid : _T_3267 ? _Queue64_UInt8_9_io_deq_valid : _T_3266 ? _Queue64_UInt8_8_io_deq_valid : _T_3265 ? _Queue64_UInt8_7_io_deq_valid : _T_3264 ? _Queue64_UInt8_6_io_deq_valid : _T_3263 ? _Queue64_UInt8_5_io_deq_valid : _T_3262 ? _Queue64_UInt8_4_io_deq_valid : _T_3261 ? _Queue64_UInt8_3_io_deq_valid : _T_3260 ? _Queue64_UInt8_2_io_deq_valid : _T_3259 ? _Queue64_UInt8_1_io_deq_valid : _T_3258 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_121 = _remapindex_T_30 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_30 = _GEN_121[5:0]; // @[MemLoader.scala:177:54]
wire _T_3290 = remapindex_30 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3291 = remapindex_30 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3292 = remapindex_30 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3293 = remapindex_30 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3294 = remapindex_30 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3295 = remapindex_30 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3296 = remapindex_30 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3297 = remapindex_30 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3298 = remapindex_30 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3299 = remapindex_30 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3300 = remapindex_30 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3301 = remapindex_30 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3302 = remapindex_30 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3303 = remapindex_30 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3304 = remapindex_30 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3305 = remapindex_30 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3306 = remapindex_30 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3307 = remapindex_30 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3308 = remapindex_30 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3309 = remapindex_30 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3310 = remapindex_30 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3311 = remapindex_30 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3312 = remapindex_30 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3313 = remapindex_30 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3314 = remapindex_30 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3315 = remapindex_30 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3316 = remapindex_30 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3317 = remapindex_30 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3318 = remapindex_30 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3319 = remapindex_30 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3320 = remapindex_30 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3321 = remapindex_30 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_bits : _T_3320 ? _Queue64_UInt8_30_io_deq_bits : _T_3319 ? _Queue64_UInt8_29_io_deq_bits : _T_3318 ? _Queue64_UInt8_28_io_deq_bits : _T_3317 ? _Queue64_UInt8_27_io_deq_bits : _T_3316 ? _Queue64_UInt8_26_io_deq_bits : _T_3315 ? _Queue64_UInt8_25_io_deq_bits : _T_3314 ? _Queue64_UInt8_24_io_deq_bits : _T_3313 ? _Queue64_UInt8_23_io_deq_bits : _T_3312 ? _Queue64_UInt8_22_io_deq_bits : _T_3311 ? _Queue64_UInt8_21_io_deq_bits : _T_3310 ? _Queue64_UInt8_20_io_deq_bits : _T_3309 ? _Queue64_UInt8_19_io_deq_bits : _T_3308 ? _Queue64_UInt8_18_io_deq_bits : _T_3307 ? _Queue64_UInt8_17_io_deq_bits : _T_3306 ? _Queue64_UInt8_16_io_deq_bits : _T_3305 ? _Queue64_UInt8_15_io_deq_bits : _T_3304 ? _Queue64_UInt8_14_io_deq_bits : _T_3303 ? _Queue64_UInt8_13_io_deq_bits : _T_3302 ? _Queue64_UInt8_12_io_deq_bits : _T_3301 ? _Queue64_UInt8_11_io_deq_bits : _T_3300 ? _Queue64_UInt8_10_io_deq_bits : _T_3299 ? _Queue64_UInt8_9_io_deq_bits : _T_3298 ? _Queue64_UInt8_8_io_deq_bits : _T_3297 ? _Queue64_UInt8_7_io_deq_bits : _T_3296 ? _Queue64_UInt8_6_io_deq_bits : _T_3295 ? _Queue64_UInt8_5_io_deq_bits : _T_3294 ? _Queue64_UInt8_4_io_deq_bits : _T_3293 ? _Queue64_UInt8_3_io_deq_bits : _T_3292 ? _Queue64_UInt8_2_io_deq_bits : _T_3291 ? _Queue64_UInt8_1_io_deq_bits : _T_3290 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_valid : _T_3320 ? _Queue64_UInt8_30_io_deq_valid : _T_3319 ? _Queue64_UInt8_29_io_deq_valid : _T_3318 ? _Queue64_UInt8_28_io_deq_valid : _T_3317 ? _Queue64_UInt8_27_io_deq_valid : _T_3316 ? _Queue64_UInt8_26_io_deq_valid : _T_3315 ? _Queue64_UInt8_25_io_deq_valid : _T_3314 ? _Queue64_UInt8_24_io_deq_valid : _T_3313 ? _Queue64_UInt8_23_io_deq_valid : _T_3312 ? _Queue64_UInt8_22_io_deq_valid : _T_3311 ? _Queue64_UInt8_21_io_deq_valid : _T_3310 ? _Queue64_UInt8_20_io_deq_valid : _T_3309 ? _Queue64_UInt8_19_io_deq_valid : _T_3308 ? _Queue64_UInt8_18_io_deq_valid : _T_3307 ? _Queue64_UInt8_17_io_deq_valid : _T_3306 ? _Queue64_UInt8_16_io_deq_valid : _T_3305 ? _Queue64_UInt8_15_io_deq_valid : _T_3304 ? _Queue64_UInt8_14_io_deq_valid : _T_3303 ? _Queue64_UInt8_13_io_deq_valid : _T_3302 ? _Queue64_UInt8_12_io_deq_valid : _T_3301 ? _Queue64_UInt8_11_io_deq_valid : _T_3300 ? _Queue64_UInt8_10_io_deq_valid : _T_3299 ? _Queue64_UInt8_9_io_deq_valid : _T_3298 ? _Queue64_UInt8_8_io_deq_valid : _T_3297 ? _Queue64_UInt8_7_io_deq_valid : _T_3296 ? _Queue64_UInt8_6_io_deq_valid : _T_3295 ? _Queue64_UInt8_5_io_deq_valid : _T_3294 ? _Queue64_UInt8_4_io_deq_valid : _T_3293 ? _Queue64_UInt8_3_io_deq_valid : _T_3292 ? _Queue64_UInt8_2_io_deq_valid : _T_3291 ? _Queue64_UInt8_1_io_deq_valid : _T_3290 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[MemLoader.scala:177:33]
wire [6:0] _GEN_122 = _remapindex_T_31 % 7'h20; // @[MemLoader.scala:177:{33,54}]
wire [5:0] remapindex_31 = _GEN_122[5:0]; // @[MemLoader.scala:177:54]
wire _T_3322 = remapindex_31 == 6'h0; // @[MemLoader.scala:177:54, :179:17]
wire _T_3323 = remapindex_31 == 6'h1; // @[MemLoader.scala:177:54, :179:17]
wire _T_3324 = remapindex_31 == 6'h2; // @[MemLoader.scala:177:54, :179:17]
wire _T_3325 = remapindex_31 == 6'h3; // @[MemLoader.scala:177:54, :179:17]
wire _T_3326 = remapindex_31 == 6'h4; // @[MemLoader.scala:177:54, :179:17]
wire _T_3327 = remapindex_31 == 6'h5; // @[MemLoader.scala:177:54, :179:17]
wire _T_3328 = remapindex_31 == 6'h6; // @[MemLoader.scala:177:54, :179:17]
wire _T_3329 = remapindex_31 == 6'h7; // @[MemLoader.scala:177:54, :179:17]
wire _T_3330 = remapindex_31 == 6'h8; // @[MemLoader.scala:177:54, :179:17]
wire _T_3331 = remapindex_31 == 6'h9; // @[MemLoader.scala:177:54, :179:17]
wire _T_3332 = remapindex_31 == 6'hA; // @[MemLoader.scala:177:54, :179:17]
wire _T_3333 = remapindex_31 == 6'hB; // @[MemLoader.scala:177:54, :179:17]
wire _T_3334 = remapindex_31 == 6'hC; // @[MemLoader.scala:177:54, :179:17]
wire _T_3335 = remapindex_31 == 6'hD; // @[MemLoader.scala:177:54, :179:17]
wire _T_3336 = remapindex_31 == 6'hE; // @[MemLoader.scala:177:54, :179:17]
wire _T_3337 = remapindex_31 == 6'hF; // @[MemLoader.scala:177:54, :179:17]
wire _T_3338 = remapindex_31 == 6'h10; // @[MemLoader.scala:177:54, :179:17]
wire _T_3339 = remapindex_31 == 6'h11; // @[MemLoader.scala:177:54, :179:17]
wire _T_3340 = remapindex_31 == 6'h12; // @[MemLoader.scala:177:54, :179:17]
wire _T_3341 = remapindex_31 == 6'h13; // @[MemLoader.scala:177:54, :179:17]
wire _T_3342 = remapindex_31 == 6'h14; // @[MemLoader.scala:177:54, :179:17]
wire _T_3343 = remapindex_31 == 6'h15; // @[MemLoader.scala:177:54, :179:17]
wire _T_3344 = remapindex_31 == 6'h16; // @[MemLoader.scala:177:54, :179:17]
wire _T_3345 = remapindex_31 == 6'h17; // @[MemLoader.scala:177:54, :179:17]
wire _T_3346 = remapindex_31 == 6'h18; // @[MemLoader.scala:177:54, :179:17]
wire _T_3347 = remapindex_31 == 6'h19; // @[MemLoader.scala:177:54, :179:17]
wire _T_3348 = remapindex_31 == 6'h1A; // @[MemLoader.scala:177:54, :179:17]
wire _T_3349 = remapindex_31 == 6'h1B; // @[MemLoader.scala:177:54, :179:17]
wire _T_3350 = remapindex_31 == 6'h1C; // @[MemLoader.scala:177:54, :179:17]
wire _T_3351 = remapindex_31 == 6'h1D; // @[MemLoader.scala:177:54, :179:17]
wire _T_3352 = remapindex_31 == 6'h1E; // @[MemLoader.scala:177:54, :179:17]
wire _T_3353 = remapindex_31 == 6'h1F; // @[MemLoader.scala:177:54, :179:17]
assign remapVecData_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_bits : _T_3352 ? _Queue64_UInt8_30_io_deq_bits : _T_3351 ? _Queue64_UInt8_29_io_deq_bits : _T_3350 ? _Queue64_UInt8_28_io_deq_bits : _T_3349 ? _Queue64_UInt8_27_io_deq_bits : _T_3348 ? _Queue64_UInt8_26_io_deq_bits : _T_3347 ? _Queue64_UInt8_25_io_deq_bits : _T_3346 ? _Queue64_UInt8_24_io_deq_bits : _T_3345 ? _Queue64_UInt8_23_io_deq_bits : _T_3344 ? _Queue64_UInt8_22_io_deq_bits : _T_3343 ? _Queue64_UInt8_21_io_deq_bits : _T_3342 ? _Queue64_UInt8_20_io_deq_bits : _T_3341 ? _Queue64_UInt8_19_io_deq_bits : _T_3340 ? _Queue64_UInt8_18_io_deq_bits : _T_3339 ? _Queue64_UInt8_17_io_deq_bits : _T_3338 ? _Queue64_UInt8_16_io_deq_bits : _T_3337 ? _Queue64_UInt8_15_io_deq_bits : _T_3336 ? _Queue64_UInt8_14_io_deq_bits : _T_3335 ? _Queue64_UInt8_13_io_deq_bits : _T_3334 ? _Queue64_UInt8_12_io_deq_bits : _T_3333 ? _Queue64_UInt8_11_io_deq_bits : _T_3332 ? _Queue64_UInt8_10_io_deq_bits : _T_3331 ? _Queue64_UInt8_9_io_deq_bits : _T_3330 ? _Queue64_UInt8_8_io_deq_bits : _T_3329 ? _Queue64_UInt8_7_io_deq_bits : _T_3328 ? _Queue64_UInt8_6_io_deq_bits : _T_3327 ? _Queue64_UInt8_5_io_deq_bits : _T_3326 ? _Queue64_UInt8_4_io_deq_bits : _T_3325 ? _Queue64_UInt8_3_io_deq_bits : _T_3324 ? _Queue64_UInt8_2_io_deq_bits : _T_3323 ? _Queue64_UInt8_1_io_deq_bits : _T_3322 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31]
assign remapVecValids_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_valid : _T_3352 ? _Queue64_UInt8_30_io_deq_valid : _T_3351 ? _Queue64_UInt8_29_io_deq_valid : _T_3350 ? _Queue64_UInt8_28_io_deq_valid : _T_3349 ? _Queue64_UInt8_27_io_deq_valid : _T_3348 ? _Queue64_UInt8_26_io_deq_valid : _T_3347 ? _Queue64_UInt8_25_io_deq_valid : _T_3346 ? _Queue64_UInt8_24_io_deq_valid : _T_3345 ? _Queue64_UInt8_23_io_deq_valid : _T_3344 ? _Queue64_UInt8_22_io_deq_valid : _T_3343 ? _Queue64_UInt8_21_io_deq_valid : _T_3342 ? _Queue64_UInt8_20_io_deq_valid : _T_3341 ? _Queue64_UInt8_19_io_deq_valid : _T_3340 ? _Queue64_UInt8_18_io_deq_valid : _T_3339 ? _Queue64_UInt8_17_io_deq_valid : _T_3338 ? _Queue64_UInt8_16_io_deq_valid : _T_3337 ? _Queue64_UInt8_15_io_deq_valid : _T_3336 ? _Queue64_UInt8_14_io_deq_valid : _T_3335 ? _Queue64_UInt8_13_io_deq_valid : _T_3334 ? _Queue64_UInt8_12_io_deq_valid : _T_3333 ? _Queue64_UInt8_11_io_deq_valid : _T_3332 ? _Queue64_UInt8_10_io_deq_valid : _T_3331 ? _Queue64_UInt8_9_io_deq_valid : _T_3330 ? _Queue64_UInt8_8_io_deq_valid : _T_3329 ? _Queue64_UInt8_7_io_deq_valid : _T_3328 ? _Queue64_UInt8_6_io_deq_valid : _T_3327 ? _Queue64_UInt8_5_io_deq_valid : _T_3326 ? _Queue64_UInt8_4_io_deq_valid : _T_3325 ? _Queue64_UInt8_3_io_deq_valid : _T_3324 ? _Queue64_UInt8_2_io_deq_valid : _T_3323 ? _Queue64_UInt8_1_io_deq_valid : _T_3322 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[MemLoader.scala:186:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[MemLoader.scala:166:26, :186:33]
wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[MemLoader.scala:166:26, :186:33]
wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[MemLoader.scala:186:33]
wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[MemLoader.scala:186:33]
assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[MemLoader.scala:186:33]
assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[MemLoader.scala:15:7, :186:33]
wire [64:0] _GEN_123 = {1'h0, len_already_consumed}; // @[MemLoader.scala:164:37, :189:40]
wire [64:0] _GEN_124 = _GEN_123 + {59'h0, io_consumer_user_consumed_bytes_0}; // @[MemLoader.scala:15:7, :189:40]
wire [64:0] _buf_last_T; // @[MemLoader.scala:189:40]
assign _buf_last_T = _GEN_124; // @[MemLoader.scala:189:40]
wire [64:0] _len_already_consumed_T; // @[MemLoader.scala:230:52]
assign _len_already_consumed_T = _GEN_124; // @[MemLoader.scala:189:40, :230:52]
wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[MemLoader.scala:189:40]
wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30, :189:{40,75}]
wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[MemLoader.scala:167:28, :190:60]
wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[MemLoader.scala:167:28, :190:60]
wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[MemLoader.scala:167:28, :190:60]
wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[MemLoader.scala:167:28, :190:60]
wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[MemLoader.scala:167:28, :190:60]
wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[MemLoader.scala:167:28, :190:60]
wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[MemLoader.scala:167:28, :190:60]
wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[MemLoader.scala:167:28, :190:60]
wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[MemLoader.scala:167:28, :190:60]
wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[MemLoader.scala:167:28, :190:60]
wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[MemLoader.scala:167:28, :190:60]
wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[MemLoader.scala:167:28, :190:60]
wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[MemLoader.scala:167:28, :190:60]
wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[MemLoader.scala:167:28, :190:60]
wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[MemLoader.scala:167:28, :190:60]
wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[MemLoader.scala:167:28, :190:60]
wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[MemLoader.scala:167:28, :190:60]
wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[MemLoader.scala:167:28, :190:60]
wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[MemLoader.scala:167:28, :190:60]
wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[MemLoader.scala:167:28, :190:60]
wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[MemLoader.scala:167:28, :190:60]
wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[MemLoader.scala:167:28, :190:60]
wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[MemLoader.scala:167:28, :190:60]
wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[MemLoader.scala:167:28, :190:60]
wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[MemLoader.scala:167:28, :190:60]
wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[MemLoader.scala:167:28, :190:60]
wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[MemLoader.scala:167:28, :190:60]
wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[MemLoader.scala:167:28, :190:60]
wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[MemLoader.scala:167:28, :190:60]
wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[MemLoader.scala:167:28, :190:60]
wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[MemLoader.scala:167:28, :190:60]
wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_123; // @[MemLoader.scala:26:30, :189:40, :191:70]
wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[MemLoader.scala:191:70]
wire _enough_data_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49]
wire _enough_data_T_1 = count_valids == 32'h20; // @[MemLoader.scala:190:60, :194:38]
wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[MemLoader.scala:190:60, :191:70, :195:38]
wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[MemLoader.scala:193:{24,49}, :194:38, :195:38]
wire _io_consumer_available_output_bytes_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49, :197:69]
wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[MemLoader.scala:191:70, :197:{44,69}]
assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[MemLoader.scala:15:7, :197:{38,44}]
assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[MemLoader.scala:191:70, :201:61]
assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[MemLoader.scala:15:7, :201:61]
wire _T_3362 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_1 = _T_3362; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_1 = _T_3362; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 5, 0)
node _source_ok_T = shr(io.in.a.bits.source, 6)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<6>(0h39))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits = bits(_uncommonBits_T, 5, 0)
node _T_4 = shr(io.in.a.bits.source, 6)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<6>(0h39))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 5, 0)
node _T_24 = shr(io.in.a.bits.source, 6)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<6>(0h39))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 5, 0)
node _T_86 = shr(io.in.a.bits.source, 6)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<6>(0h39))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 5, 0)
node _T_152 = shr(io.in.a.bits.source, 6)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<6>(0h39))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_199 = shr(io.in.a.bits.source, 6)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<6>(0h39))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_240 = shr(io.in.a.bits.source, 6)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<6>(0h39))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 5, 0)
node _T_283 = shr(io.in.a.bits.source, 6)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<6>(0h39))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 5, 0)
node _T_321 = shr(io.in.a.bits.source, 6)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<6>(0h39))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 5, 0)
node _T_359 = shr(io.in.a.bits.source, 6)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<6>(0h39))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 5, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 6)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<6>(0h39))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<58>
connect a_set, UInt<58>(0h0)
wire a_set_wo_ready : UInt<58>
connect a_set_wo_ready, UInt<58>(0h0)
wire a_opcodes_set : UInt<232>
connect a_opcodes_set, UInt<232>(0h0)
wire a_sizes_set : UInt<232>
connect a_sizes_set, UInt<232>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<58>
connect d_clr, UInt<58>(0h0)
wire d_clr_wo_ready : UInt<58>
connect d_clr_wo_ready, UInt<58>(0h0)
wire d_opcodes_clr : UInt<232>
connect d_opcodes_clr, UInt<232>(0h0)
wire d_sizes_clr : UInt<232>
connect d_sizes_clr, UInt<232>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_110
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<58>
connect c_set, UInt<58>(0h0)
wire c_set_wo_ready : UInt<58>
connect c_set_wo_ready, UInt<58>(0h0)
wire c_opcodes_set : UInt<232>
connect c_opcodes_set, UInt<232>(0h0)
wire c_sizes_set : UInt<232>
connect c_sizes_set, UInt<232>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<58>
connect d_clr_1, UInt<58>(0h0)
wire d_clr_wo_ready_1 : UInt<58>
connect d_clr_wo_ready_1, UInt<58>(0h0)
wire d_opcodes_clr_1 : UInt<232>
connect d_opcodes_clr_1, UInt<232>(0h0)
wire d_sizes_clr_1 : UInt<232>
connect d_sizes_clr_1, UInt<232>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_111
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [57:0] inflight; // @[Monitor.scala:614:27]
reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [231:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [57:0] inflight_1; // @[Monitor.scala:726:35]
reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_175 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_175( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModule :
output auto : { dmInner_dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dmOuter_int_out : { sync : UInt<1>[1]}}
output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, ctrl : { flip debugUnavail : UInt<1>[1], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, flip dmi : { dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, dmiClock : Clock, dmiReset : Reset}, flip hartIsInReset : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst dmOuter of TLDebugModuleOuterAsync
inst dmInner of TLDebugModuleInnerAsync
connect dmInner.auto.dmiXing_in, dmOuter.auto.asource_out
connect auto.dmOuter_int_out, dmOuter.auto.int_out
connect dmInner.auto.dmInner_tl_in, auto.dmInner_dmInner_tl_in
connect dmInner.auto.dmInner_custom_in, auto.dmInner_dmInner_custom_in
connect dmInner.auto.dmInner_sb2tlOpt_out.d, auto.dmInner_dmInner_sb2tlOpt_out.d
connect auto.dmInner_dmInner_sb2tlOpt_out.a.bits, dmInner.auto.dmInner_sb2tlOpt_out.a.bits
connect auto.dmInner_dmInner_sb2tlOpt_out.a.valid, dmInner.auto.dmInner_sb2tlOpt_out.a.valid
connect dmInner.auto.dmInner_sb2tlOpt_out.a.ready, auto.dmInner_dmInner_sb2tlOpt_out.a.ready
connect childClock, io.tl_clock
connect childReset, io.tl_reset
connect dmOuter.io.dmi, io.dmi.dmi
connect dmOuter.io.dmi_reset, io.dmi.dmiReset
connect dmOuter.io.dmi_clock, io.dmi.dmiClock
connect dmOuter.rf_reset, io.dmi.dmiReset
connect dmInner.rf_reset, io.debug_reset
connect dmInner.io.debug_clock, io.debug_clock
connect dmInner.io.debug_reset, io.debug_reset
connect dmInner.io.tl_clock, io.tl_clock
connect dmInner.io.tl_reset, io.tl_reset
connect dmInner.io.innerCtrl, dmOuter.io.innerCtrl
connect dmInner.io.dmactive, dmOuter.io.ctrl.dmactive
connect dmInner.io.debugUnavail[0], io.ctrl.debugUnavail[0]
connect dmOuter.io.hgDebugInt[0], dmInner.io.hgDebugInt[0]
connect dmOuter.io.ctrl.dmactiveAck, io.ctrl.dmactiveAck
connect io.ctrl.dmactive, dmOuter.io.ctrl.dmactive
connect io.ctrl.ndreset, dmOuter.io.ctrl.ndreset
connect dmOuter.io.ctrl.debugUnavail[0], io.ctrl.debugUnavail[0]
connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] | module TLDebugModule( // @[Debug.scala:1959:9]
input auto_dmInner_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_dmInner_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_dmInner_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dmInner_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmInner_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_dmInner_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_dmInner_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmOuter_int_out_sync_0, // @[LazyModuleImp.scala:107:25]
input io_debug_clock, // @[Debug.scala:1968:16]
input io_debug_reset, // @[Debug.scala:1968:16]
input io_tl_clock, // @[Debug.scala:1968:16]
input io_tl_reset, // @[Debug.scala:1968:16]
output io_ctrl_ndreset, // @[Debug.scala:1968:16]
output io_ctrl_dmactive, // @[Debug.scala:1968:16]
input io_ctrl_dmactiveAck, // @[Debug.scala:1968:16]
output io_dmi_dmi_req_ready, // @[Debug.scala:1968:16]
input io_dmi_dmi_req_valid, // @[Debug.scala:1968:16]
input [6:0] io_dmi_dmi_req_bits_addr, // @[Debug.scala:1968:16]
input [31:0] io_dmi_dmi_req_bits_data, // @[Debug.scala:1968:16]
input [1:0] io_dmi_dmi_req_bits_op, // @[Debug.scala:1968:16]
input io_dmi_dmi_resp_ready, // @[Debug.scala:1968:16]
output io_dmi_dmi_resp_valid, // @[Debug.scala:1968:16]
output [31:0] io_dmi_dmi_resp_bits_data, // @[Debug.scala:1968:16]
output [1:0] io_dmi_dmi_resp_bits_resp, // @[Debug.scala:1968:16]
input io_dmi_dmiClock, // @[Debug.scala:1968:16]
input io_dmi_dmiReset, // @[Debug.scala:1968:16]
input io_hartIsInReset_0 // @[Debug.scala:1968:16]
);
wire _dmInner_auto_dmiXing_in_a_ridx; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_a_safe_sink_reset_n; // @[Debug.scala:1950:53]
wire [2:0] _dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[Debug.scala:1950:53]
wire [1:0] _dmInner_auto_dmiXing_in_d_mem_0_size; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_mem_0_source; // @[Debug.scala:1950:53]
wire [31:0] _dmInner_auto_dmiXing_in_d_mem_0_data; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_widx; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[Debug.scala:1950:53]
wire _dmInner_auto_dmiXing_in_d_safe_source_reset_n; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_ridx; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala:1950:53]
wire _dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala:1950:53]
wire _dmInner_io_hgDebugInt_0; // @[Debug.scala:1950:53]
wire [2:0] _dmOuter_auto_asource_out_a_mem_0_opcode; // @[Debug.scala:1949:53]
wire [8:0] _dmOuter_auto_asource_out_a_mem_0_address; // @[Debug.scala:1949:53]
wire [31:0] _dmOuter_auto_asource_out_a_mem_0_data; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_widx; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_safe_widx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_a_safe_source_reset_n; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_ridx; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_safe_ridx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[Debug.scala:1949:53]
wire _dmOuter_io_ctrl_dmactive; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1949:53]
wire [9:0] _dmOuter_io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_widx; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala:1949:53]
wire _dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1949:53]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1959:9]
wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1959:9]
wire [6:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_valid_0 = auto_dmInner_dmInner_tl_in_a_valid; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_a_bits_param_0 = auto_dmInner_dmInner_tl_in_a_bits_param; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_tl_in_a_bits_size_0 = auto_dmInner_dmInner_tl_in_a_bits_size; // @[Debug.scala:1959:9]
wire [10:0] auto_dmInner_dmInner_tl_in_a_bits_source_0 = auto_dmInner_dmInner_tl_in_a_bits_source; // @[Debug.scala:1959:9]
wire [11:0] auto_dmInner_dmInner_tl_in_a_bits_address_0 = auto_dmInner_dmInner_tl_in_a_bits_address; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1959:9]
wire [63:0] auto_dmInner_dmInner_tl_in_a_bits_data_0 = auto_dmInner_dmInner_tl_in_a_bits_data; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_ready_0 = auto_dmInner_dmInner_tl_in_d_ready; // @[Debug.scala:1959:9]
wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1959:9]
wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1959:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1959:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1959:9]
wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:1959:9]
wire io_dmi_dmi_req_valid_0 = io_dmi_dmi_req_valid; // @[Debug.scala:1959:9]
wire [6:0] io_dmi_dmi_req_bits_addr_0 = io_dmi_dmi_req_bits_addr; // @[Debug.scala:1959:9]
wire [31:0] io_dmi_dmi_req_bits_data_0 = io_dmi_dmi_req_bits_data; // @[Debug.scala:1959:9]
wire [1:0] io_dmi_dmi_req_bits_op_0 = io_dmi_dmi_req_bits_op; // @[Debug.scala:1959:9]
wire io_dmi_dmi_resp_ready_0 = io_dmi_dmi_resp_ready; // @[Debug.scala:1959:9]
wire io_dmi_dmiClock_0 = io_dmi_dmiClock; // @[Debug.scala:1959:9]
wire io_dmi_dmiReset_0 = io_dmi_dmiReset; // @[Debug.scala:1959:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1959:9]
wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:1959:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1949:53, :1950:53, :1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:1950:53, :1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1949:53, :1950:53, :1959:9]
wire childClock = io_tl_clock_0; // @[Debug.scala:1959:9]
wire childReset = io_tl_reset_0; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1959:9]
wire [3:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1959:9]
wire [31:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1959:9]
wire [7:0] auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_a_ready_0; // @[Debug.scala:1959:9]
wire [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1959:9]
wire [1:0] auto_dmInner_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1959:9]
wire [10:0] auto_dmInner_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1959:9]
wire [63:0] auto_dmInner_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1959:9]
wire auto_dmInner_dmInner_tl_in_d_valid_0; // @[Debug.scala:1959:9]
wire auto_dmOuter_int_out_sync_0_0; // @[Debug.scala:1959:9]
wire io_ctrl_ndreset_0; // @[Debug.scala:1959:9]
wire io_ctrl_dmactive_0; // @[Debug.scala:1959:9]
wire io_dmi_dmi_req_ready_0; // @[Debug.scala:1959:9]
wire [31:0] io_dmi_dmi_resp_bits_data_0; // @[Debug.scala:1959:9]
wire [1:0] io_dmi_dmi_resp_bits_resp_0; // @[Debug.scala:1959:9]
wire io_dmi_dmi_resp_valid_0; // @[Debug.scala:1959:9]
TLDebugModuleOuterAsync dmOuter ( // @[Debug.scala:1949:53]
.auto_asource_out_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode),
.auto_asource_out_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address),
.auto_asource_out_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data),
.auto_asource_out_a_ridx (_dmInner_auto_dmiXing_in_a_ridx), // @[Debug.scala:1950:53]
.auto_asource_out_a_widx (_dmOuter_auto_asource_out_a_widx),
.auto_asource_out_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid), // @[Debug.scala:1950:53]
.auto_asource_out_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid),
.auto_asource_out_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n),
.auto_asource_out_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source), // @[Debug.scala:1950:53]
.auto_asource_out_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data), // @[Debug.scala:1950:53]
.auto_asource_out_d_ridx (_dmOuter_auto_asource_out_d_ridx),
.auto_asource_out_d_widx (_dmInner_auto_dmiXing_in_d_widx), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid),
.auto_asource_out_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n), // @[Debug.scala:1950:53]
.auto_asource_out_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n),
.auto_int_out_sync_0 (auto_dmOuter_int_out_sync_0_0),
.io_dmi_clock (io_dmi_dmiClock_0), // @[Debug.scala:1959:9]
.io_dmi_reset (io_dmi_dmiReset_0), // @[Debug.scala:1959:9]
.io_dmi_req_ready (io_dmi_dmi_req_ready_0),
.io_dmi_req_valid (io_dmi_dmi_req_valid_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_addr (io_dmi_dmi_req_bits_addr_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_data (io_dmi_dmi_req_bits_data_0), // @[Debug.scala:1959:9]
.io_dmi_req_bits_op (io_dmi_dmi_req_bits_op_0), // @[Debug.scala:1959:9]
.io_dmi_resp_ready (io_dmi_dmi_resp_ready_0), // @[Debug.scala:1959:9]
.io_dmi_resp_valid (io_dmi_dmi_resp_valid_0),
.io_dmi_resp_bits_data (io_dmi_dmi_resp_bits_data_0),
.io_dmi_resp_bits_resp (io_dmi_dmi_resp_bits_resp_0),
.io_ctrl_ndreset (io_ctrl_ndreset_0),
.io_ctrl_dmactive (_dmOuter_io_ctrl_dmactive),
.io_ctrl_dmactiveAck (io_ctrl_dmactiveAck_0), // @[Debug.scala:1959:9]
.io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq),
.io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel),
.io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset),
.io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0),
.io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx), // @[Debug.scala:1950:53]
.io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx),
.io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid), // @[Debug.scala:1950:53]
.io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid),
.io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n),
.io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n), // @[Debug.scala:1950:53]
.io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0), // @[Debug.scala:1950:53]
.rf_reset (io_dmi_dmiReset_0) // @[Debug.scala:1959:9]
); // @[Debug.scala:1949:53]
assign io_ctrl_dmactive_0 = _dmOuter_io_ctrl_dmactive; // @[Debug.scala:1949:53, :1959:9]
TLDebugModuleInnerAsync dmInner ( // @[Debug.scala:1950:53]
.auto_dmiXing_in_a_mem_0_opcode (_dmOuter_auto_asource_out_a_mem_0_opcode), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_mem_0_address (_dmOuter_auto_asource_out_a_mem_0_address), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_mem_0_data (_dmOuter_auto_asource_out_a_mem_0_data), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_ridx (_dmInner_auto_dmiXing_in_a_ridx),
.auto_dmiXing_in_a_widx (_dmOuter_auto_asource_out_a_widx), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_ridx_valid (_dmInner_auto_dmiXing_in_a_safe_ridx_valid),
.auto_dmiXing_in_a_safe_widx_valid (_dmOuter_auto_asource_out_a_safe_widx_valid), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_source_reset_n (_dmOuter_auto_asource_out_a_safe_source_reset_n), // @[Debug.scala:1949:53]
.auto_dmiXing_in_a_safe_sink_reset_n (_dmInner_auto_dmiXing_in_a_safe_sink_reset_n),
.auto_dmiXing_in_d_mem_0_opcode (_dmInner_auto_dmiXing_in_d_mem_0_opcode),
.auto_dmiXing_in_d_mem_0_size (_dmInner_auto_dmiXing_in_d_mem_0_size),
.auto_dmiXing_in_d_mem_0_source (_dmInner_auto_dmiXing_in_d_mem_0_source),
.auto_dmiXing_in_d_mem_0_data (_dmInner_auto_dmiXing_in_d_mem_0_data),
.auto_dmiXing_in_d_ridx (_dmOuter_auto_asource_out_d_ridx), // @[Debug.scala:1949:53]
.auto_dmiXing_in_d_widx (_dmInner_auto_dmiXing_in_d_widx),
.auto_dmiXing_in_d_safe_ridx_valid (_dmOuter_auto_asource_out_d_safe_ridx_valid), // @[Debug.scala:1949:53]
.auto_dmiXing_in_d_safe_widx_valid (_dmInner_auto_dmiXing_in_d_safe_widx_valid),
.auto_dmiXing_in_d_safe_source_reset_n (_dmInner_auto_dmiXing_in_d_safe_source_reset_n),
.auto_dmiXing_in_d_safe_sink_reset_n (_dmOuter_auto_asource_out_d_safe_sink_reset_n), // @[Debug.scala:1949:53]
.auto_dmInner_sb2tlOpt_out_a_ready (auto_dmInner_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_a_valid (auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0),
.auto_dmInner_sb2tlOpt_out_a_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0),
.auto_dmInner_sb2tlOpt_out_a_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0),
.auto_dmInner_sb2tlOpt_out_a_bits_address (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0),
.auto_dmInner_sb2tlOpt_out_a_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0),
.auto_dmInner_sb2tlOpt_out_d_ready (auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0),
.auto_dmInner_sb2tlOpt_out_d_valid (auto_dmInner_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_opcode (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_param (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_size (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_sink (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_denied (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_data (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1959:9]
.auto_dmInner_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_ready (auto_dmInner_dmInner_tl_in_a_ready_0),
.auto_dmInner_tl_in_a_valid (auto_dmInner_dmInner_tl_in_a_valid_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_opcode (auto_dmInner_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_param (auto_dmInner_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_size (auto_dmInner_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_source (auto_dmInner_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_address (auto_dmInner_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_mask (auto_dmInner_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_data (auto_dmInner_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_a_bits_corrupt (auto_dmInner_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_d_ready (auto_dmInner_dmInner_tl_in_d_ready_0), // @[Debug.scala:1959:9]
.auto_dmInner_tl_in_d_valid (auto_dmInner_dmInner_tl_in_d_valid_0),
.auto_dmInner_tl_in_d_bits_opcode (auto_dmInner_dmInner_tl_in_d_bits_opcode_0),
.auto_dmInner_tl_in_d_bits_size (auto_dmInner_dmInner_tl_in_d_bits_size_0),
.auto_dmInner_tl_in_d_bits_source (auto_dmInner_dmInner_tl_in_d_bits_source_0),
.auto_dmInner_tl_in_d_bits_data (auto_dmInner_dmInner_tl_in_d_bits_data_0),
.io_debug_clock (io_debug_clock_0), // @[Debug.scala:1959:9]
.io_debug_reset (io_debug_reset_0), // @[Debug.scala:1959:9]
.io_tl_clock (io_tl_clock_0), // @[Debug.scala:1959:9]
.io_tl_reset (io_tl_reset_0), // @[Debug.scala:1959:9]
.io_dmactive (_dmOuter_io_ctrl_dmactive), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_resumereq (_dmOuter_io_innerCtrl_mem_0_resumereq), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_hartsel (_dmOuter_io_innerCtrl_mem_0_hartsel), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_ackhavereset (_dmOuter_io_innerCtrl_mem_0_ackhavereset), // @[Debug.scala:1949:53]
.io_innerCtrl_mem_0_hrmask_0 (_dmOuter_io_innerCtrl_mem_0_hrmask_0), // @[Debug.scala:1949:53]
.io_innerCtrl_ridx (_dmInner_io_innerCtrl_ridx),
.io_innerCtrl_widx (_dmOuter_io_innerCtrl_widx), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_ridx_valid (_dmInner_io_innerCtrl_safe_ridx_valid),
.io_innerCtrl_safe_widx_valid (_dmOuter_io_innerCtrl_safe_widx_valid), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_source_reset_n (_dmOuter_io_innerCtrl_safe_source_reset_n), // @[Debug.scala:1949:53]
.io_innerCtrl_safe_sink_reset_n (_dmInner_io_innerCtrl_safe_sink_reset_n),
.io_hgDebugInt_0 (_dmInner_io_hgDebugInt_0),
.io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1959:9]
.rf_reset (io_debug_reset_0) // @[Debug.scala:1959:9]
); // @[Debug.scala:1950:53]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_a_ready = auto_dmInner_dmInner_tl_in_a_ready_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_valid = auto_dmInner_dmInner_tl_in_d_valid_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_opcode = auto_dmInner_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_size = auto_dmInner_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_source = auto_dmInner_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1959:9]
assign auto_dmInner_dmInner_tl_in_d_bits_data = auto_dmInner_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1959:9]
assign auto_dmOuter_int_out_sync_0 = auto_dmOuter_int_out_sync_0_0; // @[Debug.scala:1959:9]
assign io_ctrl_ndreset = io_ctrl_ndreset_0; // @[Debug.scala:1959:9]
assign io_ctrl_dmactive = io_ctrl_dmactive_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_req_ready = io_dmi_dmi_req_ready_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_valid = io_dmi_dmi_resp_valid_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_bits_data = io_dmi_dmi_resp_bits_data_0; // @[Debug.scala:1959:9]
assign io_dmi_dmi_resp_bits_resp = io_dmi_dmi_resp_bits_resp_0; // @[Debug.scala:1959:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_17 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_34
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_17
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _T_4 = or(_T, _T_1)
node _T_5 = or(_T_4, _T_2)
node _T_6 = or(_T_5, _T_3)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(io.in.valid, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h5)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<2>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h5))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8]
connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_13 = and(io.in.ready, io.in.valid)
node _T_14 = and(_T_13, io.in.bits.head)
node _T_15 = and(_T_14, at_dest)
when _T_15 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_16 = eq(UInt<4>(0hd), io.in.bits.egress_id)
when _T_16 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_17 = eq(UInt<4>(0he), io.in.bits.egress_id)
when _T_17 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_18 = eq(UInt<4>(0hf), io.in.bits.egress_id)
when _T_18 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_20 = and(route_q.io.enq.valid, _T_19)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_21, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_35
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_17
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_26 = and(vcalloc_q.io.enq.valid, _T_25)
node _T_27 = eq(_T_26, UInt<1>(0h0))
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2])
node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2)
node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0)
node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3)
node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3)
node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1)
node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7)
node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8)
node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12)
node _out_bundle_bits_out_virt_channel_T_16 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_13)
node _out_bundle_bits_out_virt_channel_T_17 = or(_out_bundle_bits_out_virt_channel_T_16, _out_bundle_bits_out_virt_channel_T_14)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_17
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_17( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {2'h0, {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w118_1 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<118>, q : UInt<118>, flip en : UInt<1>}
reg cdc_reg : UInt<118>, clock
when io.en :
connect cdc_reg, io.d
connect io.q, cdc_reg | module ClockCrossingReg_w118_1( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input reset, // @[SynchronizerReg.scala:191:7]
input [117:0] io_d, // @[SynchronizerReg.scala:195:14]
output [117:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
wire [117:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7]
wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7]
wire [117:0] io_q_0; // @[SynchronizerReg.scala:191:7]
reg [117:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en_0) // @[SynchronizerReg.scala:191:7]
cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge)
assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3 :
input clock : Clock
input reset : Reset
output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}}
node _post_psd_reset_T = asUInt(reset)
node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T)
inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_36
connect io_sync_reset_chain.clock, clock
connect io_sync_reset_chain.reset, post_psd_reset
connect io_sync_reset_chain.io.d, UInt<1>(0h1)
wire _io_sync_reset_WIRE : UInt<1>
connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q
node _io_sync_reset_T = not(_io_sync_reset_WIRE)
node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T)
connect io.sync_reset, _io_sync_reset_T_1 | module ResetCatchAndSync_d3( // @[ResetCatchAndSync.scala:13:7]
input clock, // @[ResetCatchAndSync.scala:13:7]
input reset // @[ResetCatchAndSync.scala:13:7]
);
wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76]
wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25]
wire io_sync_reset; // @[ResetCatchAndSync.scala:13:7]
wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}]
wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7]
assign io_sync_reset = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25]
AsyncResetSynchronizerShiftReg_w1_d3_i0_36 io_sync_reset_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27]
.io_q (_io_sync_reset_WIRE)
); // @[ShiftReg.scala:45:23]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCFromNoC_1 :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, ingress_id : UInt}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<49>, clock
node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0))
node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T)
node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready)
connect io.flit.ready, _io_flit_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_echo_WIRE : { }
wire _protocol_bits_echo_WIRE_1 : UInt<0>
connect _protocol_bits_echo_WIRE_1, const
connect protocol.bits.echo, _protocol_bits_echo_WIRE
node _T = shr(const, 0)
wire _protocol_bits_user_WIRE : { }
wire _protocol_bits_user_WIRE_1 : UInt<0>
connect _protocol_bits_user_WIRE_1, _T
connect protocol.bits.user, _protocol_bits_user_WIRE
node _T_1 = shr(_T, 0)
wire _protocol_bits_address_WIRE : UInt<32>
connect _protocol_bits_address_WIRE, _T_1
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T_2 = shr(_T_1, 32)
wire _protocol_bits_source_WIRE : UInt<7>
connect _protocol_bits_source_WIRE, _T_2
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_3 = shr(_T_2, 7)
wire _protocol_bits_size_WIRE : UInt<4>
connect _protocol_bits_size_WIRE, _T_3
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_4 = shr(_T_3, 4)
wire _protocol_bits_param_WIRE : UInt<3>
connect _protocol_bits_param_WIRE, _T_4
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_5 = shr(_T_4, 3)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_5
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_6 = shr(_T_5, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_7 = shr(io.flit.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<128>
connect _protocol_bits_data_WIRE, _T_7
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_8 = shr(_T_7, 128)
node _T_9 = and(io.flit.ready, io.flit.valid)
node _T_10 = and(_T_9, io.flit.bits.head)
when _T_10 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.flit.bits.payload
node _T_11 = and(io.flit.ready, io.flit.valid)
node _T_12 = and(_T_11, io.flit.bits.tail)
when _T_12 :
connect is_const, UInt<1>(0h1)
connect io.protocol, protocol | module TLCFromNoC_1( // @[TilelinkAdapters.scala:167:7]
input clock, // @[TilelinkAdapters.scala:167:7]
input reset, // @[TilelinkAdapters.scala:167:7]
input io_protocol_ready, // @[TilelinkAdapters.scala:56:14]
output io_protocol_valid, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14]
output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14]
output [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14]
output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14]
output [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14]
input [128:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
reg [48:0] const_reg; // @[TilelinkAdapters.scala:69:22]
wire [48:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[48:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:167:7]
if (reset) // @[TilelinkAdapters.scala:167:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :167:7]
else // @[TilelinkAdapters.scala:167:7]
is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35]
if (_GEN_0) // @[TilelinkAdapters.scala:84:22]
const_reg <= io_flit_bits_payload[48:0]; // @[TilelinkAdapters.scala:56:14, :69:22]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_70 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_70( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module PhitToFlit_p32_f32_9 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}
reg data : UInt<32>[0], clock
regreset beat : UInt<0>, clock, reset, UInt<0>(0h0)
node _io_in_ready_T = neq(beat, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<1>(0h0))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
connect io.out.bits.flit, io.in.bits.phit
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<1>(0h0))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3 | module PhitToFlit_p32_f32_9( // @[Serdes.scala:103:7]
input clock, // @[Serdes.scala:103:7]
input reset, // @[Serdes.scala:103:7]
output io_in_ready, // @[Serdes.scala:105:14]
input io_in_valid, // @[Serdes.scala:105:14]
input [31:0] io_in_bits_phit, // @[Serdes.scala:105:14]
input io_out_ready, // @[Serdes.scala:105:14]
output io_out_valid, // @[Serdes.scala:105:14]
output [31:0] io_out_bits_flit // @[Serdes.scala:105:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:103:7]
wire [31:0] io_in_bits_phit_0 = io_in_bits_phit; // @[Serdes.scala:103:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:103:7]
wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:120:53]
wire _io_out_valid_T = 1'h1; // @[Serdes.scala:116:39]
wire _beat_T = 1'h1; // @[Serdes.scala:120:22]
wire _beat_T_2 = 1'h1; // @[Serdes.scala:120:53]
wire _io_in_ready_T = 1'h0; // @[Serdes.scala:115:39]
wire _io_in_ready_T_1; // @[Serdes.scala:115:31]
wire _beat_T_3 = 1'h0; // @[Serdes.scala:120:16]
wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:103:7, :116:31]
wire [31:0] io_out_bits_flit_0 = io_in_bits_phit_0; // @[Serdes.scala:103:7]
assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:103:7, :115:31]
wire io_in_ready_0; // @[Serdes.scala:103:7]
wire io_out_valid_0; // @[Serdes.scala:103:7]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:103:7, :115:31]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:103:7, :116:31]
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:103:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:103:7]
assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:103:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_15 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_15
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h8), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0hc), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h0), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_32 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0he), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_33 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h2), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_34 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h6), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_35 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h10), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_29)
node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_30)
node _q_io_enq_bits_ingress_id_T_39 = or(_q_io_enq_bits_ingress_id_T_38, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_40 = or(_q_io_enq_bits_ingress_id_T_39, _q_io_enq_bits_ingress_id_T_32)
node _q_io_enq_bits_ingress_id_T_41 = or(_q_io_enq_bits_ingress_id_T_40, _q_io_enq_bits_ingress_id_T_33)
node _q_io_enq_bits_ingress_id_T_42 = or(_q_io_enq_bits_ingress_id_T_41, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_43 = or(_q_io_enq_bits_ingress_id_T_42, _q_io_enq_bits_ingress_id_T_35)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_43
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_15( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_25 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget8 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_4
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2)
node hasData = eq(_hasData_opdata_T, UInt<1>(0h0))
node _limit_T = dshl(UInt<4>(0hf), anonIn.a.bits.size)
node _limit_T_1 = bits(_limit_T, 3, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 3)
regreset count : UInt<1>, clock, reset, UInt<1>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg)
node _T = and(anonIn.a.ready, anonIn.a.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonIn_a_ready_T = eq(last, UInt<1>(0h0))
node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T)
connect anonIn.a.ready, _anonIn_a_ready_T_1
node _anonOut_a_valid_T = and(anonIn.a.valid, last)
connect anonOut.a.valid, _anonOut_a_valid_T
connect anonOut.a.bits, anonIn.a.bits
regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T)
node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1)
wire anonOut_a_bits_data_odata_0 : UInt
connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_1 : UInt
connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data
reg anonOut_a_bits_data_rdata : UInt<64>[1], clock
node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0])
node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonIn.a.bits.data)
node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1)
when _anonOut_a_bits_data_T_2 :
connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0
node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0)
connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3
connect anonOut.a.bits.corrupt, corrupt_out
node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<4>(0h0))
node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0)
node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount)
node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 3, 0)
node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1))
node anonOut_a_bits_mask_sub_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<3>(0h4))
node anonOut_a_bits_mask_sub_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 3, 3)
node anonOut_a_bits_mask_sub_sub_sub_bit = bits(anonOut.a.bits.address, 3, 3)
node anonOut_a_bits_mask_sub_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_sub_nbit)
node _anonOut_a_bits_mask_sub_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_sub_size, anonOut_a_bits_mask_sub_sub_sub_0_2)
node anonOut_a_bits_mask_sub_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_sub_acc_T)
node anonOut_a_bits_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_sub_bit)
node _anonOut_a_bits_mask_sub_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_sub_size, anonOut_a_bits_mask_sub_sub_sub_1_2)
node anonOut_a_bits_mask_sub_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_sub_acc_T_1)
node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2)
node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2)
node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_sub_0_2, anonOut_a_bits_mask_sub_sub_nbit)
node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2)
node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T)
node anonOut_a_bits_mask_sub_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_sub_0_2, anonOut_a_bits_mask_sub_sub_bit)
node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2)
node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1)
node anonOut_a_bits_mask_sub_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_sub_1_2, anonOut_a_bits_mask_sub_sub_nbit)
node _anonOut_a_bits_mask_sub_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_2_2)
node anonOut_a_bits_mask_sub_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_sub_1_1, _anonOut_a_bits_mask_sub_sub_acc_T_2)
node anonOut_a_bits_mask_sub_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_sub_1_2, anonOut_a_bits_mask_sub_sub_bit)
node _anonOut_a_bits_mask_sub_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_3_2)
node anonOut_a_bits_mask_sub_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_sub_1_1, _anonOut_a_bits_mask_sub_sub_acc_T_3)
node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1)
node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1)
node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2)
node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T)
node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2)
node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1)
node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2)
node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2)
node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2)
node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3)
node anonOut_a_bits_mask_sub_4_2 = and(anonOut_a_bits_mask_sub_sub_2_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T_4 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_4_2)
node anonOut_a_bits_mask_sub_4_1 = or(anonOut_a_bits_mask_sub_sub_2_1, _anonOut_a_bits_mask_sub_acc_T_4)
node anonOut_a_bits_mask_sub_5_2 = and(anonOut_a_bits_mask_sub_sub_2_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_5 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_5_2)
node anonOut_a_bits_mask_sub_5_1 = or(anonOut_a_bits_mask_sub_sub_2_1, _anonOut_a_bits_mask_sub_acc_T_5)
node anonOut_a_bits_mask_sub_6_2 = and(anonOut_a_bits_mask_sub_sub_3_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T_6 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_6_2)
node anonOut_a_bits_mask_sub_6_1 = or(anonOut_a_bits_mask_sub_sub_3_1, _anonOut_a_bits_mask_sub_acc_T_6)
node anonOut_a_bits_mask_sub_7_2 = and(anonOut_a_bits_mask_sub_sub_3_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_7 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_7_2)
node anonOut_a_bits_mask_sub_7_1 = or(anonOut_a_bits_mask_sub_sub_3_1, _anonOut_a_bits_mask_sub_acc_T_7)
node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0)
node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0)
node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq)
node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T)
node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1)
node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1)
node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2)
node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2)
node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3)
node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3)
node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4)
node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4)
node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5)
node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5)
node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6)
node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6)
node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7)
node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7)
node anonOut_a_bits_mask_eq_8 = and(anonOut_a_bits_mask_sub_4_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_8 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_8)
node anonOut_a_bits_mask_acc_8 = or(anonOut_a_bits_mask_sub_4_1, _anonOut_a_bits_mask_acc_T_8)
node anonOut_a_bits_mask_eq_9 = and(anonOut_a_bits_mask_sub_4_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_9 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_9)
node anonOut_a_bits_mask_acc_9 = or(anonOut_a_bits_mask_sub_4_1, _anonOut_a_bits_mask_acc_T_9)
node anonOut_a_bits_mask_eq_10 = and(anonOut_a_bits_mask_sub_5_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_10 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_10)
node anonOut_a_bits_mask_acc_10 = or(anonOut_a_bits_mask_sub_5_1, _anonOut_a_bits_mask_acc_T_10)
node anonOut_a_bits_mask_eq_11 = and(anonOut_a_bits_mask_sub_5_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_11 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_11)
node anonOut_a_bits_mask_acc_11 = or(anonOut_a_bits_mask_sub_5_1, _anonOut_a_bits_mask_acc_T_11)
node anonOut_a_bits_mask_eq_12 = and(anonOut_a_bits_mask_sub_6_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_12 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_12)
node anonOut_a_bits_mask_acc_12 = or(anonOut_a_bits_mask_sub_6_1, _anonOut_a_bits_mask_acc_T_12)
node anonOut_a_bits_mask_eq_13 = and(anonOut_a_bits_mask_sub_6_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_13 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_13)
node anonOut_a_bits_mask_acc_13 = or(anonOut_a_bits_mask_sub_6_1, _anonOut_a_bits_mask_acc_T_13)
node anonOut_a_bits_mask_eq_14 = and(anonOut_a_bits_mask_sub_7_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_14 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_14)
node anonOut_a_bits_mask_acc_14 = or(anonOut_a_bits_mask_sub_7_1, _anonOut_a_bits_mask_acc_T_14)
node anonOut_a_bits_mask_eq_15 = and(anonOut_a_bits_mask_sub_7_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_15 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_15)
node anonOut_a_bits_mask_acc_15 = or(anonOut_a_bits_mask_sub_7_1, _anonOut_a_bits_mask_acc_T_15)
node anonOut_a_bits_mask_lo_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc)
node anonOut_a_bits_mask_lo_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2)
node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_lo_lo_hi, anonOut_a_bits_mask_lo_lo_lo)
node anonOut_a_bits_mask_lo_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4)
node anonOut_a_bits_mask_lo_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6)
node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_lo_hi_hi, anonOut_a_bits_mask_lo_hi_lo)
node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo)
node anonOut_a_bits_mask_hi_lo_lo = cat(anonOut_a_bits_mask_acc_9, anonOut_a_bits_mask_acc_8)
node anonOut_a_bits_mask_hi_lo_hi = cat(anonOut_a_bits_mask_acc_11, anonOut_a_bits_mask_acc_10)
node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_hi_lo_hi, anonOut_a_bits_mask_hi_lo_lo)
node anonOut_a_bits_mask_hi_hi_lo = cat(anonOut_a_bits_mask_acc_13, anonOut_a_bits_mask_acc_12)
node anonOut_a_bits_mask_hi_hi_hi = cat(anonOut_a_bits_mask_acc_15, anonOut_a_bits_mask_acc_14)
node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_hi_hi_hi, anonOut_a_bits_mask_hi_hi_lo)
node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo)
node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo)
regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T)
node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1)
wire anonOut_a_bits_mask_odata_0 : UInt
connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_1 : UInt
connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask
reg anonOut_a_bits_mask_rdata : UInt<8>[1], clock
node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0])
node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask)
node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2)
when _anonOut_a_bits_mask_T_3 :
connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0
node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0)
node _anonOut_a_bits_mask_T_5 = not(UInt<16>(0h0))
node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5)
node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleD_a32d128s5k4z4u
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonOut.d
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64)
node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 63, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node repeat_hasData = bits(cated.bits.opcode, 0, 0)
node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 3)
regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonIn.d.ready, anonIn.d.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
reg repeat_sel_sel_sources : UInt<1>[17], clock
node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 3, 3)
node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid)
when _repeat_sel_sel_T :
connect repeat_sel_sel_sources[anonIn.a.bits.source], repeat_sel_sel_a_sel
node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, cated.bits.source)
node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T)
reg repeat_sel_hold_r : UInt<1>, clock
when repeat_first :
connect repeat_sel_hold_r, repeat_sel_sel_sources[cated.bits.source]
node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[cated.bits.source], repeat_sel_hold_r)
node _repeat_sel_T = not(repeat_limit)
node repeat_sel = and(repeat_sel_hold, _repeat_sel_T)
node repeat_index = or(repeat_sel, repeat_count)
connect anonIn.d.bits.corrupt, cated.bits.corrupt
connect anonIn.d.bits.data, cated.bits.data
connect anonIn.d.bits.denied, cated.bits.denied
connect anonIn.d.bits.sink, cated.bits.sink
connect anonIn.d.bits.source, cated.bits.source
connect anonIn.d.bits.size, cated.bits.size
connect anonIn.d.bits.param, cated.bits.param
connect anonIn.d.bits.opcode, cated.bits.opcode
connect anonIn.d.valid, cated.valid
connect cated.ready, anonIn.d.ready
node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 63, 0)
node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64)
wire repeat_anonIn_d_bits_data_mux : UInt<64>[2]
connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T
connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1
connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.mask, UInt<16>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_10.bits.sink, UInt<4>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget8( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [15:0] _anonOut_a_bits_mask_T_5 = 16'hFFFF; // @[WidthWidget.scala:85:119]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [15:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [127:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] anonOut_a_bits_mask_odata_0 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_mask_odata_1 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47]
wire [63:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_sink; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
wire cated_bits_denied; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [18:0] _limit_T = 19'hF << anonIn_a_bits_size; // @[package.scala:243:71]
wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}]
wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire limit = _limit_T_2[3]; // @[package.scala:243:46]
reg count; // @[WidthWidget.scala:40:27]
wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = ~count; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56]
wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonIn_a_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35]
wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35]
assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24]
wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24]
wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire [63:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire anonOut_a_bits_mask_sub_sub_sub_sub_0_1 = |(anonOut_a_bits_size[3:2]); // @[Misc.scala:206:21]
wire anonOut_a_bits_mask_sub_sub_sub_size = anonOut_a_bits_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_sub_sub_bit = anonOut_a_bits_address[3]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire anonOut_a_bits_mask_sub_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_sub_size & anonOut_a_bits_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _anonOut_a_bits_mask_sub_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_sub_size & anonOut_a_bits_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_sub_0_2 & anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_sub_0_2 & anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_sub_2_2 = anonOut_a_bits_mask_sub_sub_sub_1_2 & anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T_2 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_2_1 = anonOut_a_bits_mask_sub_sub_sub_1_1 | _anonOut_a_bits_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_sub_3_2 = anonOut_a_bits_mask_sub_sub_sub_1_2 & anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T_3 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_3_1 = anonOut_a_bits_mask_sub_sub_sub_1_1 | _anonOut_a_bits_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_4_2 = anonOut_a_bits_mask_sub_sub_2_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_4 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_4_1 = anonOut_a_bits_mask_sub_sub_2_1 | _anonOut_a_bits_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_5_2 = anonOut_a_bits_mask_sub_sub_2_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_5 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_5_1 = anonOut_a_bits_mask_sub_sub_2_1 | _anonOut_a_bits_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_6_2 = anonOut_a_bits_mask_sub_sub_3_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_6 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_6_1 = anonOut_a_bits_mask_sub_sub_3_1 | _anonOut_a_bits_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_7_2 = anonOut_a_bits_mask_sub_sub_3_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_7 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_7_1 = anonOut_a_bits_mask_sub_sub_3_1 | _anonOut_a_bits_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_8 = anonOut_a_bits_mask_sub_4_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_8 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_8 = anonOut_a_bits_mask_sub_4_1 | _anonOut_a_bits_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_9 = anonOut_a_bits_mask_sub_4_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_9 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_9 = anonOut_a_bits_mask_sub_4_1 | _anonOut_a_bits_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_10 = anonOut_a_bits_mask_sub_5_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_10 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_10 = anonOut_a_bits_mask_sub_5_1 | _anonOut_a_bits_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_11 = anonOut_a_bits_mask_sub_5_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_11 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_11 = anonOut_a_bits_mask_sub_5_1 | _anonOut_a_bits_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_12 = anonOut_a_bits_mask_sub_6_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_12 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_12 = anonOut_a_bits_mask_sub_6_1 | _anonOut_a_bits_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_13 = anonOut_a_bits_mask_sub_6_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_13 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_13 = anonOut_a_bits_mask_sub_6_1 | _anonOut_a_bits_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_14 = anonOut_a_bits_mask_sub_7_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_14 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_14 = anonOut_a_bits_mask_sub_7_1 | _anonOut_a_bits_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_15 = anonOut_a_bits_mask_sub_7_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_15 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_15 = anonOut_a_bits_mask_sub_7_1 | _anonOut_a_bits_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] anonOut_a_bits_mask_lo_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_lo_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_lo_lo_hi, anonOut_a_bits_mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] anonOut_a_bits_mask_lo_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_lo_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_lo_hi_hi, anonOut_a_bits_mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] anonOut_a_bits_mask_hi_lo_lo = {anonOut_a_bits_mask_acc_9, anonOut_a_bits_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_hi_lo_hi = {anonOut_a_bits_mask_acc_11, anonOut_a_bits_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_hi_lo_hi, anonOut_a_bits_mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] anonOut_a_bits_mask_hi_hi_lo = {anonOut_a_bits_mask_acc_13, anonOut_a_bits_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_hi_hi_hi = {anonOut_a_bits_mask_acc_15, anonOut_a_bits_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_hi_hi_hi, anonOut_a_bits_mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10]
reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [7:0] anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24]
wire [7:0] anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 ? anonOut_a_bits_mask_odata_0 : anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 ? anonOut_a_bits_mask_odata_1 : anonIn_a_bits_mask; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35]
wire [15:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [15:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 16'hFFFF; // @[WidthWidget.scala:73:12, :85:93]
assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10]
assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25]
wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonOut_d_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25]
wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71]
wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}]
wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24]
wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24]
reg repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_1; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_2; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_3; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_4; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_5; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_6; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_7; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_8; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_9; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_10; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_11; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_12; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_13; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_14; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_15; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_16; // @[WidthWidget.scala:187:27]
wire repeat_sel_sel_a_sel = anonIn_a_bits_address[3]; // @[WidthWidget.scala:188:38]
wire _repeat_sel_sel_bypass_T = anonIn_a_bits_source == cated_bits_source; // @[WidthWidget.scala:161:25, :200:53]
wire repeat_sel_sel_bypass = anonIn_a_valid & _repeat_sel_sel_bypass_T; // @[WidthWidget.scala:200:{33,53}]
reg repeat_sel_hold_r; // @[WidthWidget.scala:121:47]
wire [31:0] _GEN = {{repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_16}, {repeat_sel_sel_sources_15}, {repeat_sel_sel_sources_14}, {repeat_sel_sel_sources_13}, {repeat_sel_sel_sources_12}, {repeat_sel_sel_sources_11}, {repeat_sel_sel_sources_10}, {repeat_sel_sel_sources_9}, {repeat_sel_sel_sources_8}, {repeat_sel_sel_sources_7}, {repeat_sel_sel_sources_6}, {repeat_sel_sel_sources_5}, {repeat_sel_sel_sources_4}, {repeat_sel_sel_sources_3}, {repeat_sel_sel_sources_2}, {repeat_sel_sel_sources_1}, {repeat_sel_sel_sources_0}}; // @[WidthWidget.scala:121:47, :187:27]
wire repeat_sel_hold = repeat_first ? _GEN[cated_bits_source] : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :161:25]
wire _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18]
wire repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}]
wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24]
wire [63:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonIn_d_bits_data = repeat_index ? repeat_anonIn_d_bits_data_mux_1 : repeat_anonIn_d_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
count <= 1'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
repeat_count <= 1'h0; // @[WidthWidget.scala:105:26]
end
else begin // @[WidthWidget.scala:27:9]
if (_T) begin // @[Decoupled.scala:51:35]
count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
end
if (_anonOut_a_bits_data_T_2) // @[WidthWidget.scala:69:23]
anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
if (_anonOut_a_bits_mask_T_3) // @[WidthWidget.scala:69:23]
anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h0) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h1) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_1 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h2) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_2 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h3) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_3 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h4) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_4 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h5) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_5 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h6) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_6 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h7) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_7 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h8) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_8 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h9) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_9 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hA) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_10 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hB) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_11 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hC) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_12 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hD) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_13 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hE) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_14 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hF) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_15 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h10) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_16 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (repeat_first) // @[WidthWidget.scala:106:25]
repeat_sel_hold_r <= _GEN[cated_bits_source]; // @[WidthWidget.scala:121:47, :161:25]
always @(posedge)
TLMonitor_4 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleD_a32d128s5k4z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonOut_d_ready),
.io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (anonOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_sink (cated_bits_sink),
.io_deq_bits_denied (cated_bits_denied),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_94 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_94
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_94( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_94 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_23 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_23
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire debugNodeOut : { va_stall : UInt[2], sa_stall : UInt[2]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in
connect auto.egress_nodes_out, egressNodesOut
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_9 of InputUnit_23
connect input_unit_0_from_9.clock, clock
connect input_unit_0_from_9.reset, reset
inst ingress_unit_1_from_11 of IngressUnit_34
connect ingress_unit_1_from_11.clock, clock
connect ingress_unit_1_from_11.reset, reset
inst output_unit_0_to_11 of OutputUnit_23
connect output_unit_0_to_11.clock, clock
connect output_unit_0_to_11.reset, reset
inst egress_unit_1_to_11 of EgressUnit_30
connect egress_unit_1_to_11.clock, clock
connect egress_unit_1_to_11.reset, reset
inst switch of Switch_23
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_23
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_23
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_23
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_3 = bits(_fires_count_T_2, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_3
connect input_unit_0_from_9.io.in, destNodesIn
connect ingress_unit_1_from_11.io.in, ingressNodesIn.flit
connect output_unit_0_to_11.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_11.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_11.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_11.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_11.io.out.valid
connect egress_unit_1_to_11.io.out.ready, egressNodesOut.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_9.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_11.io.router_req
connect input_unit_0_from_9.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_11.io.router_resp, route_computer.io.resp.`1`
connect vc_allocator.io.req.`0`, input_unit_0_from_9.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_11.io.vcalloc_req
connect input_unit_0_from_9.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_11.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect output_unit_0_to_11.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_11.io.allocs, vc_allocator.io.out_allocs.`1`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_11.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_11.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_11.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_11.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_11.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_11.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_11.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_11.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_11.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_11.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_11.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_11.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_11.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_11.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_11.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_11.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_11.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_11.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_11.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_11.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_11.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_11.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_11.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_11.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_11.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_11.io.channel_status[0].occupied
connect input_unit_0_from_9.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0]
connect input_unit_0_from_9.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1]
connect input_unit_0_from_9.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2]
connect input_unit_0_from_9.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3]
connect input_unit_0_from_9.io.out_credit_available.`1`[0], egress_unit_1_to_11.io.credit_available[0]
connect ingress_unit_1_from_11.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0]
connect ingress_unit_1_from_11.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1]
connect ingress_unit_1_from_11.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2]
connect ingress_unit_1_from_11.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3]
connect ingress_unit_1_from_11.io.out_credit_available.`1`[0], egress_unit_1_to_11.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_9.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_11.io.salloc_req[0]
connect output_unit_0_to_11.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_11.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_11.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_11.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_11.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_11.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_11.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_11.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect egress_unit_1_to_11.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_11.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_9.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_11.io.out[0]
connect output_unit_0_to_11.io.in, switch.io.out.`0`
connect egress_unit_1_to_11.io.in, switch.io.out.`1`
reg REG : { `1` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect input_unit_0_from_9.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_11.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_9.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_11.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_9.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_11.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_41
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 9 10 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i11 10 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e11 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20 | module Router_23( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_1_to_11_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_11_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_11_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_11_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_11_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_1_from_11_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [36:0] _ingress_unit_1_from_11_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_11_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_11_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_11_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_11_io_in_ready; // @[Router.scala:116:13]
wire [1:0] _input_unit_0_from_9_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [36:0] _input_unit_0_from_9_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire _input_unit_0_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_9_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_11_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_in_i2_o1_a32d64s8k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_22
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_23
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<8>(0h80))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<8>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<1>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<8>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<1>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<8>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<8>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<8>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<8>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<8>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<8>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<8>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<8>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<8>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<8>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<8>(0h80))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 7)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<8>(0h80))
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<8>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<8>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<8>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<8>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<8>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<8>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<8>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<8>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
extmodule plusarg_reader_48 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_49 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_cbus_in_i2_o1_a32d64s8k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [7:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_1_a_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_22 = 3'h0; // @[Mux.scala:30:73]
wire [3:0] auto_anon_in_1_a_bits_size = 4'h2; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = 4'h2; // @[MixedNode.scala:551:17]
wire [3:0] in_1_a_bits_size = 4'h2; // @[Xbar.scala:159:18]
wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h2; // @[Xbar.scala:352:24]
wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:46:9]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsAI_opdata_T_1 = 1'h0; // @[Edges.scala:92:37]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire [7:0] auto_anon_in_1_a_bits_mask = 8'hF; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17]
wire [7:0] in_1_a_bits_mask = 8'hF; // @[Xbar.scala:159:18]
wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hF; // @[Xbar.scala:352:24]
wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire beatsAI_opdata_1 = 1'h1; // @[Edges.scala:92:28]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [8:0] beatsAI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [7:0] _addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _addressC_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _addressC_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] _requestBOI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _beatsCI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _beatsCI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] _portsCOI_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _portsCOI_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] portsCOI_filtered_1_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [7:0] in_1_a_bits_source = 8'h80; // @[Xbar.scala:159:18]
wire [7:0] _in_1_a_bits_source_T = 8'h80; // @[Xbar.scala:166:55]
wire [7:0] portsAOI_filtered_1_0_bits_source = 8'h80; // @[Xbar.scala:352:24]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_5 = 12'h3; // @[package.scala:243:46]
wire [11:0] _beatsAI_decode_T_4 = 12'hFFC; // @[package.scala:243:76]
wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC; // @[package.scala:243:71]
wire [6:0] requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [6:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [6:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [7:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [7:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [7:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [7:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [7:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[6:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [7:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [6:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[6:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[7]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire requestDOI_0_1 = out_0_d_bits_source == 8'h80; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_fbus_from_debug_sb :
input clock : Clock
input reset : Reset
output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst widget of TLWidthWidget1
connect widget.clock, clock
connect widget.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect widget.auto.anon_out.d, tlIn.d
connect tlIn.a.bits, widget.auto.anon_out.a.bits
connect tlIn.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, tlIn.a.ready
connect auto.tl_out, tlOut
connect widget.auto.anon_in, auto.widget_anon_in
extmodule plusarg_reader_32 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_33 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_fbus_from_debug_sb( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_out_d_bits_param_0 = auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_tl_out_d_bits_sink_0 = auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:230:28]
wire [2:0] auto_widget_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:230:28]
wire [2:0] auto_tl_out_a_bits_param = 3'h0; // @[WidthWidget.scala:230:28]
wire [2:0] tlOut_a_bits_param = 3'h0; // @[WidthWidget.scala:230:28]
wire [2:0] tlIn_a_bits_param = 3'h0; // @[WidthWidget.scala:230:28]
wire auto_widget_anon_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param = auto_tl_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [6:0] tlOut_d_bits_sink = auto_tl_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [6:0] tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLWidthWidget1 widget ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0),
.auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0),
.auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0),
.auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0),
.auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0),
.auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0),
.auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0),
.auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0),
.auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0),
.auto_anon_out_a_ready (tlIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlIn_a_valid),
.auto_anon_out_a_bits_opcode (tlIn_a_bits_opcode),
.auto_anon_out_a_bits_size (tlIn_a_bits_size),
.auto_anon_out_a_bits_address (tlIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlIn_a_bits_data),
.auto_anon_out_a_bits_corrupt (tlIn_a_bits_corrupt),
.auto_anon_out_d_ready (tlIn_d_ready),
.auto_anon_out_d_valid (tlIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_34 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_28 = shr(io.in.a.bits.source, 5)
node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0))
node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f))
node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_34 = shr(io.in.a.bits.source, 5)
node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1))
node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f))
node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_40 = shr(io.in.a.bits.source, 5)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_46 = shr(io.in.a.bits.source, 5)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_52 = shr(io.in.a.bits.source, 5)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_58 = shr(io.in.a.bits.source, 5)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_64 = shr(io.in.a.bits.source, 5)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_70 = shr(io.in.a.bits.source, 5)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE : UInt<1>[17]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_33
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_45
connect _source_ok_WIRE[11], _source_ok_T_51
connect _source_ok_WIRE[12], _source_ok_T_57
connect _source_ok_WIRE[13], _source_ok_T_63
connect _source_ok_WIRE[14], _source_ok_T_69
connect _source_ok_WIRE[15], _source_ok_T_75
connect _source_ok_WIRE[16], _source_ok_T_76
node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15])
node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<7>(0h40))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<7>(0h41))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<7>(0h42))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<7>(0h43))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_88 = shr(io.in.a.bits.source, 5)
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_101 = shr(io.in.a.bits.source, 5)
node _T_102 = eq(_T_101, UInt<1>(0h1))
node _T_103 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_104 = and(_T_102, _T_103)
node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_114 = shr(io.in.a.bits.source, 5)
node _T_115 = eq(_T_114, UInt<2>(0h2))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_127 = shr(io.in.a.bits.source, 5)
node _T_128 = eq(_T_127, UInt<2>(0h3))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(_T_132, UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = or(_T_133, _T_138)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_140 = shr(io.in.a.bits.source, 5)
node _T_141 = eq(_T_140, UInt<3>(0h4))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = or(_T_146, _T_151)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_153 = shr(io.in.a.bits.source, 5)
node _T_154 = eq(_T_153, UInt<3>(0h5))
node _T_155 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_156 = and(_T_154, _T_155)
node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(_T_158, UInt<1>(0h0))
node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_161 = cvt(_T_160)
node _T_162 = and(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = asSInt(_T_162)
node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = or(_T_159, _T_164)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_166 = shr(io.in.a.bits.source, 5)
node _T_167 = eq(_T_166, UInt<3>(0h6))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = or(_T_172, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_179 = shr(io.in.a.bits.source, 5)
node _T_180 = eq(_T_179, UInt<3>(0h7))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = and(_T_11, _T_24)
node _T_201 = and(_T_200, _T_37)
node _T_202 = and(_T_201, _T_50)
node _T_203 = and(_T_202, _T_63)
node _T_204 = and(_T_203, _T_71)
node _T_205 = and(_T_204, _T_79)
node _T_206 = and(_T_205, _T_87)
node _T_207 = and(_T_206, _T_100)
node _T_208 = and(_T_207, _T_113)
node _T_209 = and(_T_208, _T_126)
node _T_210 = and(_T_209, _T_139)
node _T_211 = and(_T_210, _T_152)
node _T_212 = and(_T_211, _T_165)
node _T_213 = and(_T_212, _T_178)
node _T_214 = and(_T_213, _T_191)
node _T_215 = and(_T_214, _T_199)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_215, UInt<1>(0h1), "") : assert_1
node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_219 :
node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_224 = shr(io.in.a.bits.source, 2)
node _T_225 = eq(_T_224, UInt<7>(0h40))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_229 = and(_T_227, _T_228)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_230 = shr(io.in.a.bits.source, 2)
node _T_231 = eq(_T_230, UInt<7>(0h41))
node _T_232 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_233 = and(_T_231, _T_232)
node _T_234 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_236 = shr(io.in.a.bits.source, 2)
node _T_237 = eq(_T_236, UInt<7>(0h42))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_242 = shr(io.in.a.bits.source, 2)
node _T_243 = eq(_T_242, UInt<7>(0h43))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_251 = shr(io.in.a.bits.source, 5)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_257 = shr(io.in.a.bits.source, 5)
node _T_258 = eq(_T_257, UInt<1>(0h1))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_263 = shr(io.in.a.bits.source, 5)
node _T_264 = eq(_T_263, UInt<2>(0h2))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f))
node _T_268 = and(_T_266, _T_267)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_269 = shr(io.in.a.bits.source, 5)
node _T_270 = eq(_T_269, UInt<2>(0h3))
node _T_271 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_272 = and(_T_270, _T_271)
node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f))
node _T_274 = and(_T_272, _T_273)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_275 = shr(io.in.a.bits.source, 5)
node _T_276 = eq(_T_275, UInt<3>(0h4))
node _T_277 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_278 = and(_T_276, _T_277)
node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f))
node _T_280 = and(_T_278, _T_279)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_281 = shr(io.in.a.bits.source, 5)
node _T_282 = eq(_T_281, UInt<3>(0h5))
node _T_283 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_284 = and(_T_282, _T_283)
node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f))
node _T_286 = and(_T_284, _T_285)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_287 = shr(io.in.a.bits.source, 5)
node _T_288 = eq(_T_287, UInt<3>(0h6))
node _T_289 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_290 = and(_T_288, _T_289)
node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f))
node _T_292 = and(_T_290, _T_291)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_293 = shr(io.in.a.bits.source, 5)
node _T_294 = eq(_T_293, UInt<3>(0h7))
node _T_295 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_296 = and(_T_294, _T_295)
node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_300 = or(_T_223, _T_229)
node _T_301 = or(_T_300, _T_235)
node _T_302 = or(_T_301, _T_241)
node _T_303 = or(_T_302, _T_247)
node _T_304 = or(_T_303, _T_248)
node _T_305 = or(_T_304, _T_249)
node _T_306 = or(_T_305, _T_250)
node _T_307 = or(_T_306, _T_256)
node _T_308 = or(_T_307, _T_262)
node _T_309 = or(_T_308, _T_268)
node _T_310 = or(_T_309, _T_274)
node _T_311 = or(_T_310, _T_280)
node _T_312 = or(_T_311, _T_286)
node _T_313 = or(_T_312, _T_292)
node _T_314 = or(_T_313, _T_298)
node _T_315 = or(_T_314, _T_299)
node _T_316 = and(_T_222, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = and(_T_318, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = and(_T_317, _T_325)
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_326, UInt<1>(0h1), "") : assert_2
node _T_330 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<7>(0h40))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<7>(0h41))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<7>(0h42))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<7>(0h43))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_356 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_357 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_358 = shr(io.in.a.bits.source, 5)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_361 = and(_T_359, _T_360)
node _T_362 = leq(uncommonBits_28, UInt<5>(0h1f))
node _T_363 = and(_T_361, _T_362)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_364 = shr(io.in.a.bits.source, 5)
node _T_365 = eq(_T_364, UInt<1>(0h1))
node _T_366 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_367 = and(_T_365, _T_366)
node _T_368 = leq(uncommonBits_29, UInt<5>(0h1f))
node _T_369 = and(_T_367, _T_368)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_370 = shr(io.in.a.bits.source, 5)
node _T_371 = eq(_T_370, UInt<2>(0h2))
node _T_372 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_373 = and(_T_371, _T_372)
node _T_374 = leq(uncommonBits_30, UInt<5>(0h1f))
node _T_375 = and(_T_373, _T_374)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_376 = shr(io.in.a.bits.source, 5)
node _T_377 = eq(_T_376, UInt<2>(0h3))
node _T_378 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_379 = and(_T_377, _T_378)
node _T_380 = leq(uncommonBits_31, UInt<5>(0h1f))
node _T_381 = and(_T_379, _T_380)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_382 = shr(io.in.a.bits.source, 5)
node _T_383 = eq(_T_382, UInt<3>(0h4))
node _T_384 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_385 = and(_T_383, _T_384)
node _T_386 = leq(uncommonBits_32, UInt<5>(0h1f))
node _T_387 = and(_T_385, _T_386)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_388 = shr(io.in.a.bits.source, 5)
node _T_389 = eq(_T_388, UInt<3>(0h5))
node _T_390 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_391 = and(_T_389, _T_390)
node _T_392 = leq(uncommonBits_33, UInt<5>(0h1f))
node _T_393 = and(_T_391, _T_392)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_394 = shr(io.in.a.bits.source, 5)
node _T_395 = eq(_T_394, UInt<3>(0h6))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_34, UInt<5>(0h1f))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_400 = shr(io.in.a.bits.source, 5)
node _T_401 = eq(_T_400, UInt<3>(0h7))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_35, UInt<5>(0h1f))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE : UInt<1>[17]
connect _WIRE[0], _T_330
connect _WIRE[1], _T_336
connect _WIRE[2], _T_342
connect _WIRE[3], _T_348
connect _WIRE[4], _T_354
connect _WIRE[5], _T_355
connect _WIRE[6], _T_356
connect _WIRE[7], _T_357
connect _WIRE[8], _T_363
connect _WIRE[9], _T_369
connect _WIRE[10], _T_375
connect _WIRE[11], _T_381
connect _WIRE[12], _T_387
connect _WIRE[13], _T_393
connect _WIRE[14], _T_399
connect _WIRE[15], _T_405
connect _WIRE[16], _T_406
node _T_407 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_408 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_410 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_412 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_413 = mux(_WIRE[5], _T_407, UInt<1>(0h0))
node _T_414 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_415 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_416 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = or(_T_408, _T_409)
node _T_426 = or(_T_425, _T_410)
node _T_427 = or(_T_426, _T_411)
node _T_428 = or(_T_427, _T_412)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_414)
node _T_431 = or(_T_430, _T_415)
node _T_432 = or(_T_431, _T_416)
node _T_433 = or(_T_432, _T_417)
node _T_434 = or(_T_433, _T_418)
node _T_435 = or(_T_434, _T_419)
node _T_436 = or(_T_435, _T_420)
node _T_437 = or(_T_436, _T_421)
node _T_438 = or(_T_437, _T_422)
node _T_439 = or(_T_438, _T_423)
node _T_440 = or(_T_439, _T_424)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_440
node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_443 = and(_T_441, _T_442)
node _T_444 = or(UInt<1>(0h0), _T_443)
node _T_445 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_446 = cvt(_T_445)
node _T_447 = and(_T_446, asSInt(UInt<17>(0h10000)))
node _T_448 = asSInt(_T_447)
node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0)))
node _T_450 = and(_T_444, _T_449)
node _T_451 = or(UInt<1>(0h0), _T_450)
node _T_452 = and(_WIRE_1, _T_451)
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_452, UInt<1>(0h1), "") : assert_3
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(source_ok, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_459 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_459, UInt<1>(0h1), "") : assert_5
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(is_aligned, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_466 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_466, UInt<1>(0h1), "") : assert_7
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_471, UInt<1>(0h1), "") : assert_8
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_475, UInt<1>(0h1), "") : assert_9
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<7>(0h40))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<7>(0h41))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<7>(0h42))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<7>(0h43))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_509 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_510 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_511 = shr(io.in.a.bits.source, 5)
node _T_512 = eq(_T_511, UInt<1>(0h0))
node _T_513 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_514 = and(_T_512, _T_513)
node _T_515 = leq(uncommonBits_40, UInt<5>(0h1f))
node _T_516 = and(_T_514, _T_515)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_517 = shr(io.in.a.bits.source, 5)
node _T_518 = eq(_T_517, UInt<1>(0h1))
node _T_519 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_520 = and(_T_518, _T_519)
node _T_521 = leq(uncommonBits_41, UInt<5>(0h1f))
node _T_522 = and(_T_520, _T_521)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_523 = shr(io.in.a.bits.source, 5)
node _T_524 = eq(_T_523, UInt<2>(0h2))
node _T_525 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_526 = and(_T_524, _T_525)
node _T_527 = leq(uncommonBits_42, UInt<5>(0h1f))
node _T_528 = and(_T_526, _T_527)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_529 = shr(io.in.a.bits.source, 5)
node _T_530 = eq(_T_529, UInt<2>(0h3))
node _T_531 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_532 = and(_T_530, _T_531)
node _T_533 = leq(uncommonBits_43, UInt<5>(0h1f))
node _T_534 = and(_T_532, _T_533)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0)
node _T_535 = shr(io.in.a.bits.source, 5)
node _T_536 = eq(_T_535, UInt<3>(0h4))
node _T_537 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_538 = and(_T_536, _T_537)
node _T_539 = leq(uncommonBits_44, UInt<5>(0h1f))
node _T_540 = and(_T_538, _T_539)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0)
node _T_541 = shr(io.in.a.bits.source, 5)
node _T_542 = eq(_T_541, UInt<3>(0h5))
node _T_543 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_544 = and(_T_542, _T_543)
node _T_545 = leq(uncommonBits_45, UInt<5>(0h1f))
node _T_546 = and(_T_544, _T_545)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0)
node _T_547 = shr(io.in.a.bits.source, 5)
node _T_548 = eq(_T_547, UInt<3>(0h6))
node _T_549 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_550 = and(_T_548, _T_549)
node _T_551 = leq(uncommonBits_46, UInt<5>(0h1f))
node _T_552 = and(_T_550, _T_551)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0)
node _T_553 = shr(io.in.a.bits.source, 5)
node _T_554 = eq(_T_553, UInt<3>(0h7))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_47, UInt<5>(0h1f))
node _T_558 = and(_T_556, _T_557)
node _T_559 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_560 = or(_T_483, _T_489)
node _T_561 = or(_T_560, _T_495)
node _T_562 = or(_T_561, _T_501)
node _T_563 = or(_T_562, _T_507)
node _T_564 = or(_T_563, _T_508)
node _T_565 = or(_T_564, _T_509)
node _T_566 = or(_T_565, _T_510)
node _T_567 = or(_T_566, _T_516)
node _T_568 = or(_T_567, _T_522)
node _T_569 = or(_T_568, _T_528)
node _T_570 = or(_T_569, _T_534)
node _T_571 = or(_T_570, _T_540)
node _T_572 = or(_T_571, _T_546)
node _T_573 = or(_T_572, _T_552)
node _T_574 = or(_T_573, _T_558)
node _T_575 = or(_T_574, _T_559)
node _T_576 = and(_T_482, _T_575)
node _T_577 = or(UInt<1>(0h0), _T_576)
node _T_578 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_579 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<17>(0h10000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = and(_T_578, _T_583)
node _T_585 = or(UInt<1>(0h0), _T_584)
node _T_586 = and(_T_577, _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_586, UInt<1>(0h1), "") : assert_10
node _T_590 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<7>(0h40))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<7>(0h41))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<7>(0h42))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_609 = shr(io.in.a.bits.source, 2)
node _T_610 = eq(_T_609, UInt<7>(0h43))
node _T_611 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_612 = and(_T_610, _T_611)
node _T_613 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_616 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_617 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_618 = shr(io.in.a.bits.source, 5)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_52, UInt<5>(0h1f))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_624 = shr(io.in.a.bits.source, 5)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_53, UInt<5>(0h1f))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_630 = shr(io.in.a.bits.source, 5)
node _T_631 = eq(_T_630, UInt<2>(0h2))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_54, UInt<5>(0h1f))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_636 = shr(io.in.a.bits.source, 5)
node _T_637 = eq(_T_636, UInt<2>(0h3))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_55, UInt<5>(0h1f))
node _T_641 = and(_T_639, _T_640)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0)
node _T_642 = shr(io.in.a.bits.source, 5)
node _T_643 = eq(_T_642, UInt<3>(0h4))
node _T_644 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_645 = and(_T_643, _T_644)
node _T_646 = leq(uncommonBits_56, UInt<5>(0h1f))
node _T_647 = and(_T_645, _T_646)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0)
node _T_648 = shr(io.in.a.bits.source, 5)
node _T_649 = eq(_T_648, UInt<3>(0h5))
node _T_650 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_651 = and(_T_649, _T_650)
node _T_652 = leq(uncommonBits_57, UInt<5>(0h1f))
node _T_653 = and(_T_651, _T_652)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_654 = shr(io.in.a.bits.source, 5)
node _T_655 = eq(_T_654, UInt<3>(0h6))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_58, UInt<5>(0h1f))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_660 = shr(io.in.a.bits.source, 5)
node _T_661 = eq(_T_660, UInt<3>(0h7))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_59, UInt<5>(0h1f))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE_2 : UInt<1>[17]
connect _WIRE_2[0], _T_590
connect _WIRE_2[1], _T_596
connect _WIRE_2[2], _T_602
connect _WIRE_2[3], _T_608
connect _WIRE_2[4], _T_614
connect _WIRE_2[5], _T_615
connect _WIRE_2[6], _T_616
connect _WIRE_2[7], _T_617
connect _WIRE_2[8], _T_623
connect _WIRE_2[9], _T_629
connect _WIRE_2[10], _T_635
connect _WIRE_2[11], _T_641
connect _WIRE_2[12], _T_647
connect _WIRE_2[13], _T_653
connect _WIRE_2[14], _T_659
connect _WIRE_2[15], _T_665
connect _WIRE_2[16], _T_666
node _T_667 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_668 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_669 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_670 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_671 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_672 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_673 = mux(_WIRE_2[5], _T_667, UInt<1>(0h0))
node _T_674 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_675 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_676 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_678 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_680 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_681 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_682 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_683 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_684 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_685 = or(_T_668, _T_669)
node _T_686 = or(_T_685, _T_670)
node _T_687 = or(_T_686, _T_671)
node _T_688 = or(_T_687, _T_672)
node _T_689 = or(_T_688, _T_673)
node _T_690 = or(_T_689, _T_674)
node _T_691 = or(_T_690, _T_675)
node _T_692 = or(_T_691, _T_676)
node _T_693 = or(_T_692, _T_677)
node _T_694 = or(_T_693, _T_678)
node _T_695 = or(_T_694, _T_679)
node _T_696 = or(_T_695, _T_680)
node _T_697 = or(_T_696, _T_681)
node _T_698 = or(_T_697, _T_682)
node _T_699 = or(_T_698, _T_683)
node _T_700 = or(_T_699, _T_684)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_700
node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_702 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_703 = and(_T_701, _T_702)
node _T_704 = or(UInt<1>(0h0), _T_703)
node _T_705 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<17>(0h10000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = and(_T_704, _T_709)
node _T_711 = or(UInt<1>(0h0), _T_710)
node _T_712 = and(_WIRE_3, _T_711)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_712, UInt<1>(0h1), "") : assert_11
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(source_ok, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_719 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_719, UInt<1>(0h1), "") : assert_13
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(is_aligned, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_726 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_726, UInt<1>(0h1), "") : assert_15
node _T_730 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_730, UInt<1>(0h1), "") : assert_16
node _T_734 = not(io.in.a.bits.mask)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_735, UInt<1>(0h1), "") : assert_17
node _T_739 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_739, UInt<1>(0h1), "") : assert_18
node _T_743 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_743 :
node _T_744 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_745 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_746 = and(_T_744, _T_745)
node _T_747 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_748 = shr(io.in.a.bits.source, 2)
node _T_749 = eq(_T_748, UInt<7>(0h40))
node _T_750 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_751 = and(_T_749, _T_750)
node _T_752 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_754 = shr(io.in.a.bits.source, 2)
node _T_755 = eq(_T_754, UInt<7>(0h41))
node _T_756 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_757 = and(_T_755, _T_756)
node _T_758 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_759 = and(_T_757, _T_758)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_760 = shr(io.in.a.bits.source, 2)
node _T_761 = eq(_T_760, UInt<7>(0h42))
node _T_762 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_763 = and(_T_761, _T_762)
node _T_764 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_765 = and(_T_763, _T_764)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_766 = shr(io.in.a.bits.source, 2)
node _T_767 = eq(_T_766, UInt<7>(0h43))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_771 = and(_T_769, _T_770)
node _T_772 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_774 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_775 = shr(io.in.a.bits.source, 5)
node _T_776 = eq(_T_775, UInt<1>(0h0))
node _T_777 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_778 = and(_T_776, _T_777)
node _T_779 = leq(uncommonBits_64, UInt<5>(0h1f))
node _T_780 = and(_T_778, _T_779)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_781 = shr(io.in.a.bits.source, 5)
node _T_782 = eq(_T_781, UInt<1>(0h1))
node _T_783 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_784 = and(_T_782, _T_783)
node _T_785 = leq(uncommonBits_65, UInt<5>(0h1f))
node _T_786 = and(_T_784, _T_785)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0)
node _T_787 = shr(io.in.a.bits.source, 5)
node _T_788 = eq(_T_787, UInt<2>(0h2))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_66, UInt<5>(0h1f))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0)
node _T_793 = shr(io.in.a.bits.source, 5)
node _T_794 = eq(_T_793, UInt<2>(0h3))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_67, UInt<5>(0h1f))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0)
node _T_799 = shr(io.in.a.bits.source, 5)
node _T_800 = eq(_T_799, UInt<3>(0h4))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_68, UInt<5>(0h1f))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0)
node _T_805 = shr(io.in.a.bits.source, 5)
node _T_806 = eq(_T_805, UInt<3>(0h5))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_69, UInt<5>(0h1f))
node _T_810 = and(_T_808, _T_809)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0)
node _T_811 = shr(io.in.a.bits.source, 5)
node _T_812 = eq(_T_811, UInt<3>(0h6))
node _T_813 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_814 = and(_T_812, _T_813)
node _T_815 = leq(uncommonBits_70, UInt<5>(0h1f))
node _T_816 = and(_T_814, _T_815)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0)
node _T_817 = shr(io.in.a.bits.source, 5)
node _T_818 = eq(_T_817, UInt<3>(0h7))
node _T_819 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_820 = and(_T_818, _T_819)
node _T_821 = leq(uncommonBits_71, UInt<5>(0h1f))
node _T_822 = and(_T_820, _T_821)
node _T_823 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_824 = or(_T_747, _T_753)
node _T_825 = or(_T_824, _T_759)
node _T_826 = or(_T_825, _T_765)
node _T_827 = or(_T_826, _T_771)
node _T_828 = or(_T_827, _T_772)
node _T_829 = or(_T_828, _T_773)
node _T_830 = or(_T_829, _T_774)
node _T_831 = or(_T_830, _T_780)
node _T_832 = or(_T_831, _T_786)
node _T_833 = or(_T_832, _T_792)
node _T_834 = or(_T_833, _T_798)
node _T_835 = or(_T_834, _T_804)
node _T_836 = or(_T_835, _T_810)
node _T_837 = or(_T_836, _T_816)
node _T_838 = or(_T_837, _T_822)
node _T_839 = or(_T_838, _T_823)
node _T_840 = and(_T_746, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_841, UInt<1>(0h1), "") : assert_19
node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_846 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_847 = and(_T_845, _T_846)
node _T_848 = or(UInt<1>(0h0), _T_847)
node _T_849 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<17>(0h10000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = and(_T_848, _T_853)
node _T_855 = or(UInt<1>(0h0), _T_854)
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_855, UInt<1>(0h1), "") : assert_20
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(source_ok, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(is_aligned, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_865 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_865, UInt<1>(0h1), "") : assert_23
node _T_869 = eq(io.in.a.bits.mask, mask)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_869, UInt<1>(0h1), "") : assert_24
node _T_873 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_873, UInt<1>(0h1), "") : assert_25
node _T_877 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_877 :
node _T_878 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_879 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_880 = and(_T_878, _T_879)
node _T_881 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_882 = shr(io.in.a.bits.source, 2)
node _T_883 = eq(_T_882, UInt<7>(0h40))
node _T_884 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_885 = and(_T_883, _T_884)
node _T_886 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_887 = and(_T_885, _T_886)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_888 = shr(io.in.a.bits.source, 2)
node _T_889 = eq(_T_888, UInt<7>(0h41))
node _T_890 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_891 = and(_T_889, _T_890)
node _T_892 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_893 = and(_T_891, _T_892)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_894 = shr(io.in.a.bits.source, 2)
node _T_895 = eq(_T_894, UInt<7>(0h42))
node _T_896 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_897 = and(_T_895, _T_896)
node _T_898 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_899 = and(_T_897, _T_898)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_900 = shr(io.in.a.bits.source, 2)
node _T_901 = eq(_T_900, UInt<7>(0h43))
node _T_902 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_903 = and(_T_901, _T_902)
node _T_904 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_905 = and(_T_903, _T_904)
node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0)
node _T_909 = shr(io.in.a.bits.source, 5)
node _T_910 = eq(_T_909, UInt<1>(0h0))
node _T_911 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_912 = and(_T_910, _T_911)
node _T_913 = leq(uncommonBits_76, UInt<5>(0h1f))
node _T_914 = and(_T_912, _T_913)
node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0)
node _T_915 = shr(io.in.a.bits.source, 5)
node _T_916 = eq(_T_915, UInt<1>(0h1))
node _T_917 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_918 = and(_T_916, _T_917)
node _T_919 = leq(uncommonBits_77, UInt<5>(0h1f))
node _T_920 = and(_T_918, _T_919)
node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0)
node _T_921 = shr(io.in.a.bits.source, 5)
node _T_922 = eq(_T_921, UInt<2>(0h2))
node _T_923 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_924 = and(_T_922, _T_923)
node _T_925 = leq(uncommonBits_78, UInt<5>(0h1f))
node _T_926 = and(_T_924, _T_925)
node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0)
node _T_927 = shr(io.in.a.bits.source, 5)
node _T_928 = eq(_T_927, UInt<2>(0h3))
node _T_929 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_930 = and(_T_928, _T_929)
node _T_931 = leq(uncommonBits_79, UInt<5>(0h1f))
node _T_932 = and(_T_930, _T_931)
node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0)
node _T_933 = shr(io.in.a.bits.source, 5)
node _T_934 = eq(_T_933, UInt<3>(0h4))
node _T_935 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_936 = and(_T_934, _T_935)
node _T_937 = leq(uncommonBits_80, UInt<5>(0h1f))
node _T_938 = and(_T_936, _T_937)
node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0)
node _T_939 = shr(io.in.a.bits.source, 5)
node _T_940 = eq(_T_939, UInt<3>(0h5))
node _T_941 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_942 = and(_T_940, _T_941)
node _T_943 = leq(uncommonBits_81, UInt<5>(0h1f))
node _T_944 = and(_T_942, _T_943)
node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0)
node _T_945 = shr(io.in.a.bits.source, 5)
node _T_946 = eq(_T_945, UInt<3>(0h6))
node _T_947 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_948 = and(_T_946, _T_947)
node _T_949 = leq(uncommonBits_82, UInt<5>(0h1f))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0)
node _T_951 = shr(io.in.a.bits.source, 5)
node _T_952 = eq(_T_951, UInt<3>(0h7))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_83, UInt<5>(0h1f))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_958 = or(_T_881, _T_887)
node _T_959 = or(_T_958, _T_893)
node _T_960 = or(_T_959, _T_899)
node _T_961 = or(_T_960, _T_905)
node _T_962 = or(_T_961, _T_906)
node _T_963 = or(_T_962, _T_907)
node _T_964 = or(_T_963, _T_908)
node _T_965 = or(_T_964, _T_914)
node _T_966 = or(_T_965, _T_920)
node _T_967 = or(_T_966, _T_926)
node _T_968 = or(_T_967, _T_932)
node _T_969 = or(_T_968, _T_938)
node _T_970 = or(_T_969, _T_944)
node _T_971 = or(_T_970, _T_950)
node _T_972 = or(_T_971, _T_956)
node _T_973 = or(_T_972, _T_957)
node _T_974 = and(_T_880, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_977 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = and(_T_976, _T_981)
node _T_983 = or(UInt<1>(0h0), _T_982)
node _T_984 = and(_T_975, _T_983)
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_984, UInt<1>(0h1), "") : assert_26
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(source_ok, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(is_aligned, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_994 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_994, UInt<1>(0h1), "") : assert_29
node _T_998 = eq(io.in.a.bits.mask, mask)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_998, UInt<1>(0h1), "") : assert_30
node _T_1002 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1002 :
node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1004 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1007 = shr(io.in.a.bits.source, 2)
node _T_1008 = eq(_T_1007, UInt<7>(0h40))
node _T_1009 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1012 = and(_T_1010, _T_1011)
node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1013 = shr(io.in.a.bits.source, 2)
node _T_1014 = eq(_T_1013, UInt<7>(0h41))
node _T_1015 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1016 = and(_T_1014, _T_1015)
node _T_1017 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1018 = and(_T_1016, _T_1017)
node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1019 = shr(io.in.a.bits.source, 2)
node _T_1020 = eq(_T_1019, UInt<7>(0h42))
node _T_1021 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1022 = and(_T_1020, _T_1021)
node _T_1023 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1024 = and(_T_1022, _T_1023)
node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<7>(0h43))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _T_1031 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1032 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1033 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0)
node _T_1034 = shr(io.in.a.bits.source, 5)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
node _T_1036 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1037 = and(_T_1035, _T_1036)
node _T_1038 = leq(uncommonBits_88, UInt<5>(0h1f))
node _T_1039 = and(_T_1037, _T_1038)
node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0)
node _T_1040 = shr(io.in.a.bits.source, 5)
node _T_1041 = eq(_T_1040, UInt<1>(0h1))
node _T_1042 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1043 = and(_T_1041, _T_1042)
node _T_1044 = leq(uncommonBits_89, UInt<5>(0h1f))
node _T_1045 = and(_T_1043, _T_1044)
node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0)
node _T_1046 = shr(io.in.a.bits.source, 5)
node _T_1047 = eq(_T_1046, UInt<2>(0h2))
node _T_1048 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = leq(uncommonBits_90, UInt<5>(0h1f))
node _T_1051 = and(_T_1049, _T_1050)
node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0)
node _T_1052 = shr(io.in.a.bits.source, 5)
node _T_1053 = eq(_T_1052, UInt<2>(0h3))
node _T_1054 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1055 = and(_T_1053, _T_1054)
node _T_1056 = leq(uncommonBits_91, UInt<5>(0h1f))
node _T_1057 = and(_T_1055, _T_1056)
node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0)
node _T_1058 = shr(io.in.a.bits.source, 5)
node _T_1059 = eq(_T_1058, UInt<3>(0h4))
node _T_1060 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = leq(uncommonBits_92, UInt<5>(0h1f))
node _T_1063 = and(_T_1061, _T_1062)
node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0)
node _T_1064 = shr(io.in.a.bits.source, 5)
node _T_1065 = eq(_T_1064, UInt<3>(0h5))
node _T_1066 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1067 = and(_T_1065, _T_1066)
node _T_1068 = leq(uncommonBits_93, UInt<5>(0h1f))
node _T_1069 = and(_T_1067, _T_1068)
node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0)
node _T_1070 = shr(io.in.a.bits.source, 5)
node _T_1071 = eq(_T_1070, UInt<3>(0h6))
node _T_1072 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1073 = and(_T_1071, _T_1072)
node _T_1074 = leq(uncommonBits_94, UInt<5>(0h1f))
node _T_1075 = and(_T_1073, _T_1074)
node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0)
node _T_1076 = shr(io.in.a.bits.source, 5)
node _T_1077 = eq(_T_1076, UInt<3>(0h7))
node _T_1078 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1079 = and(_T_1077, _T_1078)
node _T_1080 = leq(uncommonBits_95, UInt<5>(0h1f))
node _T_1081 = and(_T_1079, _T_1080)
node _T_1082 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1083 = or(_T_1006, _T_1012)
node _T_1084 = or(_T_1083, _T_1018)
node _T_1085 = or(_T_1084, _T_1024)
node _T_1086 = or(_T_1085, _T_1030)
node _T_1087 = or(_T_1086, _T_1031)
node _T_1088 = or(_T_1087, _T_1032)
node _T_1089 = or(_T_1088, _T_1033)
node _T_1090 = or(_T_1089, _T_1039)
node _T_1091 = or(_T_1090, _T_1045)
node _T_1092 = or(_T_1091, _T_1051)
node _T_1093 = or(_T_1092, _T_1057)
node _T_1094 = or(_T_1093, _T_1063)
node _T_1095 = or(_T_1094, _T_1069)
node _T_1096 = or(_T_1095, _T_1075)
node _T_1097 = or(_T_1096, _T_1081)
node _T_1098 = or(_T_1097, _T_1082)
node _T_1099 = and(_T_1005, _T_1098)
node _T_1100 = or(UInt<1>(0h0), _T_1099)
node _T_1101 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1102 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1103 = cvt(_T_1102)
node _T_1104 = and(_T_1103, asSInt(UInt<17>(0h10000)))
node _T_1105 = asSInt(_T_1104)
node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0)))
node _T_1107 = and(_T_1101, _T_1106)
node _T_1108 = or(UInt<1>(0h0), _T_1107)
node _T_1109 = and(_T_1100, _T_1108)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_31
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(is_aligned, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1119 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_34
node _T_1123 = not(mask)
node _T_1124 = and(io.in.a.bits.mask, _T_1123)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_35
node _T_1129 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1129 :
node _T_1130 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1131 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1134 = shr(io.in.a.bits.source, 2)
node _T_1135 = eq(_T_1134, UInt<7>(0h40))
node _T_1136 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1137 = and(_T_1135, _T_1136)
node _T_1138 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1139 = and(_T_1137, _T_1138)
node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1140 = shr(io.in.a.bits.source, 2)
node _T_1141 = eq(_T_1140, UInt<7>(0h41))
node _T_1142 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1143 = and(_T_1141, _T_1142)
node _T_1144 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1145 = and(_T_1143, _T_1144)
node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1146 = shr(io.in.a.bits.source, 2)
node _T_1147 = eq(_T_1146, UInt<7>(0h42))
node _T_1148 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1149 = and(_T_1147, _T_1148)
node _T_1150 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1151 = and(_T_1149, _T_1150)
node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1152 = shr(io.in.a.bits.source, 2)
node _T_1153 = eq(_T_1152, UInt<7>(0h43))
node _T_1154 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1159 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1160 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0)
node _T_1161 = shr(io.in.a.bits.source, 5)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
node _T_1163 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1164 = and(_T_1162, _T_1163)
node _T_1165 = leq(uncommonBits_100, UInt<5>(0h1f))
node _T_1166 = and(_T_1164, _T_1165)
node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0)
node _T_1167 = shr(io.in.a.bits.source, 5)
node _T_1168 = eq(_T_1167, UInt<1>(0h1))
node _T_1169 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = leq(uncommonBits_101, UInt<5>(0h1f))
node _T_1172 = and(_T_1170, _T_1171)
node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0)
node _T_1173 = shr(io.in.a.bits.source, 5)
node _T_1174 = eq(_T_1173, UInt<2>(0h2))
node _T_1175 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1176 = and(_T_1174, _T_1175)
node _T_1177 = leq(uncommonBits_102, UInt<5>(0h1f))
node _T_1178 = and(_T_1176, _T_1177)
node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0)
node _T_1179 = shr(io.in.a.bits.source, 5)
node _T_1180 = eq(_T_1179, UInt<2>(0h3))
node _T_1181 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = leq(uncommonBits_103, UInt<5>(0h1f))
node _T_1184 = and(_T_1182, _T_1183)
node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0)
node _T_1185 = shr(io.in.a.bits.source, 5)
node _T_1186 = eq(_T_1185, UInt<3>(0h4))
node _T_1187 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = leq(uncommonBits_104, UInt<5>(0h1f))
node _T_1190 = and(_T_1188, _T_1189)
node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0)
node _T_1191 = shr(io.in.a.bits.source, 5)
node _T_1192 = eq(_T_1191, UInt<3>(0h5))
node _T_1193 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1194 = and(_T_1192, _T_1193)
node _T_1195 = leq(uncommonBits_105, UInt<5>(0h1f))
node _T_1196 = and(_T_1194, _T_1195)
node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0)
node _T_1197 = shr(io.in.a.bits.source, 5)
node _T_1198 = eq(_T_1197, UInt<3>(0h6))
node _T_1199 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1200 = and(_T_1198, _T_1199)
node _T_1201 = leq(uncommonBits_106, UInt<5>(0h1f))
node _T_1202 = and(_T_1200, _T_1201)
node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0)
node _T_1203 = shr(io.in.a.bits.source, 5)
node _T_1204 = eq(_T_1203, UInt<3>(0h7))
node _T_1205 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1206 = and(_T_1204, _T_1205)
node _T_1207 = leq(uncommonBits_107, UInt<5>(0h1f))
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1210 = or(_T_1133, _T_1139)
node _T_1211 = or(_T_1210, _T_1145)
node _T_1212 = or(_T_1211, _T_1151)
node _T_1213 = or(_T_1212, _T_1157)
node _T_1214 = or(_T_1213, _T_1158)
node _T_1215 = or(_T_1214, _T_1159)
node _T_1216 = or(_T_1215, _T_1160)
node _T_1217 = or(_T_1216, _T_1166)
node _T_1218 = or(_T_1217, _T_1172)
node _T_1219 = or(_T_1218, _T_1178)
node _T_1220 = or(_T_1219, _T_1184)
node _T_1221 = or(_T_1220, _T_1190)
node _T_1222 = or(_T_1221, _T_1196)
node _T_1223 = or(_T_1222, _T_1202)
node _T_1224 = or(_T_1223, _T_1208)
node _T_1225 = or(_T_1224, _T_1209)
node _T_1226 = and(_T_1132, _T_1225)
node _T_1227 = or(UInt<1>(0h0), _T_1226)
node _T_1228 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1229 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1230 = cvt(_T_1229)
node _T_1231 = and(_T_1230, asSInt(UInt<17>(0h10000)))
node _T_1232 = asSInt(_T_1231)
node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0)))
node _T_1234 = and(_T_1228, _T_1233)
node _T_1235 = or(UInt<1>(0h0), _T_1234)
node _T_1236 = and(_T_1227, _T_1235)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_36
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(source_ok, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1243 = asUInt(reset)
node _T_1244 = eq(_T_1243, UInt<1>(0h0))
when _T_1244 :
node _T_1245 = eq(is_aligned, UInt<1>(0h0))
when _T_1245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1246 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_39
node _T_1250 = eq(io.in.a.bits.mask, mask)
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(_T_1250, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1250, UInt<1>(0h1), "") : assert_40
node _T_1254 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1254 :
node _T_1255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1256 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1257 = and(_T_1255, _T_1256)
node _T_1258 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0)
node _T_1259 = shr(io.in.a.bits.source, 2)
node _T_1260 = eq(_T_1259, UInt<7>(0h40))
node _T_1261 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1262 = and(_T_1260, _T_1261)
node _T_1263 = leq(uncommonBits_108, UInt<2>(0h3))
node _T_1264 = and(_T_1262, _T_1263)
node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0)
node _T_1265 = shr(io.in.a.bits.source, 2)
node _T_1266 = eq(_T_1265, UInt<7>(0h41))
node _T_1267 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = leq(uncommonBits_109, UInt<2>(0h3))
node _T_1270 = and(_T_1268, _T_1269)
node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0)
node _T_1271 = shr(io.in.a.bits.source, 2)
node _T_1272 = eq(_T_1271, UInt<7>(0h42))
node _T_1273 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = leq(uncommonBits_110, UInt<2>(0h3))
node _T_1276 = and(_T_1274, _T_1275)
node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0)
node _T_1277 = shr(io.in.a.bits.source, 2)
node _T_1278 = eq(_T_1277, UInt<7>(0h43))
node _T_1279 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1280 = and(_T_1278, _T_1279)
node _T_1281 = leq(uncommonBits_111, UInt<2>(0h3))
node _T_1282 = and(_T_1280, _T_1281)
node _T_1283 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1284 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1285 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0)
node _T_1286 = shr(io.in.a.bits.source, 5)
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
node _T_1288 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_1289 = and(_T_1287, _T_1288)
node _T_1290 = leq(uncommonBits_112, UInt<5>(0h1f))
node _T_1291 = and(_T_1289, _T_1290)
node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0)
node _T_1292 = shr(io.in.a.bits.source, 5)
node _T_1293 = eq(_T_1292, UInt<1>(0h1))
node _T_1294 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_1295 = and(_T_1293, _T_1294)
node _T_1296 = leq(uncommonBits_113, UInt<5>(0h1f))
node _T_1297 = and(_T_1295, _T_1296)
node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0)
node _T_1298 = shr(io.in.a.bits.source, 5)
node _T_1299 = eq(_T_1298, UInt<2>(0h2))
node _T_1300 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_1301 = and(_T_1299, _T_1300)
node _T_1302 = leq(uncommonBits_114, UInt<5>(0h1f))
node _T_1303 = and(_T_1301, _T_1302)
node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0)
node _T_1304 = shr(io.in.a.bits.source, 5)
node _T_1305 = eq(_T_1304, UInt<2>(0h3))
node _T_1306 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_1307 = and(_T_1305, _T_1306)
node _T_1308 = leq(uncommonBits_115, UInt<5>(0h1f))
node _T_1309 = and(_T_1307, _T_1308)
node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0)
node _T_1310 = shr(io.in.a.bits.source, 5)
node _T_1311 = eq(_T_1310, UInt<3>(0h4))
node _T_1312 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = leq(uncommonBits_116, UInt<5>(0h1f))
node _T_1315 = and(_T_1313, _T_1314)
node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0)
node _T_1316 = shr(io.in.a.bits.source, 5)
node _T_1317 = eq(_T_1316, UInt<3>(0h5))
node _T_1318 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_1319 = and(_T_1317, _T_1318)
node _T_1320 = leq(uncommonBits_117, UInt<5>(0h1f))
node _T_1321 = and(_T_1319, _T_1320)
node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0)
node _T_1322 = shr(io.in.a.bits.source, 5)
node _T_1323 = eq(_T_1322, UInt<3>(0h6))
node _T_1324 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_1325 = and(_T_1323, _T_1324)
node _T_1326 = leq(uncommonBits_118, UInt<5>(0h1f))
node _T_1327 = and(_T_1325, _T_1326)
node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0)
node _T_1328 = shr(io.in.a.bits.source, 5)
node _T_1329 = eq(_T_1328, UInt<3>(0h7))
node _T_1330 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_1331 = and(_T_1329, _T_1330)
node _T_1332 = leq(uncommonBits_119, UInt<5>(0h1f))
node _T_1333 = and(_T_1331, _T_1332)
node _T_1334 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1335 = or(_T_1258, _T_1264)
node _T_1336 = or(_T_1335, _T_1270)
node _T_1337 = or(_T_1336, _T_1276)
node _T_1338 = or(_T_1337, _T_1282)
node _T_1339 = or(_T_1338, _T_1283)
node _T_1340 = or(_T_1339, _T_1284)
node _T_1341 = or(_T_1340, _T_1285)
node _T_1342 = or(_T_1341, _T_1291)
node _T_1343 = or(_T_1342, _T_1297)
node _T_1344 = or(_T_1343, _T_1303)
node _T_1345 = or(_T_1344, _T_1309)
node _T_1346 = or(_T_1345, _T_1315)
node _T_1347 = or(_T_1346, _T_1321)
node _T_1348 = or(_T_1347, _T_1327)
node _T_1349 = or(_T_1348, _T_1333)
node _T_1350 = or(_T_1349, _T_1334)
node _T_1351 = and(_T_1257, _T_1350)
node _T_1352 = or(UInt<1>(0h0), _T_1351)
node _T_1353 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1354 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1355 = cvt(_T_1354)
node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000)))
node _T_1357 = asSInt(_T_1356)
node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0)))
node _T_1359 = and(_T_1353, _T_1358)
node _T_1360 = or(UInt<1>(0h0), _T_1359)
node _T_1361 = and(_T_1352, _T_1360)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_41
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(source_ok, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(is_aligned, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1371 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_44
node _T_1375 = eq(io.in.a.bits.mask, mask)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_45
node _T_1379 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1379 :
node _T_1380 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1381 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1382 = and(_T_1380, _T_1381)
node _T_1383 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0)
node _T_1384 = shr(io.in.a.bits.source, 2)
node _T_1385 = eq(_T_1384, UInt<7>(0h40))
node _T_1386 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = leq(uncommonBits_120, UInt<2>(0h3))
node _T_1389 = and(_T_1387, _T_1388)
node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0)
node _T_1390 = shr(io.in.a.bits.source, 2)
node _T_1391 = eq(_T_1390, UInt<7>(0h41))
node _T_1392 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_1393 = and(_T_1391, _T_1392)
node _T_1394 = leq(uncommonBits_121, UInt<2>(0h3))
node _T_1395 = and(_T_1393, _T_1394)
node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_1396 = shr(io.in.a.bits.source, 2)
node _T_1397 = eq(_T_1396, UInt<7>(0h42))
node _T_1398 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_1399 = and(_T_1397, _T_1398)
node _T_1400 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_1401 = and(_T_1399, _T_1400)
node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0)
node _T_1402 = shr(io.in.a.bits.source, 2)
node _T_1403 = eq(_T_1402, UInt<7>(0h43))
node _T_1404 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_1405 = and(_T_1403, _T_1404)
node _T_1406 = leq(uncommonBits_123, UInt<2>(0h3))
node _T_1407 = and(_T_1405, _T_1406)
node _T_1408 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1409 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1410 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0)
node _T_1411 = shr(io.in.a.bits.source, 5)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
node _T_1413 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_1414 = and(_T_1412, _T_1413)
node _T_1415 = leq(uncommonBits_124, UInt<5>(0h1f))
node _T_1416 = and(_T_1414, _T_1415)
node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0)
node _T_1417 = shr(io.in.a.bits.source, 5)
node _T_1418 = eq(_T_1417, UInt<1>(0h1))
node _T_1419 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_1420 = and(_T_1418, _T_1419)
node _T_1421 = leq(uncommonBits_125, UInt<5>(0h1f))
node _T_1422 = and(_T_1420, _T_1421)
node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0)
node _T_1423 = shr(io.in.a.bits.source, 5)
node _T_1424 = eq(_T_1423, UInt<2>(0h2))
node _T_1425 = leq(UInt<1>(0h0), uncommonBits_126)
node _T_1426 = and(_T_1424, _T_1425)
node _T_1427 = leq(uncommonBits_126, UInt<5>(0h1f))
node _T_1428 = and(_T_1426, _T_1427)
node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0)
node _T_1429 = shr(io.in.a.bits.source, 5)
node _T_1430 = eq(_T_1429, UInt<2>(0h3))
node _T_1431 = leq(UInt<1>(0h0), uncommonBits_127)
node _T_1432 = and(_T_1430, _T_1431)
node _T_1433 = leq(uncommonBits_127, UInt<5>(0h1f))
node _T_1434 = and(_T_1432, _T_1433)
node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0)
node _T_1435 = shr(io.in.a.bits.source, 5)
node _T_1436 = eq(_T_1435, UInt<3>(0h4))
node _T_1437 = leq(UInt<1>(0h0), uncommonBits_128)
node _T_1438 = and(_T_1436, _T_1437)
node _T_1439 = leq(uncommonBits_128, UInt<5>(0h1f))
node _T_1440 = and(_T_1438, _T_1439)
node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0)
node _T_1441 = shr(io.in.a.bits.source, 5)
node _T_1442 = eq(_T_1441, UInt<3>(0h5))
node _T_1443 = leq(UInt<1>(0h0), uncommonBits_129)
node _T_1444 = and(_T_1442, _T_1443)
node _T_1445 = leq(uncommonBits_129, UInt<5>(0h1f))
node _T_1446 = and(_T_1444, _T_1445)
node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0)
node _T_1447 = shr(io.in.a.bits.source, 5)
node _T_1448 = eq(_T_1447, UInt<3>(0h6))
node _T_1449 = leq(UInt<1>(0h0), uncommonBits_130)
node _T_1450 = and(_T_1448, _T_1449)
node _T_1451 = leq(uncommonBits_130, UInt<5>(0h1f))
node _T_1452 = and(_T_1450, _T_1451)
node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0)
node _T_1453 = shr(io.in.a.bits.source, 5)
node _T_1454 = eq(_T_1453, UInt<3>(0h7))
node _T_1455 = leq(UInt<1>(0h0), uncommonBits_131)
node _T_1456 = and(_T_1454, _T_1455)
node _T_1457 = leq(uncommonBits_131, UInt<5>(0h1f))
node _T_1458 = and(_T_1456, _T_1457)
node _T_1459 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1460 = or(_T_1383, _T_1389)
node _T_1461 = or(_T_1460, _T_1395)
node _T_1462 = or(_T_1461, _T_1401)
node _T_1463 = or(_T_1462, _T_1407)
node _T_1464 = or(_T_1463, _T_1408)
node _T_1465 = or(_T_1464, _T_1409)
node _T_1466 = or(_T_1465, _T_1410)
node _T_1467 = or(_T_1466, _T_1416)
node _T_1468 = or(_T_1467, _T_1422)
node _T_1469 = or(_T_1468, _T_1428)
node _T_1470 = or(_T_1469, _T_1434)
node _T_1471 = or(_T_1470, _T_1440)
node _T_1472 = or(_T_1471, _T_1446)
node _T_1473 = or(_T_1472, _T_1452)
node _T_1474 = or(_T_1473, _T_1458)
node _T_1475 = or(_T_1474, _T_1459)
node _T_1476 = and(_T_1382, _T_1475)
node _T_1477 = or(UInt<1>(0h0), _T_1476)
node _T_1478 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1479 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1480 = cvt(_T_1479)
node _T_1481 = and(_T_1480, asSInt(UInt<17>(0h10000)))
node _T_1482 = asSInt(_T_1481)
node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0)))
node _T_1484 = and(_T_1478, _T_1483)
node _T_1485 = or(UInt<1>(0h0), _T_1484)
node _T_1486 = and(_T_1477, _T_1485)
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_46
node _T_1490 = asUInt(reset)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
when _T_1491 :
node _T_1492 = eq(source_ok, UInt<1>(0h0))
when _T_1492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1493 = asUInt(reset)
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
when _T_1494 :
node _T_1495 = eq(is_aligned, UInt<1>(0h0))
when _T_1495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1496 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1497 = asUInt(reset)
node _T_1498 = eq(_T_1497, UInt<1>(0h0))
when _T_1498 :
node _T_1499 = eq(_T_1496, UInt<1>(0h0))
when _T_1499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1496, UInt<1>(0h1), "") : assert_49
node _T_1500 = eq(io.in.a.bits.mask, mask)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_50
node _T_1504 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(_T_1504, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1504, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1508 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1509 = asUInt(reset)
node _T_1510 = eq(_T_1509, UInt<1>(0h0))
when _T_1510 :
node _T_1511 = eq(_T_1508, UInt<1>(0h0))
when _T_1511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1508, UInt<1>(0h1), "") : assert_52
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.d.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.d.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.d.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.d.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0)
node _source_ok_T_120 = shr(io.in.d.bits.source, 5)
node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0))
node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122)
node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f))
node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124)
node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0)
node _source_ok_T_126 = shr(io.in.d.bits.source, 5)
node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1))
node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128)
node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f))
node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130)
node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0)
node _source_ok_T_132 = shr(io.in.d.bits.source, 5)
node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2))
node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134)
node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f))
node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136)
node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0)
node _source_ok_T_138 = shr(io.in.d.bits.source, 5)
node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3))
node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140)
node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f))
node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142)
node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0)
node _source_ok_T_144 = shr(io.in.d.bits.source, 5)
node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4))
node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146)
node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f))
node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148)
node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0)
node _source_ok_T_150 = shr(io.in.d.bits.source, 5)
node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5))
node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21)
node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152)
node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f))
node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154)
node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0)
node _source_ok_T_156 = shr(io.in.d.bits.source, 5)
node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6))
node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22)
node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158)
node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f))
node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160)
node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0)
node _source_ok_T_162 = shr(io.in.d.bits.source, 5)
node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7))
node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23)
node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164)
node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f))
node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166)
node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE_1 : UInt<1>[17]
connect _source_ok_WIRE_1[0], _source_ok_T_92
connect _source_ok_WIRE_1[1], _source_ok_T_98
connect _source_ok_WIRE_1[2], _source_ok_T_104
connect _source_ok_WIRE_1[3], _source_ok_T_110
connect _source_ok_WIRE_1[4], _source_ok_T_116
connect _source_ok_WIRE_1[5], _source_ok_T_117
connect _source_ok_WIRE_1[6], _source_ok_T_118
connect _source_ok_WIRE_1[7], _source_ok_T_119
connect _source_ok_WIRE_1[8], _source_ok_T_125
connect _source_ok_WIRE_1[9], _source_ok_T_131
connect _source_ok_WIRE_1[10], _source_ok_T_137
connect _source_ok_WIRE_1[11], _source_ok_T_143
connect _source_ok_WIRE_1[12], _source_ok_T_149
connect _source_ok_WIRE_1[13], _source_ok_T_155
connect _source_ok_WIRE_1[14], _source_ok_T_161
connect _source_ok_WIRE_1[15], _source_ok_T_167
connect _source_ok_WIRE_1[16], _source_ok_T_168
node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11])
node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12])
node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13])
node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14])
node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15])
node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1512 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1512 :
node _T_1513 = asUInt(reset)
node _T_1514 = eq(_T_1513, UInt<1>(0h0))
when _T_1514 :
node _T_1515 = eq(source_ok_1, UInt<1>(0h0))
when _T_1515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1517 = asUInt(reset)
node _T_1518 = eq(_T_1517, UInt<1>(0h0))
when _T_1518 :
node _T_1519 = eq(_T_1516, UInt<1>(0h0))
when _T_1519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1516, UInt<1>(0h1), "") : assert_54
node _T_1520 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1521 = asUInt(reset)
node _T_1522 = eq(_T_1521, UInt<1>(0h0))
when _T_1522 :
node _T_1523 = eq(_T_1520, UInt<1>(0h0))
when _T_1523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1520, UInt<1>(0h1), "") : assert_55
node _T_1524 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(_T_1524, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1524, UInt<1>(0h1), "") : assert_56
node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(_T_1528, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1528, UInt<1>(0h1), "") : assert_57
node _T_1532 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1532 :
node _T_1533 = asUInt(reset)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
when _T_1534 :
node _T_1535 = eq(source_ok_1, UInt<1>(0h0))
when _T_1535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(sink_ok, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1539 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_60
node _T_1543 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(_T_1543, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1543, UInt<1>(0h1), "") : assert_61
node _T_1547 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1548 = asUInt(reset)
node _T_1549 = eq(_T_1548, UInt<1>(0h0))
when _T_1549 :
node _T_1550 = eq(_T_1547, UInt<1>(0h0))
when _T_1550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1547, UInt<1>(0h1), "") : assert_62
node _T_1551 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_63
node _T_1555 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1556 = or(UInt<1>(0h0), _T_1555)
node _T_1557 = asUInt(reset)
node _T_1558 = eq(_T_1557, UInt<1>(0h0))
when _T_1558 :
node _T_1559 = eq(_T_1556, UInt<1>(0h0))
when _T_1559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1556, UInt<1>(0h1), "") : assert_64
node _T_1560 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1560 :
node _T_1561 = asUInt(reset)
node _T_1562 = eq(_T_1561, UInt<1>(0h0))
when _T_1562 :
node _T_1563 = eq(source_ok_1, UInt<1>(0h0))
when _T_1563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(sink_ok, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1567 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_67
node _T_1571 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1572 = asUInt(reset)
node _T_1573 = eq(_T_1572, UInt<1>(0h0))
when _T_1573 :
node _T_1574 = eq(_T_1571, UInt<1>(0h0))
when _T_1574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1571, UInt<1>(0h1), "") : assert_68
node _T_1575 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1576 = asUInt(reset)
node _T_1577 = eq(_T_1576, UInt<1>(0h0))
when _T_1577 :
node _T_1578 = eq(_T_1575, UInt<1>(0h0))
when _T_1578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1575, UInt<1>(0h1), "") : assert_69
node _T_1579 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1580 = or(_T_1579, io.in.d.bits.corrupt)
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_70
node _T_1584 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1585 = or(UInt<1>(0h0), _T_1584)
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_71
node _T_1589 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(source_ok_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1593 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_73
node _T_1597 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(_T_1597, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1597, UInt<1>(0h1), "") : assert_74
node _T_1601 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1602 = or(UInt<1>(0h0), _T_1601)
node _T_1603 = asUInt(reset)
node _T_1604 = eq(_T_1603, UInt<1>(0h0))
when _T_1604 :
node _T_1605 = eq(_T_1602, UInt<1>(0h0))
when _T_1605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1602, UInt<1>(0h1), "") : assert_75
node _T_1606 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1606 :
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(source_ok_1, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1610 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(_T_1610, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1610, UInt<1>(0h1), "") : assert_77
node _T_1614 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1615 = or(_T_1614, io.in.d.bits.corrupt)
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_78
node _T_1619 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1620 = or(UInt<1>(0h0), _T_1619)
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(_T_1620, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1620, UInt<1>(0h1), "") : assert_79
node _T_1624 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1624 :
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(source_ok_1, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1628 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_81
node _T_1632 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_82
node _T_1636 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1637 = or(UInt<1>(0h0), _T_1636)
node _T_1638 = asUInt(reset)
node _T_1639 = eq(_T_1638, UInt<1>(0h0))
when _T_1639 :
node _T_1640 = eq(_T_1637, UInt<1>(0h0))
when _T_1640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1637, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<17>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1641 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1642 = asUInt(reset)
node _T_1643 = eq(_T_1642, UInt<1>(0h0))
when _T_1643 :
node _T_1644 = eq(_T_1641, UInt<1>(0h0))
when _T_1644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1641, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1645 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1646 = asUInt(reset)
node _T_1647 = eq(_T_1646, UInt<1>(0h0))
when _T_1647 :
node _T_1648 = eq(_T_1645, UInt<1>(0h0))
when _T_1648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1645, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1649 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1650 = asUInt(reset)
node _T_1651 = eq(_T_1650, UInt<1>(0h0))
when _T_1651 :
node _T_1652 = eq(_T_1649, UInt<1>(0h0))
when _T_1652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1649, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1653 = eq(a_first, UInt<1>(0h0))
node _T_1654 = and(io.in.a.valid, _T_1653)
when _T_1654 :
node _T_1655 = eq(io.in.a.bits.opcode, opcode)
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(_T_1655, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1655, UInt<1>(0h1), "") : assert_87
node _T_1659 = eq(io.in.a.bits.param, param)
node _T_1660 = asUInt(reset)
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(_T_1659, UInt<1>(0h0))
when _T_1662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1659, UInt<1>(0h1), "") : assert_88
node _T_1663 = eq(io.in.a.bits.size, size)
node _T_1664 = asUInt(reset)
node _T_1665 = eq(_T_1664, UInt<1>(0h0))
when _T_1665 :
node _T_1666 = eq(_T_1663, UInt<1>(0h0))
when _T_1666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1663, UInt<1>(0h1), "") : assert_89
node _T_1667 = eq(io.in.a.bits.source, source)
node _T_1668 = asUInt(reset)
node _T_1669 = eq(_T_1668, UInt<1>(0h0))
when _T_1669 :
node _T_1670 = eq(_T_1667, UInt<1>(0h0))
when _T_1670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1667, UInt<1>(0h1), "") : assert_90
node _T_1671 = eq(io.in.a.bits.address, address)
node _T_1672 = asUInt(reset)
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
when _T_1673 :
node _T_1674 = eq(_T_1671, UInt<1>(0h0))
when _T_1674 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1671, UInt<1>(0h1), "") : assert_91
node _T_1675 = and(io.in.a.ready, io.in.a.valid)
node _T_1676 = and(_T_1675, a_first)
when _T_1676 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1677 = eq(d_first, UInt<1>(0h0))
node _T_1678 = and(io.in.d.valid, _T_1677)
when _T_1678 :
node _T_1679 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1680 = asUInt(reset)
node _T_1681 = eq(_T_1680, UInt<1>(0h0))
when _T_1681 :
node _T_1682 = eq(_T_1679, UInt<1>(0h0))
when _T_1682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1679, UInt<1>(0h1), "") : assert_92
node _T_1683 = eq(io.in.d.bits.param, param_1)
node _T_1684 = asUInt(reset)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(_T_1683, UInt<1>(0h0))
when _T_1686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1683, UInt<1>(0h1), "") : assert_93
node _T_1687 = eq(io.in.d.bits.size, size_1)
node _T_1688 = asUInt(reset)
node _T_1689 = eq(_T_1688, UInt<1>(0h0))
when _T_1689 :
node _T_1690 = eq(_T_1687, UInt<1>(0h0))
when _T_1690 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1687, UInt<1>(0h1), "") : assert_94
node _T_1691 = eq(io.in.d.bits.source, source_1)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_95
node _T_1695 = eq(io.in.d.bits.sink, sink)
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_96
node _T_1699 = eq(io.in.d.bits.denied, denied)
node _T_1700 = asUInt(reset)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
when _T_1701 :
node _T_1702 = eq(_T_1699, UInt<1>(0h0))
when _T_1702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1699, UInt<1>(0h1), "") : assert_97
node _T_1703 = and(io.in.d.ready, io.in.d.valid)
node _T_1704 = and(_T_1703, d_first)
when _T_1704 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<513>
connect a_set, UInt<513>(0h0)
wire a_set_wo_ready : UInt<513>
connect a_set_wo_ready, UInt<513>(0h0)
wire a_opcodes_set : UInt<2052>
connect a_opcodes_set, UInt<2052>(0h0)
wire a_sizes_set : UInt<2052>
connect a_sizes_set, UInt<2052>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1705 = and(io.in.a.valid, a_first_1)
node _T_1706 = and(_T_1705, UInt<1>(0h1))
when _T_1706 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1707 = and(io.in.a.ready, io.in.a.valid)
node _T_1708 = and(_T_1707, a_first_1)
node _T_1709 = and(_T_1708, UInt<1>(0h1))
when _T_1709 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1710 = dshr(inflight, io.in.a.bits.source)
node _T_1711 = bits(_T_1710, 0, 0)
node _T_1712 = eq(_T_1711, UInt<1>(0h0))
node _T_1713 = asUInt(reset)
node _T_1714 = eq(_T_1713, UInt<1>(0h0))
when _T_1714 :
node _T_1715 = eq(_T_1712, UInt<1>(0h0))
when _T_1715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1712, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<513>
connect d_clr, UInt<513>(0h0)
wire d_clr_wo_ready : UInt<513>
connect d_clr_wo_ready, UInt<513>(0h0)
wire d_opcodes_clr : UInt<2052>
connect d_opcodes_clr, UInt<2052>(0h0)
wire d_sizes_clr : UInt<2052>
connect d_sizes_clr, UInt<2052>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1716 = and(io.in.d.valid, d_first_1)
node _T_1717 = and(_T_1716, UInt<1>(0h1))
node _T_1718 = eq(d_release_ack, UInt<1>(0h0))
node _T_1719 = and(_T_1717, _T_1718)
when _T_1719 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1720 = and(io.in.d.ready, io.in.d.valid)
node _T_1721 = and(_T_1720, d_first_1)
node _T_1722 = and(_T_1721, UInt<1>(0h1))
node _T_1723 = eq(d_release_ack, UInt<1>(0h0))
node _T_1724 = and(_T_1722, _T_1723)
when _T_1724 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1725 = and(io.in.d.valid, d_first_1)
node _T_1726 = and(_T_1725, UInt<1>(0h1))
node _T_1727 = eq(d_release_ack, UInt<1>(0h0))
node _T_1728 = and(_T_1726, _T_1727)
when _T_1728 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1729 = dshr(inflight, io.in.d.bits.source)
node _T_1730 = bits(_T_1729, 0, 0)
node _T_1731 = or(_T_1730, same_cycle_resp)
node _T_1732 = asUInt(reset)
node _T_1733 = eq(_T_1732, UInt<1>(0h0))
when _T_1733 :
node _T_1734 = eq(_T_1731, UInt<1>(0h0))
when _T_1734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1731, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1735 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1736 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1737 = or(_T_1735, _T_1736)
node _T_1738 = asUInt(reset)
node _T_1739 = eq(_T_1738, UInt<1>(0h0))
when _T_1739 :
node _T_1740 = eq(_T_1737, UInt<1>(0h0))
when _T_1740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1737, UInt<1>(0h1), "") : assert_100
node _T_1741 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1742 = asUInt(reset)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(_T_1741, UInt<1>(0h0))
when _T_1744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1741, UInt<1>(0h1), "") : assert_101
else :
node _T_1745 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1746 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1747 = or(_T_1745, _T_1746)
node _T_1748 = asUInt(reset)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
when _T_1749 :
node _T_1750 = eq(_T_1747, UInt<1>(0h0))
when _T_1750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1747, UInt<1>(0h1), "") : assert_102
node _T_1751 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1752 = asUInt(reset)
node _T_1753 = eq(_T_1752, UInt<1>(0h0))
when _T_1753 :
node _T_1754 = eq(_T_1751, UInt<1>(0h0))
when _T_1754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1751, UInt<1>(0h1), "") : assert_103
node _T_1755 = and(io.in.d.valid, d_first_1)
node _T_1756 = and(_T_1755, a_first_1)
node _T_1757 = and(_T_1756, io.in.a.valid)
node _T_1758 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1759 = and(_T_1757, _T_1758)
node _T_1760 = eq(d_release_ack, UInt<1>(0h0))
node _T_1761 = and(_T_1759, _T_1760)
when _T_1761 :
node _T_1762 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1763 = or(_T_1762, io.in.a.ready)
node _T_1764 = asUInt(reset)
node _T_1765 = eq(_T_1764, UInt<1>(0h0))
when _T_1765 :
node _T_1766 = eq(_T_1763, UInt<1>(0h0))
when _T_1766 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1763, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_68
node _T_1767 = orr(inflight)
node _T_1768 = eq(_T_1767, UInt<1>(0h0))
node _T_1769 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1770 = or(_T_1768, _T_1769)
node _T_1771 = lt(watchdog, plusarg_reader.out)
node _T_1772 = or(_T_1770, _T_1771)
node _T_1773 = asUInt(reset)
node _T_1774 = eq(_T_1773, UInt<1>(0h0))
when _T_1774 :
node _T_1775 = eq(_T_1772, UInt<1>(0h0))
when _T_1775 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1772, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1776 = and(io.in.a.ready, io.in.a.valid)
node _T_1777 = and(io.in.d.ready, io.in.d.valid)
node _T_1778 = or(_T_1776, _T_1777)
when _T_1778 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<513>
connect c_set, UInt<513>(0h0)
wire c_set_wo_ready : UInt<513>
connect c_set_wo_ready, UInt<513>(0h0)
wire c_opcodes_set : UInt<2052>
connect c_opcodes_set, UInt<2052>(0h0)
wire c_sizes_set : UInt<2052>
connect c_sizes_set, UInt<2052>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1779 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1780 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1781 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1782 = and(_T_1780, _T_1781)
node _T_1783 = and(_T_1779, _T_1782)
when _T_1783 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1784 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1785 = and(_T_1784, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1786 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1787 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1788 = and(_T_1786, _T_1787)
node _T_1789 = and(_T_1785, _T_1788)
when _T_1789 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1790 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1791 = bits(_T_1790, 0, 0)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
node _T_1793 = asUInt(reset)
node _T_1794 = eq(_T_1793, UInt<1>(0h0))
when _T_1794 :
node _T_1795 = eq(_T_1792, UInt<1>(0h0))
when _T_1795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1792, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<513>
connect d_clr_1, UInt<513>(0h0)
wire d_clr_wo_ready_1 : UInt<513>
connect d_clr_wo_ready_1, UInt<513>(0h0)
wire d_opcodes_clr_1 : UInt<2052>
connect d_opcodes_clr_1, UInt<2052>(0h0)
wire d_sizes_clr_1 : UInt<2052>
connect d_sizes_clr_1, UInt<2052>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1796 = and(io.in.d.valid, d_first_2)
node _T_1797 = and(_T_1796, UInt<1>(0h1))
node _T_1798 = and(_T_1797, d_release_ack_1)
when _T_1798 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1799 = and(io.in.d.ready, io.in.d.valid)
node _T_1800 = and(_T_1799, d_first_2)
node _T_1801 = and(_T_1800, UInt<1>(0h1))
node _T_1802 = and(_T_1801, d_release_ack_1)
when _T_1802 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1803 = and(io.in.d.valid, d_first_2)
node _T_1804 = and(_T_1803, UInt<1>(0h1))
node _T_1805 = and(_T_1804, d_release_ack_1)
when _T_1805 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1806 = dshr(inflight_1, io.in.d.bits.source)
node _T_1807 = bits(_T_1806, 0, 0)
node _T_1808 = or(_T_1807, same_cycle_resp_1)
node _T_1809 = asUInt(reset)
node _T_1810 = eq(_T_1809, UInt<1>(0h0))
when _T_1810 :
node _T_1811 = eq(_T_1808, UInt<1>(0h0))
when _T_1811 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1808, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1812 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(_T_1812, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1812, UInt<1>(0h1), "") : assert_108
else :
node _T_1816 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(_T_1816, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1816, UInt<1>(0h1), "") : assert_109
node _T_1820 = and(io.in.d.valid, d_first_2)
node _T_1821 = and(_T_1820, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1822 = and(_T_1821, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1823 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1824 = and(_T_1822, _T_1823)
node _T_1825 = and(_T_1824, d_release_ack_1)
node _T_1826 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1827 = and(_T_1825, _T_1826)
when _T_1827 :
node _T_1828 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<17>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1829 = or(_T_1828, _WIRE_27.ready)
node _T_1830 = asUInt(reset)
node _T_1831 = eq(_T_1830, UInt<1>(0h0))
when _T_1831 :
node _T_1832 = eq(_T_1829, UInt<1>(0h0))
when _T_1832 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1829, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_69
node _T_1833 = orr(inflight_1)
node _T_1834 = eq(_T_1833, UInt<1>(0h0))
node _T_1835 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1836 = or(_T_1834, _T_1835)
node _T_1837 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1838 = or(_T_1836, _T_1837)
node _T_1839 = asUInt(reset)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
when _T_1840 :
node _T_1841 = eq(_T_1838, UInt<1>(0h0))
when _T_1841 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1838, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<17>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1842 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1843 = and(io.in.d.ready, io.in.d.valid)
node _T_1844 = or(_T_1842, _T_1843)
when _T_1844 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN = a_first_done & a_first_1; // @[Decoupled.scala:51:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_22 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_22
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_22
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_34
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_22( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_22 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_22 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_34 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SimpleHellaCacheIFReplayQueue_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, flip nack : { valid : UInt<1>, bits : UInt<6>}, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}}
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
reg reqs : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[2], clock
inst nackq of Queue2_UInt1_1
connect nackq.clock, clock
connect nackq.reset, reset
regreset replaying : UInt<1>, clock, reset, UInt<1>(0h0)
node _next_inflight_onehot_T = not(inflight)
node _next_inflight_onehot_T_1 = bits(_next_inflight_onehot_T, 0, 0)
node _next_inflight_onehot_T_2 = bits(_next_inflight_onehot_T, 1, 1)
node _next_inflight_onehot_T_3 = mux(_next_inflight_onehot_T_2, UInt<2>(0h2), UInt<2>(0h0))
node next_inflight_onehot = mux(_next_inflight_onehot_T_1, UInt<2>(0h1), _next_inflight_onehot_T_3)
node next_inflight = bits(next_inflight_onehot, 1, 1)
node next_replay_onehot = dshl(UInt<1>(0h1), nackq.io.deq.bits)
node _io_replay_valid_T = eq(replaying, UInt<1>(0h0))
node _io_replay_valid_T_1 = and(nackq.io.deq.valid, _io_replay_valid_T)
connect io.replay.valid, _io_replay_valid_T_1
connect io.replay.bits, reqs[nackq.io.deq.bits]
node _io_req_ready_T = andr(inflight)
node _io_req_ready_T_1 = eq(_io_req_ready_T, UInt<1>(0h0))
node _io_req_ready_T_2 = eq(nackq.io.deq.valid, UInt<1>(0h0))
node _io_req_ready_T_3 = and(_io_req_ready_T_1, _io_req_ready_T_2)
node _io_req_ready_T_4 = eq(io.nack.valid, UInt<1>(0h0))
node _io_req_ready_T_5 = and(_io_req_ready_T_3, _io_req_ready_T_4)
connect io.req.ready, _io_req_ready_T_5
node _nack_onehot_T = eq(reqs[0].tag, io.nack.bits)
node _nack_onehot_T_1 = eq(reqs[1].tag, io.nack.bits)
node _nack_onehot_T_2 = cat(_nack_onehot_T_1, _nack_onehot_T)
node nack_onehot = and(_nack_onehot_T_2, inflight)
node _resp_onehot_T = eq(reqs[0].tag, io.resp.bits.tag)
node _resp_onehot_T_1 = eq(reqs[1].tag, io.resp.bits.tag)
node _resp_onehot_T_2 = cat(_resp_onehot_T_1, _resp_onehot_T)
node resp_onehot = and(_resp_onehot_T_2, inflight)
node _replay_complete_T = and(io.resp.valid, replaying)
node _replay_complete_T_1 = eq(io.resp.bits.tag, reqs[nackq.io.deq.bits].tag)
node replay_complete = and(_replay_complete_T, _replay_complete_T_1)
node _nack_head_T = and(io.nack.valid, nackq.io.deq.valid)
node _nack_head_T_1 = eq(io.nack.bits, reqs[nackq.io.deq.bits].tag)
node nack_head = and(_nack_head_T, _nack_head_T_1)
node _nackq_io_enq_valid_T = eq(nack_head, UInt<1>(0h0))
node _nackq_io_enq_valid_T_1 = and(io.nack.valid, _nackq_io_enq_valid_T)
connect nackq.io.enq.valid, _nackq_io_enq_valid_T_1
node _nackq_io_enq_bits_T = bits(nack_onehot, 1, 1)
connect nackq.io.enq.bits, _nackq_io_enq_bits_T
node _T = eq(nackq.io.enq.valid, UInt<1>(0h0))
node _T_1 = or(_T, nackq.io.enq.ready)
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed: SimpleHellaCacheIF: ReplayQueue nack queue overflow\n at SimpleHellaCacheIF.scala:72 assert(!nackq.io.enq.valid || nackq.io.enq.ready,\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
connect nackq.io.deq.ready, replay_complete
node _T_5 = eq(nackq.io.deq.ready, UInt<1>(0h0))
node _T_6 = or(_T_5, nackq.io.deq.valid)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed: SimpleHellaCacheIF: ReplayQueue nack queue underflow\n at SimpleHellaCacheIF.scala:77 assert(!nackq.io.deq.ready || nackq.io.deq.valid,\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _inflight_T = and(io.req.ready, io.req.valid)
node _inflight_T_1 = mux(_inflight_T, next_inflight_onehot, UInt<1>(0h0))
node _inflight_T_2 = or(inflight, _inflight_T_1)
node _inflight_T_3 = mux(io.resp.valid, resp_onehot, UInt<1>(0h0))
node _inflight_T_4 = not(_inflight_T_3)
node _inflight_T_5 = and(_inflight_T_2, _inflight_T_4)
connect inflight, _inflight_T_5
node _T_10 = and(io.req.ready, io.req.valid)
when _T_10 :
connect reqs[next_inflight], io.req.bits
node _T_11 = and(io.replay.ready, io.replay.valid)
when _T_11 :
connect replaying, UInt<1>(0h1)
node _T_12 = or(nack_head, replay_complete)
when _T_12 :
connect replaying, UInt<1>(0h0) | module SimpleHellaCacheIFReplayQueue_1( // @[SimpleHellaCacheIF.scala:18:7]
input clock, // @[SimpleHellaCacheIF.scala:18:7]
input reset, // @[SimpleHellaCacheIF.scala:18:7]
output io_req_ready, // @[SimpleHellaCacheIF.scala:21:14]
input io_req_valid, // @[SimpleHellaCacheIF.scala:21:14]
input [39:0] io_req_bits_addr, // @[SimpleHellaCacheIF.scala:21:14]
input [7:0] io_req_bits_tag, // @[SimpleHellaCacheIF.scala:21:14]
input [1:0] io_req_bits_dprv, // @[SimpleHellaCacheIF.scala:21:14]
input io_req_bits_dv, // @[SimpleHellaCacheIF.scala:21:14]
input io_nack_valid, // @[SimpleHellaCacheIF.scala:21:14]
input [5:0] io_nack_bits, // @[SimpleHellaCacheIF.scala:21:14]
input io_resp_valid, // @[SimpleHellaCacheIF.scala:21:14]
input [39:0] io_resp_bits_addr, // @[SimpleHellaCacheIF.scala:21:14]
input [7:0] io_resp_bits_tag, // @[SimpleHellaCacheIF.scala:21:14]
input [4:0] io_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:21:14]
input [1:0] io_resp_bits_size, // @[SimpleHellaCacheIF.scala:21:14]
input io_resp_bits_signed, // @[SimpleHellaCacheIF.scala:21:14]
input [1:0] io_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:21:14]
input io_resp_bits_dv, // @[SimpleHellaCacheIF.scala:21:14]
input [63:0] io_resp_bits_data, // @[SimpleHellaCacheIF.scala:21:14]
input [7:0] io_resp_bits_mask, // @[SimpleHellaCacheIF.scala:21:14]
input io_resp_bits_replay, // @[SimpleHellaCacheIF.scala:21:14]
input io_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:21:14]
input [63:0] io_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:21:14]
input [63:0] io_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:21:14]
input [63:0] io_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:21:14]
input io_replay_ready, // @[SimpleHellaCacheIF.scala:21:14]
output io_replay_valid, // @[SimpleHellaCacheIF.scala:21:14]
output [39:0] io_replay_bits_addr, // @[SimpleHellaCacheIF.scala:21:14]
output [7:0] io_replay_bits_tag, // @[SimpleHellaCacheIF.scala:21:14]
output [1:0] io_replay_bits_dprv, // @[SimpleHellaCacheIF.scala:21:14]
output io_replay_bits_dv // @[SimpleHellaCacheIF.scala:21:14]
);
wire _nackq_io_enq_ready; // @[SimpleHellaCacheIF.scala:44:21]
wire _nackq_io_deq_valid; // @[SimpleHellaCacheIF.scala:44:21]
wire _nackq_io_deq_bits; // @[SimpleHellaCacheIF.scala:44:21]
wire io_req_valid_0 = io_req_valid; // @[SimpleHellaCacheIF.scala:18:7]
wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_req_bits_dprv_0 = io_req_bits_dprv; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_dv_0 = io_req_bits_dv; // @[SimpleHellaCacheIF.scala:18:7]
wire io_nack_valid_0 = io_nack_valid; // @[SimpleHellaCacheIF.scala:18:7]
wire [5:0] io_nack_bits_0 = io_nack_bits; // @[SimpleHellaCacheIF.scala:18:7]
wire io_resp_valid_0 = io_resp_valid; // @[SimpleHellaCacheIF.scala:18:7]
wire [39:0] io_resp_bits_addr_0 = io_resp_bits_addr; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_resp_bits_tag_0 = io_resp_bits_tag; // @[SimpleHellaCacheIF.scala:18:7]
wire [4:0] io_resp_bits_cmd_0 = io_resp_bits_cmd; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_resp_bits_size_0 = io_resp_bits_size; // @[SimpleHellaCacheIF.scala:18:7]
wire io_resp_bits_signed_0 = io_resp_bits_signed; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_resp_bits_dprv_0 = io_resp_bits_dprv; // @[SimpleHellaCacheIF.scala:18:7]
wire io_resp_bits_dv_0 = io_resp_bits_dv; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_resp_bits_data_0 = io_resp_bits_data; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_resp_bits_mask_0 = io_resp_bits_mask; // @[SimpleHellaCacheIF.scala:18:7]
wire io_resp_bits_replay_0 = io_resp_bits_replay; // @[SimpleHellaCacheIF.scala:18:7]
wire io_resp_bits_has_data_0 = io_resp_bits_has_data; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_resp_bits_data_word_bypass_0 = io_resp_bits_data_word_bypass; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_resp_bits_data_raw_0 = io_resp_bits_data_raw; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_resp_bits_store_data_0 = io_resp_bits_store_data; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_ready_0 = io_replay_ready; // @[SimpleHellaCacheIF.scala:18:7]
wire [4:0] io_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [4:0] io_replay_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_req_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_replay_bits_size = 2'h3; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [63:0] io_replay_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_replay_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:18:7]
wire _io_req_ready_T_5; // @[SimpleHellaCacheIF.scala:59:57]
wire _io_replay_valid_T_1; // @[SimpleHellaCacheIF.scala:55:41]
wire io_req_ready_0; // @[SimpleHellaCacheIF.scala:18:7]
wire [39:0] io_replay_bits_addr_0; // @[SimpleHellaCacheIF.scala:18:7]
wire [7:0] io_replay_bits_tag_0; // @[SimpleHellaCacheIF.scala:18:7]
wire [1:0] io_replay_bits_dprv_0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_bits_dv_0; // @[SimpleHellaCacheIF.scala:18:7]
wire io_replay_valid_0; // @[SimpleHellaCacheIF.scala:18:7]
reg [1:0] inflight; // @[SimpleHellaCacheIF.scala:34:25]
reg [39:0] reqs_0_addr; // @[SimpleHellaCacheIF.scala:35:17]
reg [7:0] reqs_0_tag; // @[SimpleHellaCacheIF.scala:35:17]
reg [1:0] reqs_0_dprv; // @[SimpleHellaCacheIF.scala:35:17]
reg reqs_0_dv; // @[SimpleHellaCacheIF.scala:35:17]
reg [39:0] reqs_1_addr; // @[SimpleHellaCacheIF.scala:35:17]
reg [7:0] reqs_1_tag; // @[SimpleHellaCacheIF.scala:35:17]
reg [1:0] reqs_1_dprv; // @[SimpleHellaCacheIF.scala:35:17]
reg reqs_1_dv; // @[SimpleHellaCacheIF.scala:35:17]
reg replaying; // @[SimpleHellaCacheIF.scala:45:26]
wire [1:0] _next_inflight_onehot_T = ~inflight; // @[SimpleHellaCacheIF.scala:34:25, :47:48]
wire _next_inflight_onehot_T_1 = _next_inflight_onehot_T[0]; // @[OneHot.scala:85:71]
wire _next_inflight_onehot_T_2 = _next_inflight_onehot_T[1]; // @[OneHot.scala:85:71]
wire [1:0] _next_inflight_onehot_T_3 = {_next_inflight_onehot_T_2, 1'h0}; // @[OneHot.scala:85:71]
wire [1:0] next_inflight_onehot = _next_inflight_onehot_T_1 ? 2'h1 : _next_inflight_onehot_T_3; // @[OneHot.scala:85:71]
wire next_inflight = next_inflight_onehot[1]; // @[Mux.scala:50:70]
wire [1:0] next_replay_onehot = 2'h1 << _nackq_io_deq_bits; // @[OneHot.scala:58:35]
wire _io_replay_valid_T = ~replaying; // @[SimpleHellaCacheIF.scala:45:26, :55:44]
assign _io_replay_valid_T_1 = _nackq_io_deq_valid & _io_replay_valid_T; // @[SimpleHellaCacheIF.scala:44:21, :55:{41,44}]
assign io_replay_valid_0 = _io_replay_valid_T_1; // @[SimpleHellaCacheIF.scala:18:7, :55:41]
assign io_replay_bits_addr_0 = _nackq_io_deq_bits ? reqs_1_addr : reqs_0_addr; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :44:21, :56:18]
assign io_replay_bits_tag_0 = _nackq_io_deq_bits ? reqs_1_tag : reqs_0_tag; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :44:21, :56:18]
assign io_replay_bits_dprv_0 = _nackq_io_deq_bits ? reqs_1_dprv : reqs_0_dprv; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :44:21, :56:18]
assign io_replay_bits_dv_0 = _nackq_io_deq_bits ? reqs_1_dv : reqs_0_dv; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :44:21, :56:18]
wire _io_req_ready_T = &inflight; // @[SimpleHellaCacheIF.scala:34:25, :59:29]
wire _io_req_ready_T_1 = ~_io_req_ready_T; // @[SimpleHellaCacheIF.scala:59:{19,29}]
wire _io_req_ready_T_2 = ~_nackq_io_deq_valid; // @[SimpleHellaCacheIF.scala:44:21, :59:37]
wire _io_req_ready_T_3 = _io_req_ready_T_1 & _io_req_ready_T_2; // @[SimpleHellaCacheIF.scala:59:{19,34,37}]
wire _io_req_ready_T_4 = ~io_nack_valid_0; // @[SimpleHellaCacheIF.scala:18:7, :59:60]
assign _io_req_ready_T_5 = _io_req_ready_T_3 & _io_req_ready_T_4; // @[SimpleHellaCacheIF.scala:59:{34,57,60}]
assign io_req_ready_0 = _io_req_ready_T_5; // @[SimpleHellaCacheIF.scala:18:7, :59:57]
wire [7:0] _GEN = {2'h0, io_nack_bits_0}; // @[SimpleHellaCacheIF.scala:18:7, :62:40]
wire _nack_onehot_T = reqs_0_tag == _GEN; // @[SimpleHellaCacheIF.scala:35:17, :62:40]
wire _nack_onehot_T_1 = reqs_1_tag == _GEN; // @[SimpleHellaCacheIF.scala:35:17, :62:40]
wire [1:0] _nack_onehot_T_2 = {_nack_onehot_T_1, _nack_onehot_T}; // @[SimpleHellaCacheIF.scala:62:{24,40}]
wire [1:0] nack_onehot = _nack_onehot_T_2 & inflight; // @[SimpleHellaCacheIF.scala:34:25, :62:{24,67}]
wire _resp_onehot_T = reqs_0_tag == io_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :63:40]
wire _resp_onehot_T_1 = reqs_1_tag == io_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:18:7, :35:17, :63:40]
wire [1:0] _resp_onehot_T_2 = {_resp_onehot_T_1, _resp_onehot_T}; // @[SimpleHellaCacheIF.scala:63:{24,40}]
wire [1:0] resp_onehot = _resp_onehot_T_2 & inflight; // @[SimpleHellaCacheIF.scala:34:25, :63:{24,71}]
wire _replay_complete_T = io_resp_valid_0 & replaying; // @[SimpleHellaCacheIF.scala:18:7, :45:26, :65:39]
wire _replay_complete_T_1 = io_resp_bits_tag_0 == io_replay_bits_tag_0; // @[SimpleHellaCacheIF.scala:18:7, :65:72]
wire replay_complete = _replay_complete_T & _replay_complete_T_1; // @[SimpleHellaCacheIF.scala:65:{39,52,72}]
wire _nack_head_T = io_nack_valid_0 & _nackq_io_deq_valid; // @[SimpleHellaCacheIF.scala:18:7, :44:21, :66:33]
wire _nack_head_T_1 = _GEN == io_replay_bits_tag_0; // @[SimpleHellaCacheIF.scala:18:7, :62:40, :66:71]
wire nack_head = _nack_head_T & _nack_head_T_1; // @[SimpleHellaCacheIF.scala:66:{33,55,71}]
wire _nackq_io_enq_valid_T = ~nack_head; // @[SimpleHellaCacheIF.scala:66:55, :70:42]
wire _nackq_io_enq_valid_T_1 = io_nack_valid_0 & _nackq_io_enq_valid_T; // @[SimpleHellaCacheIF.scala:18:7, :70:{39,42}]
wire _nackq_io_enq_bits_T = nack_onehot[1]; // @[CircuitMath.scala:28:8] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_111 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_125
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_111( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_125 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_119 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0)
node _source_ok_T = shr(io.in.a.bits.source, 12)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits = bits(_uncommonBits_T, 11, 0)
node _T_4 = shr(io.in.a.bits.source, 12)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<12>(0h80f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0)
node _T_24 = shr(io.in.a.bits.source, 12)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0)
node _T_86 = shr(io.in.a.bits.source, 12)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0)
node _T_152 = shr(io.in.a.bits.source, 12)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0)
node _T_199 = shr(io.in.a.bits.source, 12)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0)
node _T_240 = shr(io.in.a.bits.source, 12)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0)
node _T_283 = shr(io.in.a.bits.source, 12)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0)
node _T_321 = shr(io.in.a.bits.source, 12)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0)
node _T_359 = shr(io.in.a.bits.source, 12)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 12)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2064>
connect a_set, UInt<2064>(0h0)
wire a_set_wo_ready : UInt<2064>
connect a_set_wo_ready, UInt<2064>(0h0)
wire a_opcodes_set : UInt<8256>
connect a_opcodes_set, UInt<8256>(0h0)
wire a_sizes_set : UInt<8256>
connect a_sizes_set, UInt<8256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2064>
connect d_clr, UInt<2064>(0h0)
wire d_clr_wo_ready : UInt<2064>
connect d_clr_wo_ready, UInt<2064>(0h0)
wire d_opcodes_clr : UInt<8256>
connect d_opcodes_clr, UInt<8256>(0h0)
wire d_sizes_clr : UInt<8256>
connect d_sizes_clr, UInt<8256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_284
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<12>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2064>
connect c_set, UInt<2064>(0h0)
wire c_set_wo_ready : UInt<2064>
connect c_set_wo_ready, UInt<2064>(0h0)
wire c_opcodes_set : UInt<8256>
connect c_opcodes_set, UInt<8256>(0h0)
wire c_sizes_set : UInt<8256>
connect c_sizes_set, UInt<8256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<12>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<12>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<12>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2064>
connect d_clr_1, UInt<2064>(0h0)
wire d_clr_wo_ready_1 : UInt<2064>
connect d_clr_wo_ready_1, UInt<2064>(0h0)
wire d_opcodes_clr_1 : UInt<8256>
connect d_opcodes_clr_1, UInt<8256>(0h0)
wire d_sizes_clr_1 : UInt<8256>
connect d_sizes_clr_1, UInt<8256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<12>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<12>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<12>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<12>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_285
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<12>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_119( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_27 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_valid, slot_uop.iw_issued)
when _T_35 :
connect next_valid, rebusied | module IssueSlot_27( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_8 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<8>(0hff))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history = bits(io.f1_req_ghist, 7, 0)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 7, 0)
node tag_history = bits(io.f1_req_ghist, 7, 0)
node _tag_T = shr(_T_1, 8)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 7, 0)
smem tage_u_8 : UInt<1>[8] [256]
smem tage_table_8 : UInt<12>[4] [256]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
wire s2_req_rus : UInt<1>[8]
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
connect io.f2_resp[0].valid, s2_req_rhits[0]
node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0])
connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T
connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr
connect io.f2_resp[1].valid, s2_req_rhits[1]
node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2])
connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T
connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr
connect io.f2_resp[2].valid, s2_req_rhits[2]
node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4])
connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T
connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr
connect io.f2_resp[3].valid, s2_req_rhits[3]
node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6])
connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T
connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr
regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _clear_u_hi_T = bits(clear_u_ctr, 19, 19)
node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1))
node _clear_u_lo_T = bits(clear_u_ctr, 19, 19)
node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0))
node clear_u_idx = shr(clear_u_ctr, 11)
wire _clear_u_mask_WIRE : UInt<1>[8]
connect _clear_u_mask_WIRE[0], clear_u_lo
connect _clear_u_mask_WIRE[1], clear_u_hi
connect _clear_u_mask_WIRE[2], clear_u_lo
connect _clear_u_mask_WIRE[3], clear_u_hi
connect _clear_u_mask_WIRE[4], clear_u_lo
connect _clear_u_mask_WIRE[5], clear_u_hi
connect _clear_u_mask_WIRE[6], clear_u_lo
connect _clear_u_mask_WIRE[7], clear_u_hi
node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0])
node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2])
node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo)
node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4])
node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6])
node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo)
node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo)
node _T_2 = shr(io.update_pc, 4)
node idx_history_1 = bits(io.update_hist, 7, 0)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 7, 0)
node tag_history_1 = bits(io.update_hist, 7, 0)
node _tag_T_2 = shr(_T_2, 8)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 7, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
node _wen_T = or(io.update_mask[0], io.update_mask[1])
node _wen_T_1 = or(_wen_T, io.update_mask[2])
node _wen_T_2 = or(_wen_T_1, io.update_mask[3])
node _wen_T_3 = or(doing_reset, _wen_T_2)
wire wen : UInt<1>
connect wen, _wen_T_3
wire _rdata_WIRE : UInt<8>
invalidate _rdata_WIRE
when io.f1_req_valid :
connect _rdata_WIRE, s1_hashed_idx
read mport rdata = tage_table_8[_rdata_WIRE], clock
reg REG : UInt<1>, clock
connect REG, wen
node _T_3 = and(REG, UInt<1>(0h0))
when _T_3 :
wire _WIRE : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect _WIRE[0].ctr, UInt<3>(0h0)
connect _WIRE[0].tag, UInt<8>(0h0)
connect _WIRE[0].valid, UInt<1>(0h0)
connect _WIRE[1].ctr, UInt<3>(0h0)
connect _WIRE[1].tag, UInt<8>(0h0)
connect _WIRE[1].valid, UInt<1>(0h0)
connect _WIRE[2].ctr, UInt<3>(0h0)
connect _WIRE[2].tag, UInt<8>(0h0)
connect _WIRE[2].valid, UInt<1>(0h0)
connect _WIRE[3].ctr, UInt<3>(0h0)
connect _WIRE[3].tag, UInt<8>(0h0)
connect _WIRE[3].valid, UInt<1>(0h0)
connect s2_req_rtage, _WIRE
else :
wire _WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_2 : UInt<12>
connect _WIRE_2, rdata[0]
node _T_4 = bits(_WIRE_2, 2, 0)
connect _WIRE_1.ctr, _T_4
node _T_5 = bits(_WIRE_2, 10, 3)
connect _WIRE_1.tag, _T_5
node _T_6 = bits(_WIRE_2, 11, 11)
connect _WIRE_1.valid, _T_6
wire _WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_4 : UInt<12>
connect _WIRE_4, rdata[1]
node _T_7 = bits(_WIRE_4, 2, 0)
connect _WIRE_3.ctr, _T_7
node _T_8 = bits(_WIRE_4, 10, 3)
connect _WIRE_3.tag, _T_8
node _T_9 = bits(_WIRE_4, 11, 11)
connect _WIRE_3.valid, _T_9
wire _WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_6 : UInt<12>
connect _WIRE_6, rdata[2]
node _T_10 = bits(_WIRE_6, 2, 0)
connect _WIRE_5.ctr, _T_10
node _T_11 = bits(_WIRE_6, 10, 3)
connect _WIRE_5.tag, _T_11
node _T_12 = bits(_WIRE_6, 11, 11)
connect _WIRE_5.valid, _T_12
wire _WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_8 : UInt<12>
connect _WIRE_8, rdata[3]
node _T_13 = bits(_WIRE_8, 2, 0)
connect _WIRE_7.ctr, _T_13
node _T_14 = bits(_WIRE_8, 10, 3)
connect _WIRE_7.tag, _T_14
node _T_15 = bits(_WIRE_8, 11, 11)
connect _WIRE_7.valid, _T_15
wire _WIRE_9 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect _WIRE_9[0].ctr, _WIRE_1.ctr
connect _WIRE_9[0].tag, _WIRE_1.tag
connect _WIRE_9[0].valid, _WIRE_1.valid
connect _WIRE_9[1].ctr, _WIRE_3.ctr
connect _WIRE_9[1].tag, _WIRE_3.tag
connect _WIRE_9[1].valid, _WIRE_3.valid
connect _WIRE_9[2].ctr, _WIRE_5.ctr
connect _WIRE_9[2].tag, _WIRE_5.tag
connect _WIRE_9[2].valid, _WIRE_5.valid
connect _WIRE_9[3].ctr, _WIRE_7.ctr
connect _WIRE_9[3].tag, _WIRE_7.tag
connect _WIRE_9[3].valid, _WIRE_7.valid
connect s2_req_rtage, _WIRE_9
when wen :
node widx = mux(doing_reset, reset_idx, update_idx)
wire _wdata_WIRE : UInt<12>[4]
connect _wdata_WIRE[0], UInt<12>(0h0)
connect _wdata_WIRE[1], UInt<12>(0h0)
connect _wdata_WIRE[2], UInt<12>(0h0)
connect _wdata_WIRE[3], UInt<12>(0h0)
node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _wdata_T = cat(wdata_hi, update_wdata[0].ctr)
node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr)
node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr)
node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr)
wire _wdata_WIRE_1 : UInt<12>[4]
connect _wdata_WIRE_1[0], _wdata_T
connect _wdata_WIRE_1[1], _wdata_T_1
connect _wdata_WIRE_1[2], _wdata_T_2
connect _wdata_WIRE_1[3], _wdata_T_3
node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1)
node _wmask_T = not(UInt<4>(0h0))
node wmask_lo = cat(io.update_mask[1], io.update_mask[0])
node wmask_hi = cat(io.update_mask[3], io.update_mask[2])
node _wmask_T_1 = cat(wmask_hi, wmask_lo)
node wmask = mux(doing_reset, _wmask_T, _wmask_T_1)
node _T_16 = bits(wmask, 0, 0)
node _T_17 = bits(wmask, 1, 1)
node _T_18 = bits(wmask, 2, 2)
node _T_19 = bits(wmask, 3, 3)
write mport MPORT = tage_table_8[widx], clock
when _T_16 :
connect MPORT[0], wdata[0]
when _T_17 :
connect MPORT[1], wdata[1]
when _T_18 :
connect MPORT[2], wdata[2]
when _T_19 :
connect MPORT[3], wdata[3]
wire update_u_mask : UInt<1>[8]
connect update_u_mask[0], io.update_u_mask[0]
connect update_u_mask[1], io.update_u_mask[0]
connect update_u_mask[2], io.update_u_mask[1]
connect update_u_mask[3], io.update_u_mask[1]
connect update_u_mask[4], io.update_u_mask[2]
connect update_u_mask[5], io.update_u_mask[2]
connect update_u_mask[6], io.update_u_mask[3]
connect update_u_mask[7], io.update_u_mask[3]
node _update_u_wen_T = or(doing_reset, doing_clear_u)
node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1])
node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2])
node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3])
node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4])
node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5])
node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6])
node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7])
node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7)
wire update_u_wen : UInt<1>
connect update_u_wen, _update_u_wen_T_8
wire _u_rdata_WIRE : UInt<8>
invalidate _u_rdata_WIRE
when io.f1_req_valid :
connect _u_rdata_WIRE, s1_hashed_idx
read mport u_rdata = tage_u_8[_u_rdata_WIRE], clock
connect s2_req_rus, u_rdata
when update_u_wen :
node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx)
node widx_1 = mux(doing_reset, reset_idx, _widx_T)
node _wdata_T_4 = or(doing_reset, doing_clear_u)
wire _wdata_WIRE_2 : UInt<1>[8]
connect _wdata_WIRE_2[0], UInt<1>(0h0)
connect _wdata_WIRE_2[1], UInt<1>(0h0)
connect _wdata_WIRE_2[2], UInt<1>(0h0)
connect _wdata_WIRE_2[3], UInt<1>(0h0)
connect _wdata_WIRE_2[4], UInt<1>(0h0)
connect _wdata_WIRE_2[5], UInt<1>(0h0)
connect _wdata_WIRE_2[6], UInt<1>(0h0)
connect _wdata_WIRE_2[7], UInt<1>(0h0)
node wdata_lo = cat(io.update_u[1], io.update_u[0])
node wdata_hi_4 = cat(io.update_u[3], io.update_u[2])
node _wdata_T_5 = cat(wdata_hi_4, wdata_lo)
node _wdata_T_6 = bits(_wdata_T_5, 0, 0)
node _wdata_T_7 = bits(_wdata_T_5, 1, 1)
node _wdata_T_8 = bits(_wdata_T_5, 2, 2)
node _wdata_T_9 = bits(_wdata_T_5, 3, 3)
node _wdata_T_10 = bits(_wdata_T_5, 4, 4)
node _wdata_T_11 = bits(_wdata_T_5, 5, 5)
node _wdata_T_12 = bits(_wdata_T_5, 6, 6)
node _wdata_T_13 = bits(_wdata_T_5, 7, 7)
wire _wdata_WIRE_3 : UInt<1>[8]
connect _wdata_WIRE_3[0], _wdata_T_6
connect _wdata_WIRE_3[1], _wdata_T_7
connect _wdata_WIRE_3[2], _wdata_T_8
connect _wdata_WIRE_3[3], _wdata_T_9
connect _wdata_WIRE_3[4], _wdata_T_10
connect _wdata_WIRE_3[5], _wdata_T_11
connect _wdata_WIRE_3[6], _wdata_T_12
connect _wdata_WIRE_3[7], _wdata_T_13
node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3)
node _wmask_T_2 = not(UInt<8>(0h0))
node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0])
node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2])
node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo)
node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4])
node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6])
node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo)
node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1)
node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3)
node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4)
node _T_20 = bits(wmask_1, 0, 0)
node _T_21 = bits(wmask_1, 1, 1)
node _T_22 = bits(wmask_1, 2, 2)
node _T_23 = bits(wmask_1, 3, 3)
node _T_24 = bits(wmask_1, 4, 4)
node _T_25 = bits(wmask_1, 5, 5)
node _T_26 = bits(wmask_1, 6, 6)
node _T_27 = bits(wmask_1, 7, 7)
node _T_28 = bits(widx_1, 7, 0)
write mport MPORT_1 = tage_u_8[_T_28], clock
when _T_20 :
connect MPORT_1[0], wdata_1[0]
when _T_21 :
connect MPORT_1[1], wdata_1[1]
when _T_22 :
connect MPORT_1[2], wdata_1[2]
when _T_23 :
connect MPORT_1[3], wdata_1[3]
when _T_24 :
connect MPORT_1[4], wdata_1[4]
when _T_25 :
connect MPORT_1[5], wdata_1[5]
when _T_26 :
connect MPORT_1[6], wdata_1[6]
when _T_27 :
connect MPORT_1[7], wdata_1[7]
reg wrbypass_tags : UInt<8>[2], clock
reg wrbypass_idxs : UInt<8>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _T_29 = or(io.update_mask[0], io.update_mask[1])
node _T_30 = or(_T_29, io.update_mask[2])
node _T_31 = or(_T_30, io.update_mask[3])
when _T_31 :
node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_32 :
wire _WIRE_10 : UInt<3>[4]
connect _WIRE_10[0], update_wdata[0].ctr
connect _WIRE_10[1], update_wdata[1].ctr
connect _WIRE_10[2], update_wdata[2].ctr
connect _WIRE_10[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_10
else :
wire _WIRE_11 : UInt<3>[4]
connect _WIRE_11[0], update_wdata[0].ctr
connect _WIRE_11[1], update_wdata[1].ctr
connect _WIRE_11[2], update_wdata[2].ctr
connect _WIRE_11[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_11
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_8( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f2_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14]
output io_f2_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14]
output io_f2_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14]
output io_f2_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire [47:0] _tage_table_8_R0_data; // @[tage.scala:90:27]
wire [7:0] _tage_u_8_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26]
wire [11:0] _wdata_WIRE_0 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_1 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_2 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_3 = 12'h0; // @[tage.scala:130:41]
wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34]
wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58]
wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34]
wire s2_req_rhits_0; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_1; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_2; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_3; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34]
wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [7:0] reset_idx; // @[tage.scala:73:26]
wire [8:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26]
wire [8:0] _reset_idx_T = _GEN + {8'h0, doing_reset}; // @[tage.scala:72:28, :74:26]
wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26]
wire [7:0] idx_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:149:35]
wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:149:35]
wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99]
wire [7:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12]
wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}]
wire wdata_1_0; // @[tage.scala:145:20]
wire wdata_1_1; // @[tage.scala:145:20]
wire wdata_1_2; // @[tage.scala:145:20]
wire wdata_1_3; // @[tage.scala:145:20]
wire wdata_1_4; // @[tage.scala:145:20]
wire wdata_1_5; // @[tage.scala:145:20]
wire wdata_1_6; // @[tage.scala:145:20]
wire wdata_1_7; // @[tage.scala:145:20]
wire s2_req_rus_0 = _tage_u_8_R0_data[0]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_1 = _tage_u_8_R0_data[1]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_2 = _tage_u_8_R0_data[2]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_3 = _tage_u_8_R0_data[3]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_4 = _tage_u_8_R0_data[4]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_5 = _tage_u_8_R0_data[5]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_6 = _tage_u_8_R0_data[6]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_7 = _tage_u_8_R0_data[7]; // @[tage.scala:89:27, :99:24]
wire [11:0] wdata_0; // @[tage.scala:130:20]
wire [11:0] wdata_1; // @[tage.scala:130:20]
wire [11:0] wdata_2; // @[tage.scala:130:20]
wire [11:0] wdata_3; // @[tage.scala:130:20]
reg [7:0] s2_tag; // @[tage.scala:96:29]
assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26]
wire s2_req_rtage_0_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_0_tag; // @[tage.scala:98:26]
wire s2_req_rtage_1_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_1_tag; // @[tage.scala:98:26]
wire s2_req_rtage_2_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_2_tag; // @[tage.scala:98:26]
wire s2_req_rtage_3_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_3_tag; // @[tage.scala:98:26]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29]
assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34]
reg [19:0] clear_u_ctr; // @[tage.scala:109:28]
wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85]
wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31]
wire _clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31, :114:31]
wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}]
wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}]
wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33]
wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109]
wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109]
wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109]
wire [7:0] idx_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:149:35]
wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:149:35]
wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}]
wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}]
wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26]
wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}]
wire wen = _wen_T_3; // @[tage.scala:121:{21,34}]
reg REG; // @[tage.scala:123:16]
assign s2_req_rtage_0_ctr = _tage_table_8_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_tag = _tage_table_8_R0_data[10:3]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_valid = _tage_table_8_R0_data[11]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_ctr = _tage_table_8_R0_data[14:12]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_tag = _tage_table_8_R0_data[22:15]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_valid = _tage_table_8_R0_data[23]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_ctr = _tage_table_8_R0_data[26:24]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_tag = _tage_table_8_R0_data[34:27]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_valid = _tage_table_8_R0_data[35]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_ctr = _tage_table_8_R0_data[38:36]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_tag = _tage_table_8_R0_data[46:39]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_valid = _tage_table_8_R0_data[47]; // @[tage.scala:90:27, :98:26, :126:49]
wire [7:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19]
wire [8:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}]
assign wdata_0 = doing_reset ? 12'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_1 = doing_reset ? 12'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_2 = doing_reset ? 12'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_3 = doing_reset ? 12'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}]
wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70]
wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70]
wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70]
wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}]
wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43]
wire _update_u_wen_T; // @[tage.scala:136:43]
assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43]
wire _wdata_T_4; // @[tage.scala:145:33]
assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33]
wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}]
wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}]
wire [8:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47]
wire [8:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}]
wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110]
wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110]
wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110]
wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}]
wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}]
wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}]
wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}]
wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}]
wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}]
wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}]
wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}]
assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}]
assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}]
assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}]
assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}]
assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}]
assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}]
assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}]
assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}]
wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106]
wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}]
wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}]
reg [7:0] wrbypass_tags_0; // @[tage.scala:154:29]
reg [7:0] wrbypass_tags_1; // @[tage.scala:154:29]
reg [7:0] wrbypass_idxs_0; // @[tage.scala:155:29]
reg [7:0] wrbypass_idxs_1; // @[tage.scala:155:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:156:29]
reg wrbypass_enq_idx; // @[tage.scala:157:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}]
wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 8'h0; // @[tage.scala:73:26]
clear_u_ctr <= 20'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39]
end
else // @[tage.scala:157:33, :180:38, :181:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29]
REG <= wen; // @[tage.scala:121:21, :123:16]
if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29]
if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29]
if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
end
else begin // @[tage.scala:156:29, :180:38, :181:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
always @(posedge)
tage_u_8_0 tage_u_8 ( // @[tage.scala:89:27]
.R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_u_8_R0_data),
.W0_addr (widx_1[7:0]), // @[tage.scala:144:19, :147:13]
.W0_en (update_u_wen), // @[tage.scala:136:30]
.W0_clk (clock),
.W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20]
.W0_mask (wmask_1) // @[tage.scala:146:20]
); // @[tage.scala:89:27]
tage_table_8_0 tage_table_8 ( // @[tage.scala:90:27]
.R0_addr (_rdata_WIRE), // @[tage.scala:122:99]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_table_8_R0_data),
.W0_addr (widx), // @[tage.scala:129:19]
.W0_en (wen), // @[tage.scala:121:21]
.W0_clk (clock),
.W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20]
.W0_mask (wmask) // @[tage.scala:131:20]
); // @[tage.scala:90:27]
assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i20_o2_a32d64s9k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_19 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_2.d.bits.corrupt
invalidate anonIn_2.d.bits.data
invalidate anonIn_2.d.bits.denied
invalidate anonIn_2.d.bits.sink
invalidate anonIn_2.d.bits.source
invalidate anonIn_2.d.bits.size
invalidate anonIn_2.d.bits.param
invalidate anonIn_2.d.bits.opcode
invalidate anonIn_2.d.valid
invalidate anonIn_2.d.ready
invalidate anonIn_2.a.bits.corrupt
invalidate anonIn_2.a.bits.data
invalidate anonIn_2.a.bits.mask
invalidate anonIn_2.a.bits.address
invalidate anonIn_2.a.bits.source
invalidate anonIn_2.a.bits.size
invalidate anonIn_2.a.bits.param
invalidate anonIn_2.a.bits.opcode
invalidate anonIn_2.a.valid
invalidate anonIn_2.a.ready
wire anonIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_3.d.bits.corrupt
invalidate anonIn_3.d.bits.data
invalidate anonIn_3.d.bits.denied
invalidate anonIn_3.d.bits.sink
invalidate anonIn_3.d.bits.source
invalidate anonIn_3.d.bits.size
invalidate anonIn_3.d.bits.param
invalidate anonIn_3.d.bits.opcode
invalidate anonIn_3.d.valid
invalidate anonIn_3.d.ready
invalidate anonIn_3.a.bits.corrupt
invalidate anonIn_3.a.bits.data
invalidate anonIn_3.a.bits.mask
invalidate anonIn_3.a.bits.address
invalidate anonIn_3.a.bits.source
invalidate anonIn_3.a.bits.size
invalidate anonIn_3.a.bits.param
invalidate anonIn_3.a.bits.opcode
invalidate anonIn_3.a.valid
invalidate anonIn_3.a.ready
wire anonIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_4.d.bits.corrupt
invalidate anonIn_4.d.bits.data
invalidate anonIn_4.d.bits.denied
invalidate anonIn_4.d.bits.sink
invalidate anonIn_4.d.bits.source
invalidate anonIn_4.d.bits.size
invalidate anonIn_4.d.bits.param
invalidate anonIn_4.d.bits.opcode
invalidate anonIn_4.d.valid
invalidate anonIn_4.d.ready
invalidate anonIn_4.a.bits.corrupt
invalidate anonIn_4.a.bits.data
invalidate anonIn_4.a.bits.mask
invalidate anonIn_4.a.bits.address
invalidate anonIn_4.a.bits.source
invalidate anonIn_4.a.bits.size
invalidate anonIn_4.a.bits.param
invalidate anonIn_4.a.bits.opcode
invalidate anonIn_4.a.valid
invalidate anonIn_4.a.ready
wire anonIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_5.d.bits.corrupt
invalidate anonIn_5.d.bits.data
invalidate anonIn_5.d.bits.denied
invalidate anonIn_5.d.bits.sink
invalidate anonIn_5.d.bits.source
invalidate anonIn_5.d.bits.size
invalidate anonIn_5.d.bits.param
invalidate anonIn_5.d.bits.opcode
invalidate anonIn_5.d.valid
invalidate anonIn_5.d.ready
invalidate anonIn_5.a.bits.corrupt
invalidate anonIn_5.a.bits.data
invalidate anonIn_5.a.bits.mask
invalidate anonIn_5.a.bits.address
invalidate anonIn_5.a.bits.source
invalidate anonIn_5.a.bits.size
invalidate anonIn_5.a.bits.param
invalidate anonIn_5.a.bits.opcode
invalidate anonIn_5.a.valid
invalidate anonIn_5.a.ready
wire anonIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_6.d.bits.corrupt
invalidate anonIn_6.d.bits.data
invalidate anonIn_6.d.bits.denied
invalidate anonIn_6.d.bits.sink
invalidate anonIn_6.d.bits.source
invalidate anonIn_6.d.bits.size
invalidate anonIn_6.d.bits.param
invalidate anonIn_6.d.bits.opcode
invalidate anonIn_6.d.valid
invalidate anonIn_6.d.ready
invalidate anonIn_6.a.bits.corrupt
invalidate anonIn_6.a.bits.data
invalidate anonIn_6.a.bits.mask
invalidate anonIn_6.a.bits.address
invalidate anonIn_6.a.bits.source
invalidate anonIn_6.a.bits.size
invalidate anonIn_6.a.bits.param
invalidate anonIn_6.a.bits.opcode
invalidate anonIn_6.a.valid
invalidate anonIn_6.a.ready
wire anonIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_7.d.bits.corrupt
invalidate anonIn_7.d.bits.data
invalidate anonIn_7.d.bits.denied
invalidate anonIn_7.d.bits.sink
invalidate anonIn_7.d.bits.source
invalidate anonIn_7.d.bits.size
invalidate anonIn_7.d.bits.param
invalidate anonIn_7.d.bits.opcode
invalidate anonIn_7.d.valid
invalidate anonIn_7.d.ready
invalidate anonIn_7.a.bits.corrupt
invalidate anonIn_7.a.bits.data
invalidate anonIn_7.a.bits.mask
invalidate anonIn_7.a.bits.address
invalidate anonIn_7.a.bits.source
invalidate anonIn_7.a.bits.size
invalidate anonIn_7.a.bits.param
invalidate anonIn_7.a.bits.opcode
invalidate anonIn_7.a.valid
invalidate anonIn_7.a.ready
wire anonIn_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_8.d.bits.corrupt
invalidate anonIn_8.d.bits.data
invalidate anonIn_8.d.bits.denied
invalidate anonIn_8.d.bits.sink
invalidate anonIn_8.d.bits.source
invalidate anonIn_8.d.bits.size
invalidate anonIn_8.d.bits.param
invalidate anonIn_8.d.bits.opcode
invalidate anonIn_8.d.valid
invalidate anonIn_8.d.ready
invalidate anonIn_8.a.bits.corrupt
invalidate anonIn_8.a.bits.data
invalidate anonIn_8.a.bits.mask
invalidate anonIn_8.a.bits.address
invalidate anonIn_8.a.bits.source
invalidate anonIn_8.a.bits.size
invalidate anonIn_8.a.bits.param
invalidate anonIn_8.a.bits.opcode
invalidate anonIn_8.a.valid
invalidate anonIn_8.a.ready
wire anonIn_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_9.d.bits.corrupt
invalidate anonIn_9.d.bits.data
invalidate anonIn_9.d.bits.denied
invalidate anonIn_9.d.bits.sink
invalidate anonIn_9.d.bits.source
invalidate anonIn_9.d.bits.size
invalidate anonIn_9.d.bits.param
invalidate anonIn_9.d.bits.opcode
invalidate anonIn_9.d.valid
invalidate anonIn_9.d.ready
invalidate anonIn_9.a.bits.corrupt
invalidate anonIn_9.a.bits.data
invalidate anonIn_9.a.bits.mask
invalidate anonIn_9.a.bits.address
invalidate anonIn_9.a.bits.source
invalidate anonIn_9.a.bits.size
invalidate anonIn_9.a.bits.param
invalidate anonIn_9.a.bits.opcode
invalidate anonIn_9.a.valid
invalidate anonIn_9.a.ready
wire anonIn_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_10.d.bits.corrupt
invalidate anonIn_10.d.bits.data
invalidate anonIn_10.d.bits.denied
invalidate anonIn_10.d.bits.sink
invalidate anonIn_10.d.bits.source
invalidate anonIn_10.d.bits.size
invalidate anonIn_10.d.bits.param
invalidate anonIn_10.d.bits.opcode
invalidate anonIn_10.d.valid
invalidate anonIn_10.d.ready
invalidate anonIn_10.a.bits.corrupt
invalidate anonIn_10.a.bits.data
invalidate anonIn_10.a.bits.mask
invalidate anonIn_10.a.bits.address
invalidate anonIn_10.a.bits.source
invalidate anonIn_10.a.bits.size
invalidate anonIn_10.a.bits.param
invalidate anonIn_10.a.bits.opcode
invalidate anonIn_10.a.valid
invalidate anonIn_10.a.ready
wire anonIn_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_11.d.bits.corrupt
invalidate anonIn_11.d.bits.data
invalidate anonIn_11.d.bits.denied
invalidate anonIn_11.d.bits.sink
invalidate anonIn_11.d.bits.source
invalidate anonIn_11.d.bits.size
invalidate anonIn_11.d.bits.param
invalidate anonIn_11.d.bits.opcode
invalidate anonIn_11.d.valid
invalidate anonIn_11.d.ready
invalidate anonIn_11.a.bits.corrupt
invalidate anonIn_11.a.bits.data
invalidate anonIn_11.a.bits.mask
invalidate anonIn_11.a.bits.address
invalidate anonIn_11.a.bits.source
invalidate anonIn_11.a.bits.size
invalidate anonIn_11.a.bits.param
invalidate anonIn_11.a.bits.opcode
invalidate anonIn_11.a.valid
invalidate anonIn_11.a.ready
wire anonIn_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_12.d.bits.corrupt
invalidate anonIn_12.d.bits.data
invalidate anonIn_12.d.bits.denied
invalidate anonIn_12.d.bits.sink
invalidate anonIn_12.d.bits.source
invalidate anonIn_12.d.bits.size
invalidate anonIn_12.d.bits.param
invalidate anonIn_12.d.bits.opcode
invalidate anonIn_12.d.valid
invalidate anonIn_12.d.ready
invalidate anonIn_12.a.bits.corrupt
invalidate anonIn_12.a.bits.data
invalidate anonIn_12.a.bits.mask
invalidate anonIn_12.a.bits.address
invalidate anonIn_12.a.bits.source
invalidate anonIn_12.a.bits.size
invalidate anonIn_12.a.bits.param
invalidate anonIn_12.a.bits.opcode
invalidate anonIn_12.a.valid
invalidate anonIn_12.a.ready
wire anonIn_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_13.d.bits.corrupt
invalidate anonIn_13.d.bits.data
invalidate anonIn_13.d.bits.denied
invalidate anonIn_13.d.bits.sink
invalidate anonIn_13.d.bits.source
invalidate anonIn_13.d.bits.size
invalidate anonIn_13.d.bits.param
invalidate anonIn_13.d.bits.opcode
invalidate anonIn_13.d.valid
invalidate anonIn_13.d.ready
invalidate anonIn_13.a.bits.corrupt
invalidate anonIn_13.a.bits.data
invalidate anonIn_13.a.bits.mask
invalidate anonIn_13.a.bits.address
invalidate anonIn_13.a.bits.source
invalidate anonIn_13.a.bits.size
invalidate anonIn_13.a.bits.param
invalidate anonIn_13.a.bits.opcode
invalidate anonIn_13.a.valid
invalidate anonIn_13.a.ready
wire anonIn_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_14.d.bits.corrupt
invalidate anonIn_14.d.bits.data
invalidate anonIn_14.d.bits.denied
invalidate anonIn_14.d.bits.sink
invalidate anonIn_14.d.bits.source
invalidate anonIn_14.d.bits.size
invalidate anonIn_14.d.bits.param
invalidate anonIn_14.d.bits.opcode
invalidate anonIn_14.d.valid
invalidate anonIn_14.d.ready
invalidate anonIn_14.a.bits.corrupt
invalidate anonIn_14.a.bits.data
invalidate anonIn_14.a.bits.mask
invalidate anonIn_14.a.bits.address
invalidate anonIn_14.a.bits.source
invalidate anonIn_14.a.bits.size
invalidate anonIn_14.a.bits.param
invalidate anonIn_14.a.bits.opcode
invalidate anonIn_14.a.valid
invalidate anonIn_14.a.ready
wire anonIn_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_15.d.bits.corrupt
invalidate anonIn_15.d.bits.data
invalidate anonIn_15.d.bits.denied
invalidate anonIn_15.d.bits.sink
invalidate anonIn_15.d.bits.source
invalidate anonIn_15.d.bits.size
invalidate anonIn_15.d.bits.param
invalidate anonIn_15.d.bits.opcode
invalidate anonIn_15.d.valid
invalidate anonIn_15.d.ready
invalidate anonIn_15.a.bits.corrupt
invalidate anonIn_15.a.bits.data
invalidate anonIn_15.a.bits.mask
invalidate anonIn_15.a.bits.address
invalidate anonIn_15.a.bits.source
invalidate anonIn_15.a.bits.size
invalidate anonIn_15.a.bits.param
invalidate anonIn_15.a.bits.opcode
invalidate anonIn_15.a.valid
invalidate anonIn_15.a.ready
wire anonIn_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_16.d.bits.corrupt
invalidate anonIn_16.d.bits.data
invalidate anonIn_16.d.bits.denied
invalidate anonIn_16.d.bits.sink
invalidate anonIn_16.d.bits.source
invalidate anonIn_16.d.bits.size
invalidate anonIn_16.d.bits.param
invalidate anonIn_16.d.bits.opcode
invalidate anonIn_16.d.valid
invalidate anonIn_16.d.ready
invalidate anonIn_16.a.bits.corrupt
invalidate anonIn_16.a.bits.data
invalidate anonIn_16.a.bits.mask
invalidate anonIn_16.a.bits.address
invalidate anonIn_16.a.bits.source
invalidate anonIn_16.a.bits.size
invalidate anonIn_16.a.bits.param
invalidate anonIn_16.a.bits.opcode
invalidate anonIn_16.a.valid
invalidate anonIn_16.a.ready
wire anonIn_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_17.d.bits.corrupt
invalidate anonIn_17.d.bits.data
invalidate anonIn_17.d.bits.denied
invalidate anonIn_17.d.bits.sink
invalidate anonIn_17.d.bits.source
invalidate anonIn_17.d.bits.size
invalidate anonIn_17.d.bits.param
invalidate anonIn_17.d.bits.opcode
invalidate anonIn_17.d.valid
invalidate anonIn_17.d.ready
invalidate anonIn_17.a.bits.corrupt
invalidate anonIn_17.a.bits.data
invalidate anonIn_17.a.bits.mask
invalidate anonIn_17.a.bits.address
invalidate anonIn_17.a.bits.source
invalidate anonIn_17.a.bits.size
invalidate anonIn_17.a.bits.param
invalidate anonIn_17.a.bits.opcode
invalidate anonIn_17.a.valid
invalidate anonIn_17.a.ready
wire anonIn_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_18.d.bits.corrupt
invalidate anonIn_18.d.bits.data
invalidate anonIn_18.d.bits.denied
invalidate anonIn_18.d.bits.sink
invalidate anonIn_18.d.bits.source
invalidate anonIn_18.d.bits.size
invalidate anonIn_18.d.bits.param
invalidate anonIn_18.d.bits.opcode
invalidate anonIn_18.d.valid
invalidate anonIn_18.d.ready
invalidate anonIn_18.a.bits.corrupt
invalidate anonIn_18.a.bits.data
invalidate anonIn_18.a.bits.mask
invalidate anonIn_18.a.bits.address
invalidate anonIn_18.a.bits.source
invalidate anonIn_18.a.bits.size
invalidate anonIn_18.a.bits.param
invalidate anonIn_18.a.bits.opcode
invalidate anonIn_18.a.valid
invalidate anonIn_18.a.ready
wire anonIn_19 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn_19.e.bits.sink
invalidate anonIn_19.e.valid
invalidate anonIn_19.e.ready
invalidate anonIn_19.d.bits.corrupt
invalidate anonIn_19.d.bits.data
invalidate anonIn_19.d.bits.denied
invalidate anonIn_19.d.bits.sink
invalidate anonIn_19.d.bits.source
invalidate anonIn_19.d.bits.size
invalidate anonIn_19.d.bits.param
invalidate anonIn_19.d.bits.opcode
invalidate anonIn_19.d.valid
invalidate anonIn_19.d.ready
invalidate anonIn_19.c.bits.corrupt
invalidate anonIn_19.c.bits.data
invalidate anonIn_19.c.bits.address
invalidate anonIn_19.c.bits.source
invalidate anonIn_19.c.bits.size
invalidate anonIn_19.c.bits.param
invalidate anonIn_19.c.bits.opcode
invalidate anonIn_19.c.valid
invalidate anonIn_19.c.ready
invalidate anonIn_19.b.bits.corrupt
invalidate anonIn_19.b.bits.data
invalidate anonIn_19.b.bits.mask
invalidate anonIn_19.b.bits.address
invalidate anonIn_19.b.bits.source
invalidate anonIn_19.b.bits.size
invalidate anonIn_19.b.bits.param
invalidate anonIn_19.b.bits.opcode
invalidate anonIn_19.b.valid
invalidate anonIn_19.b.ready
invalidate anonIn_19.a.bits.corrupt
invalidate anonIn_19.a.bits.data
invalidate anonIn_19.a.bits.mask
invalidate anonIn_19.a.bits.address
invalidate anonIn_19.a.bits.source
invalidate anonIn_19.a.bits.size
invalidate anonIn_19.a.bits.param
invalidate anonIn_19.a.bits.opcode
invalidate anonIn_19.a.valid
invalidate anonIn_19.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
inst monitor_2 of TLMonitor_2
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, anonIn_2.d.valid
connect monitor_2.io.in.d.ready, anonIn_2.d.ready
connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, anonIn_2.a.valid
connect monitor_2.io.in.a.ready, anonIn_2.a.ready
inst monitor_3 of TLMonitor_3
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.d.bits.corrupt, anonIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, anonIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, anonIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, anonIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, anonIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, anonIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, anonIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, anonIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, anonIn_3.d.valid
connect monitor_3.io.in.d.ready, anonIn_3.d.ready
connect monitor_3.io.in.a.bits.corrupt, anonIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, anonIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, anonIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, anonIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, anonIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, anonIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, anonIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, anonIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, anonIn_3.a.valid
connect monitor_3.io.in.a.ready, anonIn_3.a.ready
inst monitor_4 of TLMonitor_4
connect monitor_4.clock, clock
connect monitor_4.reset, reset
connect monitor_4.io.in.d.bits.corrupt, anonIn_4.d.bits.corrupt
connect monitor_4.io.in.d.bits.data, anonIn_4.d.bits.data
connect monitor_4.io.in.d.bits.denied, anonIn_4.d.bits.denied
connect monitor_4.io.in.d.bits.sink, anonIn_4.d.bits.sink
connect monitor_4.io.in.d.bits.source, anonIn_4.d.bits.source
connect monitor_4.io.in.d.bits.size, anonIn_4.d.bits.size
connect monitor_4.io.in.d.bits.param, anonIn_4.d.bits.param
connect monitor_4.io.in.d.bits.opcode, anonIn_4.d.bits.opcode
connect monitor_4.io.in.d.valid, anonIn_4.d.valid
connect monitor_4.io.in.d.ready, anonIn_4.d.ready
connect monitor_4.io.in.a.bits.corrupt, anonIn_4.a.bits.corrupt
connect monitor_4.io.in.a.bits.data, anonIn_4.a.bits.data
connect monitor_4.io.in.a.bits.mask, anonIn_4.a.bits.mask
connect monitor_4.io.in.a.bits.address, anonIn_4.a.bits.address
connect monitor_4.io.in.a.bits.source, anonIn_4.a.bits.source
connect monitor_4.io.in.a.bits.size, anonIn_4.a.bits.size
connect monitor_4.io.in.a.bits.param, anonIn_4.a.bits.param
connect monitor_4.io.in.a.bits.opcode, anonIn_4.a.bits.opcode
connect monitor_4.io.in.a.valid, anonIn_4.a.valid
connect monitor_4.io.in.a.ready, anonIn_4.a.ready
inst monitor_5 of TLMonitor_5
connect monitor_5.clock, clock
connect monitor_5.reset, reset
connect monitor_5.io.in.d.bits.corrupt, anonIn_5.d.bits.corrupt
connect monitor_5.io.in.d.bits.data, anonIn_5.d.bits.data
connect monitor_5.io.in.d.bits.denied, anonIn_5.d.bits.denied
connect monitor_5.io.in.d.bits.sink, anonIn_5.d.bits.sink
connect monitor_5.io.in.d.bits.source, anonIn_5.d.bits.source
connect monitor_5.io.in.d.bits.size, anonIn_5.d.bits.size
connect monitor_5.io.in.d.bits.param, anonIn_5.d.bits.param
connect monitor_5.io.in.d.bits.opcode, anonIn_5.d.bits.opcode
connect monitor_5.io.in.d.valid, anonIn_5.d.valid
connect monitor_5.io.in.d.ready, anonIn_5.d.ready
connect monitor_5.io.in.a.bits.corrupt, anonIn_5.a.bits.corrupt
connect monitor_5.io.in.a.bits.data, anonIn_5.a.bits.data
connect monitor_5.io.in.a.bits.mask, anonIn_5.a.bits.mask
connect monitor_5.io.in.a.bits.address, anonIn_5.a.bits.address
connect monitor_5.io.in.a.bits.source, anonIn_5.a.bits.source
connect monitor_5.io.in.a.bits.size, anonIn_5.a.bits.size
connect monitor_5.io.in.a.bits.param, anonIn_5.a.bits.param
connect monitor_5.io.in.a.bits.opcode, anonIn_5.a.bits.opcode
connect monitor_5.io.in.a.valid, anonIn_5.a.valid
connect monitor_5.io.in.a.ready, anonIn_5.a.ready
inst monitor_6 of TLMonitor_6
connect monitor_6.clock, clock
connect monitor_6.reset, reset
connect monitor_6.io.in.d.bits.corrupt, anonIn_6.d.bits.corrupt
connect monitor_6.io.in.d.bits.data, anonIn_6.d.bits.data
connect monitor_6.io.in.d.bits.denied, anonIn_6.d.bits.denied
connect monitor_6.io.in.d.bits.sink, anonIn_6.d.bits.sink
connect monitor_6.io.in.d.bits.source, anonIn_6.d.bits.source
connect monitor_6.io.in.d.bits.size, anonIn_6.d.bits.size
connect monitor_6.io.in.d.bits.param, anonIn_6.d.bits.param
connect monitor_6.io.in.d.bits.opcode, anonIn_6.d.bits.opcode
connect monitor_6.io.in.d.valid, anonIn_6.d.valid
connect monitor_6.io.in.d.ready, anonIn_6.d.ready
connect monitor_6.io.in.a.bits.corrupt, anonIn_6.a.bits.corrupt
connect monitor_6.io.in.a.bits.data, anonIn_6.a.bits.data
connect monitor_6.io.in.a.bits.mask, anonIn_6.a.bits.mask
connect monitor_6.io.in.a.bits.address, anonIn_6.a.bits.address
connect monitor_6.io.in.a.bits.source, anonIn_6.a.bits.source
connect monitor_6.io.in.a.bits.size, anonIn_6.a.bits.size
connect monitor_6.io.in.a.bits.param, anonIn_6.a.bits.param
connect monitor_6.io.in.a.bits.opcode, anonIn_6.a.bits.opcode
connect monitor_6.io.in.a.valid, anonIn_6.a.valid
connect monitor_6.io.in.a.ready, anonIn_6.a.ready
inst monitor_7 of TLMonitor_7
connect monitor_7.clock, clock
connect monitor_7.reset, reset
connect monitor_7.io.in.d.bits.corrupt, anonIn_7.d.bits.corrupt
connect monitor_7.io.in.d.bits.data, anonIn_7.d.bits.data
connect monitor_7.io.in.d.bits.denied, anonIn_7.d.bits.denied
connect monitor_7.io.in.d.bits.sink, anonIn_7.d.bits.sink
connect monitor_7.io.in.d.bits.source, anonIn_7.d.bits.source
connect monitor_7.io.in.d.bits.size, anonIn_7.d.bits.size
connect monitor_7.io.in.d.bits.param, anonIn_7.d.bits.param
connect monitor_7.io.in.d.bits.opcode, anonIn_7.d.bits.opcode
connect monitor_7.io.in.d.valid, anonIn_7.d.valid
connect monitor_7.io.in.d.ready, anonIn_7.d.ready
connect monitor_7.io.in.a.bits.corrupt, anonIn_7.a.bits.corrupt
connect monitor_7.io.in.a.bits.data, anonIn_7.a.bits.data
connect monitor_7.io.in.a.bits.mask, anonIn_7.a.bits.mask
connect monitor_7.io.in.a.bits.address, anonIn_7.a.bits.address
connect monitor_7.io.in.a.bits.source, anonIn_7.a.bits.source
connect monitor_7.io.in.a.bits.size, anonIn_7.a.bits.size
connect monitor_7.io.in.a.bits.param, anonIn_7.a.bits.param
connect monitor_7.io.in.a.bits.opcode, anonIn_7.a.bits.opcode
connect monitor_7.io.in.a.valid, anonIn_7.a.valid
connect monitor_7.io.in.a.ready, anonIn_7.a.ready
inst monitor_8 of TLMonitor_8
connect monitor_8.clock, clock
connect monitor_8.reset, reset
connect monitor_8.io.in.d.bits.corrupt, anonIn_8.d.bits.corrupt
connect monitor_8.io.in.d.bits.data, anonIn_8.d.bits.data
connect monitor_8.io.in.d.bits.denied, anonIn_8.d.bits.denied
connect monitor_8.io.in.d.bits.sink, anonIn_8.d.bits.sink
connect monitor_8.io.in.d.bits.source, anonIn_8.d.bits.source
connect monitor_8.io.in.d.bits.size, anonIn_8.d.bits.size
connect monitor_8.io.in.d.bits.param, anonIn_8.d.bits.param
connect monitor_8.io.in.d.bits.opcode, anonIn_8.d.bits.opcode
connect monitor_8.io.in.d.valid, anonIn_8.d.valid
connect monitor_8.io.in.d.ready, anonIn_8.d.ready
connect monitor_8.io.in.a.bits.corrupt, anonIn_8.a.bits.corrupt
connect monitor_8.io.in.a.bits.data, anonIn_8.a.bits.data
connect monitor_8.io.in.a.bits.mask, anonIn_8.a.bits.mask
connect monitor_8.io.in.a.bits.address, anonIn_8.a.bits.address
connect monitor_8.io.in.a.bits.source, anonIn_8.a.bits.source
connect monitor_8.io.in.a.bits.size, anonIn_8.a.bits.size
connect monitor_8.io.in.a.bits.param, anonIn_8.a.bits.param
connect monitor_8.io.in.a.bits.opcode, anonIn_8.a.bits.opcode
connect monitor_8.io.in.a.valid, anonIn_8.a.valid
connect monitor_8.io.in.a.ready, anonIn_8.a.ready
inst monitor_9 of TLMonitor_9
connect monitor_9.clock, clock
connect monitor_9.reset, reset
connect monitor_9.io.in.d.bits.corrupt, anonIn_9.d.bits.corrupt
connect monitor_9.io.in.d.bits.data, anonIn_9.d.bits.data
connect monitor_9.io.in.d.bits.denied, anonIn_9.d.bits.denied
connect monitor_9.io.in.d.bits.sink, anonIn_9.d.bits.sink
connect monitor_9.io.in.d.bits.source, anonIn_9.d.bits.source
connect monitor_9.io.in.d.bits.size, anonIn_9.d.bits.size
connect monitor_9.io.in.d.bits.param, anonIn_9.d.bits.param
connect monitor_9.io.in.d.bits.opcode, anonIn_9.d.bits.opcode
connect monitor_9.io.in.d.valid, anonIn_9.d.valid
connect monitor_9.io.in.d.ready, anonIn_9.d.ready
connect monitor_9.io.in.a.bits.corrupt, anonIn_9.a.bits.corrupt
connect monitor_9.io.in.a.bits.data, anonIn_9.a.bits.data
connect monitor_9.io.in.a.bits.mask, anonIn_9.a.bits.mask
connect monitor_9.io.in.a.bits.address, anonIn_9.a.bits.address
connect monitor_9.io.in.a.bits.source, anonIn_9.a.bits.source
connect monitor_9.io.in.a.bits.size, anonIn_9.a.bits.size
connect monitor_9.io.in.a.bits.param, anonIn_9.a.bits.param
connect monitor_9.io.in.a.bits.opcode, anonIn_9.a.bits.opcode
connect monitor_9.io.in.a.valid, anonIn_9.a.valid
connect monitor_9.io.in.a.ready, anonIn_9.a.ready
inst monitor_10 of TLMonitor_10
connect monitor_10.clock, clock
connect monitor_10.reset, reset
connect monitor_10.io.in.d.bits.corrupt, anonIn_10.d.bits.corrupt
connect monitor_10.io.in.d.bits.data, anonIn_10.d.bits.data
connect monitor_10.io.in.d.bits.denied, anonIn_10.d.bits.denied
connect monitor_10.io.in.d.bits.sink, anonIn_10.d.bits.sink
connect monitor_10.io.in.d.bits.source, anonIn_10.d.bits.source
connect monitor_10.io.in.d.bits.size, anonIn_10.d.bits.size
connect monitor_10.io.in.d.bits.param, anonIn_10.d.bits.param
connect monitor_10.io.in.d.bits.opcode, anonIn_10.d.bits.opcode
connect monitor_10.io.in.d.valid, anonIn_10.d.valid
connect monitor_10.io.in.d.ready, anonIn_10.d.ready
connect monitor_10.io.in.a.bits.corrupt, anonIn_10.a.bits.corrupt
connect monitor_10.io.in.a.bits.data, anonIn_10.a.bits.data
connect monitor_10.io.in.a.bits.mask, anonIn_10.a.bits.mask
connect monitor_10.io.in.a.bits.address, anonIn_10.a.bits.address
connect monitor_10.io.in.a.bits.source, anonIn_10.a.bits.source
connect monitor_10.io.in.a.bits.size, anonIn_10.a.bits.size
connect monitor_10.io.in.a.bits.param, anonIn_10.a.bits.param
connect monitor_10.io.in.a.bits.opcode, anonIn_10.a.bits.opcode
connect monitor_10.io.in.a.valid, anonIn_10.a.valid
connect monitor_10.io.in.a.ready, anonIn_10.a.ready
inst monitor_11 of TLMonitor_11
connect monitor_11.clock, clock
connect monitor_11.reset, reset
connect monitor_11.io.in.d.bits.corrupt, anonIn_11.d.bits.corrupt
connect monitor_11.io.in.d.bits.data, anonIn_11.d.bits.data
connect monitor_11.io.in.d.bits.denied, anonIn_11.d.bits.denied
connect monitor_11.io.in.d.bits.sink, anonIn_11.d.bits.sink
connect monitor_11.io.in.d.bits.source, anonIn_11.d.bits.source
connect monitor_11.io.in.d.bits.size, anonIn_11.d.bits.size
connect monitor_11.io.in.d.bits.param, anonIn_11.d.bits.param
connect monitor_11.io.in.d.bits.opcode, anonIn_11.d.bits.opcode
connect monitor_11.io.in.d.valid, anonIn_11.d.valid
connect monitor_11.io.in.d.ready, anonIn_11.d.ready
connect monitor_11.io.in.a.bits.corrupt, anonIn_11.a.bits.corrupt
connect monitor_11.io.in.a.bits.data, anonIn_11.a.bits.data
connect monitor_11.io.in.a.bits.mask, anonIn_11.a.bits.mask
connect monitor_11.io.in.a.bits.address, anonIn_11.a.bits.address
connect monitor_11.io.in.a.bits.source, anonIn_11.a.bits.source
connect monitor_11.io.in.a.bits.size, anonIn_11.a.bits.size
connect monitor_11.io.in.a.bits.param, anonIn_11.a.bits.param
connect monitor_11.io.in.a.bits.opcode, anonIn_11.a.bits.opcode
connect monitor_11.io.in.a.valid, anonIn_11.a.valid
connect monitor_11.io.in.a.ready, anonIn_11.a.ready
inst monitor_12 of TLMonitor_12
connect monitor_12.clock, clock
connect monitor_12.reset, reset
connect monitor_12.io.in.d.bits.corrupt, anonIn_12.d.bits.corrupt
connect monitor_12.io.in.d.bits.data, anonIn_12.d.bits.data
connect monitor_12.io.in.d.bits.denied, anonIn_12.d.bits.denied
connect monitor_12.io.in.d.bits.sink, anonIn_12.d.bits.sink
connect monitor_12.io.in.d.bits.source, anonIn_12.d.bits.source
connect monitor_12.io.in.d.bits.size, anonIn_12.d.bits.size
connect monitor_12.io.in.d.bits.param, anonIn_12.d.bits.param
connect monitor_12.io.in.d.bits.opcode, anonIn_12.d.bits.opcode
connect monitor_12.io.in.d.valid, anonIn_12.d.valid
connect monitor_12.io.in.d.ready, anonIn_12.d.ready
connect monitor_12.io.in.a.bits.corrupt, anonIn_12.a.bits.corrupt
connect monitor_12.io.in.a.bits.data, anonIn_12.a.bits.data
connect monitor_12.io.in.a.bits.mask, anonIn_12.a.bits.mask
connect monitor_12.io.in.a.bits.address, anonIn_12.a.bits.address
connect monitor_12.io.in.a.bits.source, anonIn_12.a.bits.source
connect monitor_12.io.in.a.bits.size, anonIn_12.a.bits.size
connect monitor_12.io.in.a.bits.param, anonIn_12.a.bits.param
connect monitor_12.io.in.a.bits.opcode, anonIn_12.a.bits.opcode
connect monitor_12.io.in.a.valid, anonIn_12.a.valid
connect monitor_12.io.in.a.ready, anonIn_12.a.ready
inst monitor_13 of TLMonitor_13
connect monitor_13.clock, clock
connect monitor_13.reset, reset
connect monitor_13.io.in.d.bits.corrupt, anonIn_13.d.bits.corrupt
connect monitor_13.io.in.d.bits.data, anonIn_13.d.bits.data
connect monitor_13.io.in.d.bits.denied, anonIn_13.d.bits.denied
connect monitor_13.io.in.d.bits.sink, anonIn_13.d.bits.sink
connect monitor_13.io.in.d.bits.source, anonIn_13.d.bits.source
connect monitor_13.io.in.d.bits.size, anonIn_13.d.bits.size
connect monitor_13.io.in.d.bits.param, anonIn_13.d.bits.param
connect monitor_13.io.in.d.bits.opcode, anonIn_13.d.bits.opcode
connect monitor_13.io.in.d.valid, anonIn_13.d.valid
connect monitor_13.io.in.d.ready, anonIn_13.d.ready
connect monitor_13.io.in.a.bits.corrupt, anonIn_13.a.bits.corrupt
connect monitor_13.io.in.a.bits.data, anonIn_13.a.bits.data
connect monitor_13.io.in.a.bits.mask, anonIn_13.a.bits.mask
connect monitor_13.io.in.a.bits.address, anonIn_13.a.bits.address
connect monitor_13.io.in.a.bits.source, anonIn_13.a.bits.source
connect monitor_13.io.in.a.bits.size, anonIn_13.a.bits.size
connect monitor_13.io.in.a.bits.param, anonIn_13.a.bits.param
connect monitor_13.io.in.a.bits.opcode, anonIn_13.a.bits.opcode
connect monitor_13.io.in.a.valid, anonIn_13.a.valid
connect monitor_13.io.in.a.ready, anonIn_13.a.ready
inst monitor_14 of TLMonitor_14
connect monitor_14.clock, clock
connect monitor_14.reset, reset
connect monitor_14.io.in.d.bits.corrupt, anonIn_14.d.bits.corrupt
connect monitor_14.io.in.d.bits.data, anonIn_14.d.bits.data
connect monitor_14.io.in.d.bits.denied, anonIn_14.d.bits.denied
connect monitor_14.io.in.d.bits.sink, anonIn_14.d.bits.sink
connect monitor_14.io.in.d.bits.source, anonIn_14.d.bits.source
connect monitor_14.io.in.d.bits.size, anonIn_14.d.bits.size
connect monitor_14.io.in.d.bits.param, anonIn_14.d.bits.param
connect monitor_14.io.in.d.bits.opcode, anonIn_14.d.bits.opcode
connect monitor_14.io.in.d.valid, anonIn_14.d.valid
connect monitor_14.io.in.d.ready, anonIn_14.d.ready
connect monitor_14.io.in.a.bits.corrupt, anonIn_14.a.bits.corrupt
connect monitor_14.io.in.a.bits.data, anonIn_14.a.bits.data
connect monitor_14.io.in.a.bits.mask, anonIn_14.a.bits.mask
connect monitor_14.io.in.a.bits.address, anonIn_14.a.bits.address
connect monitor_14.io.in.a.bits.source, anonIn_14.a.bits.source
connect monitor_14.io.in.a.bits.size, anonIn_14.a.bits.size
connect monitor_14.io.in.a.bits.param, anonIn_14.a.bits.param
connect monitor_14.io.in.a.bits.opcode, anonIn_14.a.bits.opcode
connect monitor_14.io.in.a.valid, anonIn_14.a.valid
connect monitor_14.io.in.a.ready, anonIn_14.a.ready
inst monitor_15 of TLMonitor_15
connect monitor_15.clock, clock
connect monitor_15.reset, reset
connect monitor_15.io.in.d.bits.corrupt, anonIn_15.d.bits.corrupt
connect monitor_15.io.in.d.bits.data, anonIn_15.d.bits.data
connect monitor_15.io.in.d.bits.denied, anonIn_15.d.bits.denied
connect monitor_15.io.in.d.bits.sink, anonIn_15.d.bits.sink
connect monitor_15.io.in.d.bits.source, anonIn_15.d.bits.source
connect monitor_15.io.in.d.bits.size, anonIn_15.d.bits.size
connect monitor_15.io.in.d.bits.param, anonIn_15.d.bits.param
connect monitor_15.io.in.d.bits.opcode, anonIn_15.d.bits.opcode
connect monitor_15.io.in.d.valid, anonIn_15.d.valid
connect monitor_15.io.in.d.ready, anonIn_15.d.ready
connect monitor_15.io.in.a.bits.corrupt, anonIn_15.a.bits.corrupt
connect monitor_15.io.in.a.bits.data, anonIn_15.a.bits.data
connect monitor_15.io.in.a.bits.mask, anonIn_15.a.bits.mask
connect monitor_15.io.in.a.bits.address, anonIn_15.a.bits.address
connect monitor_15.io.in.a.bits.source, anonIn_15.a.bits.source
connect monitor_15.io.in.a.bits.size, anonIn_15.a.bits.size
connect monitor_15.io.in.a.bits.param, anonIn_15.a.bits.param
connect monitor_15.io.in.a.bits.opcode, anonIn_15.a.bits.opcode
connect monitor_15.io.in.a.valid, anonIn_15.a.valid
connect monitor_15.io.in.a.ready, anonIn_15.a.ready
inst monitor_16 of TLMonitor_16
connect monitor_16.clock, clock
connect monitor_16.reset, reset
connect monitor_16.io.in.d.bits.corrupt, anonIn_16.d.bits.corrupt
connect monitor_16.io.in.d.bits.data, anonIn_16.d.bits.data
connect monitor_16.io.in.d.bits.denied, anonIn_16.d.bits.denied
connect monitor_16.io.in.d.bits.sink, anonIn_16.d.bits.sink
connect monitor_16.io.in.d.bits.source, anonIn_16.d.bits.source
connect monitor_16.io.in.d.bits.size, anonIn_16.d.bits.size
connect monitor_16.io.in.d.bits.param, anonIn_16.d.bits.param
connect monitor_16.io.in.d.bits.opcode, anonIn_16.d.bits.opcode
connect monitor_16.io.in.d.valid, anonIn_16.d.valid
connect monitor_16.io.in.d.ready, anonIn_16.d.ready
connect monitor_16.io.in.a.bits.corrupt, anonIn_16.a.bits.corrupt
connect monitor_16.io.in.a.bits.data, anonIn_16.a.bits.data
connect monitor_16.io.in.a.bits.mask, anonIn_16.a.bits.mask
connect monitor_16.io.in.a.bits.address, anonIn_16.a.bits.address
connect monitor_16.io.in.a.bits.source, anonIn_16.a.bits.source
connect monitor_16.io.in.a.bits.size, anonIn_16.a.bits.size
connect monitor_16.io.in.a.bits.param, anonIn_16.a.bits.param
connect monitor_16.io.in.a.bits.opcode, anonIn_16.a.bits.opcode
connect monitor_16.io.in.a.valid, anonIn_16.a.valid
connect monitor_16.io.in.a.ready, anonIn_16.a.ready
inst monitor_17 of TLMonitor_17
connect monitor_17.clock, clock
connect monitor_17.reset, reset
connect monitor_17.io.in.d.bits.corrupt, anonIn_17.d.bits.corrupt
connect monitor_17.io.in.d.bits.data, anonIn_17.d.bits.data
connect monitor_17.io.in.d.bits.denied, anonIn_17.d.bits.denied
connect monitor_17.io.in.d.bits.sink, anonIn_17.d.bits.sink
connect monitor_17.io.in.d.bits.source, anonIn_17.d.bits.source
connect monitor_17.io.in.d.bits.size, anonIn_17.d.bits.size
connect monitor_17.io.in.d.bits.param, anonIn_17.d.bits.param
connect monitor_17.io.in.d.bits.opcode, anonIn_17.d.bits.opcode
connect monitor_17.io.in.d.valid, anonIn_17.d.valid
connect monitor_17.io.in.d.ready, anonIn_17.d.ready
connect monitor_17.io.in.a.bits.corrupt, anonIn_17.a.bits.corrupt
connect monitor_17.io.in.a.bits.data, anonIn_17.a.bits.data
connect monitor_17.io.in.a.bits.mask, anonIn_17.a.bits.mask
connect monitor_17.io.in.a.bits.address, anonIn_17.a.bits.address
connect monitor_17.io.in.a.bits.source, anonIn_17.a.bits.source
connect monitor_17.io.in.a.bits.size, anonIn_17.a.bits.size
connect monitor_17.io.in.a.bits.param, anonIn_17.a.bits.param
connect monitor_17.io.in.a.bits.opcode, anonIn_17.a.bits.opcode
connect monitor_17.io.in.a.valid, anonIn_17.a.valid
connect monitor_17.io.in.a.ready, anonIn_17.a.ready
inst monitor_18 of TLMonitor_18
connect monitor_18.clock, clock
connect monitor_18.reset, reset
connect monitor_18.io.in.d.bits.corrupt, anonIn_18.d.bits.corrupt
connect monitor_18.io.in.d.bits.data, anonIn_18.d.bits.data
connect monitor_18.io.in.d.bits.denied, anonIn_18.d.bits.denied
connect monitor_18.io.in.d.bits.sink, anonIn_18.d.bits.sink
connect monitor_18.io.in.d.bits.source, anonIn_18.d.bits.source
connect monitor_18.io.in.d.bits.size, anonIn_18.d.bits.size
connect monitor_18.io.in.d.bits.param, anonIn_18.d.bits.param
connect monitor_18.io.in.d.bits.opcode, anonIn_18.d.bits.opcode
connect monitor_18.io.in.d.valid, anonIn_18.d.valid
connect monitor_18.io.in.d.ready, anonIn_18.d.ready
connect monitor_18.io.in.a.bits.corrupt, anonIn_18.a.bits.corrupt
connect monitor_18.io.in.a.bits.data, anonIn_18.a.bits.data
connect monitor_18.io.in.a.bits.mask, anonIn_18.a.bits.mask
connect monitor_18.io.in.a.bits.address, anonIn_18.a.bits.address
connect monitor_18.io.in.a.bits.source, anonIn_18.a.bits.source
connect monitor_18.io.in.a.bits.size, anonIn_18.a.bits.size
connect monitor_18.io.in.a.bits.param, anonIn_18.a.bits.param
connect monitor_18.io.in.a.bits.opcode, anonIn_18.a.bits.opcode
connect monitor_18.io.in.a.valid, anonIn_18.a.valid
connect monitor_18.io.in.a.ready, anonIn_18.a.ready
inst monitor_19 of TLMonitor_19
connect monitor_19.clock, clock
connect monitor_19.reset, reset
connect monitor_19.io.in.e.bits.sink, anonIn_19.e.bits.sink
connect monitor_19.io.in.e.valid, anonIn_19.e.valid
connect monitor_19.io.in.e.ready, anonIn_19.e.ready
connect monitor_19.io.in.d.bits.corrupt, anonIn_19.d.bits.corrupt
connect monitor_19.io.in.d.bits.data, anonIn_19.d.bits.data
connect monitor_19.io.in.d.bits.denied, anonIn_19.d.bits.denied
connect monitor_19.io.in.d.bits.sink, anonIn_19.d.bits.sink
connect monitor_19.io.in.d.bits.source, anonIn_19.d.bits.source
connect monitor_19.io.in.d.bits.size, anonIn_19.d.bits.size
connect monitor_19.io.in.d.bits.param, anonIn_19.d.bits.param
connect monitor_19.io.in.d.bits.opcode, anonIn_19.d.bits.opcode
connect monitor_19.io.in.d.valid, anonIn_19.d.valid
connect monitor_19.io.in.d.ready, anonIn_19.d.ready
connect monitor_19.io.in.c.bits.corrupt, anonIn_19.c.bits.corrupt
connect monitor_19.io.in.c.bits.data, anonIn_19.c.bits.data
connect monitor_19.io.in.c.bits.address, anonIn_19.c.bits.address
connect monitor_19.io.in.c.bits.source, anonIn_19.c.bits.source
connect monitor_19.io.in.c.bits.size, anonIn_19.c.bits.size
connect monitor_19.io.in.c.bits.param, anonIn_19.c.bits.param
connect monitor_19.io.in.c.bits.opcode, anonIn_19.c.bits.opcode
connect monitor_19.io.in.c.valid, anonIn_19.c.valid
connect monitor_19.io.in.c.ready, anonIn_19.c.ready
connect monitor_19.io.in.b.bits.corrupt, anonIn_19.b.bits.corrupt
connect monitor_19.io.in.b.bits.data, anonIn_19.b.bits.data
connect monitor_19.io.in.b.bits.mask, anonIn_19.b.bits.mask
connect monitor_19.io.in.b.bits.address, anonIn_19.b.bits.address
connect monitor_19.io.in.b.bits.source, anonIn_19.b.bits.source
connect monitor_19.io.in.b.bits.size, anonIn_19.b.bits.size
connect monitor_19.io.in.b.bits.param, anonIn_19.b.bits.param
connect monitor_19.io.in.b.bits.opcode, anonIn_19.b.bits.opcode
connect monitor_19.io.in.b.valid, anonIn_19.b.valid
connect monitor_19.io.in.b.ready, anonIn_19.b.ready
connect monitor_19.io.in.a.bits.corrupt, anonIn_19.a.bits.corrupt
connect monitor_19.io.in.a.bits.data, anonIn_19.a.bits.data
connect monitor_19.io.in.a.bits.mask, anonIn_19.a.bits.mask
connect monitor_19.io.in.a.bits.address, anonIn_19.a.bits.address
connect monitor_19.io.in.a.bits.source, anonIn_19.a.bits.source
connect monitor_19.io.in.a.bits.size, anonIn_19.a.bits.size
connect monitor_19.io.in.a.bits.param, anonIn_19.a.bits.param
connect monitor_19.io.in.a.bits.opcode, anonIn_19.a.bits.opcode
connect monitor_19.io.in.a.valid, anonIn_19.a.valid
connect monitor_19.io.in.a.ready, anonIn_19.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate x1_anonOut.e.bits.sink
invalidate x1_anonOut.e.valid
invalidate x1_anonOut.e.ready
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.c.bits.corrupt
invalidate x1_anonOut.c.bits.data
invalidate x1_anonOut.c.bits.address
invalidate x1_anonOut.c.bits.source
invalidate x1_anonOut.c.bits.size
invalidate x1_anonOut.c.bits.param
invalidate x1_anonOut.c.bits.opcode
invalidate x1_anonOut.c.valid
invalidate x1_anonOut.c.ready
invalidate x1_anonOut.b.bits.corrupt
invalidate x1_anonOut.b.bits.data
invalidate x1_anonOut.b.bits.mask
invalidate x1_anonOut.b.bits.address
invalidate x1_anonOut.b.bits.source
invalidate x1_anonOut.b.bits.size
invalidate x1_anonOut.b.bits.param
invalidate x1_anonOut.b.bits.opcode
invalidate x1_anonOut.b.valid
invalidate x1_anonOut.b.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
connect anonIn_3, auto.anon_in_3
connect anonIn_4, auto.anon_in_4
connect anonIn_5, auto.anon_in_5
connect anonIn_6, auto.anon_in_6
connect anonIn_7, auto.anon_in_7
connect anonIn_8, auto.anon_in_8
connect anonIn_9, auto.anon_in_9
connect anonIn_10, auto.anon_in_10
connect anonIn_11, auto.anon_in_11
connect anonIn_12, auto.anon_in_12
connect anonIn_13, auto.anon_in_13
connect anonIn_14, auto.anon_in_14
connect anonIn_15, auto.anon_in_15
connect anonIn_16, auto.anon_in_16
connect anonIn_17, auto.anon_in_17
connect anonIn_18, auto.anon_in_18
connect anonIn_19, auto.anon_in_19
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[20]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<9>(0h1c0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
invalidate in[0].b.valid
invalidate in[0].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[0].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[0].c.bits.corrupt
invalidate in[0].c.bits.data
invalidate in[0].c.bits.address
invalidate in[0].c.bits.source
invalidate in[0].c.bits.size
invalidate in[0].c.bits.param
invalidate in[0].c.bits.opcode
invalidate in[0].c.valid
invalidate in[0].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[0].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
invalidate in[0].e.bits.sink
invalidate in[0].e.valid
invalidate in[0].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[0].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<9>(0h1f0))
connect in[1].a.bits.source, _in_1_a_bits_source_T
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
invalidate in[1].b.valid
invalidate in[1].b.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.mask, UInt<8>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<2>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<2>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
invalidate _WIRE_13.bits.corrupt
invalidate _WIRE_13.bits.data
invalidate _WIRE_13.bits.mask
invalidate _WIRE_13.bits.address
invalidate _WIRE_13.bits.source
invalidate _WIRE_13.bits.size
invalidate _WIRE_13.bits.param
invalidate _WIRE_13.bits.opcode
invalidate _WIRE_13.valid
invalidate _WIRE_13.ready
connect in[1].b.ready, UInt<1>(0h1)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.mask, UInt<8>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<2>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<2>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.valid, UInt<1>(0h0)
invalidate in[1].c.bits.corrupt
invalidate in[1].c.bits.data
invalidate in[1].c.bits.address
invalidate in[1].c.bits.source
invalidate in[1].c.bits.size
invalidate in[1].c.bits.param
invalidate in[1].c.bits.opcode
invalidate in[1].c.valid
invalidate in[1].c.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<2>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.corrupt
invalidate _WIRE_17.bits.data
invalidate _WIRE_17.bits.address
invalidate _WIRE_17.bits.source
invalidate _WIRE_17.bits.size
invalidate _WIRE_17.bits.param
invalidate _WIRE_17.bits.opcode
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
connect in[1].c.valid, UInt<1>(0h0)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<2>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
invalidate in[1].e.bits.sink
invalidate in[1].e.valid
invalidate in[1].e.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_20.bits.sink, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
invalidate _WIRE_21.bits.sink
invalidate _WIRE_21.valid
invalidate _WIRE_21.ready
connect in[1].e.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_22.bits.sink, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt
connect in[2].a.bits.data, anonIn_2.a.bits.data
connect in[2].a.bits.mask, anonIn_2.a.bits.mask
connect in[2].a.bits.address, anonIn_2.a.bits.address
connect in[2].a.bits.source, anonIn_2.a.bits.source
connect in[2].a.bits.size, anonIn_2.a.bits.size
connect in[2].a.bits.param, anonIn_2.a.bits.param
connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode
connect in[2].a.valid, anonIn_2.a.valid
connect anonIn_2.a.ready, in[2].a.ready
node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<9>(0h1ec))
connect in[2].a.bits.source, _in_2_a_bits_source_T
invalidate in[2].b.bits.corrupt
invalidate in[2].b.bits.data
invalidate in[2].b.bits.mask
invalidate in[2].b.bits.address
invalidate in[2].b.bits.source
invalidate in[2].b.bits.size
invalidate in[2].b.bits.param
invalidate in[2].b.bits.opcode
invalidate in[2].b.valid
invalidate in[2].b.ready
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<2>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
connect in[2].b.ready, UInt<1>(0h1)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<2>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
connect _WIRE_27.valid, UInt<1>(0h0)
invalidate in[2].c.bits.corrupt
invalidate in[2].c.bits.data
invalidate in[2].c.bits.address
invalidate in[2].c.bits.source
invalidate in[2].c.bits.size
invalidate in[2].c.bits.param
invalidate in[2].c.bits.opcode
invalidate in[2].c.valid
invalidate in[2].c.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<2>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
invalidate _WIRE_29.bits.corrupt
invalidate _WIRE_29.bits.data
invalidate _WIRE_29.bits.address
invalidate _WIRE_29.bits.source
invalidate _WIRE_29.bits.size
invalidate _WIRE_29.bits.param
invalidate _WIRE_29.bits.opcode
invalidate _WIRE_29.valid
invalidate _WIRE_29.ready
connect in[2].c.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<2>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<3>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt
connect anonIn_2.d.bits.data, in[2].d.bits.data
connect anonIn_2.d.bits.denied, in[2].d.bits.denied
connect anonIn_2.d.bits.sink, in[2].d.bits.sink
connect anonIn_2.d.bits.source, in[2].d.bits.source
connect anonIn_2.d.bits.size, in[2].d.bits.size
connect anonIn_2.d.bits.param, in[2].d.bits.param
connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode
connect anonIn_2.d.valid, in[2].d.valid
connect in[2].d.ready, anonIn_2.d.ready
node _anonIn_d_bits_source_T_2 = bits(in[2].d.bits.source, 1, 0)
connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_2
invalidate in[2].e.bits.sink
invalidate in[2].e.valid
invalidate in[2].e.ready
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_32.bits.sink, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.sink
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
connect in[2].e.valid, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_34.bits.sink, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
connect _WIRE_35.ready, UInt<1>(0h1)
connect in[3].a.bits.corrupt, anonIn_3.a.bits.corrupt
connect in[3].a.bits.data, anonIn_3.a.bits.data
connect in[3].a.bits.mask, anonIn_3.a.bits.mask
connect in[3].a.bits.address, anonIn_3.a.bits.address
connect in[3].a.bits.source, anonIn_3.a.bits.source
connect in[3].a.bits.size, anonIn_3.a.bits.size
connect in[3].a.bits.param, anonIn_3.a.bits.param
connect in[3].a.bits.opcode, anonIn_3.a.bits.opcode
connect in[3].a.valid, anonIn_3.a.valid
connect anonIn_3.a.ready, in[3].a.ready
node _in_3_a_bits_source_T = or(anonIn_3.a.bits.source, UInt<9>(0h1a0))
connect in[3].a.bits.source, _in_3_a_bits_source_T
invalidate in[3].b.bits.corrupt
invalidate in[3].b.bits.data
invalidate in[3].b.bits.mask
invalidate in[3].b.bits.address
invalidate in[3].b.bits.source
invalidate in[3].b.bits.size
invalidate in[3].b.bits.param
invalidate in[3].b.bits.opcode
invalidate in[3].b.valid
invalidate in[3].b.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.mask, UInt<8>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<5>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<2>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
invalidate _WIRE_37.bits.corrupt
invalidate _WIRE_37.bits.data
invalidate _WIRE_37.bits.mask
invalidate _WIRE_37.bits.address
invalidate _WIRE_37.bits.source
invalidate _WIRE_37.bits.size
invalidate _WIRE_37.bits.param
invalidate _WIRE_37.bits.opcode
invalidate _WIRE_37.valid
invalidate _WIRE_37.ready
connect in[3].b.ready, UInt<1>(0h1)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.mask, UInt<8>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<5>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<2>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
invalidate in[3].c.bits.corrupt
invalidate in[3].c.bits.data
invalidate in[3].c.bits.address
invalidate in[3].c.bits.source
invalidate in[3].c.bits.size
invalidate in[3].c.bits.param
invalidate in[3].c.bits.opcode
invalidate in[3].c.valid
invalidate in[3].c.ready
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_40.bits.corrupt, UInt<1>(0h0)
connect _WIRE_40.bits.data, UInt<64>(0h0)
connect _WIRE_40.bits.address, UInt<32>(0h0)
connect _WIRE_40.bits.source, UInt<5>(0h0)
connect _WIRE_40.bits.size, UInt<4>(0h0)
connect _WIRE_40.bits.param, UInt<3>(0h0)
connect _WIRE_40.bits.opcode, UInt<3>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.corrupt
invalidate _WIRE_41.bits.data
invalidate _WIRE_41.bits.address
invalidate _WIRE_41.bits.source
invalidate _WIRE_41.bits.size
invalidate _WIRE_41.bits.param
invalidate _WIRE_41.bits.opcode
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
connect in[3].c.valid, UInt<1>(0h0)
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_42.bits.corrupt, UInt<1>(0h0)
connect _WIRE_42.bits.data, UInt<64>(0h0)
connect _WIRE_42.bits.address, UInt<32>(0h0)
connect _WIRE_42.bits.source, UInt<5>(0h0)
connect _WIRE_42.bits.size, UInt<4>(0h0)
connect _WIRE_42.bits.param, UInt<3>(0h0)
connect _WIRE_42.bits.opcode, UInt<3>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
connect _WIRE_43.ready, UInt<1>(0h1)
connect anonIn_3.d.bits.corrupt, in[3].d.bits.corrupt
connect anonIn_3.d.bits.data, in[3].d.bits.data
connect anonIn_3.d.bits.denied, in[3].d.bits.denied
connect anonIn_3.d.bits.sink, in[3].d.bits.sink
connect anonIn_3.d.bits.source, in[3].d.bits.source
connect anonIn_3.d.bits.size, in[3].d.bits.size
connect anonIn_3.d.bits.param, in[3].d.bits.param
connect anonIn_3.d.bits.opcode, in[3].d.bits.opcode
connect anonIn_3.d.valid, in[3].d.valid
connect in[3].d.ready, anonIn_3.d.ready
node _anonIn_d_bits_source_T_3 = bits(in[3].d.bits.source, 4, 0)
connect anonIn_3.d.bits.source, _anonIn_d_bits_source_T_3
invalidate in[3].e.bits.sink
invalidate in[3].e.valid
invalidate in[3].e.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_44.bits.sink, UInt<3>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
invalidate _WIRE_45.bits.sink
invalidate _WIRE_45.valid
invalidate _WIRE_45.ready
connect in[3].e.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_46.bits.sink, UInt<3>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
connect in[4].a.bits.corrupt, anonIn_4.a.bits.corrupt
connect in[4].a.bits.data, anonIn_4.a.bits.data
connect in[4].a.bits.mask, anonIn_4.a.bits.mask
connect in[4].a.bits.address, anonIn_4.a.bits.address
connect in[4].a.bits.source, anonIn_4.a.bits.source
connect in[4].a.bits.size, anonIn_4.a.bits.size
connect in[4].a.bits.param, anonIn_4.a.bits.param
connect in[4].a.bits.opcode, anonIn_4.a.bits.opcode
connect in[4].a.valid, anonIn_4.a.valid
connect anonIn_4.a.ready, in[4].a.ready
node _in_4_a_bits_source_T = or(anonIn_4.a.bits.source, UInt<9>(0h180))
connect in[4].a.bits.source, _in_4_a_bits_source_T
invalidate in[4].b.bits.corrupt
invalidate in[4].b.bits.data
invalidate in[4].b.bits.mask
invalidate in[4].b.bits.address
invalidate in[4].b.bits.source
invalidate in[4].b.bits.size
invalidate in[4].b.bits.param
invalidate in[4].b.bits.opcode
invalidate in[4].b.valid
invalidate in[4].b.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<5>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
connect in[4].b.ready, UInt<1>(0h1)
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<5>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
connect _WIRE_51.valid, UInt<1>(0h0)
invalidate in[4].c.bits.corrupt
invalidate in[4].c.bits.data
invalidate in[4].c.bits.address
invalidate in[4].c.bits.source
invalidate in[4].c.bits.size
invalidate in[4].c.bits.param
invalidate in[4].c.bits.opcode
invalidate in[4].c.valid
invalidate in[4].c.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<5>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<3>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
invalidate _WIRE_53.bits.corrupt
invalidate _WIRE_53.bits.data
invalidate _WIRE_53.bits.address
invalidate _WIRE_53.bits.source
invalidate _WIRE_53.bits.size
invalidate _WIRE_53.bits.param
invalidate _WIRE_53.bits.opcode
invalidate _WIRE_53.valid
invalidate _WIRE_53.ready
connect in[4].c.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<5>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<3>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
connect anonIn_4.d.bits.corrupt, in[4].d.bits.corrupt
connect anonIn_4.d.bits.data, in[4].d.bits.data
connect anonIn_4.d.bits.denied, in[4].d.bits.denied
connect anonIn_4.d.bits.sink, in[4].d.bits.sink
connect anonIn_4.d.bits.source, in[4].d.bits.source
connect anonIn_4.d.bits.size, in[4].d.bits.size
connect anonIn_4.d.bits.param, in[4].d.bits.param
connect anonIn_4.d.bits.opcode, in[4].d.bits.opcode
connect anonIn_4.d.valid, in[4].d.valid
connect in[4].d.ready, anonIn_4.d.ready
node _anonIn_d_bits_source_T_4 = bits(in[4].d.bits.source, 4, 0)
connect anonIn_4.d.bits.source, _anonIn_d_bits_source_T_4
invalidate in[4].e.bits.sink
invalidate in[4].e.valid
invalidate in[4].e.ready
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_56.bits.sink, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.sink
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
connect in[4].e.valid, UInt<1>(0h0)
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_58.bits.sink, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
connect _WIRE_59.ready, UInt<1>(0h1)
connect in[5].a.bits.corrupt, anonIn_5.a.bits.corrupt
connect in[5].a.bits.data, anonIn_5.a.bits.data
connect in[5].a.bits.mask, anonIn_5.a.bits.mask
connect in[5].a.bits.address, anonIn_5.a.bits.address
connect in[5].a.bits.source, anonIn_5.a.bits.source
connect in[5].a.bits.size, anonIn_5.a.bits.size
connect in[5].a.bits.param, anonIn_5.a.bits.param
connect in[5].a.bits.opcode, anonIn_5.a.bits.opcode
connect in[5].a.valid, anonIn_5.a.valid
connect anonIn_5.a.ready, in[5].a.ready
node _in_5_a_bits_source_T = or(anonIn_5.a.bits.source, UInt<9>(0h160))
connect in[5].a.bits.source, _in_5_a_bits_source_T
invalidate in[5].b.bits.corrupt
invalidate in[5].b.bits.data
invalidate in[5].b.bits.mask
invalidate in[5].b.bits.address
invalidate in[5].b.bits.source
invalidate in[5].b.bits.size
invalidate in[5].b.bits.param
invalidate in[5].b.bits.opcode
invalidate in[5].b.valid
invalidate in[5].b.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.mask, UInt<8>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<5>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<2>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
invalidate _WIRE_61.bits.corrupt
invalidate _WIRE_61.bits.data
invalidate _WIRE_61.bits.mask
invalidate _WIRE_61.bits.address
invalidate _WIRE_61.bits.source
invalidate _WIRE_61.bits.size
invalidate _WIRE_61.bits.param
invalidate _WIRE_61.bits.opcode
invalidate _WIRE_61.valid
invalidate _WIRE_61.ready
connect in[5].b.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.mask, UInt<8>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<5>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<2>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
invalidate in[5].c.bits.corrupt
invalidate in[5].c.bits.data
invalidate in[5].c.bits.address
invalidate in[5].c.bits.source
invalidate in[5].c.bits.size
invalidate in[5].c.bits.param
invalidate in[5].c.bits.opcode
invalidate in[5].c.valid
invalidate in[5].c.ready
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_64.bits.corrupt, UInt<1>(0h0)
connect _WIRE_64.bits.data, UInt<64>(0h0)
connect _WIRE_64.bits.address, UInt<32>(0h0)
connect _WIRE_64.bits.source, UInt<5>(0h0)
connect _WIRE_64.bits.size, UInt<4>(0h0)
connect _WIRE_64.bits.param, UInt<3>(0h0)
connect _WIRE_64.bits.opcode, UInt<3>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.corrupt
invalidate _WIRE_65.bits.data
invalidate _WIRE_65.bits.address
invalidate _WIRE_65.bits.source
invalidate _WIRE_65.bits.size
invalidate _WIRE_65.bits.param
invalidate _WIRE_65.bits.opcode
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
connect in[5].c.valid, UInt<1>(0h0)
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_66.bits.corrupt, UInt<1>(0h0)
connect _WIRE_66.bits.data, UInt<64>(0h0)
connect _WIRE_66.bits.address, UInt<32>(0h0)
connect _WIRE_66.bits.source, UInt<5>(0h0)
connect _WIRE_66.bits.size, UInt<4>(0h0)
connect _WIRE_66.bits.param, UInt<3>(0h0)
connect _WIRE_66.bits.opcode, UInt<3>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
connect _WIRE_67.ready, UInt<1>(0h1)
connect anonIn_5.d.bits.corrupt, in[5].d.bits.corrupt
connect anonIn_5.d.bits.data, in[5].d.bits.data
connect anonIn_5.d.bits.denied, in[5].d.bits.denied
connect anonIn_5.d.bits.sink, in[5].d.bits.sink
connect anonIn_5.d.bits.source, in[5].d.bits.source
connect anonIn_5.d.bits.size, in[5].d.bits.size
connect anonIn_5.d.bits.param, in[5].d.bits.param
connect anonIn_5.d.bits.opcode, in[5].d.bits.opcode
connect anonIn_5.d.valid, in[5].d.valid
connect in[5].d.ready, anonIn_5.d.ready
node _anonIn_d_bits_source_T_5 = bits(in[5].d.bits.source, 4, 0)
connect anonIn_5.d.bits.source, _anonIn_d_bits_source_T_5
invalidate in[5].e.bits.sink
invalidate in[5].e.valid
invalidate in[5].e.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_68.bits.sink, UInt<3>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
invalidate _WIRE_69.bits.sink
invalidate _WIRE_69.valid
invalidate _WIRE_69.ready
connect in[5].e.valid, UInt<1>(0h0)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_70.bits.sink, UInt<3>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.ready, UInt<1>(0h1)
connect in[6].a.bits.corrupt, anonIn_6.a.bits.corrupt
connect in[6].a.bits.data, anonIn_6.a.bits.data
connect in[6].a.bits.mask, anonIn_6.a.bits.mask
connect in[6].a.bits.address, anonIn_6.a.bits.address
connect in[6].a.bits.source, anonIn_6.a.bits.source
connect in[6].a.bits.size, anonIn_6.a.bits.size
connect in[6].a.bits.param, anonIn_6.a.bits.param
connect in[6].a.bits.opcode, anonIn_6.a.bits.opcode
connect in[6].a.valid, anonIn_6.a.valid
connect anonIn_6.a.ready, in[6].a.ready
node _in_6_a_bits_source_T = or(anonIn_6.a.bits.source, UInt<9>(0h140))
connect in[6].a.bits.source, _in_6_a_bits_source_T
invalidate in[6].b.bits.corrupt
invalidate in[6].b.bits.data
invalidate in[6].b.bits.mask
invalidate in[6].b.bits.address
invalidate in[6].b.bits.source
invalidate in[6].b.bits.size
invalidate in[6].b.bits.param
invalidate in[6].b.bits.opcode
invalidate in[6].b.valid
invalidate in[6].b.ready
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<5>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
connect in[6].b.ready, UInt<1>(0h1)
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<32>(0h0)
connect _WIRE_74.bits.source, UInt<5>(0h0)
connect _WIRE_74.bits.size, UInt<4>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
connect _WIRE_75.valid, UInt<1>(0h0)
invalidate in[6].c.bits.corrupt
invalidate in[6].c.bits.data
invalidate in[6].c.bits.address
invalidate in[6].c.bits.source
invalidate in[6].c.bits.size
invalidate in[6].c.bits.param
invalidate in[6].c.bits.opcode
invalidate in[6].c.valid
invalidate in[6].c.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<5>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<3>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
invalidate _WIRE_77.valid
invalidate _WIRE_77.ready
connect in[6].c.valid, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<5>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<3>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.ready, UInt<1>(0h1)
connect anonIn_6.d.bits.corrupt, in[6].d.bits.corrupt
connect anonIn_6.d.bits.data, in[6].d.bits.data
connect anonIn_6.d.bits.denied, in[6].d.bits.denied
connect anonIn_6.d.bits.sink, in[6].d.bits.sink
connect anonIn_6.d.bits.source, in[6].d.bits.source
connect anonIn_6.d.bits.size, in[6].d.bits.size
connect anonIn_6.d.bits.param, in[6].d.bits.param
connect anonIn_6.d.bits.opcode, in[6].d.bits.opcode
connect anonIn_6.d.valid, in[6].d.valid
connect in[6].d.ready, anonIn_6.d.ready
node _anonIn_d_bits_source_T_6 = bits(in[6].d.bits.source, 4, 0)
connect anonIn_6.d.bits.source, _anonIn_d_bits_source_T_6
invalidate in[6].e.bits.sink
invalidate in[6].e.valid
invalidate in[6].e.ready
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_80.bits.sink, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.sink
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
connect in[6].e.valid, UInt<1>(0h0)
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_82.bits.sink, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
connect _WIRE_83.ready, UInt<1>(0h1)
connect in[7].a.bits.corrupt, anonIn_7.a.bits.corrupt
connect in[7].a.bits.data, anonIn_7.a.bits.data
connect in[7].a.bits.mask, anonIn_7.a.bits.mask
connect in[7].a.bits.address, anonIn_7.a.bits.address
connect in[7].a.bits.source, anonIn_7.a.bits.source
connect in[7].a.bits.size, anonIn_7.a.bits.size
connect in[7].a.bits.param, anonIn_7.a.bits.param
connect in[7].a.bits.opcode, anonIn_7.a.bits.opcode
connect in[7].a.valid, anonIn_7.a.valid
connect anonIn_7.a.ready, in[7].a.ready
node _in_7_a_bits_source_T = or(anonIn_7.a.bits.source, UInt<9>(0h120))
connect in[7].a.bits.source, _in_7_a_bits_source_T
invalidate in[7].b.bits.corrupt
invalidate in[7].b.bits.data
invalidate in[7].b.bits.mask
invalidate in[7].b.bits.address
invalidate in[7].b.bits.source
invalidate in[7].b.bits.size
invalidate in[7].b.bits.param
invalidate in[7].b.bits.opcode
invalidate in[7].b.valid
invalidate in[7].b.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.mask, UInt<8>(0h0)
connect _WIRE_84.bits.address, UInt<32>(0h0)
connect _WIRE_84.bits.source, UInt<5>(0h0)
connect _WIRE_84.bits.size, UInt<4>(0h0)
connect _WIRE_84.bits.param, UInt<2>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
invalidate _WIRE_85.bits.corrupt
invalidate _WIRE_85.bits.data
invalidate _WIRE_85.bits.mask
invalidate _WIRE_85.bits.address
invalidate _WIRE_85.bits.source
invalidate _WIRE_85.bits.size
invalidate _WIRE_85.bits.param
invalidate _WIRE_85.bits.opcode
invalidate _WIRE_85.valid
invalidate _WIRE_85.ready
connect in[7].b.ready, UInt<1>(0h1)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.mask, UInt<8>(0h0)
connect _WIRE_86.bits.address, UInt<32>(0h0)
connect _WIRE_86.bits.source, UInt<5>(0h0)
connect _WIRE_86.bits.size, UInt<4>(0h0)
connect _WIRE_86.bits.param, UInt<2>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.valid, UInt<1>(0h0)
invalidate in[7].c.bits.corrupt
invalidate in[7].c.bits.data
invalidate in[7].c.bits.address
invalidate in[7].c.bits.source
invalidate in[7].c.bits.size
invalidate in[7].c.bits.param
invalidate in[7].c.bits.opcode
invalidate in[7].c.valid
invalidate in[7].c.ready
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_88.bits.corrupt, UInt<1>(0h0)
connect _WIRE_88.bits.data, UInt<64>(0h0)
connect _WIRE_88.bits.address, UInt<32>(0h0)
connect _WIRE_88.bits.source, UInt<5>(0h0)
connect _WIRE_88.bits.size, UInt<4>(0h0)
connect _WIRE_88.bits.param, UInt<3>(0h0)
connect _WIRE_88.bits.opcode, UInt<3>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.corrupt
invalidate _WIRE_89.bits.data
invalidate _WIRE_89.bits.address
invalidate _WIRE_89.bits.source
invalidate _WIRE_89.bits.size
invalidate _WIRE_89.bits.param
invalidate _WIRE_89.bits.opcode
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
connect in[7].c.valid, UInt<1>(0h0)
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_90.bits.corrupt, UInt<1>(0h0)
connect _WIRE_90.bits.data, UInt<64>(0h0)
connect _WIRE_90.bits.address, UInt<32>(0h0)
connect _WIRE_90.bits.source, UInt<5>(0h0)
connect _WIRE_90.bits.size, UInt<4>(0h0)
connect _WIRE_90.bits.param, UInt<3>(0h0)
connect _WIRE_90.bits.opcode, UInt<3>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
connect _WIRE_91.ready, UInt<1>(0h1)
connect anonIn_7.d.bits.corrupt, in[7].d.bits.corrupt
connect anonIn_7.d.bits.data, in[7].d.bits.data
connect anonIn_7.d.bits.denied, in[7].d.bits.denied
connect anonIn_7.d.bits.sink, in[7].d.bits.sink
connect anonIn_7.d.bits.source, in[7].d.bits.source
connect anonIn_7.d.bits.size, in[7].d.bits.size
connect anonIn_7.d.bits.param, in[7].d.bits.param
connect anonIn_7.d.bits.opcode, in[7].d.bits.opcode
connect anonIn_7.d.valid, in[7].d.valid
connect in[7].d.ready, anonIn_7.d.ready
node _anonIn_d_bits_source_T_7 = bits(in[7].d.bits.source, 4, 0)
connect anonIn_7.d.bits.source, _anonIn_d_bits_source_T_7
invalidate in[7].e.bits.sink
invalidate in[7].e.valid
invalidate in[7].e.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_92.bits.sink, UInt<3>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
invalidate _WIRE_93.bits.sink
invalidate _WIRE_93.valid
invalidate _WIRE_93.ready
connect in[7].e.valid, UInt<1>(0h0)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_94.bits.sink, UInt<3>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.ready, UInt<1>(0h1)
connect in[8].a.bits.corrupt, anonIn_8.a.bits.corrupt
connect in[8].a.bits.data, anonIn_8.a.bits.data
connect in[8].a.bits.mask, anonIn_8.a.bits.mask
connect in[8].a.bits.address, anonIn_8.a.bits.address
connect in[8].a.bits.source, anonIn_8.a.bits.source
connect in[8].a.bits.size, anonIn_8.a.bits.size
connect in[8].a.bits.param, anonIn_8.a.bits.param
connect in[8].a.bits.opcode, anonIn_8.a.bits.opcode
connect in[8].a.valid, anonIn_8.a.valid
connect anonIn_8.a.ready, in[8].a.ready
node _in_8_a_bits_source_T = or(anonIn_8.a.bits.source, UInt<9>(0h100))
connect in[8].a.bits.source, _in_8_a_bits_source_T
invalidate in[8].b.bits.corrupt
invalidate in[8].b.bits.data
invalidate in[8].b.bits.mask
invalidate in[8].b.bits.address
invalidate in[8].b.bits.source
invalidate in[8].b.bits.size
invalidate in[8].b.bits.param
invalidate in[8].b.bits.opcode
invalidate in[8].b.valid
invalidate in[8].b.ready
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.mask, UInt<8>(0h0)
connect _WIRE_96.bits.address, UInt<32>(0h0)
connect _WIRE_96.bits.source, UInt<5>(0h0)
connect _WIRE_96.bits.size, UInt<4>(0h0)
connect _WIRE_96.bits.param, UInt<2>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.mask
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
invalidate _WIRE_97.valid
invalidate _WIRE_97.ready
connect in[8].b.ready, UInt<1>(0h1)
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_98.bits.corrupt, UInt<1>(0h0)
connect _WIRE_98.bits.data, UInt<64>(0h0)
connect _WIRE_98.bits.mask, UInt<8>(0h0)
connect _WIRE_98.bits.address, UInt<32>(0h0)
connect _WIRE_98.bits.source, UInt<5>(0h0)
connect _WIRE_98.bits.size, UInt<4>(0h0)
connect _WIRE_98.bits.param, UInt<2>(0h0)
connect _WIRE_98.bits.opcode, UInt<3>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
connect _WIRE_99.valid, UInt<1>(0h0)
invalidate in[8].c.bits.corrupt
invalidate in[8].c.bits.data
invalidate in[8].c.bits.address
invalidate in[8].c.bits.source
invalidate in[8].c.bits.size
invalidate in[8].c.bits.param
invalidate in[8].c.bits.opcode
invalidate in[8].c.valid
invalidate in[8].c.ready
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.address, UInt<32>(0h0)
connect _WIRE_100.bits.source, UInt<5>(0h0)
connect _WIRE_100.bits.size, UInt<4>(0h0)
connect _WIRE_100.bits.param, UInt<3>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
invalidate _WIRE_101.bits.corrupt
invalidate _WIRE_101.bits.data
invalidate _WIRE_101.bits.address
invalidate _WIRE_101.bits.source
invalidate _WIRE_101.bits.size
invalidate _WIRE_101.bits.param
invalidate _WIRE_101.bits.opcode
invalidate _WIRE_101.valid
invalidate _WIRE_101.ready
connect in[8].c.valid, UInt<1>(0h0)
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_102.bits.corrupt, UInt<1>(0h0)
connect _WIRE_102.bits.data, UInt<64>(0h0)
connect _WIRE_102.bits.address, UInt<32>(0h0)
connect _WIRE_102.bits.source, UInt<5>(0h0)
connect _WIRE_102.bits.size, UInt<4>(0h0)
connect _WIRE_102.bits.param, UInt<3>(0h0)
connect _WIRE_102.bits.opcode, UInt<3>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
connect _WIRE_103.ready, UInt<1>(0h1)
connect anonIn_8.d.bits.corrupt, in[8].d.bits.corrupt
connect anonIn_8.d.bits.data, in[8].d.bits.data
connect anonIn_8.d.bits.denied, in[8].d.bits.denied
connect anonIn_8.d.bits.sink, in[8].d.bits.sink
connect anonIn_8.d.bits.source, in[8].d.bits.source
connect anonIn_8.d.bits.size, in[8].d.bits.size
connect anonIn_8.d.bits.param, in[8].d.bits.param
connect anonIn_8.d.bits.opcode, in[8].d.bits.opcode
connect anonIn_8.d.valid, in[8].d.valid
connect in[8].d.ready, anonIn_8.d.ready
node _anonIn_d_bits_source_T_8 = bits(in[8].d.bits.source, 4, 0)
connect anonIn_8.d.bits.source, _anonIn_d_bits_source_T_8
invalidate in[8].e.bits.sink
invalidate in[8].e.valid
invalidate in[8].e.ready
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_104.bits.sink, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.sink
invalidate _WIRE_105.valid
invalidate _WIRE_105.ready
connect in[8].e.valid, UInt<1>(0h0)
wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_106.bits.sink, UInt<3>(0h0)
connect _WIRE_106.valid, UInt<1>(0h0)
connect _WIRE_106.ready, UInt<1>(0h0)
wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_107.bits, _WIRE_106.bits
connect _WIRE_107.valid, _WIRE_106.valid
connect _WIRE_107.ready, _WIRE_106.ready
connect _WIRE_107.ready, UInt<1>(0h1)
connect in[9].a.bits.corrupt, anonIn_9.a.bits.corrupt
connect in[9].a.bits.data, anonIn_9.a.bits.data
connect in[9].a.bits.mask, anonIn_9.a.bits.mask
connect in[9].a.bits.address, anonIn_9.a.bits.address
connect in[9].a.bits.source, anonIn_9.a.bits.source
connect in[9].a.bits.size, anonIn_9.a.bits.size
connect in[9].a.bits.param, anonIn_9.a.bits.param
connect in[9].a.bits.opcode, anonIn_9.a.bits.opcode
connect in[9].a.valid, anonIn_9.a.valid
connect anonIn_9.a.ready, in[9].a.ready
node _in_9_a_bits_source_T = or(anonIn_9.a.bits.source, UInt<9>(0h1e8))
connect in[9].a.bits.source, _in_9_a_bits_source_T
invalidate in[9].b.bits.corrupt
invalidate in[9].b.bits.data
invalidate in[9].b.bits.mask
invalidate in[9].b.bits.address
invalidate in[9].b.bits.source
invalidate in[9].b.bits.size
invalidate in[9].b.bits.param
invalidate in[9].b.bits.opcode
invalidate in[9].b.valid
invalidate in[9].b.ready
wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_108.bits.corrupt, UInt<1>(0h0)
connect _WIRE_108.bits.data, UInt<64>(0h0)
connect _WIRE_108.bits.mask, UInt<8>(0h0)
connect _WIRE_108.bits.address, UInt<32>(0h0)
connect _WIRE_108.bits.source, UInt<2>(0h0)
connect _WIRE_108.bits.size, UInt<4>(0h0)
connect _WIRE_108.bits.param, UInt<2>(0h0)
connect _WIRE_108.bits.opcode, UInt<3>(0h0)
connect _WIRE_108.valid, UInt<1>(0h0)
connect _WIRE_108.ready, UInt<1>(0h0)
wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_109.bits, _WIRE_108.bits
connect _WIRE_109.valid, _WIRE_108.valid
connect _WIRE_109.ready, _WIRE_108.ready
invalidate _WIRE_109.bits.corrupt
invalidate _WIRE_109.bits.data
invalidate _WIRE_109.bits.mask
invalidate _WIRE_109.bits.address
invalidate _WIRE_109.bits.source
invalidate _WIRE_109.bits.size
invalidate _WIRE_109.bits.param
invalidate _WIRE_109.bits.opcode
invalidate _WIRE_109.valid
invalidate _WIRE_109.ready
connect in[9].b.ready, UInt<1>(0h1)
wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_110.bits.corrupt, UInt<1>(0h0)
connect _WIRE_110.bits.data, UInt<64>(0h0)
connect _WIRE_110.bits.mask, UInt<8>(0h0)
connect _WIRE_110.bits.address, UInt<32>(0h0)
connect _WIRE_110.bits.source, UInt<2>(0h0)
connect _WIRE_110.bits.size, UInt<4>(0h0)
connect _WIRE_110.bits.param, UInt<2>(0h0)
connect _WIRE_110.bits.opcode, UInt<3>(0h0)
connect _WIRE_110.valid, UInt<1>(0h0)
connect _WIRE_110.ready, UInt<1>(0h0)
wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_111.bits, _WIRE_110.bits
connect _WIRE_111.valid, _WIRE_110.valid
connect _WIRE_111.ready, _WIRE_110.ready
connect _WIRE_111.valid, UInt<1>(0h0)
invalidate in[9].c.bits.corrupt
invalidate in[9].c.bits.data
invalidate in[9].c.bits.address
invalidate in[9].c.bits.source
invalidate in[9].c.bits.size
invalidate in[9].c.bits.param
invalidate in[9].c.bits.opcode
invalidate in[9].c.valid
invalidate in[9].c.ready
wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_112.bits.corrupt, UInt<1>(0h0)
connect _WIRE_112.bits.data, UInt<64>(0h0)
connect _WIRE_112.bits.address, UInt<32>(0h0)
connect _WIRE_112.bits.source, UInt<2>(0h0)
connect _WIRE_112.bits.size, UInt<4>(0h0)
connect _WIRE_112.bits.param, UInt<3>(0h0)
connect _WIRE_112.bits.opcode, UInt<3>(0h0)
connect _WIRE_112.valid, UInt<1>(0h0)
connect _WIRE_112.ready, UInt<1>(0h0)
wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_113.bits, _WIRE_112.bits
connect _WIRE_113.valid, _WIRE_112.valid
connect _WIRE_113.ready, _WIRE_112.ready
invalidate _WIRE_113.bits.corrupt
invalidate _WIRE_113.bits.data
invalidate _WIRE_113.bits.address
invalidate _WIRE_113.bits.source
invalidate _WIRE_113.bits.size
invalidate _WIRE_113.bits.param
invalidate _WIRE_113.bits.opcode
invalidate _WIRE_113.valid
invalidate _WIRE_113.ready
connect in[9].c.valid, UInt<1>(0h0)
wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_114.bits.corrupt, UInt<1>(0h0)
connect _WIRE_114.bits.data, UInt<64>(0h0)
connect _WIRE_114.bits.address, UInt<32>(0h0)
connect _WIRE_114.bits.source, UInt<2>(0h0)
connect _WIRE_114.bits.size, UInt<4>(0h0)
connect _WIRE_114.bits.param, UInt<3>(0h0)
connect _WIRE_114.bits.opcode, UInt<3>(0h0)
connect _WIRE_114.valid, UInt<1>(0h0)
connect _WIRE_114.ready, UInt<1>(0h0)
wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_115.bits, _WIRE_114.bits
connect _WIRE_115.valid, _WIRE_114.valid
connect _WIRE_115.ready, _WIRE_114.ready
connect _WIRE_115.ready, UInt<1>(0h1)
connect anonIn_9.d.bits.corrupt, in[9].d.bits.corrupt
connect anonIn_9.d.bits.data, in[9].d.bits.data
connect anonIn_9.d.bits.denied, in[9].d.bits.denied
connect anonIn_9.d.bits.sink, in[9].d.bits.sink
connect anonIn_9.d.bits.source, in[9].d.bits.source
connect anonIn_9.d.bits.size, in[9].d.bits.size
connect anonIn_9.d.bits.param, in[9].d.bits.param
connect anonIn_9.d.bits.opcode, in[9].d.bits.opcode
connect anonIn_9.d.valid, in[9].d.valid
connect in[9].d.ready, anonIn_9.d.ready
node _anonIn_d_bits_source_T_9 = bits(in[9].d.bits.source, 1, 0)
connect anonIn_9.d.bits.source, _anonIn_d_bits_source_T_9
invalidate in[9].e.bits.sink
invalidate in[9].e.valid
invalidate in[9].e.ready
wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_116.bits.sink, UInt<3>(0h0)
connect _WIRE_116.valid, UInt<1>(0h0)
connect _WIRE_116.ready, UInt<1>(0h0)
wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_117.bits, _WIRE_116.bits
connect _WIRE_117.valid, _WIRE_116.valid
connect _WIRE_117.ready, _WIRE_116.ready
invalidate _WIRE_117.bits.sink
invalidate _WIRE_117.valid
invalidate _WIRE_117.ready
connect in[9].e.valid, UInt<1>(0h0)
wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_118.bits.sink, UInt<3>(0h0)
connect _WIRE_118.valid, UInt<1>(0h0)
connect _WIRE_118.ready, UInt<1>(0h0)
wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_119.bits, _WIRE_118.bits
connect _WIRE_119.valid, _WIRE_118.valid
connect _WIRE_119.ready, _WIRE_118.ready
connect _WIRE_119.ready, UInt<1>(0h1)
connect in[10].a.bits.corrupt, anonIn_10.a.bits.corrupt
connect in[10].a.bits.data, anonIn_10.a.bits.data
connect in[10].a.bits.mask, anonIn_10.a.bits.mask
connect in[10].a.bits.address, anonIn_10.a.bits.address
connect in[10].a.bits.source, anonIn_10.a.bits.source
connect in[10].a.bits.size, anonIn_10.a.bits.size
connect in[10].a.bits.param, anonIn_10.a.bits.param
connect in[10].a.bits.opcode, anonIn_10.a.bits.opcode
connect in[10].a.valid, anonIn_10.a.valid
connect anonIn_10.a.ready, in[10].a.ready
node _in_10_a_bits_source_T = or(anonIn_10.a.bits.source, UInt<9>(0h1e4))
connect in[10].a.bits.source, _in_10_a_bits_source_T
invalidate in[10].b.bits.corrupt
invalidate in[10].b.bits.data
invalidate in[10].b.bits.mask
invalidate in[10].b.bits.address
invalidate in[10].b.bits.source
invalidate in[10].b.bits.size
invalidate in[10].b.bits.param
invalidate in[10].b.bits.opcode
invalidate in[10].b.valid
invalidate in[10].b.ready
wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_120.bits.corrupt, UInt<1>(0h0)
connect _WIRE_120.bits.data, UInt<64>(0h0)
connect _WIRE_120.bits.mask, UInt<8>(0h0)
connect _WIRE_120.bits.address, UInt<32>(0h0)
connect _WIRE_120.bits.source, UInt<2>(0h0)
connect _WIRE_120.bits.size, UInt<4>(0h0)
connect _WIRE_120.bits.param, UInt<2>(0h0)
connect _WIRE_120.bits.opcode, UInt<3>(0h0)
connect _WIRE_120.valid, UInt<1>(0h0)
connect _WIRE_120.ready, UInt<1>(0h0)
wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_121.bits, _WIRE_120.bits
connect _WIRE_121.valid, _WIRE_120.valid
connect _WIRE_121.ready, _WIRE_120.ready
invalidate _WIRE_121.bits.corrupt
invalidate _WIRE_121.bits.data
invalidate _WIRE_121.bits.mask
invalidate _WIRE_121.bits.address
invalidate _WIRE_121.bits.source
invalidate _WIRE_121.bits.size
invalidate _WIRE_121.bits.param
invalidate _WIRE_121.bits.opcode
invalidate _WIRE_121.valid
invalidate _WIRE_121.ready
connect in[10].b.ready, UInt<1>(0h1)
wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_122.bits.corrupt, UInt<1>(0h0)
connect _WIRE_122.bits.data, UInt<64>(0h0)
connect _WIRE_122.bits.mask, UInt<8>(0h0)
connect _WIRE_122.bits.address, UInt<32>(0h0)
connect _WIRE_122.bits.source, UInt<2>(0h0)
connect _WIRE_122.bits.size, UInt<4>(0h0)
connect _WIRE_122.bits.param, UInt<2>(0h0)
connect _WIRE_122.bits.opcode, UInt<3>(0h0)
connect _WIRE_122.valid, UInt<1>(0h0)
connect _WIRE_122.ready, UInt<1>(0h0)
wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_123.bits, _WIRE_122.bits
connect _WIRE_123.valid, _WIRE_122.valid
connect _WIRE_123.ready, _WIRE_122.ready
connect _WIRE_123.valid, UInt<1>(0h0)
invalidate in[10].c.bits.corrupt
invalidate in[10].c.bits.data
invalidate in[10].c.bits.address
invalidate in[10].c.bits.source
invalidate in[10].c.bits.size
invalidate in[10].c.bits.param
invalidate in[10].c.bits.opcode
invalidate in[10].c.valid
invalidate in[10].c.ready
wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_124.bits.corrupt, UInt<1>(0h0)
connect _WIRE_124.bits.data, UInt<64>(0h0)
connect _WIRE_124.bits.address, UInt<32>(0h0)
connect _WIRE_124.bits.source, UInt<2>(0h0)
connect _WIRE_124.bits.size, UInt<4>(0h0)
connect _WIRE_124.bits.param, UInt<3>(0h0)
connect _WIRE_124.bits.opcode, UInt<3>(0h0)
connect _WIRE_124.valid, UInt<1>(0h0)
connect _WIRE_124.ready, UInt<1>(0h0)
wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_125.bits, _WIRE_124.bits
connect _WIRE_125.valid, _WIRE_124.valid
connect _WIRE_125.ready, _WIRE_124.ready
invalidate _WIRE_125.bits.corrupt
invalidate _WIRE_125.bits.data
invalidate _WIRE_125.bits.address
invalidate _WIRE_125.bits.source
invalidate _WIRE_125.bits.size
invalidate _WIRE_125.bits.param
invalidate _WIRE_125.bits.opcode
invalidate _WIRE_125.valid
invalidate _WIRE_125.ready
connect in[10].c.valid, UInt<1>(0h0)
wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_126.bits.corrupt, UInt<1>(0h0)
connect _WIRE_126.bits.data, UInt<64>(0h0)
connect _WIRE_126.bits.address, UInt<32>(0h0)
connect _WIRE_126.bits.source, UInt<2>(0h0)
connect _WIRE_126.bits.size, UInt<4>(0h0)
connect _WIRE_126.bits.param, UInt<3>(0h0)
connect _WIRE_126.bits.opcode, UInt<3>(0h0)
connect _WIRE_126.valid, UInt<1>(0h0)
connect _WIRE_126.ready, UInt<1>(0h0)
wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_127.bits, _WIRE_126.bits
connect _WIRE_127.valid, _WIRE_126.valid
connect _WIRE_127.ready, _WIRE_126.ready
connect _WIRE_127.ready, UInt<1>(0h1)
connect anonIn_10.d.bits.corrupt, in[10].d.bits.corrupt
connect anonIn_10.d.bits.data, in[10].d.bits.data
connect anonIn_10.d.bits.denied, in[10].d.bits.denied
connect anonIn_10.d.bits.sink, in[10].d.bits.sink
connect anonIn_10.d.bits.source, in[10].d.bits.source
connect anonIn_10.d.bits.size, in[10].d.bits.size
connect anonIn_10.d.bits.param, in[10].d.bits.param
connect anonIn_10.d.bits.opcode, in[10].d.bits.opcode
connect anonIn_10.d.valid, in[10].d.valid
connect in[10].d.ready, anonIn_10.d.ready
node _anonIn_d_bits_source_T_10 = bits(in[10].d.bits.source, 1, 0)
connect anonIn_10.d.bits.source, _anonIn_d_bits_source_T_10
invalidate in[10].e.bits.sink
invalidate in[10].e.valid
invalidate in[10].e.ready
wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_128.bits.sink, UInt<3>(0h0)
connect _WIRE_128.valid, UInt<1>(0h0)
connect _WIRE_128.ready, UInt<1>(0h0)
wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_129.bits, _WIRE_128.bits
connect _WIRE_129.valid, _WIRE_128.valid
connect _WIRE_129.ready, _WIRE_128.ready
invalidate _WIRE_129.bits.sink
invalidate _WIRE_129.valid
invalidate _WIRE_129.ready
connect in[10].e.valid, UInt<1>(0h0)
wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_130.bits.sink, UInt<3>(0h0)
connect _WIRE_130.valid, UInt<1>(0h0)
connect _WIRE_130.ready, UInt<1>(0h0)
wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_131.bits, _WIRE_130.bits
connect _WIRE_131.valid, _WIRE_130.valid
connect _WIRE_131.ready, _WIRE_130.ready
connect _WIRE_131.ready, UInt<1>(0h1)
connect in[11].a.bits.corrupt, anonIn_11.a.bits.corrupt
connect in[11].a.bits.data, anonIn_11.a.bits.data
connect in[11].a.bits.mask, anonIn_11.a.bits.mask
connect in[11].a.bits.address, anonIn_11.a.bits.address
connect in[11].a.bits.source, anonIn_11.a.bits.source
connect in[11].a.bits.size, anonIn_11.a.bits.size
connect in[11].a.bits.param, anonIn_11.a.bits.param
connect in[11].a.bits.opcode, anonIn_11.a.bits.opcode
connect in[11].a.valid, anonIn_11.a.valid
connect anonIn_11.a.ready, in[11].a.ready
node _in_11_a_bits_source_T = or(anonIn_11.a.bits.source, UInt<8>(0he0))
connect in[11].a.bits.source, _in_11_a_bits_source_T
invalidate in[11].b.bits.corrupt
invalidate in[11].b.bits.data
invalidate in[11].b.bits.mask
invalidate in[11].b.bits.address
invalidate in[11].b.bits.source
invalidate in[11].b.bits.size
invalidate in[11].b.bits.param
invalidate in[11].b.bits.opcode
invalidate in[11].b.valid
invalidate in[11].b.ready
wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_132.bits.corrupt, UInt<1>(0h0)
connect _WIRE_132.bits.data, UInt<64>(0h0)
connect _WIRE_132.bits.mask, UInt<8>(0h0)
connect _WIRE_132.bits.address, UInt<32>(0h0)
connect _WIRE_132.bits.source, UInt<5>(0h0)
connect _WIRE_132.bits.size, UInt<4>(0h0)
connect _WIRE_132.bits.param, UInt<2>(0h0)
connect _WIRE_132.bits.opcode, UInt<3>(0h0)
connect _WIRE_132.valid, UInt<1>(0h0)
connect _WIRE_132.ready, UInt<1>(0h0)
wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_133.bits, _WIRE_132.bits
connect _WIRE_133.valid, _WIRE_132.valid
connect _WIRE_133.ready, _WIRE_132.ready
invalidate _WIRE_133.bits.corrupt
invalidate _WIRE_133.bits.data
invalidate _WIRE_133.bits.mask
invalidate _WIRE_133.bits.address
invalidate _WIRE_133.bits.source
invalidate _WIRE_133.bits.size
invalidate _WIRE_133.bits.param
invalidate _WIRE_133.bits.opcode
invalidate _WIRE_133.valid
invalidate _WIRE_133.ready
connect in[11].b.ready, UInt<1>(0h1)
wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_134.bits.corrupt, UInt<1>(0h0)
connect _WIRE_134.bits.data, UInt<64>(0h0)
connect _WIRE_134.bits.mask, UInt<8>(0h0)
connect _WIRE_134.bits.address, UInt<32>(0h0)
connect _WIRE_134.bits.source, UInt<5>(0h0)
connect _WIRE_134.bits.size, UInt<4>(0h0)
connect _WIRE_134.bits.param, UInt<2>(0h0)
connect _WIRE_134.bits.opcode, UInt<3>(0h0)
connect _WIRE_134.valid, UInt<1>(0h0)
connect _WIRE_134.ready, UInt<1>(0h0)
wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_135.bits, _WIRE_134.bits
connect _WIRE_135.valid, _WIRE_134.valid
connect _WIRE_135.ready, _WIRE_134.ready
connect _WIRE_135.valid, UInt<1>(0h0)
invalidate in[11].c.bits.corrupt
invalidate in[11].c.bits.data
invalidate in[11].c.bits.address
invalidate in[11].c.bits.source
invalidate in[11].c.bits.size
invalidate in[11].c.bits.param
invalidate in[11].c.bits.opcode
invalidate in[11].c.valid
invalidate in[11].c.ready
wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_136.bits.corrupt, UInt<1>(0h0)
connect _WIRE_136.bits.data, UInt<64>(0h0)
connect _WIRE_136.bits.address, UInt<32>(0h0)
connect _WIRE_136.bits.source, UInt<5>(0h0)
connect _WIRE_136.bits.size, UInt<4>(0h0)
connect _WIRE_136.bits.param, UInt<3>(0h0)
connect _WIRE_136.bits.opcode, UInt<3>(0h0)
connect _WIRE_136.valid, UInt<1>(0h0)
connect _WIRE_136.ready, UInt<1>(0h0)
wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_137.bits, _WIRE_136.bits
connect _WIRE_137.valid, _WIRE_136.valid
connect _WIRE_137.ready, _WIRE_136.ready
invalidate _WIRE_137.bits.corrupt
invalidate _WIRE_137.bits.data
invalidate _WIRE_137.bits.address
invalidate _WIRE_137.bits.source
invalidate _WIRE_137.bits.size
invalidate _WIRE_137.bits.param
invalidate _WIRE_137.bits.opcode
invalidate _WIRE_137.valid
invalidate _WIRE_137.ready
connect in[11].c.valid, UInt<1>(0h0)
wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_138.bits.corrupt, UInt<1>(0h0)
connect _WIRE_138.bits.data, UInt<64>(0h0)
connect _WIRE_138.bits.address, UInt<32>(0h0)
connect _WIRE_138.bits.source, UInt<5>(0h0)
connect _WIRE_138.bits.size, UInt<4>(0h0)
connect _WIRE_138.bits.param, UInt<3>(0h0)
connect _WIRE_138.bits.opcode, UInt<3>(0h0)
connect _WIRE_138.valid, UInt<1>(0h0)
connect _WIRE_138.ready, UInt<1>(0h0)
wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_139.bits, _WIRE_138.bits
connect _WIRE_139.valid, _WIRE_138.valid
connect _WIRE_139.ready, _WIRE_138.ready
connect _WIRE_139.ready, UInt<1>(0h1)
connect anonIn_11.d.bits.corrupt, in[11].d.bits.corrupt
connect anonIn_11.d.bits.data, in[11].d.bits.data
connect anonIn_11.d.bits.denied, in[11].d.bits.denied
connect anonIn_11.d.bits.sink, in[11].d.bits.sink
connect anonIn_11.d.bits.source, in[11].d.bits.source
connect anonIn_11.d.bits.size, in[11].d.bits.size
connect anonIn_11.d.bits.param, in[11].d.bits.param
connect anonIn_11.d.bits.opcode, in[11].d.bits.opcode
connect anonIn_11.d.valid, in[11].d.valid
connect in[11].d.ready, anonIn_11.d.ready
node _anonIn_d_bits_source_T_11 = bits(in[11].d.bits.source, 4, 0)
connect anonIn_11.d.bits.source, _anonIn_d_bits_source_T_11
invalidate in[11].e.bits.sink
invalidate in[11].e.valid
invalidate in[11].e.ready
wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_140.bits.sink, UInt<3>(0h0)
connect _WIRE_140.valid, UInt<1>(0h0)
connect _WIRE_140.ready, UInt<1>(0h0)
wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_141.bits, _WIRE_140.bits
connect _WIRE_141.valid, _WIRE_140.valid
connect _WIRE_141.ready, _WIRE_140.ready
invalidate _WIRE_141.bits.sink
invalidate _WIRE_141.valid
invalidate _WIRE_141.ready
connect in[11].e.valid, UInt<1>(0h0)
wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_142.bits.sink, UInt<3>(0h0)
connect _WIRE_142.valid, UInt<1>(0h0)
connect _WIRE_142.ready, UInt<1>(0h0)
wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_143.bits, _WIRE_142.bits
connect _WIRE_143.valid, _WIRE_142.valid
connect _WIRE_143.ready, _WIRE_142.ready
connect _WIRE_143.ready, UInt<1>(0h1)
connect in[12].a.bits.corrupt, anonIn_12.a.bits.corrupt
connect in[12].a.bits.data, anonIn_12.a.bits.data
connect in[12].a.bits.mask, anonIn_12.a.bits.mask
connect in[12].a.bits.address, anonIn_12.a.bits.address
connect in[12].a.bits.source, anonIn_12.a.bits.source
connect in[12].a.bits.size, anonIn_12.a.bits.size
connect in[12].a.bits.param, anonIn_12.a.bits.param
connect in[12].a.bits.opcode, anonIn_12.a.bits.opcode
connect in[12].a.valid, anonIn_12.a.valid
connect anonIn_12.a.ready, in[12].a.ready
node _in_12_a_bits_source_T = or(anonIn_12.a.bits.source, UInt<8>(0hc0))
connect in[12].a.bits.source, _in_12_a_bits_source_T
invalidate in[12].b.bits.corrupt
invalidate in[12].b.bits.data
invalidate in[12].b.bits.mask
invalidate in[12].b.bits.address
invalidate in[12].b.bits.source
invalidate in[12].b.bits.size
invalidate in[12].b.bits.param
invalidate in[12].b.bits.opcode
invalidate in[12].b.valid
invalidate in[12].b.ready
wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_144.bits.corrupt, UInt<1>(0h0)
connect _WIRE_144.bits.data, UInt<64>(0h0)
connect _WIRE_144.bits.mask, UInt<8>(0h0)
connect _WIRE_144.bits.address, UInt<32>(0h0)
connect _WIRE_144.bits.source, UInt<5>(0h0)
connect _WIRE_144.bits.size, UInt<4>(0h0)
connect _WIRE_144.bits.param, UInt<2>(0h0)
connect _WIRE_144.bits.opcode, UInt<3>(0h0)
connect _WIRE_144.valid, UInt<1>(0h0)
connect _WIRE_144.ready, UInt<1>(0h0)
wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_145.bits, _WIRE_144.bits
connect _WIRE_145.valid, _WIRE_144.valid
connect _WIRE_145.ready, _WIRE_144.ready
invalidate _WIRE_145.bits.corrupt
invalidate _WIRE_145.bits.data
invalidate _WIRE_145.bits.mask
invalidate _WIRE_145.bits.address
invalidate _WIRE_145.bits.source
invalidate _WIRE_145.bits.size
invalidate _WIRE_145.bits.param
invalidate _WIRE_145.bits.opcode
invalidate _WIRE_145.valid
invalidate _WIRE_145.ready
connect in[12].b.ready, UInt<1>(0h1)
wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_146.bits.corrupt, UInt<1>(0h0)
connect _WIRE_146.bits.data, UInt<64>(0h0)
connect _WIRE_146.bits.mask, UInt<8>(0h0)
connect _WIRE_146.bits.address, UInt<32>(0h0)
connect _WIRE_146.bits.source, UInt<5>(0h0)
connect _WIRE_146.bits.size, UInt<4>(0h0)
connect _WIRE_146.bits.param, UInt<2>(0h0)
connect _WIRE_146.bits.opcode, UInt<3>(0h0)
connect _WIRE_146.valid, UInt<1>(0h0)
connect _WIRE_146.ready, UInt<1>(0h0)
wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_147.bits, _WIRE_146.bits
connect _WIRE_147.valid, _WIRE_146.valid
connect _WIRE_147.ready, _WIRE_146.ready
connect _WIRE_147.valid, UInt<1>(0h0)
invalidate in[12].c.bits.corrupt
invalidate in[12].c.bits.data
invalidate in[12].c.bits.address
invalidate in[12].c.bits.source
invalidate in[12].c.bits.size
invalidate in[12].c.bits.param
invalidate in[12].c.bits.opcode
invalidate in[12].c.valid
invalidate in[12].c.ready
wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_148.bits.corrupt, UInt<1>(0h0)
connect _WIRE_148.bits.data, UInt<64>(0h0)
connect _WIRE_148.bits.address, UInt<32>(0h0)
connect _WIRE_148.bits.source, UInt<5>(0h0)
connect _WIRE_148.bits.size, UInt<4>(0h0)
connect _WIRE_148.bits.param, UInt<3>(0h0)
connect _WIRE_148.bits.opcode, UInt<3>(0h0)
connect _WIRE_148.valid, UInt<1>(0h0)
connect _WIRE_148.ready, UInt<1>(0h0)
wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_149.bits, _WIRE_148.bits
connect _WIRE_149.valid, _WIRE_148.valid
connect _WIRE_149.ready, _WIRE_148.ready
invalidate _WIRE_149.bits.corrupt
invalidate _WIRE_149.bits.data
invalidate _WIRE_149.bits.address
invalidate _WIRE_149.bits.source
invalidate _WIRE_149.bits.size
invalidate _WIRE_149.bits.param
invalidate _WIRE_149.bits.opcode
invalidate _WIRE_149.valid
invalidate _WIRE_149.ready
connect in[12].c.valid, UInt<1>(0h0)
wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_150.bits.corrupt, UInt<1>(0h0)
connect _WIRE_150.bits.data, UInt<64>(0h0)
connect _WIRE_150.bits.address, UInt<32>(0h0)
connect _WIRE_150.bits.source, UInt<5>(0h0)
connect _WIRE_150.bits.size, UInt<4>(0h0)
connect _WIRE_150.bits.param, UInt<3>(0h0)
connect _WIRE_150.bits.opcode, UInt<3>(0h0)
connect _WIRE_150.valid, UInt<1>(0h0)
connect _WIRE_150.ready, UInt<1>(0h0)
wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_151.bits, _WIRE_150.bits
connect _WIRE_151.valid, _WIRE_150.valid
connect _WIRE_151.ready, _WIRE_150.ready
connect _WIRE_151.ready, UInt<1>(0h1)
connect anonIn_12.d.bits.corrupt, in[12].d.bits.corrupt
connect anonIn_12.d.bits.data, in[12].d.bits.data
connect anonIn_12.d.bits.denied, in[12].d.bits.denied
connect anonIn_12.d.bits.sink, in[12].d.bits.sink
connect anonIn_12.d.bits.source, in[12].d.bits.source
connect anonIn_12.d.bits.size, in[12].d.bits.size
connect anonIn_12.d.bits.param, in[12].d.bits.param
connect anonIn_12.d.bits.opcode, in[12].d.bits.opcode
connect anonIn_12.d.valid, in[12].d.valid
connect in[12].d.ready, anonIn_12.d.ready
node _anonIn_d_bits_source_T_12 = bits(in[12].d.bits.source, 4, 0)
connect anonIn_12.d.bits.source, _anonIn_d_bits_source_T_12
invalidate in[12].e.bits.sink
invalidate in[12].e.valid
invalidate in[12].e.ready
wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_152.bits.sink, UInt<3>(0h0)
connect _WIRE_152.valid, UInt<1>(0h0)
connect _WIRE_152.ready, UInt<1>(0h0)
wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_153.bits, _WIRE_152.bits
connect _WIRE_153.valid, _WIRE_152.valid
connect _WIRE_153.ready, _WIRE_152.ready
invalidate _WIRE_153.bits.sink
invalidate _WIRE_153.valid
invalidate _WIRE_153.ready
connect in[12].e.valid, UInt<1>(0h0)
wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_154.bits.sink, UInt<3>(0h0)
connect _WIRE_154.valid, UInt<1>(0h0)
connect _WIRE_154.ready, UInt<1>(0h0)
wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_155.bits, _WIRE_154.bits
connect _WIRE_155.valid, _WIRE_154.valid
connect _WIRE_155.ready, _WIRE_154.ready
connect _WIRE_155.ready, UInt<1>(0h1)
connect in[13].a.bits.corrupt, anonIn_13.a.bits.corrupt
connect in[13].a.bits.data, anonIn_13.a.bits.data
connect in[13].a.bits.mask, anonIn_13.a.bits.mask
connect in[13].a.bits.address, anonIn_13.a.bits.address
connect in[13].a.bits.source, anonIn_13.a.bits.source
connect in[13].a.bits.size, anonIn_13.a.bits.size
connect in[13].a.bits.param, anonIn_13.a.bits.param
connect in[13].a.bits.opcode, anonIn_13.a.bits.opcode
connect in[13].a.valid, anonIn_13.a.valid
connect anonIn_13.a.ready, in[13].a.ready
node _in_13_a_bits_source_T = or(anonIn_13.a.bits.source, UInt<8>(0ha0))
connect in[13].a.bits.source, _in_13_a_bits_source_T
invalidate in[13].b.bits.corrupt
invalidate in[13].b.bits.data
invalidate in[13].b.bits.mask
invalidate in[13].b.bits.address
invalidate in[13].b.bits.source
invalidate in[13].b.bits.size
invalidate in[13].b.bits.param
invalidate in[13].b.bits.opcode
invalidate in[13].b.valid
invalidate in[13].b.ready
wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_156.bits.corrupt, UInt<1>(0h0)
connect _WIRE_156.bits.data, UInt<64>(0h0)
connect _WIRE_156.bits.mask, UInt<8>(0h0)
connect _WIRE_156.bits.address, UInt<32>(0h0)
connect _WIRE_156.bits.source, UInt<5>(0h0)
connect _WIRE_156.bits.size, UInt<4>(0h0)
connect _WIRE_156.bits.param, UInt<2>(0h0)
connect _WIRE_156.bits.opcode, UInt<3>(0h0)
connect _WIRE_156.valid, UInt<1>(0h0)
connect _WIRE_156.ready, UInt<1>(0h0)
wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_157.bits, _WIRE_156.bits
connect _WIRE_157.valid, _WIRE_156.valid
connect _WIRE_157.ready, _WIRE_156.ready
invalidate _WIRE_157.bits.corrupt
invalidate _WIRE_157.bits.data
invalidate _WIRE_157.bits.mask
invalidate _WIRE_157.bits.address
invalidate _WIRE_157.bits.source
invalidate _WIRE_157.bits.size
invalidate _WIRE_157.bits.param
invalidate _WIRE_157.bits.opcode
invalidate _WIRE_157.valid
invalidate _WIRE_157.ready
connect in[13].b.ready, UInt<1>(0h1)
wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_158.bits.corrupt, UInt<1>(0h0)
connect _WIRE_158.bits.data, UInt<64>(0h0)
connect _WIRE_158.bits.mask, UInt<8>(0h0)
connect _WIRE_158.bits.address, UInt<32>(0h0)
connect _WIRE_158.bits.source, UInt<5>(0h0)
connect _WIRE_158.bits.size, UInt<4>(0h0)
connect _WIRE_158.bits.param, UInt<2>(0h0)
connect _WIRE_158.bits.opcode, UInt<3>(0h0)
connect _WIRE_158.valid, UInt<1>(0h0)
connect _WIRE_158.ready, UInt<1>(0h0)
wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_159.bits, _WIRE_158.bits
connect _WIRE_159.valid, _WIRE_158.valid
connect _WIRE_159.ready, _WIRE_158.ready
connect _WIRE_159.valid, UInt<1>(0h0)
invalidate in[13].c.bits.corrupt
invalidate in[13].c.bits.data
invalidate in[13].c.bits.address
invalidate in[13].c.bits.source
invalidate in[13].c.bits.size
invalidate in[13].c.bits.param
invalidate in[13].c.bits.opcode
invalidate in[13].c.valid
invalidate in[13].c.ready
wire _WIRE_160 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_160.bits.corrupt, UInt<1>(0h0)
connect _WIRE_160.bits.data, UInt<64>(0h0)
connect _WIRE_160.bits.address, UInt<32>(0h0)
connect _WIRE_160.bits.source, UInt<5>(0h0)
connect _WIRE_160.bits.size, UInt<4>(0h0)
connect _WIRE_160.bits.param, UInt<3>(0h0)
connect _WIRE_160.bits.opcode, UInt<3>(0h0)
connect _WIRE_160.valid, UInt<1>(0h0)
connect _WIRE_160.ready, UInt<1>(0h0)
wire _WIRE_161 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_161.bits, _WIRE_160.bits
connect _WIRE_161.valid, _WIRE_160.valid
connect _WIRE_161.ready, _WIRE_160.ready
invalidate _WIRE_161.bits.corrupt
invalidate _WIRE_161.bits.data
invalidate _WIRE_161.bits.address
invalidate _WIRE_161.bits.source
invalidate _WIRE_161.bits.size
invalidate _WIRE_161.bits.param
invalidate _WIRE_161.bits.opcode
invalidate _WIRE_161.valid
invalidate _WIRE_161.ready
connect in[13].c.valid, UInt<1>(0h0)
wire _WIRE_162 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_162.bits.corrupt, UInt<1>(0h0)
connect _WIRE_162.bits.data, UInt<64>(0h0)
connect _WIRE_162.bits.address, UInt<32>(0h0)
connect _WIRE_162.bits.source, UInt<5>(0h0)
connect _WIRE_162.bits.size, UInt<4>(0h0)
connect _WIRE_162.bits.param, UInt<3>(0h0)
connect _WIRE_162.bits.opcode, UInt<3>(0h0)
connect _WIRE_162.valid, UInt<1>(0h0)
connect _WIRE_162.ready, UInt<1>(0h0)
wire _WIRE_163 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_163.bits, _WIRE_162.bits
connect _WIRE_163.valid, _WIRE_162.valid
connect _WIRE_163.ready, _WIRE_162.ready
connect _WIRE_163.ready, UInt<1>(0h1)
connect anonIn_13.d.bits.corrupt, in[13].d.bits.corrupt
connect anonIn_13.d.bits.data, in[13].d.bits.data
connect anonIn_13.d.bits.denied, in[13].d.bits.denied
connect anonIn_13.d.bits.sink, in[13].d.bits.sink
connect anonIn_13.d.bits.source, in[13].d.bits.source
connect anonIn_13.d.bits.size, in[13].d.bits.size
connect anonIn_13.d.bits.param, in[13].d.bits.param
connect anonIn_13.d.bits.opcode, in[13].d.bits.opcode
connect anonIn_13.d.valid, in[13].d.valid
connect in[13].d.ready, anonIn_13.d.ready
node _anonIn_d_bits_source_T_13 = bits(in[13].d.bits.source, 4, 0)
connect anonIn_13.d.bits.source, _anonIn_d_bits_source_T_13
invalidate in[13].e.bits.sink
invalidate in[13].e.valid
invalidate in[13].e.ready
wire _WIRE_164 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_164.bits.sink, UInt<3>(0h0)
connect _WIRE_164.valid, UInt<1>(0h0)
connect _WIRE_164.ready, UInt<1>(0h0)
wire _WIRE_165 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_165.bits, _WIRE_164.bits
connect _WIRE_165.valid, _WIRE_164.valid
connect _WIRE_165.ready, _WIRE_164.ready
invalidate _WIRE_165.bits.sink
invalidate _WIRE_165.valid
invalidate _WIRE_165.ready
connect in[13].e.valid, UInt<1>(0h0)
wire _WIRE_166 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_166.bits.sink, UInt<3>(0h0)
connect _WIRE_166.valid, UInt<1>(0h0)
connect _WIRE_166.ready, UInt<1>(0h0)
wire _WIRE_167 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_167.bits, _WIRE_166.bits
connect _WIRE_167.valid, _WIRE_166.valid
connect _WIRE_167.ready, _WIRE_166.ready
connect _WIRE_167.ready, UInt<1>(0h1)
connect in[14].a.bits.corrupt, anonIn_14.a.bits.corrupt
connect in[14].a.bits.data, anonIn_14.a.bits.data
connect in[14].a.bits.mask, anonIn_14.a.bits.mask
connect in[14].a.bits.address, anonIn_14.a.bits.address
connect in[14].a.bits.source, anonIn_14.a.bits.source
connect in[14].a.bits.size, anonIn_14.a.bits.size
connect in[14].a.bits.param, anonIn_14.a.bits.param
connect in[14].a.bits.opcode, anonIn_14.a.bits.opcode
connect in[14].a.valid, anonIn_14.a.valid
connect anonIn_14.a.ready, in[14].a.ready
node _in_14_a_bits_source_T = or(anonIn_14.a.bits.source, UInt<8>(0h80))
connect in[14].a.bits.source, _in_14_a_bits_source_T
invalidate in[14].b.bits.corrupt
invalidate in[14].b.bits.data
invalidate in[14].b.bits.mask
invalidate in[14].b.bits.address
invalidate in[14].b.bits.source
invalidate in[14].b.bits.size
invalidate in[14].b.bits.param
invalidate in[14].b.bits.opcode
invalidate in[14].b.valid
invalidate in[14].b.ready
wire _WIRE_168 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_168.bits.corrupt, UInt<1>(0h0)
connect _WIRE_168.bits.data, UInt<64>(0h0)
connect _WIRE_168.bits.mask, UInt<8>(0h0)
connect _WIRE_168.bits.address, UInt<32>(0h0)
connect _WIRE_168.bits.source, UInt<5>(0h0)
connect _WIRE_168.bits.size, UInt<4>(0h0)
connect _WIRE_168.bits.param, UInt<2>(0h0)
connect _WIRE_168.bits.opcode, UInt<3>(0h0)
connect _WIRE_168.valid, UInt<1>(0h0)
connect _WIRE_168.ready, UInt<1>(0h0)
wire _WIRE_169 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_169.bits, _WIRE_168.bits
connect _WIRE_169.valid, _WIRE_168.valid
connect _WIRE_169.ready, _WIRE_168.ready
invalidate _WIRE_169.bits.corrupt
invalidate _WIRE_169.bits.data
invalidate _WIRE_169.bits.mask
invalidate _WIRE_169.bits.address
invalidate _WIRE_169.bits.source
invalidate _WIRE_169.bits.size
invalidate _WIRE_169.bits.param
invalidate _WIRE_169.bits.opcode
invalidate _WIRE_169.valid
invalidate _WIRE_169.ready
connect in[14].b.ready, UInt<1>(0h1)
wire _WIRE_170 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_170.bits.corrupt, UInt<1>(0h0)
connect _WIRE_170.bits.data, UInt<64>(0h0)
connect _WIRE_170.bits.mask, UInt<8>(0h0)
connect _WIRE_170.bits.address, UInt<32>(0h0)
connect _WIRE_170.bits.source, UInt<5>(0h0)
connect _WIRE_170.bits.size, UInt<4>(0h0)
connect _WIRE_170.bits.param, UInt<2>(0h0)
connect _WIRE_170.bits.opcode, UInt<3>(0h0)
connect _WIRE_170.valid, UInt<1>(0h0)
connect _WIRE_170.ready, UInt<1>(0h0)
wire _WIRE_171 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_171.bits, _WIRE_170.bits
connect _WIRE_171.valid, _WIRE_170.valid
connect _WIRE_171.ready, _WIRE_170.ready
connect _WIRE_171.valid, UInt<1>(0h0)
invalidate in[14].c.bits.corrupt
invalidate in[14].c.bits.data
invalidate in[14].c.bits.address
invalidate in[14].c.bits.source
invalidate in[14].c.bits.size
invalidate in[14].c.bits.param
invalidate in[14].c.bits.opcode
invalidate in[14].c.valid
invalidate in[14].c.ready
wire _WIRE_172 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_172.bits.corrupt, UInt<1>(0h0)
connect _WIRE_172.bits.data, UInt<64>(0h0)
connect _WIRE_172.bits.address, UInt<32>(0h0)
connect _WIRE_172.bits.source, UInt<5>(0h0)
connect _WIRE_172.bits.size, UInt<4>(0h0)
connect _WIRE_172.bits.param, UInt<3>(0h0)
connect _WIRE_172.bits.opcode, UInt<3>(0h0)
connect _WIRE_172.valid, UInt<1>(0h0)
connect _WIRE_172.ready, UInt<1>(0h0)
wire _WIRE_173 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_173.bits, _WIRE_172.bits
connect _WIRE_173.valid, _WIRE_172.valid
connect _WIRE_173.ready, _WIRE_172.ready
invalidate _WIRE_173.bits.corrupt
invalidate _WIRE_173.bits.data
invalidate _WIRE_173.bits.address
invalidate _WIRE_173.bits.source
invalidate _WIRE_173.bits.size
invalidate _WIRE_173.bits.param
invalidate _WIRE_173.bits.opcode
invalidate _WIRE_173.valid
invalidate _WIRE_173.ready
connect in[14].c.valid, UInt<1>(0h0)
wire _WIRE_174 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_174.bits.corrupt, UInt<1>(0h0)
connect _WIRE_174.bits.data, UInt<64>(0h0)
connect _WIRE_174.bits.address, UInt<32>(0h0)
connect _WIRE_174.bits.source, UInt<5>(0h0)
connect _WIRE_174.bits.size, UInt<4>(0h0)
connect _WIRE_174.bits.param, UInt<3>(0h0)
connect _WIRE_174.bits.opcode, UInt<3>(0h0)
connect _WIRE_174.valid, UInt<1>(0h0)
connect _WIRE_174.ready, UInt<1>(0h0)
wire _WIRE_175 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_175.bits, _WIRE_174.bits
connect _WIRE_175.valid, _WIRE_174.valid
connect _WIRE_175.ready, _WIRE_174.ready
connect _WIRE_175.ready, UInt<1>(0h1)
connect anonIn_14.d.bits.corrupt, in[14].d.bits.corrupt
connect anonIn_14.d.bits.data, in[14].d.bits.data
connect anonIn_14.d.bits.denied, in[14].d.bits.denied
connect anonIn_14.d.bits.sink, in[14].d.bits.sink
connect anonIn_14.d.bits.source, in[14].d.bits.source
connect anonIn_14.d.bits.size, in[14].d.bits.size
connect anonIn_14.d.bits.param, in[14].d.bits.param
connect anonIn_14.d.bits.opcode, in[14].d.bits.opcode
connect anonIn_14.d.valid, in[14].d.valid
connect in[14].d.ready, anonIn_14.d.ready
node _anonIn_d_bits_source_T_14 = bits(in[14].d.bits.source, 4, 0)
connect anonIn_14.d.bits.source, _anonIn_d_bits_source_T_14
invalidate in[14].e.bits.sink
invalidate in[14].e.valid
invalidate in[14].e.ready
wire _WIRE_176 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_176.bits.sink, UInt<3>(0h0)
connect _WIRE_176.valid, UInt<1>(0h0)
connect _WIRE_176.ready, UInt<1>(0h0)
wire _WIRE_177 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_177.bits, _WIRE_176.bits
connect _WIRE_177.valid, _WIRE_176.valid
connect _WIRE_177.ready, _WIRE_176.ready
invalidate _WIRE_177.bits.sink
invalidate _WIRE_177.valid
invalidate _WIRE_177.ready
connect in[14].e.valid, UInt<1>(0h0)
wire _WIRE_178 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_178.bits.sink, UInt<3>(0h0)
connect _WIRE_178.valid, UInt<1>(0h0)
connect _WIRE_178.ready, UInt<1>(0h0)
wire _WIRE_179 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_179.bits, _WIRE_178.bits
connect _WIRE_179.valid, _WIRE_178.valid
connect _WIRE_179.ready, _WIRE_178.ready
connect _WIRE_179.ready, UInt<1>(0h1)
connect in[15].a.bits.corrupt, anonIn_15.a.bits.corrupt
connect in[15].a.bits.data, anonIn_15.a.bits.data
connect in[15].a.bits.mask, anonIn_15.a.bits.mask
connect in[15].a.bits.address, anonIn_15.a.bits.address
connect in[15].a.bits.source, anonIn_15.a.bits.source
connect in[15].a.bits.size, anonIn_15.a.bits.size
connect in[15].a.bits.param, anonIn_15.a.bits.param
connect in[15].a.bits.opcode, anonIn_15.a.bits.opcode
connect in[15].a.valid, anonIn_15.a.valid
connect anonIn_15.a.ready, in[15].a.ready
node _in_15_a_bits_source_T = or(anonIn_15.a.bits.source, UInt<7>(0h60))
connect in[15].a.bits.source, _in_15_a_bits_source_T
invalidate in[15].b.bits.corrupt
invalidate in[15].b.bits.data
invalidate in[15].b.bits.mask
invalidate in[15].b.bits.address
invalidate in[15].b.bits.source
invalidate in[15].b.bits.size
invalidate in[15].b.bits.param
invalidate in[15].b.bits.opcode
invalidate in[15].b.valid
invalidate in[15].b.ready
wire _WIRE_180 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_180.bits.corrupt, UInt<1>(0h0)
connect _WIRE_180.bits.data, UInt<64>(0h0)
connect _WIRE_180.bits.mask, UInt<8>(0h0)
connect _WIRE_180.bits.address, UInt<32>(0h0)
connect _WIRE_180.bits.source, UInt<5>(0h0)
connect _WIRE_180.bits.size, UInt<4>(0h0)
connect _WIRE_180.bits.param, UInt<2>(0h0)
connect _WIRE_180.bits.opcode, UInt<3>(0h0)
connect _WIRE_180.valid, UInt<1>(0h0)
connect _WIRE_180.ready, UInt<1>(0h0)
wire _WIRE_181 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_181.bits, _WIRE_180.bits
connect _WIRE_181.valid, _WIRE_180.valid
connect _WIRE_181.ready, _WIRE_180.ready
invalidate _WIRE_181.bits.corrupt
invalidate _WIRE_181.bits.data
invalidate _WIRE_181.bits.mask
invalidate _WIRE_181.bits.address
invalidate _WIRE_181.bits.source
invalidate _WIRE_181.bits.size
invalidate _WIRE_181.bits.param
invalidate _WIRE_181.bits.opcode
invalidate _WIRE_181.valid
invalidate _WIRE_181.ready
connect in[15].b.ready, UInt<1>(0h1)
wire _WIRE_182 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_182.bits.corrupt, UInt<1>(0h0)
connect _WIRE_182.bits.data, UInt<64>(0h0)
connect _WIRE_182.bits.mask, UInt<8>(0h0)
connect _WIRE_182.bits.address, UInt<32>(0h0)
connect _WIRE_182.bits.source, UInt<5>(0h0)
connect _WIRE_182.bits.size, UInt<4>(0h0)
connect _WIRE_182.bits.param, UInt<2>(0h0)
connect _WIRE_182.bits.opcode, UInt<3>(0h0)
connect _WIRE_182.valid, UInt<1>(0h0)
connect _WIRE_182.ready, UInt<1>(0h0)
wire _WIRE_183 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_183.bits, _WIRE_182.bits
connect _WIRE_183.valid, _WIRE_182.valid
connect _WIRE_183.ready, _WIRE_182.ready
connect _WIRE_183.valid, UInt<1>(0h0)
invalidate in[15].c.bits.corrupt
invalidate in[15].c.bits.data
invalidate in[15].c.bits.address
invalidate in[15].c.bits.source
invalidate in[15].c.bits.size
invalidate in[15].c.bits.param
invalidate in[15].c.bits.opcode
invalidate in[15].c.valid
invalidate in[15].c.ready
wire _WIRE_184 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_184.bits.corrupt, UInt<1>(0h0)
connect _WIRE_184.bits.data, UInt<64>(0h0)
connect _WIRE_184.bits.address, UInt<32>(0h0)
connect _WIRE_184.bits.source, UInt<5>(0h0)
connect _WIRE_184.bits.size, UInt<4>(0h0)
connect _WIRE_184.bits.param, UInt<3>(0h0)
connect _WIRE_184.bits.opcode, UInt<3>(0h0)
connect _WIRE_184.valid, UInt<1>(0h0)
connect _WIRE_184.ready, UInt<1>(0h0)
wire _WIRE_185 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_185.bits, _WIRE_184.bits
connect _WIRE_185.valid, _WIRE_184.valid
connect _WIRE_185.ready, _WIRE_184.ready
invalidate _WIRE_185.bits.corrupt
invalidate _WIRE_185.bits.data
invalidate _WIRE_185.bits.address
invalidate _WIRE_185.bits.source
invalidate _WIRE_185.bits.size
invalidate _WIRE_185.bits.param
invalidate _WIRE_185.bits.opcode
invalidate _WIRE_185.valid
invalidate _WIRE_185.ready
connect in[15].c.valid, UInt<1>(0h0)
wire _WIRE_186 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_186.bits.corrupt, UInt<1>(0h0)
connect _WIRE_186.bits.data, UInt<64>(0h0)
connect _WIRE_186.bits.address, UInt<32>(0h0)
connect _WIRE_186.bits.source, UInt<5>(0h0)
connect _WIRE_186.bits.size, UInt<4>(0h0)
connect _WIRE_186.bits.param, UInt<3>(0h0)
connect _WIRE_186.bits.opcode, UInt<3>(0h0)
connect _WIRE_186.valid, UInt<1>(0h0)
connect _WIRE_186.ready, UInt<1>(0h0)
wire _WIRE_187 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_187.bits, _WIRE_186.bits
connect _WIRE_187.valid, _WIRE_186.valid
connect _WIRE_187.ready, _WIRE_186.ready
connect _WIRE_187.ready, UInt<1>(0h1)
connect anonIn_15.d.bits.corrupt, in[15].d.bits.corrupt
connect anonIn_15.d.bits.data, in[15].d.bits.data
connect anonIn_15.d.bits.denied, in[15].d.bits.denied
connect anonIn_15.d.bits.sink, in[15].d.bits.sink
connect anonIn_15.d.bits.source, in[15].d.bits.source
connect anonIn_15.d.bits.size, in[15].d.bits.size
connect anonIn_15.d.bits.param, in[15].d.bits.param
connect anonIn_15.d.bits.opcode, in[15].d.bits.opcode
connect anonIn_15.d.valid, in[15].d.valid
connect in[15].d.ready, anonIn_15.d.ready
node _anonIn_d_bits_source_T_15 = bits(in[15].d.bits.source, 4, 0)
connect anonIn_15.d.bits.source, _anonIn_d_bits_source_T_15
invalidate in[15].e.bits.sink
invalidate in[15].e.valid
invalidate in[15].e.ready
wire _WIRE_188 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_188.bits.sink, UInt<3>(0h0)
connect _WIRE_188.valid, UInt<1>(0h0)
connect _WIRE_188.ready, UInt<1>(0h0)
wire _WIRE_189 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_189.bits, _WIRE_188.bits
connect _WIRE_189.valid, _WIRE_188.valid
connect _WIRE_189.ready, _WIRE_188.ready
invalidate _WIRE_189.bits.sink
invalidate _WIRE_189.valid
invalidate _WIRE_189.ready
connect in[15].e.valid, UInt<1>(0h0)
wire _WIRE_190 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_190.bits.sink, UInt<3>(0h0)
connect _WIRE_190.valid, UInt<1>(0h0)
connect _WIRE_190.ready, UInt<1>(0h0)
wire _WIRE_191 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_191.bits, _WIRE_190.bits
connect _WIRE_191.valid, _WIRE_190.valid
connect _WIRE_191.ready, _WIRE_190.ready
connect _WIRE_191.ready, UInt<1>(0h1)
connect in[16].a.bits.corrupt, anonIn_16.a.bits.corrupt
connect in[16].a.bits.data, anonIn_16.a.bits.data
connect in[16].a.bits.mask, anonIn_16.a.bits.mask
connect in[16].a.bits.address, anonIn_16.a.bits.address
connect in[16].a.bits.source, anonIn_16.a.bits.source
connect in[16].a.bits.size, anonIn_16.a.bits.size
connect in[16].a.bits.param, anonIn_16.a.bits.param
connect in[16].a.bits.opcode, anonIn_16.a.bits.opcode
connect in[16].a.valid, anonIn_16.a.valid
connect anonIn_16.a.ready, in[16].a.ready
node _in_16_a_bits_source_T = or(anonIn_16.a.bits.source, UInt<7>(0h40))
connect in[16].a.bits.source, _in_16_a_bits_source_T
invalidate in[16].b.bits.corrupt
invalidate in[16].b.bits.data
invalidate in[16].b.bits.mask
invalidate in[16].b.bits.address
invalidate in[16].b.bits.source
invalidate in[16].b.bits.size
invalidate in[16].b.bits.param
invalidate in[16].b.bits.opcode
invalidate in[16].b.valid
invalidate in[16].b.ready
wire _WIRE_192 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_192.bits.corrupt, UInt<1>(0h0)
connect _WIRE_192.bits.data, UInt<64>(0h0)
connect _WIRE_192.bits.mask, UInt<8>(0h0)
connect _WIRE_192.bits.address, UInt<32>(0h0)
connect _WIRE_192.bits.source, UInt<5>(0h0)
connect _WIRE_192.bits.size, UInt<4>(0h0)
connect _WIRE_192.bits.param, UInt<2>(0h0)
connect _WIRE_192.bits.opcode, UInt<3>(0h0)
connect _WIRE_192.valid, UInt<1>(0h0)
connect _WIRE_192.ready, UInt<1>(0h0)
wire _WIRE_193 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_193.bits, _WIRE_192.bits
connect _WIRE_193.valid, _WIRE_192.valid
connect _WIRE_193.ready, _WIRE_192.ready
invalidate _WIRE_193.bits.corrupt
invalidate _WIRE_193.bits.data
invalidate _WIRE_193.bits.mask
invalidate _WIRE_193.bits.address
invalidate _WIRE_193.bits.source
invalidate _WIRE_193.bits.size
invalidate _WIRE_193.bits.param
invalidate _WIRE_193.bits.opcode
invalidate _WIRE_193.valid
invalidate _WIRE_193.ready
connect in[16].b.ready, UInt<1>(0h1)
wire _WIRE_194 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_194.bits.corrupt, UInt<1>(0h0)
connect _WIRE_194.bits.data, UInt<64>(0h0)
connect _WIRE_194.bits.mask, UInt<8>(0h0)
connect _WIRE_194.bits.address, UInt<32>(0h0)
connect _WIRE_194.bits.source, UInt<5>(0h0)
connect _WIRE_194.bits.size, UInt<4>(0h0)
connect _WIRE_194.bits.param, UInt<2>(0h0)
connect _WIRE_194.bits.opcode, UInt<3>(0h0)
connect _WIRE_194.valid, UInt<1>(0h0)
connect _WIRE_194.ready, UInt<1>(0h0)
wire _WIRE_195 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_195.bits, _WIRE_194.bits
connect _WIRE_195.valid, _WIRE_194.valid
connect _WIRE_195.ready, _WIRE_194.ready
connect _WIRE_195.valid, UInt<1>(0h0)
invalidate in[16].c.bits.corrupt
invalidate in[16].c.bits.data
invalidate in[16].c.bits.address
invalidate in[16].c.bits.source
invalidate in[16].c.bits.size
invalidate in[16].c.bits.param
invalidate in[16].c.bits.opcode
invalidate in[16].c.valid
invalidate in[16].c.ready
wire _WIRE_196 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_196.bits.corrupt, UInt<1>(0h0)
connect _WIRE_196.bits.data, UInt<64>(0h0)
connect _WIRE_196.bits.address, UInt<32>(0h0)
connect _WIRE_196.bits.source, UInt<5>(0h0)
connect _WIRE_196.bits.size, UInt<4>(0h0)
connect _WIRE_196.bits.param, UInt<3>(0h0)
connect _WIRE_196.bits.opcode, UInt<3>(0h0)
connect _WIRE_196.valid, UInt<1>(0h0)
connect _WIRE_196.ready, UInt<1>(0h0)
wire _WIRE_197 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_197.bits, _WIRE_196.bits
connect _WIRE_197.valid, _WIRE_196.valid
connect _WIRE_197.ready, _WIRE_196.ready
invalidate _WIRE_197.bits.corrupt
invalidate _WIRE_197.bits.data
invalidate _WIRE_197.bits.address
invalidate _WIRE_197.bits.source
invalidate _WIRE_197.bits.size
invalidate _WIRE_197.bits.param
invalidate _WIRE_197.bits.opcode
invalidate _WIRE_197.valid
invalidate _WIRE_197.ready
connect in[16].c.valid, UInt<1>(0h0)
wire _WIRE_198 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_198.bits.corrupt, UInt<1>(0h0)
connect _WIRE_198.bits.data, UInt<64>(0h0)
connect _WIRE_198.bits.address, UInt<32>(0h0)
connect _WIRE_198.bits.source, UInt<5>(0h0)
connect _WIRE_198.bits.size, UInt<4>(0h0)
connect _WIRE_198.bits.param, UInt<3>(0h0)
connect _WIRE_198.bits.opcode, UInt<3>(0h0)
connect _WIRE_198.valid, UInt<1>(0h0)
connect _WIRE_198.ready, UInt<1>(0h0)
wire _WIRE_199 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_199.bits, _WIRE_198.bits
connect _WIRE_199.valid, _WIRE_198.valid
connect _WIRE_199.ready, _WIRE_198.ready
connect _WIRE_199.ready, UInt<1>(0h1)
connect anonIn_16.d.bits.corrupt, in[16].d.bits.corrupt
connect anonIn_16.d.bits.data, in[16].d.bits.data
connect anonIn_16.d.bits.denied, in[16].d.bits.denied
connect anonIn_16.d.bits.sink, in[16].d.bits.sink
connect anonIn_16.d.bits.source, in[16].d.bits.source
connect anonIn_16.d.bits.size, in[16].d.bits.size
connect anonIn_16.d.bits.param, in[16].d.bits.param
connect anonIn_16.d.bits.opcode, in[16].d.bits.opcode
connect anonIn_16.d.valid, in[16].d.valid
connect in[16].d.ready, anonIn_16.d.ready
node _anonIn_d_bits_source_T_16 = bits(in[16].d.bits.source, 4, 0)
connect anonIn_16.d.bits.source, _anonIn_d_bits_source_T_16
invalidate in[16].e.bits.sink
invalidate in[16].e.valid
invalidate in[16].e.ready
wire _WIRE_200 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_200.bits.sink, UInt<3>(0h0)
connect _WIRE_200.valid, UInt<1>(0h0)
connect _WIRE_200.ready, UInt<1>(0h0)
wire _WIRE_201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_201.bits, _WIRE_200.bits
connect _WIRE_201.valid, _WIRE_200.valid
connect _WIRE_201.ready, _WIRE_200.ready
invalidate _WIRE_201.bits.sink
invalidate _WIRE_201.valid
invalidate _WIRE_201.ready
connect in[16].e.valid, UInt<1>(0h0)
wire _WIRE_202 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_202.bits.sink, UInt<3>(0h0)
connect _WIRE_202.valid, UInt<1>(0h0)
connect _WIRE_202.ready, UInt<1>(0h0)
wire _WIRE_203 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_203.bits, _WIRE_202.bits
connect _WIRE_203.valid, _WIRE_202.valid
connect _WIRE_203.ready, _WIRE_202.ready
connect _WIRE_203.ready, UInt<1>(0h1)
connect in[17].a.bits.corrupt, anonIn_17.a.bits.corrupt
connect in[17].a.bits.data, anonIn_17.a.bits.data
connect in[17].a.bits.mask, anonIn_17.a.bits.mask
connect in[17].a.bits.address, anonIn_17.a.bits.address
connect in[17].a.bits.source, anonIn_17.a.bits.source
connect in[17].a.bits.size, anonIn_17.a.bits.size
connect in[17].a.bits.param, anonIn_17.a.bits.param
connect in[17].a.bits.opcode, anonIn_17.a.bits.opcode
connect in[17].a.valid, anonIn_17.a.valid
connect anonIn_17.a.ready, in[17].a.ready
node _in_17_a_bits_source_T = or(anonIn_17.a.bits.source, UInt<6>(0h20))
connect in[17].a.bits.source, _in_17_a_bits_source_T
invalidate in[17].b.bits.corrupt
invalidate in[17].b.bits.data
invalidate in[17].b.bits.mask
invalidate in[17].b.bits.address
invalidate in[17].b.bits.source
invalidate in[17].b.bits.size
invalidate in[17].b.bits.param
invalidate in[17].b.bits.opcode
invalidate in[17].b.valid
invalidate in[17].b.ready
wire _WIRE_204 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_204.bits.corrupt, UInt<1>(0h0)
connect _WIRE_204.bits.data, UInt<64>(0h0)
connect _WIRE_204.bits.mask, UInt<8>(0h0)
connect _WIRE_204.bits.address, UInt<32>(0h0)
connect _WIRE_204.bits.source, UInt<5>(0h0)
connect _WIRE_204.bits.size, UInt<4>(0h0)
connect _WIRE_204.bits.param, UInt<2>(0h0)
connect _WIRE_204.bits.opcode, UInt<3>(0h0)
connect _WIRE_204.valid, UInt<1>(0h0)
connect _WIRE_204.ready, UInt<1>(0h0)
wire _WIRE_205 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_205.bits, _WIRE_204.bits
connect _WIRE_205.valid, _WIRE_204.valid
connect _WIRE_205.ready, _WIRE_204.ready
invalidate _WIRE_205.bits.corrupt
invalidate _WIRE_205.bits.data
invalidate _WIRE_205.bits.mask
invalidate _WIRE_205.bits.address
invalidate _WIRE_205.bits.source
invalidate _WIRE_205.bits.size
invalidate _WIRE_205.bits.param
invalidate _WIRE_205.bits.opcode
invalidate _WIRE_205.valid
invalidate _WIRE_205.ready
connect in[17].b.ready, UInt<1>(0h1)
wire _WIRE_206 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_206.bits.corrupt, UInt<1>(0h0)
connect _WIRE_206.bits.data, UInt<64>(0h0)
connect _WIRE_206.bits.mask, UInt<8>(0h0)
connect _WIRE_206.bits.address, UInt<32>(0h0)
connect _WIRE_206.bits.source, UInt<5>(0h0)
connect _WIRE_206.bits.size, UInt<4>(0h0)
connect _WIRE_206.bits.param, UInt<2>(0h0)
connect _WIRE_206.bits.opcode, UInt<3>(0h0)
connect _WIRE_206.valid, UInt<1>(0h0)
connect _WIRE_206.ready, UInt<1>(0h0)
wire _WIRE_207 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_207.bits, _WIRE_206.bits
connect _WIRE_207.valid, _WIRE_206.valid
connect _WIRE_207.ready, _WIRE_206.ready
connect _WIRE_207.valid, UInt<1>(0h0)
invalidate in[17].c.bits.corrupt
invalidate in[17].c.bits.data
invalidate in[17].c.bits.address
invalidate in[17].c.bits.source
invalidate in[17].c.bits.size
invalidate in[17].c.bits.param
invalidate in[17].c.bits.opcode
invalidate in[17].c.valid
invalidate in[17].c.ready
wire _WIRE_208 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_208.bits.corrupt, UInt<1>(0h0)
connect _WIRE_208.bits.data, UInt<64>(0h0)
connect _WIRE_208.bits.address, UInt<32>(0h0)
connect _WIRE_208.bits.source, UInt<5>(0h0)
connect _WIRE_208.bits.size, UInt<4>(0h0)
connect _WIRE_208.bits.param, UInt<3>(0h0)
connect _WIRE_208.bits.opcode, UInt<3>(0h0)
connect _WIRE_208.valid, UInt<1>(0h0)
connect _WIRE_208.ready, UInt<1>(0h0)
wire _WIRE_209 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_209.bits, _WIRE_208.bits
connect _WIRE_209.valid, _WIRE_208.valid
connect _WIRE_209.ready, _WIRE_208.ready
invalidate _WIRE_209.bits.corrupt
invalidate _WIRE_209.bits.data
invalidate _WIRE_209.bits.address
invalidate _WIRE_209.bits.source
invalidate _WIRE_209.bits.size
invalidate _WIRE_209.bits.param
invalidate _WIRE_209.bits.opcode
invalidate _WIRE_209.valid
invalidate _WIRE_209.ready
connect in[17].c.valid, UInt<1>(0h0)
wire _WIRE_210 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_210.bits.corrupt, UInt<1>(0h0)
connect _WIRE_210.bits.data, UInt<64>(0h0)
connect _WIRE_210.bits.address, UInt<32>(0h0)
connect _WIRE_210.bits.source, UInt<5>(0h0)
connect _WIRE_210.bits.size, UInt<4>(0h0)
connect _WIRE_210.bits.param, UInt<3>(0h0)
connect _WIRE_210.bits.opcode, UInt<3>(0h0)
connect _WIRE_210.valid, UInt<1>(0h0)
connect _WIRE_210.ready, UInt<1>(0h0)
wire _WIRE_211 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_211.bits, _WIRE_210.bits
connect _WIRE_211.valid, _WIRE_210.valid
connect _WIRE_211.ready, _WIRE_210.ready
connect _WIRE_211.ready, UInt<1>(0h1)
connect anonIn_17.d.bits.corrupt, in[17].d.bits.corrupt
connect anonIn_17.d.bits.data, in[17].d.bits.data
connect anonIn_17.d.bits.denied, in[17].d.bits.denied
connect anonIn_17.d.bits.sink, in[17].d.bits.sink
connect anonIn_17.d.bits.source, in[17].d.bits.source
connect anonIn_17.d.bits.size, in[17].d.bits.size
connect anonIn_17.d.bits.param, in[17].d.bits.param
connect anonIn_17.d.bits.opcode, in[17].d.bits.opcode
connect anonIn_17.d.valid, in[17].d.valid
connect in[17].d.ready, anonIn_17.d.ready
node _anonIn_d_bits_source_T_17 = bits(in[17].d.bits.source, 4, 0)
connect anonIn_17.d.bits.source, _anonIn_d_bits_source_T_17
invalidate in[17].e.bits.sink
invalidate in[17].e.valid
invalidate in[17].e.ready
wire _WIRE_212 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_212.bits.sink, UInt<3>(0h0)
connect _WIRE_212.valid, UInt<1>(0h0)
connect _WIRE_212.ready, UInt<1>(0h0)
wire _WIRE_213 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_213.bits, _WIRE_212.bits
connect _WIRE_213.valid, _WIRE_212.valid
connect _WIRE_213.ready, _WIRE_212.ready
invalidate _WIRE_213.bits.sink
invalidate _WIRE_213.valid
invalidate _WIRE_213.ready
connect in[17].e.valid, UInt<1>(0h0)
wire _WIRE_214 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_214.bits.sink, UInt<3>(0h0)
connect _WIRE_214.valid, UInt<1>(0h0)
connect _WIRE_214.ready, UInt<1>(0h0)
wire _WIRE_215 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_215.bits, _WIRE_214.bits
connect _WIRE_215.valid, _WIRE_214.valid
connect _WIRE_215.ready, _WIRE_214.ready
connect _WIRE_215.ready, UInt<1>(0h1)
connect in[18].a.bits.corrupt, anonIn_18.a.bits.corrupt
connect in[18].a.bits.data, anonIn_18.a.bits.data
connect in[18].a.bits.mask, anonIn_18.a.bits.mask
connect in[18].a.bits.address, anonIn_18.a.bits.address
connect in[18].a.bits.source, anonIn_18.a.bits.source
connect in[18].a.bits.size, anonIn_18.a.bits.size
connect in[18].a.bits.param, anonIn_18.a.bits.param
connect in[18].a.bits.opcode, anonIn_18.a.bits.opcode
connect in[18].a.valid, anonIn_18.a.valid
connect anonIn_18.a.ready, in[18].a.ready
node _in_18_a_bits_source_T = or(anonIn_18.a.bits.source, UInt<1>(0h0))
connect in[18].a.bits.source, _in_18_a_bits_source_T
invalidate in[18].b.bits.corrupt
invalidate in[18].b.bits.data
invalidate in[18].b.bits.mask
invalidate in[18].b.bits.address
invalidate in[18].b.bits.source
invalidate in[18].b.bits.size
invalidate in[18].b.bits.param
invalidate in[18].b.bits.opcode
invalidate in[18].b.valid
invalidate in[18].b.ready
wire _WIRE_216 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_216.bits.corrupt, UInt<1>(0h0)
connect _WIRE_216.bits.data, UInt<64>(0h0)
connect _WIRE_216.bits.mask, UInt<8>(0h0)
connect _WIRE_216.bits.address, UInt<32>(0h0)
connect _WIRE_216.bits.source, UInt<5>(0h0)
connect _WIRE_216.bits.size, UInt<4>(0h0)
connect _WIRE_216.bits.param, UInt<2>(0h0)
connect _WIRE_216.bits.opcode, UInt<3>(0h0)
connect _WIRE_216.valid, UInt<1>(0h0)
connect _WIRE_216.ready, UInt<1>(0h0)
wire _WIRE_217 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_217.bits, _WIRE_216.bits
connect _WIRE_217.valid, _WIRE_216.valid
connect _WIRE_217.ready, _WIRE_216.ready
invalidate _WIRE_217.bits.corrupt
invalidate _WIRE_217.bits.data
invalidate _WIRE_217.bits.mask
invalidate _WIRE_217.bits.address
invalidate _WIRE_217.bits.source
invalidate _WIRE_217.bits.size
invalidate _WIRE_217.bits.param
invalidate _WIRE_217.bits.opcode
invalidate _WIRE_217.valid
invalidate _WIRE_217.ready
connect in[18].b.ready, UInt<1>(0h1)
wire _WIRE_218 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_218.bits.corrupt, UInt<1>(0h0)
connect _WIRE_218.bits.data, UInt<64>(0h0)
connect _WIRE_218.bits.mask, UInt<8>(0h0)
connect _WIRE_218.bits.address, UInt<32>(0h0)
connect _WIRE_218.bits.source, UInt<5>(0h0)
connect _WIRE_218.bits.size, UInt<4>(0h0)
connect _WIRE_218.bits.param, UInt<2>(0h0)
connect _WIRE_218.bits.opcode, UInt<3>(0h0)
connect _WIRE_218.valid, UInt<1>(0h0)
connect _WIRE_218.ready, UInt<1>(0h0)
wire _WIRE_219 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_219.bits, _WIRE_218.bits
connect _WIRE_219.valid, _WIRE_218.valid
connect _WIRE_219.ready, _WIRE_218.ready
connect _WIRE_219.valid, UInt<1>(0h0)
invalidate in[18].c.bits.corrupt
invalidate in[18].c.bits.data
invalidate in[18].c.bits.address
invalidate in[18].c.bits.source
invalidate in[18].c.bits.size
invalidate in[18].c.bits.param
invalidate in[18].c.bits.opcode
invalidate in[18].c.valid
invalidate in[18].c.ready
wire _WIRE_220 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_220.bits.corrupt, UInt<1>(0h0)
connect _WIRE_220.bits.data, UInt<64>(0h0)
connect _WIRE_220.bits.address, UInt<32>(0h0)
connect _WIRE_220.bits.source, UInt<5>(0h0)
connect _WIRE_220.bits.size, UInt<4>(0h0)
connect _WIRE_220.bits.param, UInt<3>(0h0)
connect _WIRE_220.bits.opcode, UInt<3>(0h0)
connect _WIRE_220.valid, UInt<1>(0h0)
connect _WIRE_220.ready, UInt<1>(0h0)
wire _WIRE_221 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_221.bits, _WIRE_220.bits
connect _WIRE_221.valid, _WIRE_220.valid
connect _WIRE_221.ready, _WIRE_220.ready
invalidate _WIRE_221.bits.corrupt
invalidate _WIRE_221.bits.data
invalidate _WIRE_221.bits.address
invalidate _WIRE_221.bits.source
invalidate _WIRE_221.bits.size
invalidate _WIRE_221.bits.param
invalidate _WIRE_221.bits.opcode
invalidate _WIRE_221.valid
invalidate _WIRE_221.ready
connect in[18].c.valid, UInt<1>(0h0)
wire _WIRE_222 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_222.bits.corrupt, UInt<1>(0h0)
connect _WIRE_222.bits.data, UInt<64>(0h0)
connect _WIRE_222.bits.address, UInt<32>(0h0)
connect _WIRE_222.bits.source, UInt<5>(0h0)
connect _WIRE_222.bits.size, UInt<4>(0h0)
connect _WIRE_222.bits.param, UInt<3>(0h0)
connect _WIRE_222.bits.opcode, UInt<3>(0h0)
connect _WIRE_222.valid, UInt<1>(0h0)
connect _WIRE_222.ready, UInt<1>(0h0)
wire _WIRE_223 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_223.bits, _WIRE_222.bits
connect _WIRE_223.valid, _WIRE_222.valid
connect _WIRE_223.ready, _WIRE_222.ready
connect _WIRE_223.ready, UInt<1>(0h1)
connect anonIn_18.d.bits.corrupt, in[18].d.bits.corrupt
connect anonIn_18.d.bits.data, in[18].d.bits.data
connect anonIn_18.d.bits.denied, in[18].d.bits.denied
connect anonIn_18.d.bits.sink, in[18].d.bits.sink
connect anonIn_18.d.bits.source, in[18].d.bits.source
connect anonIn_18.d.bits.size, in[18].d.bits.size
connect anonIn_18.d.bits.param, in[18].d.bits.param
connect anonIn_18.d.bits.opcode, in[18].d.bits.opcode
connect anonIn_18.d.valid, in[18].d.valid
connect in[18].d.ready, anonIn_18.d.ready
node _anonIn_d_bits_source_T_18 = bits(in[18].d.bits.source, 4, 0)
connect anonIn_18.d.bits.source, _anonIn_d_bits_source_T_18
invalidate in[18].e.bits.sink
invalidate in[18].e.valid
invalidate in[18].e.ready
wire _WIRE_224 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_224.bits.sink, UInt<3>(0h0)
connect _WIRE_224.valid, UInt<1>(0h0)
connect _WIRE_224.ready, UInt<1>(0h0)
wire _WIRE_225 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_225.bits, _WIRE_224.bits
connect _WIRE_225.valid, _WIRE_224.valid
connect _WIRE_225.ready, _WIRE_224.ready
invalidate _WIRE_225.bits.sink
invalidate _WIRE_225.valid
invalidate _WIRE_225.ready
connect in[18].e.valid, UInt<1>(0h0)
wire _WIRE_226 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_226.bits.sink, UInt<3>(0h0)
connect _WIRE_226.valid, UInt<1>(0h0)
connect _WIRE_226.ready, UInt<1>(0h0)
wire _WIRE_227 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_227.bits, _WIRE_226.bits
connect _WIRE_227.valid, _WIRE_226.valid
connect _WIRE_227.ready, _WIRE_226.ready
connect _WIRE_227.ready, UInt<1>(0h1)
connect in[19].a.bits.corrupt, anonIn_19.a.bits.corrupt
connect in[19].a.bits.data, anonIn_19.a.bits.data
connect in[19].a.bits.mask, anonIn_19.a.bits.mask
connect in[19].a.bits.address, anonIn_19.a.bits.address
connect in[19].a.bits.source, anonIn_19.a.bits.source
connect in[19].a.bits.size, anonIn_19.a.bits.size
connect in[19].a.bits.param, anonIn_19.a.bits.param
connect in[19].a.bits.opcode, anonIn_19.a.bits.opcode
connect in[19].a.valid, anonIn_19.a.valid
connect anonIn_19.a.ready, in[19].a.ready
node _in_19_a_bits_source_T = or(anonIn_19.a.bits.source, UInt<9>(0h1e0))
connect in[19].a.bits.source, _in_19_a_bits_source_T
connect anonIn_19.b.bits.corrupt, in[19].b.bits.corrupt
connect anonIn_19.b.bits.data, in[19].b.bits.data
connect anonIn_19.b.bits.mask, in[19].b.bits.mask
connect anonIn_19.b.bits.address, in[19].b.bits.address
connect anonIn_19.b.bits.source, in[19].b.bits.source
connect anonIn_19.b.bits.size, in[19].b.bits.size
connect anonIn_19.b.bits.param, in[19].b.bits.param
connect anonIn_19.b.bits.opcode, in[19].b.bits.opcode
connect anonIn_19.b.valid, in[19].b.valid
connect in[19].b.ready, anonIn_19.b.ready
node _anonIn_b_bits_source_T = bits(in[19].b.bits.source, 1, 0)
connect anonIn_19.b.bits.source, _anonIn_b_bits_source_T
connect in[19].c.bits.corrupt, anonIn_19.c.bits.corrupt
connect in[19].c.bits.data, anonIn_19.c.bits.data
connect in[19].c.bits.address, anonIn_19.c.bits.address
connect in[19].c.bits.source, anonIn_19.c.bits.source
connect in[19].c.bits.size, anonIn_19.c.bits.size
connect in[19].c.bits.param, anonIn_19.c.bits.param
connect in[19].c.bits.opcode, anonIn_19.c.bits.opcode
connect in[19].c.valid, anonIn_19.c.valid
connect anonIn_19.c.ready, in[19].c.ready
node _in_19_c_bits_source_T = or(anonIn_19.c.bits.source, UInt<9>(0h1e0))
connect in[19].c.bits.source, _in_19_c_bits_source_T
connect anonIn_19.d.bits.corrupt, in[19].d.bits.corrupt
connect anonIn_19.d.bits.data, in[19].d.bits.data
connect anonIn_19.d.bits.denied, in[19].d.bits.denied
connect anonIn_19.d.bits.sink, in[19].d.bits.sink
connect anonIn_19.d.bits.source, in[19].d.bits.source
connect anonIn_19.d.bits.size, in[19].d.bits.size
connect anonIn_19.d.bits.param, in[19].d.bits.param
connect anonIn_19.d.bits.opcode, in[19].d.bits.opcode
connect anonIn_19.d.valid, in[19].d.valid
connect in[19].d.ready, anonIn_19.d.ready
node _anonIn_d_bits_source_T_19 = bits(in[19].d.bits.source, 1, 0)
connect anonIn_19.d.bits.source, _anonIn_d_bits_source_T_19
connect in[19].e.bits.sink, anonIn_19.e.bits.sink
connect in[19].e.valid, anonIn_19.e.valid
connect anonIn_19.e.ready, in[19].e.ready
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
invalidate out[0].b.bits.corrupt
invalidate out[0].b.bits.data
invalidate out[0].b.bits.mask
invalidate out[0].b.bits.address
invalidate out[0].b.bits.source
invalidate out[0].b.bits.size
invalidate out[0].b.bits.param
invalidate out[0].b.bits.opcode
invalidate out[0].b.valid
invalidate out[0].b.ready
wire _WIRE_228 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_228.bits.corrupt, UInt<1>(0h0)
connect _WIRE_228.bits.data, UInt<64>(0h0)
connect _WIRE_228.bits.mask, UInt<8>(0h0)
connect _WIRE_228.bits.address, UInt<29>(0h0)
connect _WIRE_228.bits.source, UInt<9>(0h0)
connect _WIRE_228.bits.size, UInt<4>(0h0)
connect _WIRE_228.bits.param, UInt<2>(0h0)
connect _WIRE_228.bits.opcode, UInt<3>(0h0)
connect _WIRE_228.valid, UInt<1>(0h0)
connect _WIRE_228.ready, UInt<1>(0h0)
wire _WIRE_229 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_229.bits, _WIRE_228.bits
connect _WIRE_229.valid, _WIRE_228.valid
connect _WIRE_229.ready, _WIRE_228.ready
invalidate _WIRE_229.bits.corrupt
invalidate _WIRE_229.bits.data
invalidate _WIRE_229.bits.mask
invalidate _WIRE_229.bits.address
invalidate _WIRE_229.bits.source
invalidate _WIRE_229.bits.size
invalidate _WIRE_229.bits.param
invalidate _WIRE_229.bits.opcode
invalidate _WIRE_229.valid
invalidate _WIRE_229.ready
connect out[0].b.valid, UInt<1>(0h0)
wire _WIRE_230 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_230.bits.corrupt, UInt<1>(0h0)
connect _WIRE_230.bits.data, UInt<64>(0h0)
connect _WIRE_230.bits.mask, UInt<8>(0h0)
connect _WIRE_230.bits.address, UInt<29>(0h0)
connect _WIRE_230.bits.source, UInt<9>(0h0)
connect _WIRE_230.bits.size, UInt<4>(0h0)
connect _WIRE_230.bits.param, UInt<2>(0h0)
connect _WIRE_230.bits.opcode, UInt<3>(0h0)
connect _WIRE_230.valid, UInt<1>(0h0)
connect _WIRE_230.ready, UInt<1>(0h0)
wire _WIRE_231 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_231.bits, _WIRE_230.bits
connect _WIRE_231.valid, _WIRE_230.valid
connect _WIRE_231.ready, _WIRE_230.ready
connect _WIRE_231.ready, UInt<1>(0h1)
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].c.valid
invalidate out[0].c.ready
wire _WIRE_232 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_232.bits.corrupt, UInt<1>(0h0)
connect _WIRE_232.bits.data, UInt<64>(0h0)
connect _WIRE_232.bits.address, UInt<29>(0h0)
connect _WIRE_232.bits.source, UInt<9>(0h0)
connect _WIRE_232.bits.size, UInt<4>(0h0)
connect _WIRE_232.bits.param, UInt<3>(0h0)
connect _WIRE_232.bits.opcode, UInt<3>(0h0)
connect _WIRE_232.valid, UInt<1>(0h0)
connect _WIRE_232.ready, UInt<1>(0h0)
wire _WIRE_233 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_233.bits, _WIRE_232.bits
connect _WIRE_233.valid, _WIRE_232.valid
connect _WIRE_233.ready, _WIRE_232.ready
invalidate _WIRE_233.bits.corrupt
invalidate _WIRE_233.bits.data
invalidate _WIRE_233.bits.address
invalidate _WIRE_233.bits.source
invalidate _WIRE_233.bits.size
invalidate _WIRE_233.bits.param
invalidate _WIRE_233.bits.opcode
invalidate _WIRE_233.valid
invalidate _WIRE_233.ready
connect out[0].c.ready, UInt<1>(0h1)
wire _WIRE_234 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_234.bits.corrupt, UInt<1>(0h0)
connect _WIRE_234.bits.data, UInt<64>(0h0)
connect _WIRE_234.bits.address, UInt<29>(0h0)
connect _WIRE_234.bits.source, UInt<9>(0h0)
connect _WIRE_234.bits.size, UInt<4>(0h0)
connect _WIRE_234.bits.param, UInt<3>(0h0)
connect _WIRE_234.bits.opcode, UInt<3>(0h0)
connect _WIRE_234.valid, UInt<1>(0h0)
connect _WIRE_234.ready, UInt<1>(0h0)
wire _WIRE_235 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_235.bits, _WIRE_234.bits
connect _WIRE_235.valid, _WIRE_234.valid
connect _WIRE_235.ready, _WIRE_234.ready
connect _WIRE_235.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
invalidate out[0].e.bits.sink
invalidate out[0].e.valid
invalidate out[0].e.ready
wire _WIRE_236 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_236.bits.sink, UInt<1>(0h0)
connect _WIRE_236.valid, UInt<1>(0h0)
connect _WIRE_236.ready, UInt<1>(0h0)
wire _WIRE_237 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_237.bits, _WIRE_236.bits
connect _WIRE_237.valid, _WIRE_236.valid
connect _WIRE_237.ready, _WIRE_236.ready
invalidate _WIRE_237.bits.sink
invalidate _WIRE_237.valid
invalidate _WIRE_237.ready
connect out[0].e.ready, UInt<1>(0h1)
wire _WIRE_238 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_238.bits.sink, UInt<1>(0h0)
connect _WIRE_238.valid, UInt<1>(0h0)
connect _WIRE_238.ready, UInt<1>(0h0)
wire _WIRE_239 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_239.bits, _WIRE_238.bits
connect _WIRE_239.valid, _WIRE_238.valid
connect _WIRE_239.ready, _WIRE_238.ready
connect _WIRE_239.valid, UInt<1>(0h0)
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt
connect out[1].b.bits.data, x1_anonOut.b.bits.data
connect out[1].b.bits.mask, x1_anonOut.b.bits.mask
connect out[1].b.bits.address, x1_anonOut.b.bits.address
connect out[1].b.bits.source, x1_anonOut.b.bits.source
connect out[1].b.bits.size, x1_anonOut.b.bits.size
connect out[1].b.bits.param, x1_anonOut.b.bits.param
connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode
connect out[1].b.valid, x1_anonOut.b.valid
connect x1_anonOut.b.ready, out[1].b.ready
connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt
connect x1_anonOut.c.bits.data, out[1].c.bits.data
connect x1_anonOut.c.bits.address, out[1].c.bits.address
connect x1_anonOut.c.bits.source, out[1].c.bits.source
connect x1_anonOut.c.bits.size, out[1].c.bits.size
connect x1_anonOut.c.bits.param, out[1].c.bits.param
connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode
connect x1_anonOut.c.valid, out[1].c.valid
connect out[1].c.ready, x1_anonOut.c.ready
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
connect x1_anonOut.e.bits.sink, out[1].e.bits.sink
connect x1_anonOut.e.valid, out[1].e.valid
connect out[1].e.ready, x1_anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 2, 0)
connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9)
node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14)
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16)
node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_18 = cvt(_requestAIO_T_17)
node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_20 = asSInt(_requestAIO_T_19)
node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0)))
node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_23 = cvt(_requestAIO_T_22)
node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_25 = asSInt(_requestAIO_T_24)
node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0)))
node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26)
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27)
node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_29 = cvt(_requestAIO_T_28)
node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_31 = asSInt(_requestAIO_T_30)
node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0)))
node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_34 = cvt(_requestAIO_T_33)
node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_36 = asSInt(_requestAIO_T_35)
node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0)))
node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_39 = cvt(_requestAIO_T_38)
node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_41 = asSInt(_requestAIO_T_40)
node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0)))
node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37)
node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42)
node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44)
node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_46 = cvt(_requestAIO_T_45)
node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_48 = asSInt(_requestAIO_T_47)
node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0)))
node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_51 = cvt(_requestAIO_T_50)
node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_53 = asSInt(_requestAIO_T_52)
node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0)))
node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54)
node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55)
node _requestAIO_T_56 = xor(in[2].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_57 = cvt(_requestAIO_T_56)
node _requestAIO_T_58 = and(_requestAIO_T_57, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_59 = asSInt(_requestAIO_T_58)
node _requestAIO_T_60 = eq(_requestAIO_T_59, asSInt(UInt<1>(0h0)))
node _requestAIO_T_61 = xor(in[2].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_62 = cvt(_requestAIO_T_61)
node _requestAIO_T_63 = and(_requestAIO_T_62, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_64 = asSInt(_requestAIO_T_63)
node _requestAIO_T_65 = eq(_requestAIO_T_64, asSInt(UInt<1>(0h0)))
node _requestAIO_T_66 = xor(in[2].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_67 = cvt(_requestAIO_T_66)
node _requestAIO_T_68 = and(_requestAIO_T_67, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_69 = asSInt(_requestAIO_T_68)
node _requestAIO_T_70 = eq(_requestAIO_T_69, asSInt(UInt<1>(0h0)))
node _requestAIO_T_71 = or(_requestAIO_T_60, _requestAIO_T_65)
node _requestAIO_T_72 = or(_requestAIO_T_71, _requestAIO_T_70)
node requestAIO_2_0 = or(UInt<1>(0h0), _requestAIO_T_72)
node _requestAIO_T_73 = xor(in[2].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_74 = cvt(_requestAIO_T_73)
node _requestAIO_T_75 = and(_requestAIO_T_74, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_76 = asSInt(_requestAIO_T_75)
node _requestAIO_T_77 = eq(_requestAIO_T_76, asSInt(UInt<1>(0h0)))
node _requestAIO_T_78 = xor(in[2].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_79 = cvt(_requestAIO_T_78)
node _requestAIO_T_80 = and(_requestAIO_T_79, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_81 = asSInt(_requestAIO_T_80)
node _requestAIO_T_82 = eq(_requestAIO_T_81, asSInt(UInt<1>(0h0)))
node _requestAIO_T_83 = or(_requestAIO_T_77, _requestAIO_T_82)
node requestAIO_2_1 = or(UInt<1>(0h0), _requestAIO_T_83)
node _requestAIO_T_84 = xor(in[3].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_85 = cvt(_requestAIO_T_84)
node _requestAIO_T_86 = and(_requestAIO_T_85, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_87 = asSInt(_requestAIO_T_86)
node _requestAIO_T_88 = eq(_requestAIO_T_87, asSInt(UInt<1>(0h0)))
node _requestAIO_T_89 = xor(in[3].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_90 = cvt(_requestAIO_T_89)
node _requestAIO_T_91 = and(_requestAIO_T_90, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_92 = asSInt(_requestAIO_T_91)
node _requestAIO_T_93 = eq(_requestAIO_T_92, asSInt(UInt<1>(0h0)))
node _requestAIO_T_94 = xor(in[3].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_95 = cvt(_requestAIO_T_94)
node _requestAIO_T_96 = and(_requestAIO_T_95, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_97 = asSInt(_requestAIO_T_96)
node _requestAIO_T_98 = eq(_requestAIO_T_97, asSInt(UInt<1>(0h0)))
node _requestAIO_T_99 = or(_requestAIO_T_88, _requestAIO_T_93)
node _requestAIO_T_100 = or(_requestAIO_T_99, _requestAIO_T_98)
node requestAIO_3_0 = or(UInt<1>(0h0), _requestAIO_T_100)
node _requestAIO_T_101 = xor(in[3].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_102 = cvt(_requestAIO_T_101)
node _requestAIO_T_103 = and(_requestAIO_T_102, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_104 = asSInt(_requestAIO_T_103)
node _requestAIO_T_105 = eq(_requestAIO_T_104, asSInt(UInt<1>(0h0)))
node _requestAIO_T_106 = xor(in[3].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_107 = cvt(_requestAIO_T_106)
node _requestAIO_T_108 = and(_requestAIO_T_107, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_109 = asSInt(_requestAIO_T_108)
node _requestAIO_T_110 = eq(_requestAIO_T_109, asSInt(UInt<1>(0h0)))
node _requestAIO_T_111 = or(_requestAIO_T_105, _requestAIO_T_110)
node requestAIO_3_1 = or(UInt<1>(0h0), _requestAIO_T_111)
node _requestAIO_T_112 = xor(in[4].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_113 = cvt(_requestAIO_T_112)
node _requestAIO_T_114 = and(_requestAIO_T_113, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_115 = asSInt(_requestAIO_T_114)
node _requestAIO_T_116 = eq(_requestAIO_T_115, asSInt(UInt<1>(0h0)))
node _requestAIO_T_117 = xor(in[4].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_118 = cvt(_requestAIO_T_117)
node _requestAIO_T_119 = and(_requestAIO_T_118, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_120 = asSInt(_requestAIO_T_119)
node _requestAIO_T_121 = eq(_requestAIO_T_120, asSInt(UInt<1>(0h0)))
node _requestAIO_T_122 = xor(in[4].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_123 = cvt(_requestAIO_T_122)
node _requestAIO_T_124 = and(_requestAIO_T_123, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_125 = asSInt(_requestAIO_T_124)
node _requestAIO_T_126 = eq(_requestAIO_T_125, asSInt(UInt<1>(0h0)))
node _requestAIO_T_127 = or(_requestAIO_T_116, _requestAIO_T_121)
node _requestAIO_T_128 = or(_requestAIO_T_127, _requestAIO_T_126)
node requestAIO_4_0 = or(UInt<1>(0h0), _requestAIO_T_128)
node _requestAIO_T_129 = xor(in[4].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_130 = cvt(_requestAIO_T_129)
node _requestAIO_T_131 = and(_requestAIO_T_130, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_132 = asSInt(_requestAIO_T_131)
node _requestAIO_T_133 = eq(_requestAIO_T_132, asSInt(UInt<1>(0h0)))
node _requestAIO_T_134 = xor(in[4].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_135 = cvt(_requestAIO_T_134)
node _requestAIO_T_136 = and(_requestAIO_T_135, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_137 = asSInt(_requestAIO_T_136)
node _requestAIO_T_138 = eq(_requestAIO_T_137, asSInt(UInt<1>(0h0)))
node _requestAIO_T_139 = or(_requestAIO_T_133, _requestAIO_T_138)
node requestAIO_4_1 = or(UInt<1>(0h0), _requestAIO_T_139)
node _requestAIO_T_140 = xor(in[5].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_141 = cvt(_requestAIO_T_140)
node _requestAIO_T_142 = and(_requestAIO_T_141, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_143 = asSInt(_requestAIO_T_142)
node _requestAIO_T_144 = eq(_requestAIO_T_143, asSInt(UInt<1>(0h0)))
node _requestAIO_T_145 = xor(in[5].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_146 = cvt(_requestAIO_T_145)
node _requestAIO_T_147 = and(_requestAIO_T_146, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_148 = asSInt(_requestAIO_T_147)
node _requestAIO_T_149 = eq(_requestAIO_T_148, asSInt(UInt<1>(0h0)))
node _requestAIO_T_150 = xor(in[5].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_151 = cvt(_requestAIO_T_150)
node _requestAIO_T_152 = and(_requestAIO_T_151, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_153 = asSInt(_requestAIO_T_152)
node _requestAIO_T_154 = eq(_requestAIO_T_153, asSInt(UInt<1>(0h0)))
node _requestAIO_T_155 = or(_requestAIO_T_144, _requestAIO_T_149)
node _requestAIO_T_156 = or(_requestAIO_T_155, _requestAIO_T_154)
node requestAIO_5_0 = or(UInt<1>(0h0), _requestAIO_T_156)
node _requestAIO_T_157 = xor(in[5].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_158 = cvt(_requestAIO_T_157)
node _requestAIO_T_159 = and(_requestAIO_T_158, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_160 = asSInt(_requestAIO_T_159)
node _requestAIO_T_161 = eq(_requestAIO_T_160, asSInt(UInt<1>(0h0)))
node _requestAIO_T_162 = xor(in[5].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_163 = cvt(_requestAIO_T_162)
node _requestAIO_T_164 = and(_requestAIO_T_163, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_165 = asSInt(_requestAIO_T_164)
node _requestAIO_T_166 = eq(_requestAIO_T_165, asSInt(UInt<1>(0h0)))
node _requestAIO_T_167 = or(_requestAIO_T_161, _requestAIO_T_166)
node requestAIO_5_1 = or(UInt<1>(0h0), _requestAIO_T_167)
node _requestAIO_T_168 = xor(in[6].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_169 = cvt(_requestAIO_T_168)
node _requestAIO_T_170 = and(_requestAIO_T_169, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_171 = asSInt(_requestAIO_T_170)
node _requestAIO_T_172 = eq(_requestAIO_T_171, asSInt(UInt<1>(0h0)))
node _requestAIO_T_173 = xor(in[6].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_174 = cvt(_requestAIO_T_173)
node _requestAIO_T_175 = and(_requestAIO_T_174, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_176 = asSInt(_requestAIO_T_175)
node _requestAIO_T_177 = eq(_requestAIO_T_176, asSInt(UInt<1>(0h0)))
node _requestAIO_T_178 = xor(in[6].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_179 = cvt(_requestAIO_T_178)
node _requestAIO_T_180 = and(_requestAIO_T_179, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_181 = asSInt(_requestAIO_T_180)
node _requestAIO_T_182 = eq(_requestAIO_T_181, asSInt(UInt<1>(0h0)))
node _requestAIO_T_183 = or(_requestAIO_T_172, _requestAIO_T_177)
node _requestAIO_T_184 = or(_requestAIO_T_183, _requestAIO_T_182)
node requestAIO_6_0 = or(UInt<1>(0h0), _requestAIO_T_184)
node _requestAIO_T_185 = xor(in[6].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_186 = cvt(_requestAIO_T_185)
node _requestAIO_T_187 = and(_requestAIO_T_186, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_188 = asSInt(_requestAIO_T_187)
node _requestAIO_T_189 = eq(_requestAIO_T_188, asSInt(UInt<1>(0h0)))
node _requestAIO_T_190 = xor(in[6].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_191 = cvt(_requestAIO_T_190)
node _requestAIO_T_192 = and(_requestAIO_T_191, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_193 = asSInt(_requestAIO_T_192)
node _requestAIO_T_194 = eq(_requestAIO_T_193, asSInt(UInt<1>(0h0)))
node _requestAIO_T_195 = or(_requestAIO_T_189, _requestAIO_T_194)
node requestAIO_6_1 = or(UInt<1>(0h0), _requestAIO_T_195)
node _requestAIO_T_196 = xor(in[7].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_197 = cvt(_requestAIO_T_196)
node _requestAIO_T_198 = and(_requestAIO_T_197, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_199 = asSInt(_requestAIO_T_198)
node _requestAIO_T_200 = eq(_requestAIO_T_199, asSInt(UInt<1>(0h0)))
node _requestAIO_T_201 = xor(in[7].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_202 = cvt(_requestAIO_T_201)
node _requestAIO_T_203 = and(_requestAIO_T_202, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_204 = asSInt(_requestAIO_T_203)
node _requestAIO_T_205 = eq(_requestAIO_T_204, asSInt(UInt<1>(0h0)))
node _requestAIO_T_206 = xor(in[7].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_207 = cvt(_requestAIO_T_206)
node _requestAIO_T_208 = and(_requestAIO_T_207, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_209 = asSInt(_requestAIO_T_208)
node _requestAIO_T_210 = eq(_requestAIO_T_209, asSInt(UInt<1>(0h0)))
node _requestAIO_T_211 = or(_requestAIO_T_200, _requestAIO_T_205)
node _requestAIO_T_212 = or(_requestAIO_T_211, _requestAIO_T_210)
node requestAIO_7_0 = or(UInt<1>(0h0), _requestAIO_T_212)
node _requestAIO_T_213 = xor(in[7].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_214 = cvt(_requestAIO_T_213)
node _requestAIO_T_215 = and(_requestAIO_T_214, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_216 = asSInt(_requestAIO_T_215)
node _requestAIO_T_217 = eq(_requestAIO_T_216, asSInt(UInt<1>(0h0)))
node _requestAIO_T_218 = xor(in[7].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_219 = cvt(_requestAIO_T_218)
node _requestAIO_T_220 = and(_requestAIO_T_219, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_221 = asSInt(_requestAIO_T_220)
node _requestAIO_T_222 = eq(_requestAIO_T_221, asSInt(UInt<1>(0h0)))
node _requestAIO_T_223 = or(_requestAIO_T_217, _requestAIO_T_222)
node requestAIO_7_1 = or(UInt<1>(0h0), _requestAIO_T_223)
node _requestAIO_T_224 = xor(in[8].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_225 = cvt(_requestAIO_T_224)
node _requestAIO_T_226 = and(_requestAIO_T_225, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_227 = asSInt(_requestAIO_T_226)
node _requestAIO_T_228 = eq(_requestAIO_T_227, asSInt(UInt<1>(0h0)))
node _requestAIO_T_229 = xor(in[8].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_230 = cvt(_requestAIO_T_229)
node _requestAIO_T_231 = and(_requestAIO_T_230, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_232 = asSInt(_requestAIO_T_231)
node _requestAIO_T_233 = eq(_requestAIO_T_232, asSInt(UInt<1>(0h0)))
node _requestAIO_T_234 = xor(in[8].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_235 = cvt(_requestAIO_T_234)
node _requestAIO_T_236 = and(_requestAIO_T_235, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_237 = asSInt(_requestAIO_T_236)
node _requestAIO_T_238 = eq(_requestAIO_T_237, asSInt(UInt<1>(0h0)))
node _requestAIO_T_239 = or(_requestAIO_T_228, _requestAIO_T_233)
node _requestAIO_T_240 = or(_requestAIO_T_239, _requestAIO_T_238)
node requestAIO_8_0 = or(UInt<1>(0h0), _requestAIO_T_240)
node _requestAIO_T_241 = xor(in[8].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_242 = cvt(_requestAIO_T_241)
node _requestAIO_T_243 = and(_requestAIO_T_242, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_244 = asSInt(_requestAIO_T_243)
node _requestAIO_T_245 = eq(_requestAIO_T_244, asSInt(UInt<1>(0h0)))
node _requestAIO_T_246 = xor(in[8].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_247 = cvt(_requestAIO_T_246)
node _requestAIO_T_248 = and(_requestAIO_T_247, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_249 = asSInt(_requestAIO_T_248)
node _requestAIO_T_250 = eq(_requestAIO_T_249, asSInt(UInt<1>(0h0)))
node _requestAIO_T_251 = or(_requestAIO_T_245, _requestAIO_T_250)
node requestAIO_8_1 = or(UInt<1>(0h0), _requestAIO_T_251)
node _requestAIO_T_252 = xor(in[9].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_253 = cvt(_requestAIO_T_252)
node _requestAIO_T_254 = and(_requestAIO_T_253, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_255 = asSInt(_requestAIO_T_254)
node _requestAIO_T_256 = eq(_requestAIO_T_255, asSInt(UInt<1>(0h0)))
node _requestAIO_T_257 = xor(in[9].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_258 = cvt(_requestAIO_T_257)
node _requestAIO_T_259 = and(_requestAIO_T_258, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_260 = asSInt(_requestAIO_T_259)
node _requestAIO_T_261 = eq(_requestAIO_T_260, asSInt(UInt<1>(0h0)))
node _requestAIO_T_262 = xor(in[9].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_263 = cvt(_requestAIO_T_262)
node _requestAIO_T_264 = and(_requestAIO_T_263, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_265 = asSInt(_requestAIO_T_264)
node _requestAIO_T_266 = eq(_requestAIO_T_265, asSInt(UInt<1>(0h0)))
node _requestAIO_T_267 = or(_requestAIO_T_256, _requestAIO_T_261)
node _requestAIO_T_268 = or(_requestAIO_T_267, _requestAIO_T_266)
node requestAIO_9_0 = or(UInt<1>(0h0), _requestAIO_T_268)
node _requestAIO_T_269 = xor(in[9].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_270 = cvt(_requestAIO_T_269)
node _requestAIO_T_271 = and(_requestAIO_T_270, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_272 = asSInt(_requestAIO_T_271)
node _requestAIO_T_273 = eq(_requestAIO_T_272, asSInt(UInt<1>(0h0)))
node _requestAIO_T_274 = xor(in[9].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_275 = cvt(_requestAIO_T_274)
node _requestAIO_T_276 = and(_requestAIO_T_275, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_277 = asSInt(_requestAIO_T_276)
node _requestAIO_T_278 = eq(_requestAIO_T_277, asSInt(UInt<1>(0h0)))
node _requestAIO_T_279 = or(_requestAIO_T_273, _requestAIO_T_278)
node requestAIO_9_1 = or(UInt<1>(0h0), _requestAIO_T_279)
node _requestAIO_T_280 = xor(in[10].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_281 = cvt(_requestAIO_T_280)
node _requestAIO_T_282 = and(_requestAIO_T_281, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_283 = asSInt(_requestAIO_T_282)
node _requestAIO_T_284 = eq(_requestAIO_T_283, asSInt(UInt<1>(0h0)))
node _requestAIO_T_285 = xor(in[10].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_286 = cvt(_requestAIO_T_285)
node _requestAIO_T_287 = and(_requestAIO_T_286, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_288 = asSInt(_requestAIO_T_287)
node _requestAIO_T_289 = eq(_requestAIO_T_288, asSInt(UInt<1>(0h0)))
node _requestAIO_T_290 = xor(in[10].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_291 = cvt(_requestAIO_T_290)
node _requestAIO_T_292 = and(_requestAIO_T_291, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_293 = asSInt(_requestAIO_T_292)
node _requestAIO_T_294 = eq(_requestAIO_T_293, asSInt(UInt<1>(0h0)))
node _requestAIO_T_295 = or(_requestAIO_T_284, _requestAIO_T_289)
node _requestAIO_T_296 = or(_requestAIO_T_295, _requestAIO_T_294)
node requestAIO_10_0 = or(UInt<1>(0h0), _requestAIO_T_296)
node _requestAIO_T_297 = xor(in[10].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_298 = cvt(_requestAIO_T_297)
node _requestAIO_T_299 = and(_requestAIO_T_298, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_300 = asSInt(_requestAIO_T_299)
node _requestAIO_T_301 = eq(_requestAIO_T_300, asSInt(UInt<1>(0h0)))
node _requestAIO_T_302 = xor(in[10].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_303 = cvt(_requestAIO_T_302)
node _requestAIO_T_304 = and(_requestAIO_T_303, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_305 = asSInt(_requestAIO_T_304)
node _requestAIO_T_306 = eq(_requestAIO_T_305, asSInt(UInt<1>(0h0)))
node _requestAIO_T_307 = or(_requestAIO_T_301, _requestAIO_T_306)
node requestAIO_10_1 = or(UInt<1>(0h0), _requestAIO_T_307)
node _requestAIO_T_308 = xor(in[11].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_309 = cvt(_requestAIO_T_308)
node _requestAIO_T_310 = and(_requestAIO_T_309, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_311 = asSInt(_requestAIO_T_310)
node _requestAIO_T_312 = eq(_requestAIO_T_311, asSInt(UInt<1>(0h0)))
node _requestAIO_T_313 = xor(in[11].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_314 = cvt(_requestAIO_T_313)
node _requestAIO_T_315 = and(_requestAIO_T_314, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_316 = asSInt(_requestAIO_T_315)
node _requestAIO_T_317 = eq(_requestAIO_T_316, asSInt(UInt<1>(0h0)))
node _requestAIO_T_318 = xor(in[11].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_319 = cvt(_requestAIO_T_318)
node _requestAIO_T_320 = and(_requestAIO_T_319, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_321 = asSInt(_requestAIO_T_320)
node _requestAIO_T_322 = eq(_requestAIO_T_321, asSInt(UInt<1>(0h0)))
node _requestAIO_T_323 = or(_requestAIO_T_312, _requestAIO_T_317)
node _requestAIO_T_324 = or(_requestAIO_T_323, _requestAIO_T_322)
node requestAIO_11_0 = or(UInt<1>(0h0), _requestAIO_T_324)
node _requestAIO_T_325 = xor(in[11].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_326 = cvt(_requestAIO_T_325)
node _requestAIO_T_327 = and(_requestAIO_T_326, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_328 = asSInt(_requestAIO_T_327)
node _requestAIO_T_329 = eq(_requestAIO_T_328, asSInt(UInt<1>(0h0)))
node _requestAIO_T_330 = xor(in[11].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_331 = cvt(_requestAIO_T_330)
node _requestAIO_T_332 = and(_requestAIO_T_331, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_333 = asSInt(_requestAIO_T_332)
node _requestAIO_T_334 = eq(_requestAIO_T_333, asSInt(UInt<1>(0h0)))
node _requestAIO_T_335 = or(_requestAIO_T_329, _requestAIO_T_334)
node requestAIO_11_1 = or(UInt<1>(0h0), _requestAIO_T_335)
node _requestAIO_T_336 = xor(in[12].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_337 = cvt(_requestAIO_T_336)
node _requestAIO_T_338 = and(_requestAIO_T_337, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_339 = asSInt(_requestAIO_T_338)
node _requestAIO_T_340 = eq(_requestAIO_T_339, asSInt(UInt<1>(0h0)))
node _requestAIO_T_341 = xor(in[12].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_342 = cvt(_requestAIO_T_341)
node _requestAIO_T_343 = and(_requestAIO_T_342, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_344 = asSInt(_requestAIO_T_343)
node _requestAIO_T_345 = eq(_requestAIO_T_344, asSInt(UInt<1>(0h0)))
node _requestAIO_T_346 = xor(in[12].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_347 = cvt(_requestAIO_T_346)
node _requestAIO_T_348 = and(_requestAIO_T_347, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_349 = asSInt(_requestAIO_T_348)
node _requestAIO_T_350 = eq(_requestAIO_T_349, asSInt(UInt<1>(0h0)))
node _requestAIO_T_351 = or(_requestAIO_T_340, _requestAIO_T_345)
node _requestAIO_T_352 = or(_requestAIO_T_351, _requestAIO_T_350)
node requestAIO_12_0 = or(UInt<1>(0h0), _requestAIO_T_352)
node _requestAIO_T_353 = xor(in[12].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_354 = cvt(_requestAIO_T_353)
node _requestAIO_T_355 = and(_requestAIO_T_354, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_356 = asSInt(_requestAIO_T_355)
node _requestAIO_T_357 = eq(_requestAIO_T_356, asSInt(UInt<1>(0h0)))
node _requestAIO_T_358 = xor(in[12].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_359 = cvt(_requestAIO_T_358)
node _requestAIO_T_360 = and(_requestAIO_T_359, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_361 = asSInt(_requestAIO_T_360)
node _requestAIO_T_362 = eq(_requestAIO_T_361, asSInt(UInt<1>(0h0)))
node _requestAIO_T_363 = or(_requestAIO_T_357, _requestAIO_T_362)
node requestAIO_12_1 = or(UInt<1>(0h0), _requestAIO_T_363)
node _requestAIO_T_364 = xor(in[13].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_365 = cvt(_requestAIO_T_364)
node _requestAIO_T_366 = and(_requestAIO_T_365, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_367 = asSInt(_requestAIO_T_366)
node _requestAIO_T_368 = eq(_requestAIO_T_367, asSInt(UInt<1>(0h0)))
node _requestAIO_T_369 = xor(in[13].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_370 = cvt(_requestAIO_T_369)
node _requestAIO_T_371 = and(_requestAIO_T_370, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_372 = asSInt(_requestAIO_T_371)
node _requestAIO_T_373 = eq(_requestAIO_T_372, asSInt(UInt<1>(0h0)))
node _requestAIO_T_374 = xor(in[13].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_375 = cvt(_requestAIO_T_374)
node _requestAIO_T_376 = and(_requestAIO_T_375, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_377 = asSInt(_requestAIO_T_376)
node _requestAIO_T_378 = eq(_requestAIO_T_377, asSInt(UInt<1>(0h0)))
node _requestAIO_T_379 = or(_requestAIO_T_368, _requestAIO_T_373)
node _requestAIO_T_380 = or(_requestAIO_T_379, _requestAIO_T_378)
node requestAIO_13_0 = or(UInt<1>(0h0), _requestAIO_T_380)
node _requestAIO_T_381 = xor(in[13].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_382 = cvt(_requestAIO_T_381)
node _requestAIO_T_383 = and(_requestAIO_T_382, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_384 = asSInt(_requestAIO_T_383)
node _requestAIO_T_385 = eq(_requestAIO_T_384, asSInt(UInt<1>(0h0)))
node _requestAIO_T_386 = xor(in[13].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_387 = cvt(_requestAIO_T_386)
node _requestAIO_T_388 = and(_requestAIO_T_387, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_389 = asSInt(_requestAIO_T_388)
node _requestAIO_T_390 = eq(_requestAIO_T_389, asSInt(UInt<1>(0h0)))
node _requestAIO_T_391 = or(_requestAIO_T_385, _requestAIO_T_390)
node requestAIO_13_1 = or(UInt<1>(0h0), _requestAIO_T_391)
node _requestAIO_T_392 = xor(in[14].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_393 = cvt(_requestAIO_T_392)
node _requestAIO_T_394 = and(_requestAIO_T_393, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_395 = asSInt(_requestAIO_T_394)
node _requestAIO_T_396 = eq(_requestAIO_T_395, asSInt(UInt<1>(0h0)))
node _requestAIO_T_397 = xor(in[14].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_398 = cvt(_requestAIO_T_397)
node _requestAIO_T_399 = and(_requestAIO_T_398, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_400 = asSInt(_requestAIO_T_399)
node _requestAIO_T_401 = eq(_requestAIO_T_400, asSInt(UInt<1>(0h0)))
node _requestAIO_T_402 = xor(in[14].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_403 = cvt(_requestAIO_T_402)
node _requestAIO_T_404 = and(_requestAIO_T_403, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_405 = asSInt(_requestAIO_T_404)
node _requestAIO_T_406 = eq(_requestAIO_T_405, asSInt(UInt<1>(0h0)))
node _requestAIO_T_407 = or(_requestAIO_T_396, _requestAIO_T_401)
node _requestAIO_T_408 = or(_requestAIO_T_407, _requestAIO_T_406)
node requestAIO_14_0 = or(UInt<1>(0h0), _requestAIO_T_408)
node _requestAIO_T_409 = xor(in[14].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_410 = cvt(_requestAIO_T_409)
node _requestAIO_T_411 = and(_requestAIO_T_410, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_412 = asSInt(_requestAIO_T_411)
node _requestAIO_T_413 = eq(_requestAIO_T_412, asSInt(UInt<1>(0h0)))
node _requestAIO_T_414 = xor(in[14].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_415 = cvt(_requestAIO_T_414)
node _requestAIO_T_416 = and(_requestAIO_T_415, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_417 = asSInt(_requestAIO_T_416)
node _requestAIO_T_418 = eq(_requestAIO_T_417, asSInt(UInt<1>(0h0)))
node _requestAIO_T_419 = or(_requestAIO_T_413, _requestAIO_T_418)
node requestAIO_14_1 = or(UInt<1>(0h0), _requestAIO_T_419)
node _requestAIO_T_420 = xor(in[15].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_421 = cvt(_requestAIO_T_420)
node _requestAIO_T_422 = and(_requestAIO_T_421, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_423 = asSInt(_requestAIO_T_422)
node _requestAIO_T_424 = eq(_requestAIO_T_423, asSInt(UInt<1>(0h0)))
node _requestAIO_T_425 = xor(in[15].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_426 = cvt(_requestAIO_T_425)
node _requestAIO_T_427 = and(_requestAIO_T_426, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_428 = asSInt(_requestAIO_T_427)
node _requestAIO_T_429 = eq(_requestAIO_T_428, asSInt(UInt<1>(0h0)))
node _requestAIO_T_430 = xor(in[15].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_431 = cvt(_requestAIO_T_430)
node _requestAIO_T_432 = and(_requestAIO_T_431, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_433 = asSInt(_requestAIO_T_432)
node _requestAIO_T_434 = eq(_requestAIO_T_433, asSInt(UInt<1>(0h0)))
node _requestAIO_T_435 = or(_requestAIO_T_424, _requestAIO_T_429)
node _requestAIO_T_436 = or(_requestAIO_T_435, _requestAIO_T_434)
node requestAIO_15_0 = or(UInt<1>(0h0), _requestAIO_T_436)
node _requestAIO_T_437 = xor(in[15].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_438 = cvt(_requestAIO_T_437)
node _requestAIO_T_439 = and(_requestAIO_T_438, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_440 = asSInt(_requestAIO_T_439)
node _requestAIO_T_441 = eq(_requestAIO_T_440, asSInt(UInt<1>(0h0)))
node _requestAIO_T_442 = xor(in[15].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_443 = cvt(_requestAIO_T_442)
node _requestAIO_T_444 = and(_requestAIO_T_443, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_445 = asSInt(_requestAIO_T_444)
node _requestAIO_T_446 = eq(_requestAIO_T_445, asSInt(UInt<1>(0h0)))
node _requestAIO_T_447 = or(_requestAIO_T_441, _requestAIO_T_446)
node requestAIO_15_1 = or(UInt<1>(0h0), _requestAIO_T_447)
node _requestAIO_T_448 = xor(in[16].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_449 = cvt(_requestAIO_T_448)
node _requestAIO_T_450 = and(_requestAIO_T_449, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_451 = asSInt(_requestAIO_T_450)
node _requestAIO_T_452 = eq(_requestAIO_T_451, asSInt(UInt<1>(0h0)))
node _requestAIO_T_453 = xor(in[16].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_454 = cvt(_requestAIO_T_453)
node _requestAIO_T_455 = and(_requestAIO_T_454, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_456 = asSInt(_requestAIO_T_455)
node _requestAIO_T_457 = eq(_requestAIO_T_456, asSInt(UInt<1>(0h0)))
node _requestAIO_T_458 = xor(in[16].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_459 = cvt(_requestAIO_T_458)
node _requestAIO_T_460 = and(_requestAIO_T_459, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_461 = asSInt(_requestAIO_T_460)
node _requestAIO_T_462 = eq(_requestAIO_T_461, asSInt(UInt<1>(0h0)))
node _requestAIO_T_463 = or(_requestAIO_T_452, _requestAIO_T_457)
node _requestAIO_T_464 = or(_requestAIO_T_463, _requestAIO_T_462)
node requestAIO_16_0 = or(UInt<1>(0h0), _requestAIO_T_464)
node _requestAIO_T_465 = xor(in[16].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_466 = cvt(_requestAIO_T_465)
node _requestAIO_T_467 = and(_requestAIO_T_466, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_468 = asSInt(_requestAIO_T_467)
node _requestAIO_T_469 = eq(_requestAIO_T_468, asSInt(UInt<1>(0h0)))
node _requestAIO_T_470 = xor(in[16].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_471 = cvt(_requestAIO_T_470)
node _requestAIO_T_472 = and(_requestAIO_T_471, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_473 = asSInt(_requestAIO_T_472)
node _requestAIO_T_474 = eq(_requestAIO_T_473, asSInt(UInt<1>(0h0)))
node _requestAIO_T_475 = or(_requestAIO_T_469, _requestAIO_T_474)
node requestAIO_16_1 = or(UInt<1>(0h0), _requestAIO_T_475)
node _requestAIO_T_476 = xor(in[17].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_477 = cvt(_requestAIO_T_476)
node _requestAIO_T_478 = and(_requestAIO_T_477, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_479 = asSInt(_requestAIO_T_478)
node _requestAIO_T_480 = eq(_requestAIO_T_479, asSInt(UInt<1>(0h0)))
node _requestAIO_T_481 = xor(in[17].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_482 = cvt(_requestAIO_T_481)
node _requestAIO_T_483 = and(_requestAIO_T_482, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_484 = asSInt(_requestAIO_T_483)
node _requestAIO_T_485 = eq(_requestAIO_T_484, asSInt(UInt<1>(0h0)))
node _requestAIO_T_486 = xor(in[17].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_487 = cvt(_requestAIO_T_486)
node _requestAIO_T_488 = and(_requestAIO_T_487, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_489 = asSInt(_requestAIO_T_488)
node _requestAIO_T_490 = eq(_requestAIO_T_489, asSInt(UInt<1>(0h0)))
node _requestAIO_T_491 = or(_requestAIO_T_480, _requestAIO_T_485)
node _requestAIO_T_492 = or(_requestAIO_T_491, _requestAIO_T_490)
node requestAIO_17_0 = or(UInt<1>(0h0), _requestAIO_T_492)
node _requestAIO_T_493 = xor(in[17].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_494 = cvt(_requestAIO_T_493)
node _requestAIO_T_495 = and(_requestAIO_T_494, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_496 = asSInt(_requestAIO_T_495)
node _requestAIO_T_497 = eq(_requestAIO_T_496, asSInt(UInt<1>(0h0)))
node _requestAIO_T_498 = xor(in[17].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_499 = cvt(_requestAIO_T_498)
node _requestAIO_T_500 = and(_requestAIO_T_499, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_501 = asSInt(_requestAIO_T_500)
node _requestAIO_T_502 = eq(_requestAIO_T_501, asSInt(UInt<1>(0h0)))
node _requestAIO_T_503 = or(_requestAIO_T_497, _requestAIO_T_502)
node requestAIO_17_1 = or(UInt<1>(0h0), _requestAIO_T_503)
node _requestAIO_T_504 = xor(in[18].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_505 = cvt(_requestAIO_T_504)
node _requestAIO_T_506 = and(_requestAIO_T_505, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_507 = asSInt(_requestAIO_T_506)
node _requestAIO_T_508 = eq(_requestAIO_T_507, asSInt(UInt<1>(0h0)))
node _requestAIO_T_509 = xor(in[18].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_510 = cvt(_requestAIO_T_509)
node _requestAIO_T_511 = and(_requestAIO_T_510, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_512 = asSInt(_requestAIO_T_511)
node _requestAIO_T_513 = eq(_requestAIO_T_512, asSInt(UInt<1>(0h0)))
node _requestAIO_T_514 = xor(in[18].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_515 = cvt(_requestAIO_T_514)
node _requestAIO_T_516 = and(_requestAIO_T_515, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_517 = asSInt(_requestAIO_T_516)
node _requestAIO_T_518 = eq(_requestAIO_T_517, asSInt(UInt<1>(0h0)))
node _requestAIO_T_519 = or(_requestAIO_T_508, _requestAIO_T_513)
node _requestAIO_T_520 = or(_requestAIO_T_519, _requestAIO_T_518)
node requestAIO_18_0 = or(UInt<1>(0h0), _requestAIO_T_520)
node _requestAIO_T_521 = xor(in[18].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_522 = cvt(_requestAIO_T_521)
node _requestAIO_T_523 = and(_requestAIO_T_522, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_524 = asSInt(_requestAIO_T_523)
node _requestAIO_T_525 = eq(_requestAIO_T_524, asSInt(UInt<1>(0h0)))
node _requestAIO_T_526 = xor(in[18].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_527 = cvt(_requestAIO_T_526)
node _requestAIO_T_528 = and(_requestAIO_T_527, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_529 = asSInt(_requestAIO_T_528)
node _requestAIO_T_530 = eq(_requestAIO_T_529, asSInt(UInt<1>(0h0)))
node _requestAIO_T_531 = or(_requestAIO_T_525, _requestAIO_T_530)
node requestAIO_18_1 = or(UInt<1>(0h0), _requestAIO_T_531)
node _requestAIO_T_532 = xor(in[19].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_533 = cvt(_requestAIO_T_532)
node _requestAIO_T_534 = and(_requestAIO_T_533, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_535 = asSInt(_requestAIO_T_534)
node _requestAIO_T_536 = eq(_requestAIO_T_535, asSInt(UInt<1>(0h0)))
node _requestAIO_T_537 = xor(in[19].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_538 = cvt(_requestAIO_T_537)
node _requestAIO_T_539 = and(_requestAIO_T_538, asSInt(UInt<33>(0h8c011000)))
node _requestAIO_T_540 = asSInt(_requestAIO_T_539)
node _requestAIO_T_541 = eq(_requestAIO_T_540, asSInt(UInt<1>(0h0)))
node _requestAIO_T_542 = xor(in[19].a.bits.address, UInt<28>(0hc000000))
node _requestAIO_T_543 = cvt(_requestAIO_T_542)
node _requestAIO_T_544 = and(_requestAIO_T_543, asSInt(UInt<33>(0h8c000000)))
node _requestAIO_T_545 = asSInt(_requestAIO_T_544)
node _requestAIO_T_546 = eq(_requestAIO_T_545, asSInt(UInt<1>(0h0)))
node _requestAIO_T_547 = or(_requestAIO_T_536, _requestAIO_T_541)
node _requestAIO_T_548 = or(_requestAIO_T_547, _requestAIO_T_546)
node requestAIO_19_0 = or(UInt<1>(0h0), _requestAIO_T_548)
node _requestAIO_T_549 = xor(in[19].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_550 = cvt(_requestAIO_T_549)
node _requestAIO_T_551 = and(_requestAIO_T_550, asSInt(UInt<33>(0h8c010000)))
node _requestAIO_T_552 = asSInt(_requestAIO_T_551)
node _requestAIO_T_553 = eq(_requestAIO_T_552, asSInt(UInt<1>(0h0)))
node _requestAIO_T_554 = xor(in[19].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_555 = cvt(_requestAIO_T_554)
node _requestAIO_T_556 = and(_requestAIO_T_555, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_557 = asSInt(_requestAIO_T_556)
node _requestAIO_T_558 = eq(_requestAIO_T_557, asSInt(UInt<1>(0h0)))
node _requestAIO_T_559 = or(_requestAIO_T_553, _requestAIO_T_558)
node requestAIO_19_1 = or(UInt<1>(0h0), _requestAIO_T_559)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestCIO_T_20 = xor(in[2].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_21 = cvt(_requestCIO_T_20)
node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0)))
node _requestCIO_T_23 = asSInt(_requestCIO_T_22)
node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0)))
node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_24)
node _requestCIO_T_25 = xor(in[2].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_26 = cvt(_requestCIO_T_25)
node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0)))
node _requestCIO_T_28 = asSInt(_requestCIO_T_27)
node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0)))
node requestCIO_2_1 = or(UInt<1>(0h1), _requestCIO_T_29)
node _requestCIO_T_30 = xor(in[3].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_31 = cvt(_requestCIO_T_30)
node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0)))
node _requestCIO_T_33 = asSInt(_requestCIO_T_32)
node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0)))
node requestCIO_3_0 = or(UInt<1>(0h1), _requestCIO_T_34)
node _requestCIO_T_35 = xor(in[3].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_36 = cvt(_requestCIO_T_35)
node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0)))
node _requestCIO_T_38 = asSInt(_requestCIO_T_37)
node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0)))
node requestCIO_3_1 = or(UInt<1>(0h1), _requestCIO_T_39)
node _requestCIO_T_40 = xor(in[4].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_41 = cvt(_requestCIO_T_40)
node _requestCIO_T_42 = and(_requestCIO_T_41, asSInt(UInt<1>(0h0)))
node _requestCIO_T_43 = asSInt(_requestCIO_T_42)
node _requestCIO_T_44 = eq(_requestCIO_T_43, asSInt(UInt<1>(0h0)))
node requestCIO_4_0 = or(UInt<1>(0h1), _requestCIO_T_44)
node _requestCIO_T_45 = xor(in[4].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_46 = cvt(_requestCIO_T_45)
node _requestCIO_T_47 = and(_requestCIO_T_46, asSInt(UInt<1>(0h0)))
node _requestCIO_T_48 = asSInt(_requestCIO_T_47)
node _requestCIO_T_49 = eq(_requestCIO_T_48, asSInt(UInt<1>(0h0)))
node requestCIO_4_1 = or(UInt<1>(0h1), _requestCIO_T_49)
node _requestCIO_T_50 = xor(in[5].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_51 = cvt(_requestCIO_T_50)
node _requestCIO_T_52 = and(_requestCIO_T_51, asSInt(UInt<1>(0h0)))
node _requestCIO_T_53 = asSInt(_requestCIO_T_52)
node _requestCIO_T_54 = eq(_requestCIO_T_53, asSInt(UInt<1>(0h0)))
node requestCIO_5_0 = or(UInt<1>(0h1), _requestCIO_T_54)
node _requestCIO_T_55 = xor(in[5].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_56 = cvt(_requestCIO_T_55)
node _requestCIO_T_57 = and(_requestCIO_T_56, asSInt(UInt<1>(0h0)))
node _requestCIO_T_58 = asSInt(_requestCIO_T_57)
node _requestCIO_T_59 = eq(_requestCIO_T_58, asSInt(UInt<1>(0h0)))
node requestCIO_5_1 = or(UInt<1>(0h1), _requestCIO_T_59)
node _requestCIO_T_60 = xor(in[6].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_61 = cvt(_requestCIO_T_60)
node _requestCIO_T_62 = and(_requestCIO_T_61, asSInt(UInt<1>(0h0)))
node _requestCIO_T_63 = asSInt(_requestCIO_T_62)
node _requestCIO_T_64 = eq(_requestCIO_T_63, asSInt(UInt<1>(0h0)))
node requestCIO_6_0 = or(UInt<1>(0h1), _requestCIO_T_64)
node _requestCIO_T_65 = xor(in[6].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_66 = cvt(_requestCIO_T_65)
node _requestCIO_T_67 = and(_requestCIO_T_66, asSInt(UInt<1>(0h0)))
node _requestCIO_T_68 = asSInt(_requestCIO_T_67)
node _requestCIO_T_69 = eq(_requestCIO_T_68, asSInt(UInt<1>(0h0)))
node requestCIO_6_1 = or(UInt<1>(0h1), _requestCIO_T_69)
node _requestCIO_T_70 = xor(in[7].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_71 = cvt(_requestCIO_T_70)
node _requestCIO_T_72 = and(_requestCIO_T_71, asSInt(UInt<1>(0h0)))
node _requestCIO_T_73 = asSInt(_requestCIO_T_72)
node _requestCIO_T_74 = eq(_requestCIO_T_73, asSInt(UInt<1>(0h0)))
node requestCIO_7_0 = or(UInt<1>(0h1), _requestCIO_T_74)
node _requestCIO_T_75 = xor(in[7].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_76 = cvt(_requestCIO_T_75)
node _requestCIO_T_77 = and(_requestCIO_T_76, asSInt(UInt<1>(0h0)))
node _requestCIO_T_78 = asSInt(_requestCIO_T_77)
node _requestCIO_T_79 = eq(_requestCIO_T_78, asSInt(UInt<1>(0h0)))
node requestCIO_7_1 = or(UInt<1>(0h1), _requestCIO_T_79)
node _requestCIO_T_80 = xor(in[8].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_81 = cvt(_requestCIO_T_80)
node _requestCIO_T_82 = and(_requestCIO_T_81, asSInt(UInt<1>(0h0)))
node _requestCIO_T_83 = asSInt(_requestCIO_T_82)
node _requestCIO_T_84 = eq(_requestCIO_T_83, asSInt(UInt<1>(0h0)))
node requestCIO_8_0 = or(UInt<1>(0h1), _requestCIO_T_84)
node _requestCIO_T_85 = xor(in[8].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_86 = cvt(_requestCIO_T_85)
node _requestCIO_T_87 = and(_requestCIO_T_86, asSInt(UInt<1>(0h0)))
node _requestCIO_T_88 = asSInt(_requestCIO_T_87)
node _requestCIO_T_89 = eq(_requestCIO_T_88, asSInt(UInt<1>(0h0)))
node requestCIO_8_1 = or(UInt<1>(0h1), _requestCIO_T_89)
node _requestCIO_T_90 = xor(in[9].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_91 = cvt(_requestCIO_T_90)
node _requestCIO_T_92 = and(_requestCIO_T_91, asSInt(UInt<1>(0h0)))
node _requestCIO_T_93 = asSInt(_requestCIO_T_92)
node _requestCIO_T_94 = eq(_requestCIO_T_93, asSInt(UInt<1>(0h0)))
node requestCIO_9_0 = or(UInt<1>(0h1), _requestCIO_T_94)
node _requestCIO_T_95 = xor(in[9].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_96 = cvt(_requestCIO_T_95)
node _requestCIO_T_97 = and(_requestCIO_T_96, asSInt(UInt<1>(0h0)))
node _requestCIO_T_98 = asSInt(_requestCIO_T_97)
node _requestCIO_T_99 = eq(_requestCIO_T_98, asSInt(UInt<1>(0h0)))
node requestCIO_9_1 = or(UInt<1>(0h1), _requestCIO_T_99)
node _requestCIO_T_100 = xor(in[10].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_101 = cvt(_requestCIO_T_100)
node _requestCIO_T_102 = and(_requestCIO_T_101, asSInt(UInt<1>(0h0)))
node _requestCIO_T_103 = asSInt(_requestCIO_T_102)
node _requestCIO_T_104 = eq(_requestCIO_T_103, asSInt(UInt<1>(0h0)))
node requestCIO_10_0 = or(UInt<1>(0h1), _requestCIO_T_104)
node _requestCIO_T_105 = xor(in[10].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_106 = cvt(_requestCIO_T_105)
node _requestCIO_T_107 = and(_requestCIO_T_106, asSInt(UInt<1>(0h0)))
node _requestCIO_T_108 = asSInt(_requestCIO_T_107)
node _requestCIO_T_109 = eq(_requestCIO_T_108, asSInt(UInt<1>(0h0)))
node requestCIO_10_1 = or(UInt<1>(0h1), _requestCIO_T_109)
node _requestCIO_T_110 = xor(in[11].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_111 = cvt(_requestCIO_T_110)
node _requestCIO_T_112 = and(_requestCIO_T_111, asSInt(UInt<1>(0h0)))
node _requestCIO_T_113 = asSInt(_requestCIO_T_112)
node _requestCIO_T_114 = eq(_requestCIO_T_113, asSInt(UInt<1>(0h0)))
node requestCIO_11_0 = or(UInt<1>(0h1), _requestCIO_T_114)
node _requestCIO_T_115 = xor(in[11].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_116 = cvt(_requestCIO_T_115)
node _requestCIO_T_117 = and(_requestCIO_T_116, asSInt(UInt<1>(0h0)))
node _requestCIO_T_118 = asSInt(_requestCIO_T_117)
node _requestCIO_T_119 = eq(_requestCIO_T_118, asSInt(UInt<1>(0h0)))
node requestCIO_11_1 = or(UInt<1>(0h1), _requestCIO_T_119)
node _requestCIO_T_120 = xor(in[12].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_121 = cvt(_requestCIO_T_120)
node _requestCIO_T_122 = and(_requestCIO_T_121, asSInt(UInt<1>(0h0)))
node _requestCIO_T_123 = asSInt(_requestCIO_T_122)
node _requestCIO_T_124 = eq(_requestCIO_T_123, asSInt(UInt<1>(0h0)))
node requestCIO_12_0 = or(UInt<1>(0h1), _requestCIO_T_124)
node _requestCIO_T_125 = xor(in[12].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_126 = cvt(_requestCIO_T_125)
node _requestCIO_T_127 = and(_requestCIO_T_126, asSInt(UInt<1>(0h0)))
node _requestCIO_T_128 = asSInt(_requestCIO_T_127)
node _requestCIO_T_129 = eq(_requestCIO_T_128, asSInt(UInt<1>(0h0)))
node requestCIO_12_1 = or(UInt<1>(0h1), _requestCIO_T_129)
node _requestCIO_T_130 = xor(in[13].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_131 = cvt(_requestCIO_T_130)
node _requestCIO_T_132 = and(_requestCIO_T_131, asSInt(UInt<1>(0h0)))
node _requestCIO_T_133 = asSInt(_requestCIO_T_132)
node _requestCIO_T_134 = eq(_requestCIO_T_133, asSInt(UInt<1>(0h0)))
node requestCIO_13_0 = or(UInt<1>(0h1), _requestCIO_T_134)
node _requestCIO_T_135 = xor(in[13].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_136 = cvt(_requestCIO_T_135)
node _requestCIO_T_137 = and(_requestCIO_T_136, asSInt(UInt<1>(0h0)))
node _requestCIO_T_138 = asSInt(_requestCIO_T_137)
node _requestCIO_T_139 = eq(_requestCIO_T_138, asSInt(UInt<1>(0h0)))
node requestCIO_13_1 = or(UInt<1>(0h1), _requestCIO_T_139)
node _requestCIO_T_140 = xor(in[14].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_141 = cvt(_requestCIO_T_140)
node _requestCIO_T_142 = and(_requestCIO_T_141, asSInt(UInt<1>(0h0)))
node _requestCIO_T_143 = asSInt(_requestCIO_T_142)
node _requestCIO_T_144 = eq(_requestCIO_T_143, asSInt(UInt<1>(0h0)))
node requestCIO_14_0 = or(UInt<1>(0h1), _requestCIO_T_144)
node _requestCIO_T_145 = xor(in[14].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_146 = cvt(_requestCIO_T_145)
node _requestCIO_T_147 = and(_requestCIO_T_146, asSInt(UInt<1>(0h0)))
node _requestCIO_T_148 = asSInt(_requestCIO_T_147)
node _requestCIO_T_149 = eq(_requestCIO_T_148, asSInt(UInt<1>(0h0)))
node requestCIO_14_1 = or(UInt<1>(0h1), _requestCIO_T_149)
node _requestCIO_T_150 = xor(in[15].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_151 = cvt(_requestCIO_T_150)
node _requestCIO_T_152 = and(_requestCIO_T_151, asSInt(UInt<1>(0h0)))
node _requestCIO_T_153 = asSInt(_requestCIO_T_152)
node _requestCIO_T_154 = eq(_requestCIO_T_153, asSInt(UInt<1>(0h0)))
node requestCIO_15_0 = or(UInt<1>(0h1), _requestCIO_T_154)
node _requestCIO_T_155 = xor(in[15].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_156 = cvt(_requestCIO_T_155)
node _requestCIO_T_157 = and(_requestCIO_T_156, asSInt(UInt<1>(0h0)))
node _requestCIO_T_158 = asSInt(_requestCIO_T_157)
node _requestCIO_T_159 = eq(_requestCIO_T_158, asSInt(UInt<1>(0h0)))
node requestCIO_15_1 = or(UInt<1>(0h1), _requestCIO_T_159)
node _requestCIO_T_160 = xor(in[16].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_161 = cvt(_requestCIO_T_160)
node _requestCIO_T_162 = and(_requestCIO_T_161, asSInt(UInt<1>(0h0)))
node _requestCIO_T_163 = asSInt(_requestCIO_T_162)
node _requestCIO_T_164 = eq(_requestCIO_T_163, asSInt(UInt<1>(0h0)))
node requestCIO_16_0 = or(UInt<1>(0h1), _requestCIO_T_164)
node _requestCIO_T_165 = xor(in[16].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_166 = cvt(_requestCIO_T_165)
node _requestCIO_T_167 = and(_requestCIO_T_166, asSInt(UInt<1>(0h0)))
node _requestCIO_T_168 = asSInt(_requestCIO_T_167)
node _requestCIO_T_169 = eq(_requestCIO_T_168, asSInt(UInt<1>(0h0)))
node requestCIO_16_1 = or(UInt<1>(0h1), _requestCIO_T_169)
node _requestCIO_T_170 = xor(in[17].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_171 = cvt(_requestCIO_T_170)
node _requestCIO_T_172 = and(_requestCIO_T_171, asSInt(UInt<1>(0h0)))
node _requestCIO_T_173 = asSInt(_requestCIO_T_172)
node _requestCIO_T_174 = eq(_requestCIO_T_173, asSInt(UInt<1>(0h0)))
node requestCIO_17_0 = or(UInt<1>(0h1), _requestCIO_T_174)
node _requestCIO_T_175 = xor(in[17].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_176 = cvt(_requestCIO_T_175)
node _requestCIO_T_177 = and(_requestCIO_T_176, asSInt(UInt<1>(0h0)))
node _requestCIO_T_178 = asSInt(_requestCIO_T_177)
node _requestCIO_T_179 = eq(_requestCIO_T_178, asSInt(UInt<1>(0h0)))
node requestCIO_17_1 = or(UInt<1>(0h1), _requestCIO_T_179)
node _requestCIO_T_180 = xor(in[18].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_181 = cvt(_requestCIO_T_180)
node _requestCIO_T_182 = and(_requestCIO_T_181, asSInt(UInt<1>(0h0)))
node _requestCIO_T_183 = asSInt(_requestCIO_T_182)
node _requestCIO_T_184 = eq(_requestCIO_T_183, asSInt(UInt<1>(0h0)))
node requestCIO_18_0 = or(UInt<1>(0h1), _requestCIO_T_184)
node _requestCIO_T_185 = xor(in[18].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_186 = cvt(_requestCIO_T_185)
node _requestCIO_T_187 = and(_requestCIO_T_186, asSInt(UInt<1>(0h0)))
node _requestCIO_T_188 = asSInt(_requestCIO_T_187)
node _requestCIO_T_189 = eq(_requestCIO_T_188, asSInt(UInt<1>(0h0)))
node requestCIO_18_1 = or(UInt<1>(0h1), _requestCIO_T_189)
node _requestCIO_T_190 = xor(in[19].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_191 = cvt(_requestCIO_T_190)
node _requestCIO_T_192 = and(_requestCIO_T_191, asSInt(UInt<1>(0h0)))
node _requestCIO_T_193 = asSInt(_requestCIO_T_192)
node _requestCIO_T_194 = eq(_requestCIO_T_193, asSInt(UInt<1>(0h0)))
node requestCIO_19_0 = or(UInt<1>(0h1), _requestCIO_T_194)
node _requestCIO_T_195 = xor(in[19].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_196 = cvt(_requestCIO_T_195)
node _requestCIO_T_197 = and(_requestCIO_T_196, asSInt(UInt<1>(0h0)))
node _requestCIO_T_198 = asSInt(_requestCIO_T_197)
node _requestCIO_T_199 = eq(_requestCIO_T_198, asSInt(UInt<1>(0h0)))
node requestCIO_19_1 = or(UInt<1>(0h1), _requestCIO_T_199)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<4>(0he))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0)
node _requestBOI_T_5 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<7>(0h7c))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestBOI_uncommonBits_T_2 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 1, 0)
node _requestBOI_T_10 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<7>(0h7b))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<2>(0h3))
node requestBOI_0_2 = and(_requestBOI_T_13, _requestBOI_T_14)
node _requestBOI_uncommonBits_T_3 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 4, 0)
node _requestBOI_T_15 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<4>(0hd))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<5>(0h1f))
node requestBOI_0_3 = and(_requestBOI_T_18, _requestBOI_T_19)
node _requestBOI_uncommonBits_T_4 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 4, 0)
node _requestBOI_T_20 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<4>(0hc))
node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4)
node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22)
node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<5>(0h1f))
node requestBOI_0_4 = and(_requestBOI_T_23, _requestBOI_T_24)
node _requestBOI_uncommonBits_T_5 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 4, 0)
node _requestBOI_T_25 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<4>(0hb))
node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5)
node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27)
node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<5>(0h1f))
node requestBOI_0_5 = and(_requestBOI_T_28, _requestBOI_T_29)
node _requestBOI_uncommonBits_T_6 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 4, 0)
node _requestBOI_T_30 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<4>(0ha))
node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6)
node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32)
node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<5>(0h1f))
node requestBOI_0_6 = and(_requestBOI_T_33, _requestBOI_T_34)
node _requestBOI_uncommonBits_T_7 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 4, 0)
node _requestBOI_T_35 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<4>(0h9))
node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7)
node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37)
node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<5>(0h1f))
node requestBOI_0_7 = and(_requestBOI_T_38, _requestBOI_T_39)
node _requestBOI_uncommonBits_T_8 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_8 = bits(_requestBOI_uncommonBits_T_8, 4, 0)
node _requestBOI_T_40 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_41 = eq(_requestBOI_T_40, UInt<4>(0h8))
node _requestBOI_T_42 = leq(UInt<1>(0h0), requestBOI_uncommonBits_8)
node _requestBOI_T_43 = and(_requestBOI_T_41, _requestBOI_T_42)
node _requestBOI_T_44 = leq(requestBOI_uncommonBits_8, UInt<5>(0h1f))
node requestBOI_0_8 = and(_requestBOI_T_43, _requestBOI_T_44)
node _requestBOI_uncommonBits_T_9 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_9 = bits(_requestBOI_uncommonBits_T_9, 1, 0)
node _requestBOI_T_45 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_46 = eq(_requestBOI_T_45, UInt<7>(0h7a))
node _requestBOI_T_47 = leq(UInt<1>(0h0), requestBOI_uncommonBits_9)
node _requestBOI_T_48 = and(_requestBOI_T_46, _requestBOI_T_47)
node _requestBOI_T_49 = leq(requestBOI_uncommonBits_9, UInt<2>(0h3))
node requestBOI_0_9 = and(_requestBOI_T_48, _requestBOI_T_49)
node _requestBOI_uncommonBits_T_10 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_10 = bits(_requestBOI_uncommonBits_T_10, 1, 0)
node _requestBOI_T_50 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_51 = eq(_requestBOI_T_50, UInt<7>(0h79))
node _requestBOI_T_52 = leq(UInt<1>(0h0), requestBOI_uncommonBits_10)
node _requestBOI_T_53 = and(_requestBOI_T_51, _requestBOI_T_52)
node _requestBOI_T_54 = leq(requestBOI_uncommonBits_10, UInt<2>(0h3))
node requestBOI_0_10 = and(_requestBOI_T_53, _requestBOI_T_54)
node _requestBOI_uncommonBits_T_11 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_11 = bits(_requestBOI_uncommonBits_T_11, 4, 0)
node _requestBOI_T_55 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_56 = eq(_requestBOI_T_55, UInt<3>(0h7))
node _requestBOI_T_57 = leq(UInt<1>(0h0), requestBOI_uncommonBits_11)
node _requestBOI_T_58 = and(_requestBOI_T_56, _requestBOI_T_57)
node _requestBOI_T_59 = leq(requestBOI_uncommonBits_11, UInt<5>(0h1f))
node requestBOI_0_11 = and(_requestBOI_T_58, _requestBOI_T_59)
node _requestBOI_uncommonBits_T_12 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_12 = bits(_requestBOI_uncommonBits_T_12, 4, 0)
node _requestBOI_T_60 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_61 = eq(_requestBOI_T_60, UInt<3>(0h6))
node _requestBOI_T_62 = leq(UInt<1>(0h0), requestBOI_uncommonBits_12)
node _requestBOI_T_63 = and(_requestBOI_T_61, _requestBOI_T_62)
node _requestBOI_T_64 = leq(requestBOI_uncommonBits_12, UInt<5>(0h1f))
node requestBOI_0_12 = and(_requestBOI_T_63, _requestBOI_T_64)
node _requestBOI_uncommonBits_T_13 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_13 = bits(_requestBOI_uncommonBits_T_13, 4, 0)
node _requestBOI_T_65 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_66 = eq(_requestBOI_T_65, UInt<3>(0h5))
node _requestBOI_T_67 = leq(UInt<1>(0h0), requestBOI_uncommonBits_13)
node _requestBOI_T_68 = and(_requestBOI_T_66, _requestBOI_T_67)
node _requestBOI_T_69 = leq(requestBOI_uncommonBits_13, UInt<5>(0h1f))
node requestBOI_0_13 = and(_requestBOI_T_68, _requestBOI_T_69)
node _requestBOI_uncommonBits_T_14 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_14 = bits(_requestBOI_uncommonBits_T_14, 4, 0)
node _requestBOI_T_70 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_71 = eq(_requestBOI_T_70, UInt<3>(0h4))
node _requestBOI_T_72 = leq(UInt<1>(0h0), requestBOI_uncommonBits_14)
node _requestBOI_T_73 = and(_requestBOI_T_71, _requestBOI_T_72)
node _requestBOI_T_74 = leq(requestBOI_uncommonBits_14, UInt<5>(0h1f))
node requestBOI_0_14 = and(_requestBOI_T_73, _requestBOI_T_74)
node _requestBOI_uncommonBits_T_15 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_15 = bits(_requestBOI_uncommonBits_T_15, 4, 0)
node _requestBOI_T_75 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_76 = eq(_requestBOI_T_75, UInt<2>(0h3))
node _requestBOI_T_77 = leq(UInt<1>(0h0), requestBOI_uncommonBits_15)
node _requestBOI_T_78 = and(_requestBOI_T_76, _requestBOI_T_77)
node _requestBOI_T_79 = leq(requestBOI_uncommonBits_15, UInt<5>(0h1f))
node requestBOI_0_15 = and(_requestBOI_T_78, _requestBOI_T_79)
node _requestBOI_uncommonBits_T_16 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_16 = bits(_requestBOI_uncommonBits_T_16, 4, 0)
node _requestBOI_T_80 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_81 = eq(_requestBOI_T_80, UInt<2>(0h2))
node _requestBOI_T_82 = leq(UInt<1>(0h0), requestBOI_uncommonBits_16)
node _requestBOI_T_83 = and(_requestBOI_T_81, _requestBOI_T_82)
node _requestBOI_T_84 = leq(requestBOI_uncommonBits_16, UInt<5>(0h1f))
node requestBOI_0_16 = and(_requestBOI_T_83, _requestBOI_T_84)
node _requestBOI_uncommonBits_T_17 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_17 = bits(_requestBOI_uncommonBits_T_17, 4, 0)
node _requestBOI_T_85 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_86 = eq(_requestBOI_T_85, UInt<1>(0h1))
node _requestBOI_T_87 = leq(UInt<1>(0h0), requestBOI_uncommonBits_17)
node _requestBOI_T_88 = and(_requestBOI_T_86, _requestBOI_T_87)
node _requestBOI_T_89 = leq(requestBOI_uncommonBits_17, UInt<5>(0h1f))
node requestBOI_0_17 = and(_requestBOI_T_88, _requestBOI_T_89)
node _requestBOI_uncommonBits_T_18 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_18 = bits(_requestBOI_uncommonBits_T_18, 4, 0)
node _requestBOI_T_90 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_91 = eq(_requestBOI_T_90, UInt<1>(0h0))
node _requestBOI_T_92 = leq(UInt<1>(0h0), requestBOI_uncommonBits_18)
node _requestBOI_T_93 = and(_requestBOI_T_91, _requestBOI_T_92)
node _requestBOI_T_94 = leq(requestBOI_uncommonBits_18, UInt<5>(0h1f))
node requestBOI_0_18 = and(_requestBOI_T_93, _requestBOI_T_94)
node _requestBOI_uncommonBits_T_19 = or(out[0].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_19 = bits(_requestBOI_uncommonBits_T_19, 1, 0)
node _requestBOI_T_95 = shr(out[0].b.bits.source, 2)
node _requestBOI_T_96 = eq(_requestBOI_T_95, UInt<7>(0h78))
node _requestBOI_T_97 = leq(UInt<1>(0h0), requestBOI_uncommonBits_19)
node _requestBOI_T_98 = and(_requestBOI_T_96, _requestBOI_T_97)
node _requestBOI_T_99 = leq(requestBOI_uncommonBits_19, UInt<2>(0h3))
node requestBOI_0_19 = and(_requestBOI_T_98, _requestBOI_T_99)
node _requestBOI_uncommonBits_T_20 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_20 = bits(_requestBOI_uncommonBits_T_20, 4, 0)
node _requestBOI_T_100 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_101 = eq(_requestBOI_T_100, UInt<4>(0he))
node _requestBOI_T_102 = leq(UInt<1>(0h0), requestBOI_uncommonBits_20)
node _requestBOI_T_103 = and(_requestBOI_T_101, _requestBOI_T_102)
node _requestBOI_T_104 = leq(requestBOI_uncommonBits_20, UInt<5>(0h1f))
node requestBOI_1_0 = and(_requestBOI_T_103, _requestBOI_T_104)
node _requestBOI_uncommonBits_T_21 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_21 = bits(_requestBOI_uncommonBits_T_21, 1, 0)
node _requestBOI_T_105 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_106 = eq(_requestBOI_T_105, UInt<7>(0h7c))
node _requestBOI_T_107 = leq(UInt<1>(0h0), requestBOI_uncommonBits_21)
node _requestBOI_T_108 = and(_requestBOI_T_106, _requestBOI_T_107)
node _requestBOI_T_109 = leq(requestBOI_uncommonBits_21, UInt<2>(0h3))
node requestBOI_1_1 = and(_requestBOI_T_108, _requestBOI_T_109)
node _requestBOI_uncommonBits_T_22 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_22 = bits(_requestBOI_uncommonBits_T_22, 1, 0)
node _requestBOI_T_110 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_111 = eq(_requestBOI_T_110, UInt<7>(0h7b))
node _requestBOI_T_112 = leq(UInt<1>(0h0), requestBOI_uncommonBits_22)
node _requestBOI_T_113 = and(_requestBOI_T_111, _requestBOI_T_112)
node _requestBOI_T_114 = leq(requestBOI_uncommonBits_22, UInt<2>(0h3))
node requestBOI_1_2 = and(_requestBOI_T_113, _requestBOI_T_114)
node _requestBOI_uncommonBits_T_23 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_23 = bits(_requestBOI_uncommonBits_T_23, 4, 0)
node _requestBOI_T_115 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_116 = eq(_requestBOI_T_115, UInt<4>(0hd))
node _requestBOI_T_117 = leq(UInt<1>(0h0), requestBOI_uncommonBits_23)
node _requestBOI_T_118 = and(_requestBOI_T_116, _requestBOI_T_117)
node _requestBOI_T_119 = leq(requestBOI_uncommonBits_23, UInt<5>(0h1f))
node requestBOI_1_3 = and(_requestBOI_T_118, _requestBOI_T_119)
node _requestBOI_uncommonBits_T_24 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_24 = bits(_requestBOI_uncommonBits_T_24, 4, 0)
node _requestBOI_T_120 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_121 = eq(_requestBOI_T_120, UInt<4>(0hc))
node _requestBOI_T_122 = leq(UInt<1>(0h0), requestBOI_uncommonBits_24)
node _requestBOI_T_123 = and(_requestBOI_T_121, _requestBOI_T_122)
node _requestBOI_T_124 = leq(requestBOI_uncommonBits_24, UInt<5>(0h1f))
node requestBOI_1_4 = and(_requestBOI_T_123, _requestBOI_T_124)
node _requestBOI_uncommonBits_T_25 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_25 = bits(_requestBOI_uncommonBits_T_25, 4, 0)
node _requestBOI_T_125 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_126 = eq(_requestBOI_T_125, UInt<4>(0hb))
node _requestBOI_T_127 = leq(UInt<1>(0h0), requestBOI_uncommonBits_25)
node _requestBOI_T_128 = and(_requestBOI_T_126, _requestBOI_T_127)
node _requestBOI_T_129 = leq(requestBOI_uncommonBits_25, UInt<5>(0h1f))
node requestBOI_1_5 = and(_requestBOI_T_128, _requestBOI_T_129)
node _requestBOI_uncommonBits_T_26 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_26 = bits(_requestBOI_uncommonBits_T_26, 4, 0)
node _requestBOI_T_130 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_131 = eq(_requestBOI_T_130, UInt<4>(0ha))
node _requestBOI_T_132 = leq(UInt<1>(0h0), requestBOI_uncommonBits_26)
node _requestBOI_T_133 = and(_requestBOI_T_131, _requestBOI_T_132)
node _requestBOI_T_134 = leq(requestBOI_uncommonBits_26, UInt<5>(0h1f))
node requestBOI_1_6 = and(_requestBOI_T_133, _requestBOI_T_134)
node _requestBOI_uncommonBits_T_27 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_27 = bits(_requestBOI_uncommonBits_T_27, 4, 0)
node _requestBOI_T_135 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_136 = eq(_requestBOI_T_135, UInt<4>(0h9))
node _requestBOI_T_137 = leq(UInt<1>(0h0), requestBOI_uncommonBits_27)
node _requestBOI_T_138 = and(_requestBOI_T_136, _requestBOI_T_137)
node _requestBOI_T_139 = leq(requestBOI_uncommonBits_27, UInt<5>(0h1f))
node requestBOI_1_7 = and(_requestBOI_T_138, _requestBOI_T_139)
node _requestBOI_uncommonBits_T_28 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_28 = bits(_requestBOI_uncommonBits_T_28, 4, 0)
node _requestBOI_T_140 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_141 = eq(_requestBOI_T_140, UInt<4>(0h8))
node _requestBOI_T_142 = leq(UInt<1>(0h0), requestBOI_uncommonBits_28)
node _requestBOI_T_143 = and(_requestBOI_T_141, _requestBOI_T_142)
node _requestBOI_T_144 = leq(requestBOI_uncommonBits_28, UInt<5>(0h1f))
node requestBOI_1_8 = and(_requestBOI_T_143, _requestBOI_T_144)
node _requestBOI_uncommonBits_T_29 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_29 = bits(_requestBOI_uncommonBits_T_29, 1, 0)
node _requestBOI_T_145 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_146 = eq(_requestBOI_T_145, UInt<7>(0h7a))
node _requestBOI_T_147 = leq(UInt<1>(0h0), requestBOI_uncommonBits_29)
node _requestBOI_T_148 = and(_requestBOI_T_146, _requestBOI_T_147)
node _requestBOI_T_149 = leq(requestBOI_uncommonBits_29, UInt<2>(0h3))
node requestBOI_1_9 = and(_requestBOI_T_148, _requestBOI_T_149)
node _requestBOI_uncommonBits_T_30 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_30 = bits(_requestBOI_uncommonBits_T_30, 1, 0)
node _requestBOI_T_150 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_151 = eq(_requestBOI_T_150, UInt<7>(0h79))
node _requestBOI_T_152 = leq(UInt<1>(0h0), requestBOI_uncommonBits_30)
node _requestBOI_T_153 = and(_requestBOI_T_151, _requestBOI_T_152)
node _requestBOI_T_154 = leq(requestBOI_uncommonBits_30, UInt<2>(0h3))
node requestBOI_1_10 = and(_requestBOI_T_153, _requestBOI_T_154)
node _requestBOI_uncommonBits_T_31 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_31 = bits(_requestBOI_uncommonBits_T_31, 4, 0)
node _requestBOI_T_155 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_156 = eq(_requestBOI_T_155, UInt<3>(0h7))
node _requestBOI_T_157 = leq(UInt<1>(0h0), requestBOI_uncommonBits_31)
node _requestBOI_T_158 = and(_requestBOI_T_156, _requestBOI_T_157)
node _requestBOI_T_159 = leq(requestBOI_uncommonBits_31, UInt<5>(0h1f))
node requestBOI_1_11 = and(_requestBOI_T_158, _requestBOI_T_159)
node _requestBOI_uncommonBits_T_32 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_32 = bits(_requestBOI_uncommonBits_T_32, 4, 0)
node _requestBOI_T_160 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_161 = eq(_requestBOI_T_160, UInt<3>(0h6))
node _requestBOI_T_162 = leq(UInt<1>(0h0), requestBOI_uncommonBits_32)
node _requestBOI_T_163 = and(_requestBOI_T_161, _requestBOI_T_162)
node _requestBOI_T_164 = leq(requestBOI_uncommonBits_32, UInt<5>(0h1f))
node requestBOI_1_12 = and(_requestBOI_T_163, _requestBOI_T_164)
node _requestBOI_uncommonBits_T_33 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_33 = bits(_requestBOI_uncommonBits_T_33, 4, 0)
node _requestBOI_T_165 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_166 = eq(_requestBOI_T_165, UInt<3>(0h5))
node _requestBOI_T_167 = leq(UInt<1>(0h0), requestBOI_uncommonBits_33)
node _requestBOI_T_168 = and(_requestBOI_T_166, _requestBOI_T_167)
node _requestBOI_T_169 = leq(requestBOI_uncommonBits_33, UInt<5>(0h1f))
node requestBOI_1_13 = and(_requestBOI_T_168, _requestBOI_T_169)
node _requestBOI_uncommonBits_T_34 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_34 = bits(_requestBOI_uncommonBits_T_34, 4, 0)
node _requestBOI_T_170 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_171 = eq(_requestBOI_T_170, UInt<3>(0h4))
node _requestBOI_T_172 = leq(UInt<1>(0h0), requestBOI_uncommonBits_34)
node _requestBOI_T_173 = and(_requestBOI_T_171, _requestBOI_T_172)
node _requestBOI_T_174 = leq(requestBOI_uncommonBits_34, UInt<5>(0h1f))
node requestBOI_1_14 = and(_requestBOI_T_173, _requestBOI_T_174)
node _requestBOI_uncommonBits_T_35 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_35 = bits(_requestBOI_uncommonBits_T_35, 4, 0)
node _requestBOI_T_175 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_176 = eq(_requestBOI_T_175, UInt<2>(0h3))
node _requestBOI_T_177 = leq(UInt<1>(0h0), requestBOI_uncommonBits_35)
node _requestBOI_T_178 = and(_requestBOI_T_176, _requestBOI_T_177)
node _requestBOI_T_179 = leq(requestBOI_uncommonBits_35, UInt<5>(0h1f))
node requestBOI_1_15 = and(_requestBOI_T_178, _requestBOI_T_179)
node _requestBOI_uncommonBits_T_36 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_36 = bits(_requestBOI_uncommonBits_T_36, 4, 0)
node _requestBOI_T_180 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_181 = eq(_requestBOI_T_180, UInt<2>(0h2))
node _requestBOI_T_182 = leq(UInt<1>(0h0), requestBOI_uncommonBits_36)
node _requestBOI_T_183 = and(_requestBOI_T_181, _requestBOI_T_182)
node _requestBOI_T_184 = leq(requestBOI_uncommonBits_36, UInt<5>(0h1f))
node requestBOI_1_16 = and(_requestBOI_T_183, _requestBOI_T_184)
node _requestBOI_uncommonBits_T_37 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_37 = bits(_requestBOI_uncommonBits_T_37, 4, 0)
node _requestBOI_T_185 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_186 = eq(_requestBOI_T_185, UInt<1>(0h1))
node _requestBOI_T_187 = leq(UInt<1>(0h0), requestBOI_uncommonBits_37)
node _requestBOI_T_188 = and(_requestBOI_T_186, _requestBOI_T_187)
node _requestBOI_T_189 = leq(requestBOI_uncommonBits_37, UInt<5>(0h1f))
node requestBOI_1_17 = and(_requestBOI_T_188, _requestBOI_T_189)
node _requestBOI_uncommonBits_T_38 = or(out[1].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_38 = bits(_requestBOI_uncommonBits_T_38, 4, 0)
node _requestBOI_T_190 = shr(out[1].b.bits.source, 5)
node _requestBOI_T_191 = eq(_requestBOI_T_190, UInt<1>(0h0))
node _requestBOI_T_192 = leq(UInt<1>(0h0), requestBOI_uncommonBits_38)
node _requestBOI_T_193 = and(_requestBOI_T_191, _requestBOI_T_192)
node _requestBOI_T_194 = leq(requestBOI_uncommonBits_38, UInt<5>(0h1f))
node requestBOI_1_18 = and(_requestBOI_T_193, _requestBOI_T_194)
node _requestBOI_uncommonBits_T_39 = or(out[1].b.bits.source, UInt<2>(0h0))
node requestBOI_uncommonBits_39 = bits(_requestBOI_uncommonBits_T_39, 1, 0)
node _requestBOI_T_195 = shr(out[1].b.bits.source, 2)
node _requestBOI_T_196 = eq(_requestBOI_T_195, UInt<7>(0h78))
node _requestBOI_T_197 = leq(UInt<1>(0h0), requestBOI_uncommonBits_39)
node _requestBOI_T_198 = and(_requestBOI_T_196, _requestBOI_T_197)
node _requestBOI_T_199 = leq(requestBOI_uncommonBits_39, UInt<2>(0h3))
node requestBOI_1_19 = and(_requestBOI_T_198, _requestBOI_T_199)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<4>(0he))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<7>(0h7c))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 1, 0)
node _requestDOI_T_10 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<7>(0h7b))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<2>(0h3))
node requestDOI_0_2 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 4, 0)
node _requestDOI_T_15 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<4>(0hd))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<5>(0h1f))
node requestDOI_0_3 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestDOI_uncommonBits_T_4 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 4, 0)
node _requestDOI_T_20 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<4>(0hc))
node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4)
node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22)
node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<5>(0h1f))
node requestDOI_0_4 = and(_requestDOI_T_23, _requestDOI_T_24)
node _requestDOI_uncommonBits_T_5 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 4, 0)
node _requestDOI_T_25 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<4>(0hb))
node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5)
node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27)
node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<5>(0h1f))
node requestDOI_0_5 = and(_requestDOI_T_28, _requestDOI_T_29)
node _requestDOI_uncommonBits_T_6 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 4, 0)
node _requestDOI_T_30 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<4>(0ha))
node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6)
node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32)
node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<5>(0h1f))
node requestDOI_0_6 = and(_requestDOI_T_33, _requestDOI_T_34)
node _requestDOI_uncommonBits_T_7 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 4, 0)
node _requestDOI_T_35 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<4>(0h9))
node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7)
node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37)
node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<5>(0h1f))
node requestDOI_0_7 = and(_requestDOI_T_38, _requestDOI_T_39)
node _requestDOI_uncommonBits_T_8 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_8 = bits(_requestDOI_uncommonBits_T_8, 4, 0)
node _requestDOI_T_40 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_41 = eq(_requestDOI_T_40, UInt<4>(0h8))
node _requestDOI_T_42 = leq(UInt<1>(0h0), requestDOI_uncommonBits_8)
node _requestDOI_T_43 = and(_requestDOI_T_41, _requestDOI_T_42)
node _requestDOI_T_44 = leq(requestDOI_uncommonBits_8, UInt<5>(0h1f))
node requestDOI_0_8 = and(_requestDOI_T_43, _requestDOI_T_44)
node _requestDOI_uncommonBits_T_9 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_9 = bits(_requestDOI_uncommonBits_T_9, 1, 0)
node _requestDOI_T_45 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_46 = eq(_requestDOI_T_45, UInt<7>(0h7a))
node _requestDOI_T_47 = leq(UInt<1>(0h0), requestDOI_uncommonBits_9)
node _requestDOI_T_48 = and(_requestDOI_T_46, _requestDOI_T_47)
node _requestDOI_T_49 = leq(requestDOI_uncommonBits_9, UInt<2>(0h3))
node requestDOI_0_9 = and(_requestDOI_T_48, _requestDOI_T_49)
node _requestDOI_uncommonBits_T_10 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_10 = bits(_requestDOI_uncommonBits_T_10, 1, 0)
node _requestDOI_T_50 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_51 = eq(_requestDOI_T_50, UInt<7>(0h79))
node _requestDOI_T_52 = leq(UInt<1>(0h0), requestDOI_uncommonBits_10)
node _requestDOI_T_53 = and(_requestDOI_T_51, _requestDOI_T_52)
node _requestDOI_T_54 = leq(requestDOI_uncommonBits_10, UInt<2>(0h3))
node requestDOI_0_10 = and(_requestDOI_T_53, _requestDOI_T_54)
node _requestDOI_uncommonBits_T_11 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_11 = bits(_requestDOI_uncommonBits_T_11, 4, 0)
node _requestDOI_T_55 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_56 = eq(_requestDOI_T_55, UInt<3>(0h7))
node _requestDOI_T_57 = leq(UInt<1>(0h0), requestDOI_uncommonBits_11)
node _requestDOI_T_58 = and(_requestDOI_T_56, _requestDOI_T_57)
node _requestDOI_T_59 = leq(requestDOI_uncommonBits_11, UInt<5>(0h1f))
node requestDOI_0_11 = and(_requestDOI_T_58, _requestDOI_T_59)
node _requestDOI_uncommonBits_T_12 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_12 = bits(_requestDOI_uncommonBits_T_12, 4, 0)
node _requestDOI_T_60 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_61 = eq(_requestDOI_T_60, UInt<3>(0h6))
node _requestDOI_T_62 = leq(UInt<1>(0h0), requestDOI_uncommonBits_12)
node _requestDOI_T_63 = and(_requestDOI_T_61, _requestDOI_T_62)
node _requestDOI_T_64 = leq(requestDOI_uncommonBits_12, UInt<5>(0h1f))
node requestDOI_0_12 = and(_requestDOI_T_63, _requestDOI_T_64)
node _requestDOI_uncommonBits_T_13 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_13 = bits(_requestDOI_uncommonBits_T_13, 4, 0)
node _requestDOI_T_65 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_66 = eq(_requestDOI_T_65, UInt<3>(0h5))
node _requestDOI_T_67 = leq(UInt<1>(0h0), requestDOI_uncommonBits_13)
node _requestDOI_T_68 = and(_requestDOI_T_66, _requestDOI_T_67)
node _requestDOI_T_69 = leq(requestDOI_uncommonBits_13, UInt<5>(0h1f))
node requestDOI_0_13 = and(_requestDOI_T_68, _requestDOI_T_69)
node _requestDOI_uncommonBits_T_14 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_14 = bits(_requestDOI_uncommonBits_T_14, 4, 0)
node _requestDOI_T_70 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_71 = eq(_requestDOI_T_70, UInt<3>(0h4))
node _requestDOI_T_72 = leq(UInt<1>(0h0), requestDOI_uncommonBits_14)
node _requestDOI_T_73 = and(_requestDOI_T_71, _requestDOI_T_72)
node _requestDOI_T_74 = leq(requestDOI_uncommonBits_14, UInt<5>(0h1f))
node requestDOI_0_14 = and(_requestDOI_T_73, _requestDOI_T_74)
node _requestDOI_uncommonBits_T_15 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_15 = bits(_requestDOI_uncommonBits_T_15, 4, 0)
node _requestDOI_T_75 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_76 = eq(_requestDOI_T_75, UInt<2>(0h3))
node _requestDOI_T_77 = leq(UInt<1>(0h0), requestDOI_uncommonBits_15)
node _requestDOI_T_78 = and(_requestDOI_T_76, _requestDOI_T_77)
node _requestDOI_T_79 = leq(requestDOI_uncommonBits_15, UInt<5>(0h1f))
node requestDOI_0_15 = and(_requestDOI_T_78, _requestDOI_T_79)
node _requestDOI_uncommonBits_T_16 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_16 = bits(_requestDOI_uncommonBits_T_16, 4, 0)
node _requestDOI_T_80 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_81 = eq(_requestDOI_T_80, UInt<2>(0h2))
node _requestDOI_T_82 = leq(UInt<1>(0h0), requestDOI_uncommonBits_16)
node _requestDOI_T_83 = and(_requestDOI_T_81, _requestDOI_T_82)
node _requestDOI_T_84 = leq(requestDOI_uncommonBits_16, UInt<5>(0h1f))
node requestDOI_0_16 = and(_requestDOI_T_83, _requestDOI_T_84)
node _requestDOI_uncommonBits_T_17 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_17 = bits(_requestDOI_uncommonBits_T_17, 4, 0)
node _requestDOI_T_85 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_86 = eq(_requestDOI_T_85, UInt<1>(0h1))
node _requestDOI_T_87 = leq(UInt<1>(0h0), requestDOI_uncommonBits_17)
node _requestDOI_T_88 = and(_requestDOI_T_86, _requestDOI_T_87)
node _requestDOI_T_89 = leq(requestDOI_uncommonBits_17, UInt<5>(0h1f))
node requestDOI_0_17 = and(_requestDOI_T_88, _requestDOI_T_89)
node _requestDOI_uncommonBits_T_18 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_18 = bits(_requestDOI_uncommonBits_T_18, 4, 0)
node _requestDOI_T_90 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_91 = eq(_requestDOI_T_90, UInt<1>(0h0))
node _requestDOI_T_92 = leq(UInt<1>(0h0), requestDOI_uncommonBits_18)
node _requestDOI_T_93 = and(_requestDOI_T_91, _requestDOI_T_92)
node _requestDOI_T_94 = leq(requestDOI_uncommonBits_18, UInt<5>(0h1f))
node requestDOI_0_18 = and(_requestDOI_T_93, _requestDOI_T_94)
node _requestDOI_uncommonBits_T_19 = or(out[0].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_19 = bits(_requestDOI_uncommonBits_T_19, 1, 0)
node _requestDOI_T_95 = shr(out[0].d.bits.source, 2)
node _requestDOI_T_96 = eq(_requestDOI_T_95, UInt<7>(0h78))
node _requestDOI_T_97 = leq(UInt<1>(0h0), requestDOI_uncommonBits_19)
node _requestDOI_T_98 = and(_requestDOI_T_96, _requestDOI_T_97)
node _requestDOI_T_99 = leq(requestDOI_uncommonBits_19, UInt<2>(0h3))
node requestDOI_0_19 = and(_requestDOI_T_98, _requestDOI_T_99)
node _requestDOI_uncommonBits_T_20 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_20 = bits(_requestDOI_uncommonBits_T_20, 4, 0)
node _requestDOI_T_100 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_101 = eq(_requestDOI_T_100, UInt<4>(0he))
node _requestDOI_T_102 = leq(UInt<1>(0h0), requestDOI_uncommonBits_20)
node _requestDOI_T_103 = and(_requestDOI_T_101, _requestDOI_T_102)
node _requestDOI_T_104 = leq(requestDOI_uncommonBits_20, UInt<5>(0h1f))
node requestDOI_1_0 = and(_requestDOI_T_103, _requestDOI_T_104)
node _requestDOI_uncommonBits_T_21 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_21 = bits(_requestDOI_uncommonBits_T_21, 1, 0)
node _requestDOI_T_105 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_106 = eq(_requestDOI_T_105, UInt<7>(0h7c))
node _requestDOI_T_107 = leq(UInt<1>(0h0), requestDOI_uncommonBits_21)
node _requestDOI_T_108 = and(_requestDOI_T_106, _requestDOI_T_107)
node _requestDOI_T_109 = leq(requestDOI_uncommonBits_21, UInt<2>(0h3))
node requestDOI_1_1 = and(_requestDOI_T_108, _requestDOI_T_109)
node _requestDOI_uncommonBits_T_22 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_22 = bits(_requestDOI_uncommonBits_T_22, 1, 0)
node _requestDOI_T_110 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_111 = eq(_requestDOI_T_110, UInt<7>(0h7b))
node _requestDOI_T_112 = leq(UInt<1>(0h0), requestDOI_uncommonBits_22)
node _requestDOI_T_113 = and(_requestDOI_T_111, _requestDOI_T_112)
node _requestDOI_T_114 = leq(requestDOI_uncommonBits_22, UInt<2>(0h3))
node requestDOI_1_2 = and(_requestDOI_T_113, _requestDOI_T_114)
node _requestDOI_uncommonBits_T_23 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_23 = bits(_requestDOI_uncommonBits_T_23, 4, 0)
node _requestDOI_T_115 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_116 = eq(_requestDOI_T_115, UInt<4>(0hd))
node _requestDOI_T_117 = leq(UInt<1>(0h0), requestDOI_uncommonBits_23)
node _requestDOI_T_118 = and(_requestDOI_T_116, _requestDOI_T_117)
node _requestDOI_T_119 = leq(requestDOI_uncommonBits_23, UInt<5>(0h1f))
node requestDOI_1_3 = and(_requestDOI_T_118, _requestDOI_T_119)
node _requestDOI_uncommonBits_T_24 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_24 = bits(_requestDOI_uncommonBits_T_24, 4, 0)
node _requestDOI_T_120 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_121 = eq(_requestDOI_T_120, UInt<4>(0hc))
node _requestDOI_T_122 = leq(UInt<1>(0h0), requestDOI_uncommonBits_24)
node _requestDOI_T_123 = and(_requestDOI_T_121, _requestDOI_T_122)
node _requestDOI_T_124 = leq(requestDOI_uncommonBits_24, UInt<5>(0h1f))
node requestDOI_1_4 = and(_requestDOI_T_123, _requestDOI_T_124)
node _requestDOI_uncommonBits_T_25 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_25 = bits(_requestDOI_uncommonBits_T_25, 4, 0)
node _requestDOI_T_125 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_126 = eq(_requestDOI_T_125, UInt<4>(0hb))
node _requestDOI_T_127 = leq(UInt<1>(0h0), requestDOI_uncommonBits_25)
node _requestDOI_T_128 = and(_requestDOI_T_126, _requestDOI_T_127)
node _requestDOI_T_129 = leq(requestDOI_uncommonBits_25, UInt<5>(0h1f))
node requestDOI_1_5 = and(_requestDOI_T_128, _requestDOI_T_129)
node _requestDOI_uncommonBits_T_26 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_26 = bits(_requestDOI_uncommonBits_T_26, 4, 0)
node _requestDOI_T_130 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_131 = eq(_requestDOI_T_130, UInt<4>(0ha))
node _requestDOI_T_132 = leq(UInt<1>(0h0), requestDOI_uncommonBits_26)
node _requestDOI_T_133 = and(_requestDOI_T_131, _requestDOI_T_132)
node _requestDOI_T_134 = leq(requestDOI_uncommonBits_26, UInt<5>(0h1f))
node requestDOI_1_6 = and(_requestDOI_T_133, _requestDOI_T_134)
node _requestDOI_uncommonBits_T_27 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_27 = bits(_requestDOI_uncommonBits_T_27, 4, 0)
node _requestDOI_T_135 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_136 = eq(_requestDOI_T_135, UInt<4>(0h9))
node _requestDOI_T_137 = leq(UInt<1>(0h0), requestDOI_uncommonBits_27)
node _requestDOI_T_138 = and(_requestDOI_T_136, _requestDOI_T_137)
node _requestDOI_T_139 = leq(requestDOI_uncommonBits_27, UInt<5>(0h1f))
node requestDOI_1_7 = and(_requestDOI_T_138, _requestDOI_T_139)
node _requestDOI_uncommonBits_T_28 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_28 = bits(_requestDOI_uncommonBits_T_28, 4, 0)
node _requestDOI_T_140 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_141 = eq(_requestDOI_T_140, UInt<4>(0h8))
node _requestDOI_T_142 = leq(UInt<1>(0h0), requestDOI_uncommonBits_28)
node _requestDOI_T_143 = and(_requestDOI_T_141, _requestDOI_T_142)
node _requestDOI_T_144 = leq(requestDOI_uncommonBits_28, UInt<5>(0h1f))
node requestDOI_1_8 = and(_requestDOI_T_143, _requestDOI_T_144)
node _requestDOI_uncommonBits_T_29 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_29 = bits(_requestDOI_uncommonBits_T_29, 1, 0)
node _requestDOI_T_145 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_146 = eq(_requestDOI_T_145, UInt<7>(0h7a))
node _requestDOI_T_147 = leq(UInt<1>(0h0), requestDOI_uncommonBits_29)
node _requestDOI_T_148 = and(_requestDOI_T_146, _requestDOI_T_147)
node _requestDOI_T_149 = leq(requestDOI_uncommonBits_29, UInt<2>(0h3))
node requestDOI_1_9 = and(_requestDOI_T_148, _requestDOI_T_149)
node _requestDOI_uncommonBits_T_30 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_30 = bits(_requestDOI_uncommonBits_T_30, 1, 0)
node _requestDOI_T_150 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_151 = eq(_requestDOI_T_150, UInt<7>(0h79))
node _requestDOI_T_152 = leq(UInt<1>(0h0), requestDOI_uncommonBits_30)
node _requestDOI_T_153 = and(_requestDOI_T_151, _requestDOI_T_152)
node _requestDOI_T_154 = leq(requestDOI_uncommonBits_30, UInt<2>(0h3))
node requestDOI_1_10 = and(_requestDOI_T_153, _requestDOI_T_154)
node _requestDOI_uncommonBits_T_31 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_31 = bits(_requestDOI_uncommonBits_T_31, 4, 0)
node _requestDOI_T_155 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_156 = eq(_requestDOI_T_155, UInt<3>(0h7))
node _requestDOI_T_157 = leq(UInt<1>(0h0), requestDOI_uncommonBits_31)
node _requestDOI_T_158 = and(_requestDOI_T_156, _requestDOI_T_157)
node _requestDOI_T_159 = leq(requestDOI_uncommonBits_31, UInt<5>(0h1f))
node requestDOI_1_11 = and(_requestDOI_T_158, _requestDOI_T_159)
node _requestDOI_uncommonBits_T_32 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_32 = bits(_requestDOI_uncommonBits_T_32, 4, 0)
node _requestDOI_T_160 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_161 = eq(_requestDOI_T_160, UInt<3>(0h6))
node _requestDOI_T_162 = leq(UInt<1>(0h0), requestDOI_uncommonBits_32)
node _requestDOI_T_163 = and(_requestDOI_T_161, _requestDOI_T_162)
node _requestDOI_T_164 = leq(requestDOI_uncommonBits_32, UInt<5>(0h1f))
node requestDOI_1_12 = and(_requestDOI_T_163, _requestDOI_T_164)
node _requestDOI_uncommonBits_T_33 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_33 = bits(_requestDOI_uncommonBits_T_33, 4, 0)
node _requestDOI_T_165 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_166 = eq(_requestDOI_T_165, UInt<3>(0h5))
node _requestDOI_T_167 = leq(UInt<1>(0h0), requestDOI_uncommonBits_33)
node _requestDOI_T_168 = and(_requestDOI_T_166, _requestDOI_T_167)
node _requestDOI_T_169 = leq(requestDOI_uncommonBits_33, UInt<5>(0h1f))
node requestDOI_1_13 = and(_requestDOI_T_168, _requestDOI_T_169)
node _requestDOI_uncommonBits_T_34 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_34 = bits(_requestDOI_uncommonBits_T_34, 4, 0)
node _requestDOI_T_170 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_171 = eq(_requestDOI_T_170, UInt<3>(0h4))
node _requestDOI_T_172 = leq(UInt<1>(0h0), requestDOI_uncommonBits_34)
node _requestDOI_T_173 = and(_requestDOI_T_171, _requestDOI_T_172)
node _requestDOI_T_174 = leq(requestDOI_uncommonBits_34, UInt<5>(0h1f))
node requestDOI_1_14 = and(_requestDOI_T_173, _requestDOI_T_174)
node _requestDOI_uncommonBits_T_35 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_35 = bits(_requestDOI_uncommonBits_T_35, 4, 0)
node _requestDOI_T_175 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_176 = eq(_requestDOI_T_175, UInt<2>(0h3))
node _requestDOI_T_177 = leq(UInt<1>(0h0), requestDOI_uncommonBits_35)
node _requestDOI_T_178 = and(_requestDOI_T_176, _requestDOI_T_177)
node _requestDOI_T_179 = leq(requestDOI_uncommonBits_35, UInt<5>(0h1f))
node requestDOI_1_15 = and(_requestDOI_T_178, _requestDOI_T_179)
node _requestDOI_uncommonBits_T_36 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_36 = bits(_requestDOI_uncommonBits_T_36, 4, 0)
node _requestDOI_T_180 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_181 = eq(_requestDOI_T_180, UInt<2>(0h2))
node _requestDOI_T_182 = leq(UInt<1>(0h0), requestDOI_uncommonBits_36)
node _requestDOI_T_183 = and(_requestDOI_T_181, _requestDOI_T_182)
node _requestDOI_T_184 = leq(requestDOI_uncommonBits_36, UInt<5>(0h1f))
node requestDOI_1_16 = and(_requestDOI_T_183, _requestDOI_T_184)
node _requestDOI_uncommonBits_T_37 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_37 = bits(_requestDOI_uncommonBits_T_37, 4, 0)
node _requestDOI_T_185 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_186 = eq(_requestDOI_T_185, UInt<1>(0h1))
node _requestDOI_T_187 = leq(UInt<1>(0h0), requestDOI_uncommonBits_37)
node _requestDOI_T_188 = and(_requestDOI_T_186, _requestDOI_T_187)
node _requestDOI_T_189 = leq(requestDOI_uncommonBits_37, UInt<5>(0h1f))
node requestDOI_1_17 = and(_requestDOI_T_188, _requestDOI_T_189)
node _requestDOI_uncommonBits_T_38 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_38 = bits(_requestDOI_uncommonBits_T_38, 4, 0)
node _requestDOI_T_190 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_191 = eq(_requestDOI_T_190, UInt<1>(0h0))
node _requestDOI_T_192 = leq(UInt<1>(0h0), requestDOI_uncommonBits_38)
node _requestDOI_T_193 = and(_requestDOI_T_191, _requestDOI_T_192)
node _requestDOI_T_194 = leq(requestDOI_uncommonBits_38, UInt<5>(0h1f))
node requestDOI_1_18 = and(_requestDOI_T_193, _requestDOI_T_194)
node _requestDOI_uncommonBits_T_39 = or(out[1].d.bits.source, UInt<2>(0h0))
node requestDOI_uncommonBits_39 = bits(_requestDOI_uncommonBits_T_39, 1, 0)
node _requestDOI_T_195 = shr(out[1].d.bits.source, 2)
node _requestDOI_T_196 = eq(_requestDOI_T_195, UInt<7>(0h78))
node _requestDOI_T_197 = leq(UInt<1>(0h0), requestDOI_uncommonBits_39)
node _requestDOI_T_198 = and(_requestDOI_T_196, _requestDOI_T_197)
node _requestDOI_T_199 = leq(requestDOI_uncommonBits_39, UInt<2>(0h3))
node requestDOI_1_19 = and(_requestDOI_T_198, _requestDOI_T_199)
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9)
node _requestEIO_uncommonBits_T_2 = or(in[2].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_2 = bits(_requestEIO_uncommonBits_T_2, 2, 0)
node _requestEIO_T_10 = shr(in[2].e.bits.sink, 3)
node _requestEIO_T_11 = eq(_requestEIO_T_10, UInt<1>(0h0))
node _requestEIO_T_12 = leq(UInt<1>(0h0), requestEIO_uncommonBits_2)
node _requestEIO_T_13 = and(_requestEIO_T_11, _requestEIO_T_12)
node _requestEIO_T_14 = leq(requestEIO_uncommonBits_2, UInt<3>(0h7))
node requestEIO_2_1 = and(_requestEIO_T_13, _requestEIO_T_14)
node _requestEIO_uncommonBits_T_3 = or(in[3].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_3 = bits(_requestEIO_uncommonBits_T_3, 2, 0)
node _requestEIO_T_15 = shr(in[3].e.bits.sink, 3)
node _requestEIO_T_16 = eq(_requestEIO_T_15, UInt<1>(0h0))
node _requestEIO_T_17 = leq(UInt<1>(0h0), requestEIO_uncommonBits_3)
node _requestEIO_T_18 = and(_requestEIO_T_16, _requestEIO_T_17)
node _requestEIO_T_19 = leq(requestEIO_uncommonBits_3, UInt<3>(0h7))
node requestEIO_3_1 = and(_requestEIO_T_18, _requestEIO_T_19)
node _requestEIO_uncommonBits_T_4 = or(in[4].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_4 = bits(_requestEIO_uncommonBits_T_4, 2, 0)
node _requestEIO_T_20 = shr(in[4].e.bits.sink, 3)
node _requestEIO_T_21 = eq(_requestEIO_T_20, UInt<1>(0h0))
node _requestEIO_T_22 = leq(UInt<1>(0h0), requestEIO_uncommonBits_4)
node _requestEIO_T_23 = and(_requestEIO_T_21, _requestEIO_T_22)
node _requestEIO_T_24 = leq(requestEIO_uncommonBits_4, UInt<3>(0h7))
node requestEIO_4_1 = and(_requestEIO_T_23, _requestEIO_T_24)
node _requestEIO_uncommonBits_T_5 = or(in[5].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_5 = bits(_requestEIO_uncommonBits_T_5, 2, 0)
node _requestEIO_T_25 = shr(in[5].e.bits.sink, 3)
node _requestEIO_T_26 = eq(_requestEIO_T_25, UInt<1>(0h0))
node _requestEIO_T_27 = leq(UInt<1>(0h0), requestEIO_uncommonBits_5)
node _requestEIO_T_28 = and(_requestEIO_T_26, _requestEIO_T_27)
node _requestEIO_T_29 = leq(requestEIO_uncommonBits_5, UInt<3>(0h7))
node requestEIO_5_1 = and(_requestEIO_T_28, _requestEIO_T_29)
node _requestEIO_uncommonBits_T_6 = or(in[6].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_6 = bits(_requestEIO_uncommonBits_T_6, 2, 0)
node _requestEIO_T_30 = shr(in[6].e.bits.sink, 3)
node _requestEIO_T_31 = eq(_requestEIO_T_30, UInt<1>(0h0))
node _requestEIO_T_32 = leq(UInt<1>(0h0), requestEIO_uncommonBits_6)
node _requestEIO_T_33 = and(_requestEIO_T_31, _requestEIO_T_32)
node _requestEIO_T_34 = leq(requestEIO_uncommonBits_6, UInt<3>(0h7))
node requestEIO_6_1 = and(_requestEIO_T_33, _requestEIO_T_34)
node _requestEIO_uncommonBits_T_7 = or(in[7].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_7 = bits(_requestEIO_uncommonBits_T_7, 2, 0)
node _requestEIO_T_35 = shr(in[7].e.bits.sink, 3)
node _requestEIO_T_36 = eq(_requestEIO_T_35, UInt<1>(0h0))
node _requestEIO_T_37 = leq(UInt<1>(0h0), requestEIO_uncommonBits_7)
node _requestEIO_T_38 = and(_requestEIO_T_36, _requestEIO_T_37)
node _requestEIO_T_39 = leq(requestEIO_uncommonBits_7, UInt<3>(0h7))
node requestEIO_7_1 = and(_requestEIO_T_38, _requestEIO_T_39)
node _requestEIO_uncommonBits_T_8 = or(in[8].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_8 = bits(_requestEIO_uncommonBits_T_8, 2, 0)
node _requestEIO_T_40 = shr(in[8].e.bits.sink, 3)
node _requestEIO_T_41 = eq(_requestEIO_T_40, UInt<1>(0h0))
node _requestEIO_T_42 = leq(UInt<1>(0h0), requestEIO_uncommonBits_8)
node _requestEIO_T_43 = and(_requestEIO_T_41, _requestEIO_T_42)
node _requestEIO_T_44 = leq(requestEIO_uncommonBits_8, UInt<3>(0h7))
node requestEIO_8_1 = and(_requestEIO_T_43, _requestEIO_T_44)
node _requestEIO_uncommonBits_T_9 = or(in[9].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_9 = bits(_requestEIO_uncommonBits_T_9, 2, 0)
node _requestEIO_T_45 = shr(in[9].e.bits.sink, 3)
node _requestEIO_T_46 = eq(_requestEIO_T_45, UInt<1>(0h0))
node _requestEIO_T_47 = leq(UInt<1>(0h0), requestEIO_uncommonBits_9)
node _requestEIO_T_48 = and(_requestEIO_T_46, _requestEIO_T_47)
node _requestEIO_T_49 = leq(requestEIO_uncommonBits_9, UInt<3>(0h7))
node requestEIO_9_1 = and(_requestEIO_T_48, _requestEIO_T_49)
node _requestEIO_uncommonBits_T_10 = or(in[10].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_10 = bits(_requestEIO_uncommonBits_T_10, 2, 0)
node _requestEIO_T_50 = shr(in[10].e.bits.sink, 3)
node _requestEIO_T_51 = eq(_requestEIO_T_50, UInt<1>(0h0))
node _requestEIO_T_52 = leq(UInt<1>(0h0), requestEIO_uncommonBits_10)
node _requestEIO_T_53 = and(_requestEIO_T_51, _requestEIO_T_52)
node _requestEIO_T_54 = leq(requestEIO_uncommonBits_10, UInt<3>(0h7))
node requestEIO_10_1 = and(_requestEIO_T_53, _requestEIO_T_54)
node _requestEIO_uncommonBits_T_11 = or(in[11].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_11 = bits(_requestEIO_uncommonBits_T_11, 2, 0)
node _requestEIO_T_55 = shr(in[11].e.bits.sink, 3)
node _requestEIO_T_56 = eq(_requestEIO_T_55, UInt<1>(0h0))
node _requestEIO_T_57 = leq(UInt<1>(0h0), requestEIO_uncommonBits_11)
node _requestEIO_T_58 = and(_requestEIO_T_56, _requestEIO_T_57)
node _requestEIO_T_59 = leq(requestEIO_uncommonBits_11, UInt<3>(0h7))
node requestEIO_11_1 = and(_requestEIO_T_58, _requestEIO_T_59)
node _requestEIO_uncommonBits_T_12 = or(in[12].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_12 = bits(_requestEIO_uncommonBits_T_12, 2, 0)
node _requestEIO_T_60 = shr(in[12].e.bits.sink, 3)
node _requestEIO_T_61 = eq(_requestEIO_T_60, UInt<1>(0h0))
node _requestEIO_T_62 = leq(UInt<1>(0h0), requestEIO_uncommonBits_12)
node _requestEIO_T_63 = and(_requestEIO_T_61, _requestEIO_T_62)
node _requestEIO_T_64 = leq(requestEIO_uncommonBits_12, UInt<3>(0h7))
node requestEIO_12_1 = and(_requestEIO_T_63, _requestEIO_T_64)
node _requestEIO_uncommonBits_T_13 = or(in[13].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_13 = bits(_requestEIO_uncommonBits_T_13, 2, 0)
node _requestEIO_T_65 = shr(in[13].e.bits.sink, 3)
node _requestEIO_T_66 = eq(_requestEIO_T_65, UInt<1>(0h0))
node _requestEIO_T_67 = leq(UInt<1>(0h0), requestEIO_uncommonBits_13)
node _requestEIO_T_68 = and(_requestEIO_T_66, _requestEIO_T_67)
node _requestEIO_T_69 = leq(requestEIO_uncommonBits_13, UInt<3>(0h7))
node requestEIO_13_1 = and(_requestEIO_T_68, _requestEIO_T_69)
node _requestEIO_uncommonBits_T_14 = or(in[14].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_14 = bits(_requestEIO_uncommonBits_T_14, 2, 0)
node _requestEIO_T_70 = shr(in[14].e.bits.sink, 3)
node _requestEIO_T_71 = eq(_requestEIO_T_70, UInt<1>(0h0))
node _requestEIO_T_72 = leq(UInt<1>(0h0), requestEIO_uncommonBits_14)
node _requestEIO_T_73 = and(_requestEIO_T_71, _requestEIO_T_72)
node _requestEIO_T_74 = leq(requestEIO_uncommonBits_14, UInt<3>(0h7))
node requestEIO_14_1 = and(_requestEIO_T_73, _requestEIO_T_74)
node _requestEIO_uncommonBits_T_15 = or(in[15].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_15 = bits(_requestEIO_uncommonBits_T_15, 2, 0)
node _requestEIO_T_75 = shr(in[15].e.bits.sink, 3)
node _requestEIO_T_76 = eq(_requestEIO_T_75, UInt<1>(0h0))
node _requestEIO_T_77 = leq(UInt<1>(0h0), requestEIO_uncommonBits_15)
node _requestEIO_T_78 = and(_requestEIO_T_76, _requestEIO_T_77)
node _requestEIO_T_79 = leq(requestEIO_uncommonBits_15, UInt<3>(0h7))
node requestEIO_15_1 = and(_requestEIO_T_78, _requestEIO_T_79)
node _requestEIO_uncommonBits_T_16 = or(in[16].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_16 = bits(_requestEIO_uncommonBits_T_16, 2, 0)
node _requestEIO_T_80 = shr(in[16].e.bits.sink, 3)
node _requestEIO_T_81 = eq(_requestEIO_T_80, UInt<1>(0h0))
node _requestEIO_T_82 = leq(UInt<1>(0h0), requestEIO_uncommonBits_16)
node _requestEIO_T_83 = and(_requestEIO_T_81, _requestEIO_T_82)
node _requestEIO_T_84 = leq(requestEIO_uncommonBits_16, UInt<3>(0h7))
node requestEIO_16_1 = and(_requestEIO_T_83, _requestEIO_T_84)
node _requestEIO_uncommonBits_T_17 = or(in[17].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_17 = bits(_requestEIO_uncommonBits_T_17, 2, 0)
node _requestEIO_T_85 = shr(in[17].e.bits.sink, 3)
node _requestEIO_T_86 = eq(_requestEIO_T_85, UInt<1>(0h0))
node _requestEIO_T_87 = leq(UInt<1>(0h0), requestEIO_uncommonBits_17)
node _requestEIO_T_88 = and(_requestEIO_T_86, _requestEIO_T_87)
node _requestEIO_T_89 = leq(requestEIO_uncommonBits_17, UInt<3>(0h7))
node requestEIO_17_1 = and(_requestEIO_T_88, _requestEIO_T_89)
node _requestEIO_uncommonBits_T_18 = or(in[18].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_18 = bits(_requestEIO_uncommonBits_T_18, 2, 0)
node _requestEIO_T_90 = shr(in[18].e.bits.sink, 3)
node _requestEIO_T_91 = eq(_requestEIO_T_90, UInt<1>(0h0))
node _requestEIO_T_92 = leq(UInt<1>(0h0), requestEIO_uncommonBits_18)
node _requestEIO_T_93 = and(_requestEIO_T_91, _requestEIO_T_92)
node _requestEIO_T_94 = leq(requestEIO_uncommonBits_18, UInt<3>(0h7))
node requestEIO_18_1 = and(_requestEIO_T_93, _requestEIO_T_94)
node _requestEIO_uncommonBits_T_19 = or(in[19].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_19 = bits(_requestEIO_uncommonBits_T_19, 2, 0)
node _requestEIO_T_95 = shr(in[19].e.bits.sink, 3)
node _requestEIO_T_96 = eq(_requestEIO_T_95, UInt<1>(0h0))
node _requestEIO_T_97 = leq(UInt<1>(0h0), requestEIO_uncommonBits_19)
node _requestEIO_T_98 = and(_requestEIO_T_96, _requestEIO_T_97)
node _requestEIO_T_99 = leq(requestEIO_uncommonBits_19, UInt<3>(0h7))
node requestEIO_19_1 = and(_requestEIO_T_98, _requestEIO_T_99)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size)
node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0)
node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7)
node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 3)
node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2)
node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0))
node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0))
node _beatsAI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].a.bits.size)
node _beatsAI_decode_T_10 = bits(_beatsAI_decode_T_9, 11, 0)
node _beatsAI_decode_T_11 = not(_beatsAI_decode_T_10)
node beatsAI_decode_3 = shr(_beatsAI_decode_T_11, 3)
node _beatsAI_opdata_T_3 = bits(in[3].a.bits.opcode, 2, 2)
node beatsAI_opdata_3 = eq(_beatsAI_opdata_T_3, UInt<1>(0h0))
node beatsAI_3 = mux(beatsAI_opdata_3, beatsAI_decode_3, UInt<1>(0h0))
node _beatsAI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].a.bits.size)
node _beatsAI_decode_T_13 = bits(_beatsAI_decode_T_12, 11, 0)
node _beatsAI_decode_T_14 = not(_beatsAI_decode_T_13)
node beatsAI_decode_4 = shr(_beatsAI_decode_T_14, 3)
node _beatsAI_opdata_T_4 = bits(in[4].a.bits.opcode, 2, 2)
node beatsAI_opdata_4 = eq(_beatsAI_opdata_T_4, UInt<1>(0h0))
node beatsAI_4 = mux(beatsAI_opdata_4, beatsAI_decode_4, UInt<1>(0h0))
node _beatsAI_decode_T_15 = dshl(UInt<12>(0hfff), in[5].a.bits.size)
node _beatsAI_decode_T_16 = bits(_beatsAI_decode_T_15, 11, 0)
node _beatsAI_decode_T_17 = not(_beatsAI_decode_T_16)
node beatsAI_decode_5 = shr(_beatsAI_decode_T_17, 3)
node _beatsAI_opdata_T_5 = bits(in[5].a.bits.opcode, 2, 2)
node beatsAI_opdata_5 = eq(_beatsAI_opdata_T_5, UInt<1>(0h0))
node beatsAI_5 = mux(beatsAI_opdata_5, beatsAI_decode_5, UInt<1>(0h0))
node _beatsAI_decode_T_18 = dshl(UInt<12>(0hfff), in[6].a.bits.size)
node _beatsAI_decode_T_19 = bits(_beatsAI_decode_T_18, 11, 0)
node _beatsAI_decode_T_20 = not(_beatsAI_decode_T_19)
node beatsAI_decode_6 = shr(_beatsAI_decode_T_20, 3)
node _beatsAI_opdata_T_6 = bits(in[6].a.bits.opcode, 2, 2)
node beatsAI_opdata_6 = eq(_beatsAI_opdata_T_6, UInt<1>(0h0))
node beatsAI_6 = mux(beatsAI_opdata_6, beatsAI_decode_6, UInt<1>(0h0))
node _beatsAI_decode_T_21 = dshl(UInt<12>(0hfff), in[7].a.bits.size)
node _beatsAI_decode_T_22 = bits(_beatsAI_decode_T_21, 11, 0)
node _beatsAI_decode_T_23 = not(_beatsAI_decode_T_22)
node beatsAI_decode_7 = shr(_beatsAI_decode_T_23, 3)
node _beatsAI_opdata_T_7 = bits(in[7].a.bits.opcode, 2, 2)
node beatsAI_opdata_7 = eq(_beatsAI_opdata_T_7, UInt<1>(0h0))
node beatsAI_7 = mux(beatsAI_opdata_7, beatsAI_decode_7, UInt<1>(0h0))
node _beatsAI_decode_T_24 = dshl(UInt<12>(0hfff), in[8].a.bits.size)
node _beatsAI_decode_T_25 = bits(_beatsAI_decode_T_24, 11, 0)
node _beatsAI_decode_T_26 = not(_beatsAI_decode_T_25)
node beatsAI_decode_8 = shr(_beatsAI_decode_T_26, 3)
node _beatsAI_opdata_T_8 = bits(in[8].a.bits.opcode, 2, 2)
node beatsAI_opdata_8 = eq(_beatsAI_opdata_T_8, UInt<1>(0h0))
node beatsAI_8 = mux(beatsAI_opdata_8, beatsAI_decode_8, UInt<1>(0h0))
node _beatsAI_decode_T_27 = dshl(UInt<12>(0hfff), in[9].a.bits.size)
node _beatsAI_decode_T_28 = bits(_beatsAI_decode_T_27, 11, 0)
node _beatsAI_decode_T_29 = not(_beatsAI_decode_T_28)
node beatsAI_decode_9 = shr(_beatsAI_decode_T_29, 3)
node _beatsAI_opdata_T_9 = bits(in[9].a.bits.opcode, 2, 2)
node beatsAI_opdata_9 = eq(_beatsAI_opdata_T_9, UInt<1>(0h0))
node beatsAI_9 = mux(beatsAI_opdata_9, beatsAI_decode_9, UInt<1>(0h0))
node _beatsAI_decode_T_30 = dshl(UInt<12>(0hfff), in[10].a.bits.size)
node _beatsAI_decode_T_31 = bits(_beatsAI_decode_T_30, 11, 0)
node _beatsAI_decode_T_32 = not(_beatsAI_decode_T_31)
node beatsAI_decode_10 = shr(_beatsAI_decode_T_32, 3)
node _beatsAI_opdata_T_10 = bits(in[10].a.bits.opcode, 2, 2)
node beatsAI_opdata_10 = eq(_beatsAI_opdata_T_10, UInt<1>(0h0))
node beatsAI_10 = mux(beatsAI_opdata_10, beatsAI_decode_10, UInt<1>(0h0))
node _beatsAI_decode_T_33 = dshl(UInt<12>(0hfff), in[11].a.bits.size)
node _beatsAI_decode_T_34 = bits(_beatsAI_decode_T_33, 11, 0)
node _beatsAI_decode_T_35 = not(_beatsAI_decode_T_34)
node beatsAI_decode_11 = shr(_beatsAI_decode_T_35, 3)
node _beatsAI_opdata_T_11 = bits(in[11].a.bits.opcode, 2, 2)
node beatsAI_opdata_11 = eq(_beatsAI_opdata_T_11, UInt<1>(0h0))
node beatsAI_11 = mux(beatsAI_opdata_11, beatsAI_decode_11, UInt<1>(0h0))
node _beatsAI_decode_T_36 = dshl(UInt<12>(0hfff), in[12].a.bits.size)
node _beatsAI_decode_T_37 = bits(_beatsAI_decode_T_36, 11, 0)
node _beatsAI_decode_T_38 = not(_beatsAI_decode_T_37)
node beatsAI_decode_12 = shr(_beatsAI_decode_T_38, 3)
node _beatsAI_opdata_T_12 = bits(in[12].a.bits.opcode, 2, 2)
node beatsAI_opdata_12 = eq(_beatsAI_opdata_T_12, UInt<1>(0h0))
node beatsAI_12 = mux(beatsAI_opdata_12, beatsAI_decode_12, UInt<1>(0h0))
node _beatsAI_decode_T_39 = dshl(UInt<12>(0hfff), in[13].a.bits.size)
node _beatsAI_decode_T_40 = bits(_beatsAI_decode_T_39, 11, 0)
node _beatsAI_decode_T_41 = not(_beatsAI_decode_T_40)
node beatsAI_decode_13 = shr(_beatsAI_decode_T_41, 3)
node _beatsAI_opdata_T_13 = bits(in[13].a.bits.opcode, 2, 2)
node beatsAI_opdata_13 = eq(_beatsAI_opdata_T_13, UInt<1>(0h0))
node beatsAI_13 = mux(beatsAI_opdata_13, beatsAI_decode_13, UInt<1>(0h0))
node _beatsAI_decode_T_42 = dshl(UInt<12>(0hfff), in[14].a.bits.size)
node _beatsAI_decode_T_43 = bits(_beatsAI_decode_T_42, 11, 0)
node _beatsAI_decode_T_44 = not(_beatsAI_decode_T_43)
node beatsAI_decode_14 = shr(_beatsAI_decode_T_44, 3)
node _beatsAI_opdata_T_14 = bits(in[14].a.bits.opcode, 2, 2)
node beatsAI_opdata_14 = eq(_beatsAI_opdata_T_14, UInt<1>(0h0))
node beatsAI_14 = mux(beatsAI_opdata_14, beatsAI_decode_14, UInt<1>(0h0))
node _beatsAI_decode_T_45 = dshl(UInt<12>(0hfff), in[15].a.bits.size)
node _beatsAI_decode_T_46 = bits(_beatsAI_decode_T_45, 11, 0)
node _beatsAI_decode_T_47 = not(_beatsAI_decode_T_46)
node beatsAI_decode_15 = shr(_beatsAI_decode_T_47, 3)
node _beatsAI_opdata_T_15 = bits(in[15].a.bits.opcode, 2, 2)
node beatsAI_opdata_15 = eq(_beatsAI_opdata_T_15, UInt<1>(0h0))
node beatsAI_15 = mux(beatsAI_opdata_15, beatsAI_decode_15, UInt<1>(0h0))
node _beatsAI_decode_T_48 = dshl(UInt<12>(0hfff), in[16].a.bits.size)
node _beatsAI_decode_T_49 = bits(_beatsAI_decode_T_48, 11, 0)
node _beatsAI_decode_T_50 = not(_beatsAI_decode_T_49)
node beatsAI_decode_16 = shr(_beatsAI_decode_T_50, 3)
node _beatsAI_opdata_T_16 = bits(in[16].a.bits.opcode, 2, 2)
node beatsAI_opdata_16 = eq(_beatsAI_opdata_T_16, UInt<1>(0h0))
node beatsAI_16 = mux(beatsAI_opdata_16, beatsAI_decode_16, UInt<1>(0h0))
node _beatsAI_decode_T_51 = dshl(UInt<12>(0hfff), in[17].a.bits.size)
node _beatsAI_decode_T_52 = bits(_beatsAI_decode_T_51, 11, 0)
node _beatsAI_decode_T_53 = not(_beatsAI_decode_T_52)
node beatsAI_decode_17 = shr(_beatsAI_decode_T_53, 3)
node _beatsAI_opdata_T_17 = bits(in[17].a.bits.opcode, 2, 2)
node beatsAI_opdata_17 = eq(_beatsAI_opdata_T_17, UInt<1>(0h0))
node beatsAI_17 = mux(beatsAI_opdata_17, beatsAI_decode_17, UInt<1>(0h0))
node _beatsAI_decode_T_54 = dshl(UInt<12>(0hfff), in[18].a.bits.size)
node _beatsAI_decode_T_55 = bits(_beatsAI_decode_T_54, 11, 0)
node _beatsAI_decode_T_56 = not(_beatsAI_decode_T_55)
node beatsAI_decode_18 = shr(_beatsAI_decode_T_56, 3)
node _beatsAI_opdata_T_18 = bits(in[18].a.bits.opcode, 2, 2)
node beatsAI_opdata_18 = eq(_beatsAI_opdata_T_18, UInt<1>(0h0))
node beatsAI_18 = mux(beatsAI_opdata_18, beatsAI_decode_18, UInt<1>(0h0))
node _beatsAI_decode_T_57 = dshl(UInt<12>(0hfff), in[19].a.bits.size)
node _beatsAI_decode_T_58 = bits(_beatsAI_decode_T_57, 11, 0)
node _beatsAI_decode_T_59 = not(_beatsAI_decode_T_58)
node beatsAI_decode_19 = shr(_beatsAI_decode_T_59, 3)
node _beatsAI_opdata_T_19 = bits(in[19].a.bits.opcode, 2, 2)
node beatsAI_opdata_19 = eq(_beatsAI_opdata_T_19, UInt<1>(0h0))
node beatsAI_19 = mux(beatsAI_opdata_19, beatsAI_decode_19, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].c.bits.size)
node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0)
node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7)
node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 3)
node beatsCI_opdata_2 = bits(in[2].c.bits.opcode, 0, 0)
node beatsCI_2 = mux(UInt<1>(0h0), beatsCI_decode_2, UInt<1>(0h0))
node _beatsCI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].c.bits.size)
node _beatsCI_decode_T_10 = bits(_beatsCI_decode_T_9, 11, 0)
node _beatsCI_decode_T_11 = not(_beatsCI_decode_T_10)
node beatsCI_decode_3 = shr(_beatsCI_decode_T_11, 3)
node beatsCI_opdata_3 = bits(in[3].c.bits.opcode, 0, 0)
node beatsCI_3 = mux(UInt<1>(0h0), beatsCI_decode_3, UInt<1>(0h0))
node _beatsCI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].c.bits.size)
node _beatsCI_decode_T_13 = bits(_beatsCI_decode_T_12, 11, 0)
node _beatsCI_decode_T_14 = not(_beatsCI_decode_T_13)
node beatsCI_decode_4 = shr(_beatsCI_decode_T_14, 3)
node beatsCI_opdata_4 = bits(in[4].c.bits.opcode, 0, 0)
node beatsCI_4 = mux(UInt<1>(0h0), beatsCI_decode_4, UInt<1>(0h0))
node _beatsCI_decode_T_15 = dshl(UInt<12>(0hfff), in[5].c.bits.size)
node _beatsCI_decode_T_16 = bits(_beatsCI_decode_T_15, 11, 0)
node _beatsCI_decode_T_17 = not(_beatsCI_decode_T_16)
node beatsCI_decode_5 = shr(_beatsCI_decode_T_17, 3)
node beatsCI_opdata_5 = bits(in[5].c.bits.opcode, 0, 0)
node beatsCI_5 = mux(UInt<1>(0h0), beatsCI_decode_5, UInt<1>(0h0))
node _beatsCI_decode_T_18 = dshl(UInt<12>(0hfff), in[6].c.bits.size)
node _beatsCI_decode_T_19 = bits(_beatsCI_decode_T_18, 11, 0)
node _beatsCI_decode_T_20 = not(_beatsCI_decode_T_19)
node beatsCI_decode_6 = shr(_beatsCI_decode_T_20, 3)
node beatsCI_opdata_6 = bits(in[6].c.bits.opcode, 0, 0)
node beatsCI_6 = mux(UInt<1>(0h0), beatsCI_decode_6, UInt<1>(0h0))
node _beatsCI_decode_T_21 = dshl(UInt<12>(0hfff), in[7].c.bits.size)
node _beatsCI_decode_T_22 = bits(_beatsCI_decode_T_21, 11, 0)
node _beatsCI_decode_T_23 = not(_beatsCI_decode_T_22)
node beatsCI_decode_7 = shr(_beatsCI_decode_T_23, 3)
node beatsCI_opdata_7 = bits(in[7].c.bits.opcode, 0, 0)
node beatsCI_7 = mux(UInt<1>(0h0), beatsCI_decode_7, UInt<1>(0h0))
node _beatsCI_decode_T_24 = dshl(UInt<12>(0hfff), in[8].c.bits.size)
node _beatsCI_decode_T_25 = bits(_beatsCI_decode_T_24, 11, 0)
node _beatsCI_decode_T_26 = not(_beatsCI_decode_T_25)
node beatsCI_decode_8 = shr(_beatsCI_decode_T_26, 3)
node beatsCI_opdata_8 = bits(in[8].c.bits.opcode, 0, 0)
node beatsCI_8 = mux(UInt<1>(0h0), beatsCI_decode_8, UInt<1>(0h0))
node _beatsCI_decode_T_27 = dshl(UInt<12>(0hfff), in[9].c.bits.size)
node _beatsCI_decode_T_28 = bits(_beatsCI_decode_T_27, 11, 0)
node _beatsCI_decode_T_29 = not(_beatsCI_decode_T_28)
node beatsCI_decode_9 = shr(_beatsCI_decode_T_29, 3)
node beatsCI_opdata_9 = bits(in[9].c.bits.opcode, 0, 0)
node beatsCI_9 = mux(UInt<1>(0h0), beatsCI_decode_9, UInt<1>(0h0))
node _beatsCI_decode_T_30 = dshl(UInt<12>(0hfff), in[10].c.bits.size)
node _beatsCI_decode_T_31 = bits(_beatsCI_decode_T_30, 11, 0)
node _beatsCI_decode_T_32 = not(_beatsCI_decode_T_31)
node beatsCI_decode_10 = shr(_beatsCI_decode_T_32, 3)
node beatsCI_opdata_10 = bits(in[10].c.bits.opcode, 0, 0)
node beatsCI_10 = mux(UInt<1>(0h0), beatsCI_decode_10, UInt<1>(0h0))
node _beatsCI_decode_T_33 = dshl(UInt<12>(0hfff), in[11].c.bits.size)
node _beatsCI_decode_T_34 = bits(_beatsCI_decode_T_33, 11, 0)
node _beatsCI_decode_T_35 = not(_beatsCI_decode_T_34)
node beatsCI_decode_11 = shr(_beatsCI_decode_T_35, 3)
node beatsCI_opdata_11 = bits(in[11].c.bits.opcode, 0, 0)
node beatsCI_11 = mux(UInt<1>(0h0), beatsCI_decode_11, UInt<1>(0h0))
node _beatsCI_decode_T_36 = dshl(UInt<12>(0hfff), in[12].c.bits.size)
node _beatsCI_decode_T_37 = bits(_beatsCI_decode_T_36, 11, 0)
node _beatsCI_decode_T_38 = not(_beatsCI_decode_T_37)
node beatsCI_decode_12 = shr(_beatsCI_decode_T_38, 3)
node beatsCI_opdata_12 = bits(in[12].c.bits.opcode, 0, 0)
node beatsCI_12 = mux(UInt<1>(0h0), beatsCI_decode_12, UInt<1>(0h0))
node _beatsCI_decode_T_39 = dshl(UInt<12>(0hfff), in[13].c.bits.size)
node _beatsCI_decode_T_40 = bits(_beatsCI_decode_T_39, 11, 0)
node _beatsCI_decode_T_41 = not(_beatsCI_decode_T_40)
node beatsCI_decode_13 = shr(_beatsCI_decode_T_41, 3)
node beatsCI_opdata_13 = bits(in[13].c.bits.opcode, 0, 0)
node beatsCI_13 = mux(UInt<1>(0h0), beatsCI_decode_13, UInt<1>(0h0))
node _beatsCI_decode_T_42 = dshl(UInt<12>(0hfff), in[14].c.bits.size)
node _beatsCI_decode_T_43 = bits(_beatsCI_decode_T_42, 11, 0)
node _beatsCI_decode_T_44 = not(_beatsCI_decode_T_43)
node beatsCI_decode_14 = shr(_beatsCI_decode_T_44, 3)
node beatsCI_opdata_14 = bits(in[14].c.bits.opcode, 0, 0)
node beatsCI_14 = mux(UInt<1>(0h0), beatsCI_decode_14, UInt<1>(0h0))
node _beatsCI_decode_T_45 = dshl(UInt<12>(0hfff), in[15].c.bits.size)
node _beatsCI_decode_T_46 = bits(_beatsCI_decode_T_45, 11, 0)
node _beatsCI_decode_T_47 = not(_beatsCI_decode_T_46)
node beatsCI_decode_15 = shr(_beatsCI_decode_T_47, 3)
node beatsCI_opdata_15 = bits(in[15].c.bits.opcode, 0, 0)
node beatsCI_15 = mux(UInt<1>(0h0), beatsCI_decode_15, UInt<1>(0h0))
node _beatsCI_decode_T_48 = dshl(UInt<12>(0hfff), in[16].c.bits.size)
node _beatsCI_decode_T_49 = bits(_beatsCI_decode_T_48, 11, 0)
node _beatsCI_decode_T_50 = not(_beatsCI_decode_T_49)
node beatsCI_decode_16 = shr(_beatsCI_decode_T_50, 3)
node beatsCI_opdata_16 = bits(in[16].c.bits.opcode, 0, 0)
node beatsCI_16 = mux(UInt<1>(0h0), beatsCI_decode_16, UInt<1>(0h0))
node _beatsCI_decode_T_51 = dshl(UInt<12>(0hfff), in[17].c.bits.size)
node _beatsCI_decode_T_52 = bits(_beatsCI_decode_T_51, 11, 0)
node _beatsCI_decode_T_53 = not(_beatsCI_decode_T_52)
node beatsCI_decode_17 = shr(_beatsCI_decode_T_53, 3)
node beatsCI_opdata_17 = bits(in[17].c.bits.opcode, 0, 0)
node beatsCI_17 = mux(UInt<1>(0h0), beatsCI_decode_17, UInt<1>(0h0))
node _beatsCI_decode_T_54 = dshl(UInt<12>(0hfff), in[18].c.bits.size)
node _beatsCI_decode_T_55 = bits(_beatsCI_decode_T_54, 11, 0)
node _beatsCI_decode_T_56 = not(_beatsCI_decode_T_55)
node beatsCI_decode_18 = shr(_beatsCI_decode_T_56, 3)
node beatsCI_opdata_18 = bits(in[18].c.bits.opcode, 0, 0)
node beatsCI_18 = mux(UInt<1>(0h0), beatsCI_decode_18, UInt<1>(0h0))
node _beatsCI_decode_T_57 = dshl(UInt<12>(0hfff), in[19].c.bits.size)
node _beatsCI_decode_T_58 = bits(_beatsCI_decode_T_57, 11, 0)
node _beatsCI_decode_T_59 = not(_beatsCI_decode_T_58)
node beatsCI_decode_19 = shr(_beatsCI_decode_T_59, 3)
node beatsCI_opdata_19 = bits(in[19].c.bits.opcode, 0, 0)
node beatsCI_19 = mux(beatsCI_opdata_19, beatsCI_decode_19, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect portsAOI_filtered_1[1].bits, in[1].a.bits
node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2)
connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3
node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1)
wire _portsAOI_in_1_a_ready_WIRE : UInt<1>
connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2
connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE
wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_2[0].bits, in[2].a.bits
node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4)
connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5
connect portsAOI_filtered_2[1].bits, in[2].a.bits
node _portsAOI_filtered_1_valid_T_4 = or(requestAIO_2_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_1_valid_T_4)
connect portsAOI_filtered_2[1].valid, _portsAOI_filtered_1_valid_T_5
node _portsAOI_in_2_a_ready_T = mux(requestAIO_2_0, portsAOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsAOI_in_2_a_ready_T_1 = mux(requestAIO_2_1, portsAOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsAOI_in_2_a_ready_T_2 = or(_portsAOI_in_2_a_ready_T, _portsAOI_in_2_a_ready_T_1)
wire _portsAOI_in_2_a_ready_WIRE : UInt<1>
connect _portsAOI_in_2_a_ready_WIRE, _portsAOI_in_2_a_ready_T_2
connect in[2].a.ready, _portsAOI_in_2_a_ready_WIRE
wire portsAOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_3[0].bits, in[3].a.bits
node _portsAOI_filtered_0_valid_T_6 = or(requestAIO_3_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_0_valid_T_6)
connect portsAOI_filtered_3[0].valid, _portsAOI_filtered_0_valid_T_7
connect portsAOI_filtered_3[1].bits, in[3].a.bits
node _portsAOI_filtered_1_valid_T_6 = or(requestAIO_3_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_1_valid_T_6)
connect portsAOI_filtered_3[1].valid, _portsAOI_filtered_1_valid_T_7
node _portsAOI_in_3_a_ready_T = mux(requestAIO_3_0, portsAOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsAOI_in_3_a_ready_T_1 = mux(requestAIO_3_1, portsAOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsAOI_in_3_a_ready_T_2 = or(_portsAOI_in_3_a_ready_T, _portsAOI_in_3_a_ready_T_1)
wire _portsAOI_in_3_a_ready_WIRE : UInt<1>
connect _portsAOI_in_3_a_ready_WIRE, _portsAOI_in_3_a_ready_T_2
connect in[3].a.ready, _portsAOI_in_3_a_ready_WIRE
wire portsAOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_4[0].bits, in[4].a.bits
node _portsAOI_filtered_0_valid_T_8 = or(requestAIO_4_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_0_valid_T_8)
connect portsAOI_filtered_4[0].valid, _portsAOI_filtered_0_valid_T_9
connect portsAOI_filtered_4[1].bits, in[4].a.bits
node _portsAOI_filtered_1_valid_T_8 = or(requestAIO_4_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_1_valid_T_8)
connect portsAOI_filtered_4[1].valid, _portsAOI_filtered_1_valid_T_9
node _portsAOI_in_4_a_ready_T = mux(requestAIO_4_0, portsAOI_filtered_4[0].ready, UInt<1>(0h0))
node _portsAOI_in_4_a_ready_T_1 = mux(requestAIO_4_1, portsAOI_filtered_4[1].ready, UInt<1>(0h0))
node _portsAOI_in_4_a_ready_T_2 = or(_portsAOI_in_4_a_ready_T, _portsAOI_in_4_a_ready_T_1)
wire _portsAOI_in_4_a_ready_WIRE : UInt<1>
connect _portsAOI_in_4_a_ready_WIRE, _portsAOI_in_4_a_ready_T_2
connect in[4].a.ready, _portsAOI_in_4_a_ready_WIRE
wire portsAOI_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_5[0].bits, in[5].a.bits
node _portsAOI_filtered_0_valid_T_10 = or(requestAIO_5_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_11 = and(in[5].a.valid, _portsAOI_filtered_0_valid_T_10)
connect portsAOI_filtered_5[0].valid, _portsAOI_filtered_0_valid_T_11
connect portsAOI_filtered_5[1].bits, in[5].a.bits
node _portsAOI_filtered_1_valid_T_10 = or(requestAIO_5_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_11 = and(in[5].a.valid, _portsAOI_filtered_1_valid_T_10)
connect portsAOI_filtered_5[1].valid, _portsAOI_filtered_1_valid_T_11
node _portsAOI_in_5_a_ready_T = mux(requestAIO_5_0, portsAOI_filtered_5[0].ready, UInt<1>(0h0))
node _portsAOI_in_5_a_ready_T_1 = mux(requestAIO_5_1, portsAOI_filtered_5[1].ready, UInt<1>(0h0))
node _portsAOI_in_5_a_ready_T_2 = or(_portsAOI_in_5_a_ready_T, _portsAOI_in_5_a_ready_T_1)
wire _portsAOI_in_5_a_ready_WIRE : UInt<1>
connect _portsAOI_in_5_a_ready_WIRE, _portsAOI_in_5_a_ready_T_2
connect in[5].a.ready, _portsAOI_in_5_a_ready_WIRE
wire portsAOI_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_6[0].bits, in[6].a.bits
node _portsAOI_filtered_0_valid_T_12 = or(requestAIO_6_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_13 = and(in[6].a.valid, _portsAOI_filtered_0_valid_T_12)
connect portsAOI_filtered_6[0].valid, _portsAOI_filtered_0_valid_T_13
connect portsAOI_filtered_6[1].bits, in[6].a.bits
node _portsAOI_filtered_1_valid_T_12 = or(requestAIO_6_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_13 = and(in[6].a.valid, _portsAOI_filtered_1_valid_T_12)
connect portsAOI_filtered_6[1].valid, _portsAOI_filtered_1_valid_T_13
node _portsAOI_in_6_a_ready_T = mux(requestAIO_6_0, portsAOI_filtered_6[0].ready, UInt<1>(0h0))
node _portsAOI_in_6_a_ready_T_1 = mux(requestAIO_6_1, portsAOI_filtered_6[1].ready, UInt<1>(0h0))
node _portsAOI_in_6_a_ready_T_2 = or(_portsAOI_in_6_a_ready_T, _portsAOI_in_6_a_ready_T_1)
wire _portsAOI_in_6_a_ready_WIRE : UInt<1>
connect _portsAOI_in_6_a_ready_WIRE, _portsAOI_in_6_a_ready_T_2
connect in[6].a.ready, _portsAOI_in_6_a_ready_WIRE
wire portsAOI_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_7[0].bits, in[7].a.bits
node _portsAOI_filtered_0_valid_T_14 = or(requestAIO_7_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_15 = and(in[7].a.valid, _portsAOI_filtered_0_valid_T_14)
connect portsAOI_filtered_7[0].valid, _portsAOI_filtered_0_valid_T_15
connect portsAOI_filtered_7[1].bits, in[7].a.bits
node _portsAOI_filtered_1_valid_T_14 = or(requestAIO_7_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_15 = and(in[7].a.valid, _portsAOI_filtered_1_valid_T_14)
connect portsAOI_filtered_7[1].valid, _portsAOI_filtered_1_valid_T_15
node _portsAOI_in_7_a_ready_T = mux(requestAIO_7_0, portsAOI_filtered_7[0].ready, UInt<1>(0h0))
node _portsAOI_in_7_a_ready_T_1 = mux(requestAIO_7_1, portsAOI_filtered_7[1].ready, UInt<1>(0h0))
node _portsAOI_in_7_a_ready_T_2 = or(_portsAOI_in_7_a_ready_T, _portsAOI_in_7_a_ready_T_1)
wire _portsAOI_in_7_a_ready_WIRE : UInt<1>
connect _portsAOI_in_7_a_ready_WIRE, _portsAOI_in_7_a_ready_T_2
connect in[7].a.ready, _portsAOI_in_7_a_ready_WIRE
wire portsAOI_filtered_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_8[0].bits, in[8].a.bits
node _portsAOI_filtered_0_valid_T_16 = or(requestAIO_8_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_17 = and(in[8].a.valid, _portsAOI_filtered_0_valid_T_16)
connect portsAOI_filtered_8[0].valid, _portsAOI_filtered_0_valid_T_17
connect portsAOI_filtered_8[1].bits, in[8].a.bits
node _portsAOI_filtered_1_valid_T_16 = or(requestAIO_8_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_17 = and(in[8].a.valid, _portsAOI_filtered_1_valid_T_16)
connect portsAOI_filtered_8[1].valid, _portsAOI_filtered_1_valid_T_17
node _portsAOI_in_8_a_ready_T = mux(requestAIO_8_0, portsAOI_filtered_8[0].ready, UInt<1>(0h0))
node _portsAOI_in_8_a_ready_T_1 = mux(requestAIO_8_1, portsAOI_filtered_8[1].ready, UInt<1>(0h0))
node _portsAOI_in_8_a_ready_T_2 = or(_portsAOI_in_8_a_ready_T, _portsAOI_in_8_a_ready_T_1)
wire _portsAOI_in_8_a_ready_WIRE : UInt<1>
connect _portsAOI_in_8_a_ready_WIRE, _portsAOI_in_8_a_ready_T_2
connect in[8].a.ready, _portsAOI_in_8_a_ready_WIRE
wire portsAOI_filtered_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_9[0].bits, in[9].a.bits
node _portsAOI_filtered_0_valid_T_18 = or(requestAIO_9_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_19 = and(in[9].a.valid, _portsAOI_filtered_0_valid_T_18)
connect portsAOI_filtered_9[0].valid, _portsAOI_filtered_0_valid_T_19
connect portsAOI_filtered_9[1].bits, in[9].a.bits
node _portsAOI_filtered_1_valid_T_18 = or(requestAIO_9_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_19 = and(in[9].a.valid, _portsAOI_filtered_1_valid_T_18)
connect portsAOI_filtered_9[1].valid, _portsAOI_filtered_1_valid_T_19
node _portsAOI_in_9_a_ready_T = mux(requestAIO_9_0, portsAOI_filtered_9[0].ready, UInt<1>(0h0))
node _portsAOI_in_9_a_ready_T_1 = mux(requestAIO_9_1, portsAOI_filtered_9[1].ready, UInt<1>(0h0))
node _portsAOI_in_9_a_ready_T_2 = or(_portsAOI_in_9_a_ready_T, _portsAOI_in_9_a_ready_T_1)
wire _portsAOI_in_9_a_ready_WIRE : UInt<1>
connect _portsAOI_in_9_a_ready_WIRE, _portsAOI_in_9_a_ready_T_2
connect in[9].a.ready, _portsAOI_in_9_a_ready_WIRE
wire portsAOI_filtered_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_10[0].bits, in[10].a.bits
node _portsAOI_filtered_0_valid_T_20 = or(requestAIO_10_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_21 = and(in[10].a.valid, _portsAOI_filtered_0_valid_T_20)
connect portsAOI_filtered_10[0].valid, _portsAOI_filtered_0_valid_T_21
connect portsAOI_filtered_10[1].bits, in[10].a.bits
node _portsAOI_filtered_1_valid_T_20 = or(requestAIO_10_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_21 = and(in[10].a.valid, _portsAOI_filtered_1_valid_T_20)
connect portsAOI_filtered_10[1].valid, _portsAOI_filtered_1_valid_T_21
node _portsAOI_in_10_a_ready_T = mux(requestAIO_10_0, portsAOI_filtered_10[0].ready, UInt<1>(0h0))
node _portsAOI_in_10_a_ready_T_1 = mux(requestAIO_10_1, portsAOI_filtered_10[1].ready, UInt<1>(0h0))
node _portsAOI_in_10_a_ready_T_2 = or(_portsAOI_in_10_a_ready_T, _portsAOI_in_10_a_ready_T_1)
wire _portsAOI_in_10_a_ready_WIRE : UInt<1>
connect _portsAOI_in_10_a_ready_WIRE, _portsAOI_in_10_a_ready_T_2
connect in[10].a.ready, _portsAOI_in_10_a_ready_WIRE
wire portsAOI_filtered_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_11[0].bits, in[11].a.bits
node _portsAOI_filtered_0_valid_T_22 = or(requestAIO_11_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_23 = and(in[11].a.valid, _portsAOI_filtered_0_valid_T_22)
connect portsAOI_filtered_11[0].valid, _portsAOI_filtered_0_valid_T_23
connect portsAOI_filtered_11[1].bits, in[11].a.bits
node _portsAOI_filtered_1_valid_T_22 = or(requestAIO_11_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_23 = and(in[11].a.valid, _portsAOI_filtered_1_valid_T_22)
connect portsAOI_filtered_11[1].valid, _portsAOI_filtered_1_valid_T_23
node _portsAOI_in_11_a_ready_T = mux(requestAIO_11_0, portsAOI_filtered_11[0].ready, UInt<1>(0h0))
node _portsAOI_in_11_a_ready_T_1 = mux(requestAIO_11_1, portsAOI_filtered_11[1].ready, UInt<1>(0h0))
node _portsAOI_in_11_a_ready_T_2 = or(_portsAOI_in_11_a_ready_T, _portsAOI_in_11_a_ready_T_1)
wire _portsAOI_in_11_a_ready_WIRE : UInt<1>
connect _portsAOI_in_11_a_ready_WIRE, _portsAOI_in_11_a_ready_T_2
connect in[11].a.ready, _portsAOI_in_11_a_ready_WIRE
wire portsAOI_filtered_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_12[0].bits, in[12].a.bits
node _portsAOI_filtered_0_valid_T_24 = or(requestAIO_12_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_25 = and(in[12].a.valid, _portsAOI_filtered_0_valid_T_24)
connect portsAOI_filtered_12[0].valid, _portsAOI_filtered_0_valid_T_25
connect portsAOI_filtered_12[1].bits, in[12].a.bits
node _portsAOI_filtered_1_valid_T_24 = or(requestAIO_12_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_25 = and(in[12].a.valid, _portsAOI_filtered_1_valid_T_24)
connect portsAOI_filtered_12[1].valid, _portsAOI_filtered_1_valid_T_25
node _portsAOI_in_12_a_ready_T = mux(requestAIO_12_0, portsAOI_filtered_12[0].ready, UInt<1>(0h0))
node _portsAOI_in_12_a_ready_T_1 = mux(requestAIO_12_1, portsAOI_filtered_12[1].ready, UInt<1>(0h0))
node _portsAOI_in_12_a_ready_T_2 = or(_portsAOI_in_12_a_ready_T, _portsAOI_in_12_a_ready_T_1)
wire _portsAOI_in_12_a_ready_WIRE : UInt<1>
connect _portsAOI_in_12_a_ready_WIRE, _portsAOI_in_12_a_ready_T_2
connect in[12].a.ready, _portsAOI_in_12_a_ready_WIRE
wire portsAOI_filtered_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_13[0].bits, in[13].a.bits
node _portsAOI_filtered_0_valid_T_26 = or(requestAIO_13_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_27 = and(in[13].a.valid, _portsAOI_filtered_0_valid_T_26)
connect portsAOI_filtered_13[0].valid, _portsAOI_filtered_0_valid_T_27
connect portsAOI_filtered_13[1].bits, in[13].a.bits
node _portsAOI_filtered_1_valid_T_26 = or(requestAIO_13_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_27 = and(in[13].a.valid, _portsAOI_filtered_1_valid_T_26)
connect portsAOI_filtered_13[1].valid, _portsAOI_filtered_1_valid_T_27
node _portsAOI_in_13_a_ready_T = mux(requestAIO_13_0, portsAOI_filtered_13[0].ready, UInt<1>(0h0))
node _portsAOI_in_13_a_ready_T_1 = mux(requestAIO_13_1, portsAOI_filtered_13[1].ready, UInt<1>(0h0))
node _portsAOI_in_13_a_ready_T_2 = or(_portsAOI_in_13_a_ready_T, _portsAOI_in_13_a_ready_T_1)
wire _portsAOI_in_13_a_ready_WIRE : UInt<1>
connect _portsAOI_in_13_a_ready_WIRE, _portsAOI_in_13_a_ready_T_2
connect in[13].a.ready, _portsAOI_in_13_a_ready_WIRE
wire portsAOI_filtered_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_14[0].bits, in[14].a.bits
node _portsAOI_filtered_0_valid_T_28 = or(requestAIO_14_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_29 = and(in[14].a.valid, _portsAOI_filtered_0_valid_T_28)
connect portsAOI_filtered_14[0].valid, _portsAOI_filtered_0_valid_T_29
connect portsAOI_filtered_14[1].bits, in[14].a.bits
node _portsAOI_filtered_1_valid_T_28 = or(requestAIO_14_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_29 = and(in[14].a.valid, _portsAOI_filtered_1_valid_T_28)
connect portsAOI_filtered_14[1].valid, _portsAOI_filtered_1_valid_T_29
node _portsAOI_in_14_a_ready_T = mux(requestAIO_14_0, portsAOI_filtered_14[0].ready, UInt<1>(0h0))
node _portsAOI_in_14_a_ready_T_1 = mux(requestAIO_14_1, portsAOI_filtered_14[1].ready, UInt<1>(0h0))
node _portsAOI_in_14_a_ready_T_2 = or(_portsAOI_in_14_a_ready_T, _portsAOI_in_14_a_ready_T_1)
wire _portsAOI_in_14_a_ready_WIRE : UInt<1>
connect _portsAOI_in_14_a_ready_WIRE, _portsAOI_in_14_a_ready_T_2
connect in[14].a.ready, _portsAOI_in_14_a_ready_WIRE
wire portsAOI_filtered_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_15[0].bits, in[15].a.bits
node _portsAOI_filtered_0_valid_T_30 = or(requestAIO_15_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_31 = and(in[15].a.valid, _portsAOI_filtered_0_valid_T_30)
connect portsAOI_filtered_15[0].valid, _portsAOI_filtered_0_valid_T_31
connect portsAOI_filtered_15[1].bits, in[15].a.bits
node _portsAOI_filtered_1_valid_T_30 = or(requestAIO_15_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_31 = and(in[15].a.valid, _portsAOI_filtered_1_valid_T_30)
connect portsAOI_filtered_15[1].valid, _portsAOI_filtered_1_valid_T_31
node _portsAOI_in_15_a_ready_T = mux(requestAIO_15_0, portsAOI_filtered_15[0].ready, UInt<1>(0h0))
node _portsAOI_in_15_a_ready_T_1 = mux(requestAIO_15_1, portsAOI_filtered_15[1].ready, UInt<1>(0h0))
node _portsAOI_in_15_a_ready_T_2 = or(_portsAOI_in_15_a_ready_T, _portsAOI_in_15_a_ready_T_1)
wire _portsAOI_in_15_a_ready_WIRE : UInt<1>
connect _portsAOI_in_15_a_ready_WIRE, _portsAOI_in_15_a_ready_T_2
connect in[15].a.ready, _portsAOI_in_15_a_ready_WIRE
wire portsAOI_filtered_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_16[0].bits, in[16].a.bits
node _portsAOI_filtered_0_valid_T_32 = or(requestAIO_16_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_33 = and(in[16].a.valid, _portsAOI_filtered_0_valid_T_32)
connect portsAOI_filtered_16[0].valid, _portsAOI_filtered_0_valid_T_33
connect portsAOI_filtered_16[1].bits, in[16].a.bits
node _portsAOI_filtered_1_valid_T_32 = or(requestAIO_16_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_33 = and(in[16].a.valid, _portsAOI_filtered_1_valid_T_32)
connect portsAOI_filtered_16[1].valid, _portsAOI_filtered_1_valid_T_33
node _portsAOI_in_16_a_ready_T = mux(requestAIO_16_0, portsAOI_filtered_16[0].ready, UInt<1>(0h0))
node _portsAOI_in_16_a_ready_T_1 = mux(requestAIO_16_1, portsAOI_filtered_16[1].ready, UInt<1>(0h0))
node _portsAOI_in_16_a_ready_T_2 = or(_portsAOI_in_16_a_ready_T, _portsAOI_in_16_a_ready_T_1)
wire _portsAOI_in_16_a_ready_WIRE : UInt<1>
connect _portsAOI_in_16_a_ready_WIRE, _portsAOI_in_16_a_ready_T_2
connect in[16].a.ready, _portsAOI_in_16_a_ready_WIRE
wire portsAOI_filtered_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_17[0].bits, in[17].a.bits
node _portsAOI_filtered_0_valid_T_34 = or(requestAIO_17_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_35 = and(in[17].a.valid, _portsAOI_filtered_0_valid_T_34)
connect portsAOI_filtered_17[0].valid, _portsAOI_filtered_0_valid_T_35
connect portsAOI_filtered_17[1].bits, in[17].a.bits
node _portsAOI_filtered_1_valid_T_34 = or(requestAIO_17_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_35 = and(in[17].a.valid, _portsAOI_filtered_1_valid_T_34)
connect portsAOI_filtered_17[1].valid, _portsAOI_filtered_1_valid_T_35
node _portsAOI_in_17_a_ready_T = mux(requestAIO_17_0, portsAOI_filtered_17[0].ready, UInt<1>(0h0))
node _portsAOI_in_17_a_ready_T_1 = mux(requestAIO_17_1, portsAOI_filtered_17[1].ready, UInt<1>(0h0))
node _portsAOI_in_17_a_ready_T_2 = or(_portsAOI_in_17_a_ready_T, _portsAOI_in_17_a_ready_T_1)
wire _portsAOI_in_17_a_ready_WIRE : UInt<1>
connect _portsAOI_in_17_a_ready_WIRE, _portsAOI_in_17_a_ready_T_2
connect in[17].a.ready, _portsAOI_in_17_a_ready_WIRE
wire portsAOI_filtered_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_18[0].bits, in[18].a.bits
node _portsAOI_filtered_0_valid_T_36 = or(requestAIO_18_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_37 = and(in[18].a.valid, _portsAOI_filtered_0_valid_T_36)
connect portsAOI_filtered_18[0].valid, _portsAOI_filtered_0_valid_T_37
connect portsAOI_filtered_18[1].bits, in[18].a.bits
node _portsAOI_filtered_1_valid_T_36 = or(requestAIO_18_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_37 = and(in[18].a.valid, _portsAOI_filtered_1_valid_T_36)
connect portsAOI_filtered_18[1].valid, _portsAOI_filtered_1_valid_T_37
node _portsAOI_in_18_a_ready_T = mux(requestAIO_18_0, portsAOI_filtered_18[0].ready, UInt<1>(0h0))
node _portsAOI_in_18_a_ready_T_1 = mux(requestAIO_18_1, portsAOI_filtered_18[1].ready, UInt<1>(0h0))
node _portsAOI_in_18_a_ready_T_2 = or(_portsAOI_in_18_a_ready_T, _portsAOI_in_18_a_ready_T_1)
wire _portsAOI_in_18_a_ready_WIRE : UInt<1>
connect _portsAOI_in_18_a_ready_WIRE, _portsAOI_in_18_a_ready_T_2
connect in[18].a.ready, _portsAOI_in_18_a_ready_WIRE
wire portsAOI_filtered_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_19[0].bits, in[19].a.bits
node _portsAOI_filtered_0_valid_T_38 = or(requestAIO_19_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_39 = and(in[19].a.valid, _portsAOI_filtered_0_valid_T_38)
connect portsAOI_filtered_19[0].valid, _portsAOI_filtered_0_valid_T_39
connect portsAOI_filtered_19[1].bits, in[19].a.bits
node _portsAOI_filtered_1_valid_T_38 = or(requestAIO_19_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_39 = and(in[19].a.valid, _portsAOI_filtered_1_valid_T_38)
connect portsAOI_filtered_19[1].valid, _portsAOI_filtered_1_valid_T_39
node _portsAOI_in_19_a_ready_T = mux(requestAIO_19_0, portsAOI_filtered_19[0].ready, UInt<1>(0h0))
node _portsAOI_in_19_a_ready_T_1 = mux(requestAIO_19_1, portsAOI_filtered_19[1].ready, UInt<1>(0h0))
node _portsAOI_in_19_a_ready_T_2 = or(_portsAOI_in_19_a_ready_T, _portsAOI_in_19_a_ready_T_1)
wire _portsAOI_in_19_a_ready_WIRE : UInt<1>
connect _portsAOI_in_19_a_ready_WIRE, _portsAOI_in_19_a_ready_T_2
connect in[19].a.ready, _portsAOI_in_19_a_ready_WIRE
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[20]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
connect portsBIO_filtered[2].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[2].bits.data, out[0].b.bits.data
connect portsBIO_filtered[2].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[2].bits.address, out[0].b.bits.address
connect portsBIO_filtered[2].bits.source, out[0].b.bits.source
connect portsBIO_filtered[2].bits.size, out[0].b.bits.size
connect portsBIO_filtered[2].bits.param, out[0].b.bits.param
connect portsBIO_filtered[2].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_2_valid_T)
connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1
connect portsBIO_filtered[3].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[3].bits.data, out[0].b.bits.data
connect portsBIO_filtered[3].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[3].bits.address, out[0].b.bits.address
connect portsBIO_filtered[3].bits.source, out[0].b.bits.source
connect portsBIO_filtered[3].bits.size, out[0].b.bits.size
connect portsBIO_filtered[3].bits.param, out[0].b.bits.param
connect portsBIO_filtered[3].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_3_valid_T = or(requestBOI_0_3, UInt<1>(0h0))
node _portsBIO_filtered_3_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_3_valid_T)
connect portsBIO_filtered[3].valid, _portsBIO_filtered_3_valid_T_1
connect portsBIO_filtered[4].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[4].bits.data, out[0].b.bits.data
connect portsBIO_filtered[4].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[4].bits.address, out[0].b.bits.address
connect portsBIO_filtered[4].bits.source, out[0].b.bits.source
connect portsBIO_filtered[4].bits.size, out[0].b.bits.size
connect portsBIO_filtered[4].bits.param, out[0].b.bits.param
connect portsBIO_filtered[4].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_4_valid_T = or(requestBOI_0_4, UInt<1>(0h0))
node _portsBIO_filtered_4_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_4_valid_T)
connect portsBIO_filtered[4].valid, _portsBIO_filtered_4_valid_T_1
connect portsBIO_filtered[5].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[5].bits.data, out[0].b.bits.data
connect portsBIO_filtered[5].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[5].bits.address, out[0].b.bits.address
connect portsBIO_filtered[5].bits.source, out[0].b.bits.source
connect portsBIO_filtered[5].bits.size, out[0].b.bits.size
connect portsBIO_filtered[5].bits.param, out[0].b.bits.param
connect portsBIO_filtered[5].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_5_valid_T = or(requestBOI_0_5, UInt<1>(0h0))
node _portsBIO_filtered_5_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_5_valid_T)
connect portsBIO_filtered[5].valid, _portsBIO_filtered_5_valid_T_1
connect portsBIO_filtered[6].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[6].bits.data, out[0].b.bits.data
connect portsBIO_filtered[6].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[6].bits.address, out[0].b.bits.address
connect portsBIO_filtered[6].bits.source, out[0].b.bits.source
connect portsBIO_filtered[6].bits.size, out[0].b.bits.size
connect portsBIO_filtered[6].bits.param, out[0].b.bits.param
connect portsBIO_filtered[6].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_6_valid_T = or(requestBOI_0_6, UInt<1>(0h0))
node _portsBIO_filtered_6_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_6_valid_T)
connect portsBIO_filtered[6].valid, _portsBIO_filtered_6_valid_T_1
connect portsBIO_filtered[7].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[7].bits.data, out[0].b.bits.data
connect portsBIO_filtered[7].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[7].bits.address, out[0].b.bits.address
connect portsBIO_filtered[7].bits.source, out[0].b.bits.source
connect portsBIO_filtered[7].bits.size, out[0].b.bits.size
connect portsBIO_filtered[7].bits.param, out[0].b.bits.param
connect portsBIO_filtered[7].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_7_valid_T = or(requestBOI_0_7, UInt<1>(0h0))
node _portsBIO_filtered_7_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_7_valid_T)
connect portsBIO_filtered[7].valid, _portsBIO_filtered_7_valid_T_1
connect portsBIO_filtered[8].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[8].bits.data, out[0].b.bits.data
connect portsBIO_filtered[8].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[8].bits.address, out[0].b.bits.address
connect portsBIO_filtered[8].bits.source, out[0].b.bits.source
connect portsBIO_filtered[8].bits.size, out[0].b.bits.size
connect portsBIO_filtered[8].bits.param, out[0].b.bits.param
connect portsBIO_filtered[8].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_8_valid_T = or(requestBOI_0_8, UInt<1>(0h0))
node _portsBIO_filtered_8_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_8_valid_T)
connect portsBIO_filtered[8].valid, _portsBIO_filtered_8_valid_T_1
connect portsBIO_filtered[9].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[9].bits.data, out[0].b.bits.data
connect portsBIO_filtered[9].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[9].bits.address, out[0].b.bits.address
connect portsBIO_filtered[9].bits.source, out[0].b.bits.source
connect portsBIO_filtered[9].bits.size, out[0].b.bits.size
connect portsBIO_filtered[9].bits.param, out[0].b.bits.param
connect portsBIO_filtered[9].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_9_valid_T = or(requestBOI_0_9, UInt<1>(0h0))
node _portsBIO_filtered_9_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_9_valid_T)
connect portsBIO_filtered[9].valid, _portsBIO_filtered_9_valid_T_1
connect portsBIO_filtered[10].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[10].bits.data, out[0].b.bits.data
connect portsBIO_filtered[10].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[10].bits.address, out[0].b.bits.address
connect portsBIO_filtered[10].bits.source, out[0].b.bits.source
connect portsBIO_filtered[10].bits.size, out[0].b.bits.size
connect portsBIO_filtered[10].bits.param, out[0].b.bits.param
connect portsBIO_filtered[10].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_10_valid_T = or(requestBOI_0_10, UInt<1>(0h0))
node _portsBIO_filtered_10_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_10_valid_T)
connect portsBIO_filtered[10].valid, _portsBIO_filtered_10_valid_T_1
connect portsBIO_filtered[11].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[11].bits.data, out[0].b.bits.data
connect portsBIO_filtered[11].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[11].bits.address, out[0].b.bits.address
connect portsBIO_filtered[11].bits.source, out[0].b.bits.source
connect portsBIO_filtered[11].bits.size, out[0].b.bits.size
connect portsBIO_filtered[11].bits.param, out[0].b.bits.param
connect portsBIO_filtered[11].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_11_valid_T = or(requestBOI_0_11, UInt<1>(0h0))
node _portsBIO_filtered_11_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_11_valid_T)
connect portsBIO_filtered[11].valid, _portsBIO_filtered_11_valid_T_1
connect portsBIO_filtered[12].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[12].bits.data, out[0].b.bits.data
connect portsBIO_filtered[12].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[12].bits.address, out[0].b.bits.address
connect portsBIO_filtered[12].bits.source, out[0].b.bits.source
connect portsBIO_filtered[12].bits.size, out[0].b.bits.size
connect portsBIO_filtered[12].bits.param, out[0].b.bits.param
connect portsBIO_filtered[12].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_12_valid_T = or(requestBOI_0_12, UInt<1>(0h0))
node _portsBIO_filtered_12_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_12_valid_T)
connect portsBIO_filtered[12].valid, _portsBIO_filtered_12_valid_T_1
connect portsBIO_filtered[13].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[13].bits.data, out[0].b.bits.data
connect portsBIO_filtered[13].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[13].bits.address, out[0].b.bits.address
connect portsBIO_filtered[13].bits.source, out[0].b.bits.source
connect portsBIO_filtered[13].bits.size, out[0].b.bits.size
connect portsBIO_filtered[13].bits.param, out[0].b.bits.param
connect portsBIO_filtered[13].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_13_valid_T = or(requestBOI_0_13, UInt<1>(0h0))
node _portsBIO_filtered_13_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_13_valid_T)
connect portsBIO_filtered[13].valid, _portsBIO_filtered_13_valid_T_1
connect portsBIO_filtered[14].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[14].bits.data, out[0].b.bits.data
connect portsBIO_filtered[14].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[14].bits.address, out[0].b.bits.address
connect portsBIO_filtered[14].bits.source, out[0].b.bits.source
connect portsBIO_filtered[14].bits.size, out[0].b.bits.size
connect portsBIO_filtered[14].bits.param, out[0].b.bits.param
connect portsBIO_filtered[14].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_14_valid_T = or(requestBOI_0_14, UInt<1>(0h0))
node _portsBIO_filtered_14_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_14_valid_T)
connect portsBIO_filtered[14].valid, _portsBIO_filtered_14_valid_T_1
connect portsBIO_filtered[15].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[15].bits.data, out[0].b.bits.data
connect portsBIO_filtered[15].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[15].bits.address, out[0].b.bits.address
connect portsBIO_filtered[15].bits.source, out[0].b.bits.source
connect portsBIO_filtered[15].bits.size, out[0].b.bits.size
connect portsBIO_filtered[15].bits.param, out[0].b.bits.param
connect portsBIO_filtered[15].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_15_valid_T = or(requestBOI_0_15, UInt<1>(0h0))
node _portsBIO_filtered_15_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_15_valid_T)
connect portsBIO_filtered[15].valid, _portsBIO_filtered_15_valid_T_1
connect portsBIO_filtered[16].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[16].bits.data, out[0].b.bits.data
connect portsBIO_filtered[16].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[16].bits.address, out[0].b.bits.address
connect portsBIO_filtered[16].bits.source, out[0].b.bits.source
connect portsBIO_filtered[16].bits.size, out[0].b.bits.size
connect portsBIO_filtered[16].bits.param, out[0].b.bits.param
connect portsBIO_filtered[16].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_16_valid_T = or(requestBOI_0_16, UInt<1>(0h0))
node _portsBIO_filtered_16_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_16_valid_T)
connect portsBIO_filtered[16].valid, _portsBIO_filtered_16_valid_T_1
connect portsBIO_filtered[17].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[17].bits.data, out[0].b.bits.data
connect portsBIO_filtered[17].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[17].bits.address, out[0].b.bits.address
connect portsBIO_filtered[17].bits.source, out[0].b.bits.source
connect portsBIO_filtered[17].bits.size, out[0].b.bits.size
connect portsBIO_filtered[17].bits.param, out[0].b.bits.param
connect portsBIO_filtered[17].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_17_valid_T = or(requestBOI_0_17, UInt<1>(0h0))
node _portsBIO_filtered_17_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_17_valid_T)
connect portsBIO_filtered[17].valid, _portsBIO_filtered_17_valid_T_1
connect portsBIO_filtered[18].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[18].bits.data, out[0].b.bits.data
connect portsBIO_filtered[18].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[18].bits.address, out[0].b.bits.address
connect portsBIO_filtered[18].bits.source, out[0].b.bits.source
connect portsBIO_filtered[18].bits.size, out[0].b.bits.size
connect portsBIO_filtered[18].bits.param, out[0].b.bits.param
connect portsBIO_filtered[18].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_18_valid_T = or(requestBOI_0_18, UInt<1>(0h0))
node _portsBIO_filtered_18_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_18_valid_T)
connect portsBIO_filtered[18].valid, _portsBIO_filtered_18_valid_T_1
connect portsBIO_filtered[19].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[19].bits.data, out[0].b.bits.data
connect portsBIO_filtered[19].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[19].bits.address, out[0].b.bits.address
connect portsBIO_filtered[19].bits.source, out[0].b.bits.source
connect portsBIO_filtered[19].bits.size, out[0].b.bits.size
connect portsBIO_filtered[19].bits.param, out[0].b.bits.param
connect portsBIO_filtered[19].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_19_valid_T = or(requestBOI_0_19, UInt<1>(0h0))
node _portsBIO_filtered_19_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_19_valid_T)
connect portsBIO_filtered[19].valid, _portsBIO_filtered_19_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_3 = mux(requestBOI_0_3, portsBIO_filtered[3].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_4 = mux(requestBOI_0_4, portsBIO_filtered[4].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_5 = mux(requestBOI_0_5, portsBIO_filtered[5].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_6 = mux(requestBOI_0_6, portsBIO_filtered[6].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_7 = mux(requestBOI_0_7, portsBIO_filtered[7].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_8 = mux(requestBOI_0_8, portsBIO_filtered[8].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_9 = mux(requestBOI_0_9, portsBIO_filtered[9].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_10 = mux(requestBOI_0_10, portsBIO_filtered[10].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_11 = mux(requestBOI_0_11, portsBIO_filtered[11].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_12 = mux(requestBOI_0_12, portsBIO_filtered[12].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_13 = mux(requestBOI_0_13, portsBIO_filtered[13].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_14 = mux(requestBOI_0_14, portsBIO_filtered[14].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_15 = mux(requestBOI_0_15, portsBIO_filtered[15].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_16 = mux(requestBOI_0_16, portsBIO_filtered[16].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_17 = mux(requestBOI_0_17, portsBIO_filtered[17].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_18 = mux(requestBOI_0_18, portsBIO_filtered[18].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_19 = mux(requestBOI_0_19, portsBIO_filtered[19].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_20 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
node _portsBIO_out_0_b_ready_T_21 = or(_portsBIO_out_0_b_ready_T_20, _portsBIO_out_0_b_ready_T_2)
node _portsBIO_out_0_b_ready_T_22 = or(_portsBIO_out_0_b_ready_T_21, _portsBIO_out_0_b_ready_T_3)
node _portsBIO_out_0_b_ready_T_23 = or(_portsBIO_out_0_b_ready_T_22, _portsBIO_out_0_b_ready_T_4)
node _portsBIO_out_0_b_ready_T_24 = or(_portsBIO_out_0_b_ready_T_23, _portsBIO_out_0_b_ready_T_5)
node _portsBIO_out_0_b_ready_T_25 = or(_portsBIO_out_0_b_ready_T_24, _portsBIO_out_0_b_ready_T_6)
node _portsBIO_out_0_b_ready_T_26 = or(_portsBIO_out_0_b_ready_T_25, _portsBIO_out_0_b_ready_T_7)
node _portsBIO_out_0_b_ready_T_27 = or(_portsBIO_out_0_b_ready_T_26, _portsBIO_out_0_b_ready_T_8)
node _portsBIO_out_0_b_ready_T_28 = or(_portsBIO_out_0_b_ready_T_27, _portsBIO_out_0_b_ready_T_9)
node _portsBIO_out_0_b_ready_T_29 = or(_portsBIO_out_0_b_ready_T_28, _portsBIO_out_0_b_ready_T_10)
node _portsBIO_out_0_b_ready_T_30 = or(_portsBIO_out_0_b_ready_T_29, _portsBIO_out_0_b_ready_T_11)
node _portsBIO_out_0_b_ready_T_31 = or(_portsBIO_out_0_b_ready_T_30, _portsBIO_out_0_b_ready_T_12)
node _portsBIO_out_0_b_ready_T_32 = or(_portsBIO_out_0_b_ready_T_31, _portsBIO_out_0_b_ready_T_13)
node _portsBIO_out_0_b_ready_T_33 = or(_portsBIO_out_0_b_ready_T_32, _portsBIO_out_0_b_ready_T_14)
node _portsBIO_out_0_b_ready_T_34 = or(_portsBIO_out_0_b_ready_T_33, _portsBIO_out_0_b_ready_T_15)
node _portsBIO_out_0_b_ready_T_35 = or(_portsBIO_out_0_b_ready_T_34, _portsBIO_out_0_b_ready_T_16)
node _portsBIO_out_0_b_ready_T_36 = or(_portsBIO_out_0_b_ready_T_35, _portsBIO_out_0_b_ready_T_17)
node _portsBIO_out_0_b_ready_T_37 = or(_portsBIO_out_0_b_ready_T_36, _portsBIO_out_0_b_ready_T_18)
node _portsBIO_out_0_b_ready_T_38 = or(_portsBIO_out_0_b_ready_T_37, _portsBIO_out_0_b_ready_T_19)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_38
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[20]
connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2)
connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3
connect portsBIO_filtered_1[2].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[2].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[2].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[2].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[2].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[2].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[2].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[2].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_2_valid_T_2 = or(requestBOI_1_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_2_valid_T_2)
connect portsBIO_filtered_1[2].valid, _portsBIO_filtered_2_valid_T_3
connect portsBIO_filtered_1[3].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[3].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[3].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[3].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[3].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[3].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[3].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[3].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_3_valid_T_2 = or(requestBOI_1_3, UInt<1>(0h0))
node _portsBIO_filtered_3_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_3_valid_T_2)
connect portsBIO_filtered_1[3].valid, _portsBIO_filtered_3_valid_T_3
connect portsBIO_filtered_1[4].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[4].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[4].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[4].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[4].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[4].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[4].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[4].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_4_valid_T_2 = or(requestBOI_1_4, UInt<1>(0h0))
node _portsBIO_filtered_4_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_4_valid_T_2)
connect portsBIO_filtered_1[4].valid, _portsBIO_filtered_4_valid_T_3
connect portsBIO_filtered_1[5].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[5].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[5].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[5].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[5].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[5].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[5].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[5].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_5_valid_T_2 = or(requestBOI_1_5, UInt<1>(0h0))
node _portsBIO_filtered_5_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_5_valid_T_2)
connect portsBIO_filtered_1[5].valid, _portsBIO_filtered_5_valid_T_3
connect portsBIO_filtered_1[6].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[6].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[6].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[6].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[6].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[6].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[6].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[6].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_6_valid_T_2 = or(requestBOI_1_6, UInt<1>(0h0))
node _portsBIO_filtered_6_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_6_valid_T_2)
connect portsBIO_filtered_1[6].valid, _portsBIO_filtered_6_valid_T_3
connect portsBIO_filtered_1[7].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[7].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[7].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[7].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[7].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[7].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[7].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[7].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_7_valid_T_2 = or(requestBOI_1_7, UInt<1>(0h0))
node _portsBIO_filtered_7_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_7_valid_T_2)
connect portsBIO_filtered_1[7].valid, _portsBIO_filtered_7_valid_T_3
connect portsBIO_filtered_1[8].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[8].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[8].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[8].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[8].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[8].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[8].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[8].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_8_valid_T_2 = or(requestBOI_1_8, UInt<1>(0h0))
node _portsBIO_filtered_8_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_8_valid_T_2)
connect portsBIO_filtered_1[8].valid, _portsBIO_filtered_8_valid_T_3
connect portsBIO_filtered_1[9].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[9].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[9].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[9].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[9].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[9].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[9].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[9].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_9_valid_T_2 = or(requestBOI_1_9, UInt<1>(0h0))
node _portsBIO_filtered_9_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_9_valid_T_2)
connect portsBIO_filtered_1[9].valid, _portsBIO_filtered_9_valid_T_3
connect portsBIO_filtered_1[10].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[10].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[10].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[10].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[10].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[10].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[10].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[10].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_10_valid_T_2 = or(requestBOI_1_10, UInt<1>(0h0))
node _portsBIO_filtered_10_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_10_valid_T_2)
connect portsBIO_filtered_1[10].valid, _portsBIO_filtered_10_valid_T_3
connect portsBIO_filtered_1[11].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[11].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[11].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[11].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[11].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[11].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[11].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[11].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_11_valid_T_2 = or(requestBOI_1_11, UInt<1>(0h0))
node _portsBIO_filtered_11_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_11_valid_T_2)
connect portsBIO_filtered_1[11].valid, _portsBIO_filtered_11_valid_T_3
connect portsBIO_filtered_1[12].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[12].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[12].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[12].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[12].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[12].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[12].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[12].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_12_valid_T_2 = or(requestBOI_1_12, UInt<1>(0h0))
node _portsBIO_filtered_12_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_12_valid_T_2)
connect portsBIO_filtered_1[12].valid, _portsBIO_filtered_12_valid_T_3
connect portsBIO_filtered_1[13].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[13].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[13].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[13].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[13].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[13].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[13].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[13].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_13_valid_T_2 = or(requestBOI_1_13, UInt<1>(0h0))
node _portsBIO_filtered_13_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_13_valid_T_2)
connect portsBIO_filtered_1[13].valid, _portsBIO_filtered_13_valid_T_3
connect portsBIO_filtered_1[14].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[14].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[14].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[14].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[14].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[14].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[14].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[14].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_14_valid_T_2 = or(requestBOI_1_14, UInt<1>(0h0))
node _portsBIO_filtered_14_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_14_valid_T_2)
connect portsBIO_filtered_1[14].valid, _portsBIO_filtered_14_valid_T_3
connect portsBIO_filtered_1[15].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[15].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[15].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[15].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[15].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[15].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[15].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[15].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_15_valid_T_2 = or(requestBOI_1_15, UInt<1>(0h0))
node _portsBIO_filtered_15_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_15_valid_T_2)
connect portsBIO_filtered_1[15].valid, _portsBIO_filtered_15_valid_T_3
connect portsBIO_filtered_1[16].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[16].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[16].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[16].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[16].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[16].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[16].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[16].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_16_valid_T_2 = or(requestBOI_1_16, UInt<1>(0h0))
node _portsBIO_filtered_16_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_16_valid_T_2)
connect portsBIO_filtered_1[16].valid, _portsBIO_filtered_16_valid_T_3
connect portsBIO_filtered_1[17].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[17].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[17].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[17].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[17].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[17].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[17].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[17].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_17_valid_T_2 = or(requestBOI_1_17, UInt<1>(0h0))
node _portsBIO_filtered_17_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_17_valid_T_2)
connect portsBIO_filtered_1[17].valid, _portsBIO_filtered_17_valid_T_3
connect portsBIO_filtered_1[18].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[18].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[18].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[18].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[18].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[18].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[18].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[18].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_18_valid_T_2 = or(requestBOI_1_18, UInt<1>(0h0))
node _portsBIO_filtered_18_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_18_valid_T_2)
connect portsBIO_filtered_1[18].valid, _portsBIO_filtered_18_valid_T_3
connect portsBIO_filtered_1[19].bits.corrupt, out[1].b.bits.corrupt
connect portsBIO_filtered_1[19].bits.data, out[1].b.bits.data
connect portsBIO_filtered_1[19].bits.mask, out[1].b.bits.mask
connect portsBIO_filtered_1[19].bits.address, out[1].b.bits.address
connect portsBIO_filtered_1[19].bits.source, out[1].b.bits.source
connect portsBIO_filtered_1[19].bits.size, out[1].b.bits.size
connect portsBIO_filtered_1[19].bits.param, out[1].b.bits.param
connect portsBIO_filtered_1[19].bits.opcode, out[1].b.bits.opcode
node _portsBIO_filtered_19_valid_T_2 = or(requestBOI_1_19, UInt<1>(0h0))
node _portsBIO_filtered_19_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_19_valid_T_2)
connect portsBIO_filtered_1[19].valid, _portsBIO_filtered_19_valid_T_3
node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_2 = mux(requestBOI_1_2, portsBIO_filtered_1[2].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_3 = mux(requestBOI_1_3, portsBIO_filtered_1[3].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_4 = mux(requestBOI_1_4, portsBIO_filtered_1[4].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_5 = mux(requestBOI_1_5, portsBIO_filtered_1[5].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_6 = mux(requestBOI_1_6, portsBIO_filtered_1[6].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_7 = mux(requestBOI_1_7, portsBIO_filtered_1[7].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_8 = mux(requestBOI_1_8, portsBIO_filtered_1[8].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_9 = mux(requestBOI_1_9, portsBIO_filtered_1[9].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_10 = mux(requestBOI_1_10, portsBIO_filtered_1[10].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_11 = mux(requestBOI_1_11, portsBIO_filtered_1[11].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_12 = mux(requestBOI_1_12, portsBIO_filtered_1[12].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_13 = mux(requestBOI_1_13, portsBIO_filtered_1[13].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_14 = mux(requestBOI_1_14, portsBIO_filtered_1[14].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_15 = mux(requestBOI_1_15, portsBIO_filtered_1[15].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_16 = mux(requestBOI_1_16, portsBIO_filtered_1[16].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_17 = mux(requestBOI_1_17, portsBIO_filtered_1[17].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_18 = mux(requestBOI_1_18, portsBIO_filtered_1[18].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_19 = mux(requestBOI_1_19, portsBIO_filtered_1[19].ready, UInt<1>(0h0))
node _portsBIO_out_1_b_ready_T_20 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1)
node _portsBIO_out_1_b_ready_T_21 = or(_portsBIO_out_1_b_ready_T_20, _portsBIO_out_1_b_ready_T_2)
node _portsBIO_out_1_b_ready_T_22 = or(_portsBIO_out_1_b_ready_T_21, _portsBIO_out_1_b_ready_T_3)
node _portsBIO_out_1_b_ready_T_23 = or(_portsBIO_out_1_b_ready_T_22, _portsBIO_out_1_b_ready_T_4)
node _portsBIO_out_1_b_ready_T_24 = or(_portsBIO_out_1_b_ready_T_23, _portsBIO_out_1_b_ready_T_5)
node _portsBIO_out_1_b_ready_T_25 = or(_portsBIO_out_1_b_ready_T_24, _portsBIO_out_1_b_ready_T_6)
node _portsBIO_out_1_b_ready_T_26 = or(_portsBIO_out_1_b_ready_T_25, _portsBIO_out_1_b_ready_T_7)
node _portsBIO_out_1_b_ready_T_27 = or(_portsBIO_out_1_b_ready_T_26, _portsBIO_out_1_b_ready_T_8)
node _portsBIO_out_1_b_ready_T_28 = or(_portsBIO_out_1_b_ready_T_27, _portsBIO_out_1_b_ready_T_9)
node _portsBIO_out_1_b_ready_T_29 = or(_portsBIO_out_1_b_ready_T_28, _portsBIO_out_1_b_ready_T_10)
node _portsBIO_out_1_b_ready_T_30 = or(_portsBIO_out_1_b_ready_T_29, _portsBIO_out_1_b_ready_T_11)
node _portsBIO_out_1_b_ready_T_31 = or(_portsBIO_out_1_b_ready_T_30, _portsBIO_out_1_b_ready_T_12)
node _portsBIO_out_1_b_ready_T_32 = or(_portsBIO_out_1_b_ready_T_31, _portsBIO_out_1_b_ready_T_13)
node _portsBIO_out_1_b_ready_T_33 = or(_portsBIO_out_1_b_ready_T_32, _portsBIO_out_1_b_ready_T_14)
node _portsBIO_out_1_b_ready_T_34 = or(_portsBIO_out_1_b_ready_T_33, _portsBIO_out_1_b_ready_T_15)
node _portsBIO_out_1_b_ready_T_35 = or(_portsBIO_out_1_b_ready_T_34, _portsBIO_out_1_b_ready_T_16)
node _portsBIO_out_1_b_ready_T_36 = or(_portsBIO_out_1_b_ready_T_35, _portsBIO_out_1_b_ready_T_17)
node _portsBIO_out_1_b_ready_T_37 = or(_portsBIO_out_1_b_ready_T_36, _portsBIO_out_1_b_ready_T_18)
node _portsBIO_out_1_b_ready_T_38 = or(_portsBIO_out_1_b_ready_T_37, _portsBIO_out_1_b_ready_T_19)
wire _portsBIO_out_1_b_ready_WIRE : UInt<1>
connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_38
connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, in[0].c.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1)
wire _portsCOI_in_0_c_ready_WIRE : UInt<1>
connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2
connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect portsCOI_filtered_1[1].bits, in[1].c.bits
node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2)
connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3
node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1)
wire _portsCOI_in_1_c_ready_WIRE : UInt<1>
connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2
connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE
wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_2[0].bits, in[2].c.bits
node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_0_valid_T_4)
connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5
connect portsCOI_filtered_2[1].bits, in[2].c.bits
node _portsCOI_filtered_1_valid_T_4 = or(requestCIO_2_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_1_valid_T_4)
connect portsCOI_filtered_2[1].valid, _portsCOI_filtered_1_valid_T_5
node _portsCOI_in_2_c_ready_T = mux(requestCIO_2_0, portsCOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsCOI_in_2_c_ready_T_1 = mux(requestCIO_2_1, portsCOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsCOI_in_2_c_ready_T_2 = or(_portsCOI_in_2_c_ready_T, _portsCOI_in_2_c_ready_T_1)
wire _portsCOI_in_2_c_ready_WIRE : UInt<1>
connect _portsCOI_in_2_c_ready_WIRE, _portsCOI_in_2_c_ready_T_2
connect in[2].c.ready, _portsCOI_in_2_c_ready_WIRE
wire portsCOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_3[0].bits, in[3].c.bits
node _portsCOI_filtered_0_valid_T_6 = or(requestCIO_3_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_0_valid_T_6)
connect portsCOI_filtered_3[0].valid, _portsCOI_filtered_0_valid_T_7
connect portsCOI_filtered_3[1].bits, in[3].c.bits
node _portsCOI_filtered_1_valid_T_6 = or(requestCIO_3_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_1_valid_T_6)
connect portsCOI_filtered_3[1].valid, _portsCOI_filtered_1_valid_T_7
node _portsCOI_in_3_c_ready_T = mux(requestCIO_3_0, portsCOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsCOI_in_3_c_ready_T_1 = mux(requestCIO_3_1, portsCOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsCOI_in_3_c_ready_T_2 = or(_portsCOI_in_3_c_ready_T, _portsCOI_in_3_c_ready_T_1)
wire _portsCOI_in_3_c_ready_WIRE : UInt<1>
connect _portsCOI_in_3_c_ready_WIRE, _portsCOI_in_3_c_ready_T_2
connect in[3].c.ready, _portsCOI_in_3_c_ready_WIRE
wire portsCOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_4[0].bits, in[4].c.bits
node _portsCOI_filtered_0_valid_T_8 = or(requestCIO_4_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_0_valid_T_8)
connect portsCOI_filtered_4[0].valid, _portsCOI_filtered_0_valid_T_9
connect portsCOI_filtered_4[1].bits, in[4].c.bits
node _portsCOI_filtered_1_valid_T_8 = or(requestCIO_4_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_1_valid_T_8)
connect portsCOI_filtered_4[1].valid, _portsCOI_filtered_1_valid_T_9
node _portsCOI_in_4_c_ready_T = mux(requestCIO_4_0, portsCOI_filtered_4[0].ready, UInt<1>(0h0))
node _portsCOI_in_4_c_ready_T_1 = mux(requestCIO_4_1, portsCOI_filtered_4[1].ready, UInt<1>(0h0))
node _portsCOI_in_4_c_ready_T_2 = or(_portsCOI_in_4_c_ready_T, _portsCOI_in_4_c_ready_T_1)
wire _portsCOI_in_4_c_ready_WIRE : UInt<1>
connect _portsCOI_in_4_c_ready_WIRE, _portsCOI_in_4_c_ready_T_2
connect in[4].c.ready, _portsCOI_in_4_c_ready_WIRE
wire portsCOI_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_5[0].bits, in[5].c.bits
node _portsCOI_filtered_0_valid_T_10 = or(requestCIO_5_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_11 = and(in[5].c.valid, _portsCOI_filtered_0_valid_T_10)
connect portsCOI_filtered_5[0].valid, _portsCOI_filtered_0_valid_T_11
connect portsCOI_filtered_5[1].bits, in[5].c.bits
node _portsCOI_filtered_1_valid_T_10 = or(requestCIO_5_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_11 = and(in[5].c.valid, _portsCOI_filtered_1_valid_T_10)
connect portsCOI_filtered_5[1].valid, _portsCOI_filtered_1_valid_T_11
node _portsCOI_in_5_c_ready_T = mux(requestCIO_5_0, portsCOI_filtered_5[0].ready, UInt<1>(0h0))
node _portsCOI_in_5_c_ready_T_1 = mux(requestCIO_5_1, portsCOI_filtered_5[1].ready, UInt<1>(0h0))
node _portsCOI_in_5_c_ready_T_2 = or(_portsCOI_in_5_c_ready_T, _portsCOI_in_5_c_ready_T_1)
wire _portsCOI_in_5_c_ready_WIRE : UInt<1>
connect _portsCOI_in_5_c_ready_WIRE, _portsCOI_in_5_c_ready_T_2
connect in[5].c.ready, _portsCOI_in_5_c_ready_WIRE
wire portsCOI_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_6[0].bits, in[6].c.bits
node _portsCOI_filtered_0_valid_T_12 = or(requestCIO_6_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_13 = and(in[6].c.valid, _portsCOI_filtered_0_valid_T_12)
connect portsCOI_filtered_6[0].valid, _portsCOI_filtered_0_valid_T_13
connect portsCOI_filtered_6[1].bits, in[6].c.bits
node _portsCOI_filtered_1_valid_T_12 = or(requestCIO_6_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_13 = and(in[6].c.valid, _portsCOI_filtered_1_valid_T_12)
connect portsCOI_filtered_6[1].valid, _portsCOI_filtered_1_valid_T_13
node _portsCOI_in_6_c_ready_T = mux(requestCIO_6_0, portsCOI_filtered_6[0].ready, UInt<1>(0h0))
node _portsCOI_in_6_c_ready_T_1 = mux(requestCIO_6_1, portsCOI_filtered_6[1].ready, UInt<1>(0h0))
node _portsCOI_in_6_c_ready_T_2 = or(_portsCOI_in_6_c_ready_T, _portsCOI_in_6_c_ready_T_1)
wire _portsCOI_in_6_c_ready_WIRE : UInt<1>
connect _portsCOI_in_6_c_ready_WIRE, _portsCOI_in_6_c_ready_T_2
connect in[6].c.ready, _portsCOI_in_6_c_ready_WIRE
wire portsCOI_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_7[0].bits, in[7].c.bits
node _portsCOI_filtered_0_valid_T_14 = or(requestCIO_7_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_15 = and(in[7].c.valid, _portsCOI_filtered_0_valid_T_14)
connect portsCOI_filtered_7[0].valid, _portsCOI_filtered_0_valid_T_15
connect portsCOI_filtered_7[1].bits, in[7].c.bits
node _portsCOI_filtered_1_valid_T_14 = or(requestCIO_7_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_15 = and(in[7].c.valid, _portsCOI_filtered_1_valid_T_14)
connect portsCOI_filtered_7[1].valid, _portsCOI_filtered_1_valid_T_15
node _portsCOI_in_7_c_ready_T = mux(requestCIO_7_0, portsCOI_filtered_7[0].ready, UInt<1>(0h0))
node _portsCOI_in_7_c_ready_T_1 = mux(requestCIO_7_1, portsCOI_filtered_7[1].ready, UInt<1>(0h0))
node _portsCOI_in_7_c_ready_T_2 = or(_portsCOI_in_7_c_ready_T, _portsCOI_in_7_c_ready_T_1)
wire _portsCOI_in_7_c_ready_WIRE : UInt<1>
connect _portsCOI_in_7_c_ready_WIRE, _portsCOI_in_7_c_ready_T_2
connect in[7].c.ready, _portsCOI_in_7_c_ready_WIRE
wire portsCOI_filtered_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_8[0].bits, in[8].c.bits
node _portsCOI_filtered_0_valid_T_16 = or(requestCIO_8_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_17 = and(in[8].c.valid, _portsCOI_filtered_0_valid_T_16)
connect portsCOI_filtered_8[0].valid, _portsCOI_filtered_0_valid_T_17
connect portsCOI_filtered_8[1].bits, in[8].c.bits
node _portsCOI_filtered_1_valid_T_16 = or(requestCIO_8_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_17 = and(in[8].c.valid, _portsCOI_filtered_1_valid_T_16)
connect portsCOI_filtered_8[1].valid, _portsCOI_filtered_1_valid_T_17
node _portsCOI_in_8_c_ready_T = mux(requestCIO_8_0, portsCOI_filtered_8[0].ready, UInt<1>(0h0))
node _portsCOI_in_8_c_ready_T_1 = mux(requestCIO_8_1, portsCOI_filtered_8[1].ready, UInt<1>(0h0))
node _portsCOI_in_8_c_ready_T_2 = or(_portsCOI_in_8_c_ready_T, _portsCOI_in_8_c_ready_T_1)
wire _portsCOI_in_8_c_ready_WIRE : UInt<1>
connect _portsCOI_in_8_c_ready_WIRE, _portsCOI_in_8_c_ready_T_2
connect in[8].c.ready, _portsCOI_in_8_c_ready_WIRE
wire portsCOI_filtered_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_9[0].bits, in[9].c.bits
node _portsCOI_filtered_0_valid_T_18 = or(requestCIO_9_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_19 = and(in[9].c.valid, _portsCOI_filtered_0_valid_T_18)
connect portsCOI_filtered_9[0].valid, _portsCOI_filtered_0_valid_T_19
connect portsCOI_filtered_9[1].bits, in[9].c.bits
node _portsCOI_filtered_1_valid_T_18 = or(requestCIO_9_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_19 = and(in[9].c.valid, _portsCOI_filtered_1_valid_T_18)
connect portsCOI_filtered_9[1].valid, _portsCOI_filtered_1_valid_T_19
node _portsCOI_in_9_c_ready_T = mux(requestCIO_9_0, portsCOI_filtered_9[0].ready, UInt<1>(0h0))
node _portsCOI_in_9_c_ready_T_1 = mux(requestCIO_9_1, portsCOI_filtered_9[1].ready, UInt<1>(0h0))
node _portsCOI_in_9_c_ready_T_2 = or(_portsCOI_in_9_c_ready_T, _portsCOI_in_9_c_ready_T_1)
wire _portsCOI_in_9_c_ready_WIRE : UInt<1>
connect _portsCOI_in_9_c_ready_WIRE, _portsCOI_in_9_c_ready_T_2
connect in[9].c.ready, _portsCOI_in_9_c_ready_WIRE
wire portsCOI_filtered_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_10[0].bits, in[10].c.bits
node _portsCOI_filtered_0_valid_T_20 = or(requestCIO_10_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_21 = and(in[10].c.valid, _portsCOI_filtered_0_valid_T_20)
connect portsCOI_filtered_10[0].valid, _portsCOI_filtered_0_valid_T_21
connect portsCOI_filtered_10[1].bits, in[10].c.bits
node _portsCOI_filtered_1_valid_T_20 = or(requestCIO_10_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_21 = and(in[10].c.valid, _portsCOI_filtered_1_valid_T_20)
connect portsCOI_filtered_10[1].valid, _portsCOI_filtered_1_valid_T_21
node _portsCOI_in_10_c_ready_T = mux(requestCIO_10_0, portsCOI_filtered_10[0].ready, UInt<1>(0h0))
node _portsCOI_in_10_c_ready_T_1 = mux(requestCIO_10_1, portsCOI_filtered_10[1].ready, UInt<1>(0h0))
node _portsCOI_in_10_c_ready_T_2 = or(_portsCOI_in_10_c_ready_T, _portsCOI_in_10_c_ready_T_1)
wire _portsCOI_in_10_c_ready_WIRE : UInt<1>
connect _portsCOI_in_10_c_ready_WIRE, _portsCOI_in_10_c_ready_T_2
connect in[10].c.ready, _portsCOI_in_10_c_ready_WIRE
wire portsCOI_filtered_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_11[0].bits, in[11].c.bits
node _portsCOI_filtered_0_valid_T_22 = or(requestCIO_11_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_23 = and(in[11].c.valid, _portsCOI_filtered_0_valid_T_22)
connect portsCOI_filtered_11[0].valid, _portsCOI_filtered_0_valid_T_23
connect portsCOI_filtered_11[1].bits, in[11].c.bits
node _portsCOI_filtered_1_valid_T_22 = or(requestCIO_11_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_23 = and(in[11].c.valid, _portsCOI_filtered_1_valid_T_22)
connect portsCOI_filtered_11[1].valid, _portsCOI_filtered_1_valid_T_23
node _portsCOI_in_11_c_ready_T = mux(requestCIO_11_0, portsCOI_filtered_11[0].ready, UInt<1>(0h0))
node _portsCOI_in_11_c_ready_T_1 = mux(requestCIO_11_1, portsCOI_filtered_11[1].ready, UInt<1>(0h0))
node _portsCOI_in_11_c_ready_T_2 = or(_portsCOI_in_11_c_ready_T, _portsCOI_in_11_c_ready_T_1)
wire _portsCOI_in_11_c_ready_WIRE : UInt<1>
connect _portsCOI_in_11_c_ready_WIRE, _portsCOI_in_11_c_ready_T_2
connect in[11].c.ready, _portsCOI_in_11_c_ready_WIRE
wire portsCOI_filtered_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_12[0].bits, in[12].c.bits
node _portsCOI_filtered_0_valid_T_24 = or(requestCIO_12_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_25 = and(in[12].c.valid, _portsCOI_filtered_0_valid_T_24)
connect portsCOI_filtered_12[0].valid, _portsCOI_filtered_0_valid_T_25
connect portsCOI_filtered_12[1].bits, in[12].c.bits
node _portsCOI_filtered_1_valid_T_24 = or(requestCIO_12_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_25 = and(in[12].c.valid, _portsCOI_filtered_1_valid_T_24)
connect portsCOI_filtered_12[1].valid, _portsCOI_filtered_1_valid_T_25
node _portsCOI_in_12_c_ready_T = mux(requestCIO_12_0, portsCOI_filtered_12[0].ready, UInt<1>(0h0))
node _portsCOI_in_12_c_ready_T_1 = mux(requestCIO_12_1, portsCOI_filtered_12[1].ready, UInt<1>(0h0))
node _portsCOI_in_12_c_ready_T_2 = or(_portsCOI_in_12_c_ready_T, _portsCOI_in_12_c_ready_T_1)
wire _portsCOI_in_12_c_ready_WIRE : UInt<1>
connect _portsCOI_in_12_c_ready_WIRE, _portsCOI_in_12_c_ready_T_2
connect in[12].c.ready, _portsCOI_in_12_c_ready_WIRE
wire portsCOI_filtered_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_13[0].bits, in[13].c.bits
node _portsCOI_filtered_0_valid_T_26 = or(requestCIO_13_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_27 = and(in[13].c.valid, _portsCOI_filtered_0_valid_T_26)
connect portsCOI_filtered_13[0].valid, _portsCOI_filtered_0_valid_T_27
connect portsCOI_filtered_13[1].bits, in[13].c.bits
node _portsCOI_filtered_1_valid_T_26 = or(requestCIO_13_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_27 = and(in[13].c.valid, _portsCOI_filtered_1_valid_T_26)
connect portsCOI_filtered_13[1].valid, _portsCOI_filtered_1_valid_T_27
node _portsCOI_in_13_c_ready_T = mux(requestCIO_13_0, portsCOI_filtered_13[0].ready, UInt<1>(0h0))
node _portsCOI_in_13_c_ready_T_1 = mux(requestCIO_13_1, portsCOI_filtered_13[1].ready, UInt<1>(0h0))
node _portsCOI_in_13_c_ready_T_2 = or(_portsCOI_in_13_c_ready_T, _portsCOI_in_13_c_ready_T_1)
wire _portsCOI_in_13_c_ready_WIRE : UInt<1>
connect _portsCOI_in_13_c_ready_WIRE, _portsCOI_in_13_c_ready_T_2
connect in[13].c.ready, _portsCOI_in_13_c_ready_WIRE
wire portsCOI_filtered_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_14[0].bits, in[14].c.bits
node _portsCOI_filtered_0_valid_T_28 = or(requestCIO_14_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_29 = and(in[14].c.valid, _portsCOI_filtered_0_valid_T_28)
connect portsCOI_filtered_14[0].valid, _portsCOI_filtered_0_valid_T_29
connect portsCOI_filtered_14[1].bits, in[14].c.bits
node _portsCOI_filtered_1_valid_T_28 = or(requestCIO_14_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_29 = and(in[14].c.valid, _portsCOI_filtered_1_valid_T_28)
connect portsCOI_filtered_14[1].valid, _portsCOI_filtered_1_valid_T_29
node _portsCOI_in_14_c_ready_T = mux(requestCIO_14_0, portsCOI_filtered_14[0].ready, UInt<1>(0h0))
node _portsCOI_in_14_c_ready_T_1 = mux(requestCIO_14_1, portsCOI_filtered_14[1].ready, UInt<1>(0h0))
node _portsCOI_in_14_c_ready_T_2 = or(_portsCOI_in_14_c_ready_T, _portsCOI_in_14_c_ready_T_1)
wire _portsCOI_in_14_c_ready_WIRE : UInt<1>
connect _portsCOI_in_14_c_ready_WIRE, _portsCOI_in_14_c_ready_T_2
connect in[14].c.ready, _portsCOI_in_14_c_ready_WIRE
wire portsCOI_filtered_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_15[0].bits, in[15].c.bits
node _portsCOI_filtered_0_valid_T_30 = or(requestCIO_15_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_31 = and(in[15].c.valid, _portsCOI_filtered_0_valid_T_30)
connect portsCOI_filtered_15[0].valid, _portsCOI_filtered_0_valid_T_31
connect portsCOI_filtered_15[1].bits, in[15].c.bits
node _portsCOI_filtered_1_valid_T_30 = or(requestCIO_15_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_31 = and(in[15].c.valid, _portsCOI_filtered_1_valid_T_30)
connect portsCOI_filtered_15[1].valid, _portsCOI_filtered_1_valid_T_31
node _portsCOI_in_15_c_ready_T = mux(requestCIO_15_0, portsCOI_filtered_15[0].ready, UInt<1>(0h0))
node _portsCOI_in_15_c_ready_T_1 = mux(requestCIO_15_1, portsCOI_filtered_15[1].ready, UInt<1>(0h0))
node _portsCOI_in_15_c_ready_T_2 = or(_portsCOI_in_15_c_ready_T, _portsCOI_in_15_c_ready_T_1)
wire _portsCOI_in_15_c_ready_WIRE : UInt<1>
connect _portsCOI_in_15_c_ready_WIRE, _portsCOI_in_15_c_ready_T_2
connect in[15].c.ready, _portsCOI_in_15_c_ready_WIRE
wire portsCOI_filtered_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_16[0].bits, in[16].c.bits
node _portsCOI_filtered_0_valid_T_32 = or(requestCIO_16_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_33 = and(in[16].c.valid, _portsCOI_filtered_0_valid_T_32)
connect portsCOI_filtered_16[0].valid, _portsCOI_filtered_0_valid_T_33
connect portsCOI_filtered_16[1].bits, in[16].c.bits
node _portsCOI_filtered_1_valid_T_32 = or(requestCIO_16_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_33 = and(in[16].c.valid, _portsCOI_filtered_1_valid_T_32)
connect portsCOI_filtered_16[1].valid, _portsCOI_filtered_1_valid_T_33
node _portsCOI_in_16_c_ready_T = mux(requestCIO_16_0, portsCOI_filtered_16[0].ready, UInt<1>(0h0))
node _portsCOI_in_16_c_ready_T_1 = mux(requestCIO_16_1, portsCOI_filtered_16[1].ready, UInt<1>(0h0))
node _portsCOI_in_16_c_ready_T_2 = or(_portsCOI_in_16_c_ready_T, _portsCOI_in_16_c_ready_T_1)
wire _portsCOI_in_16_c_ready_WIRE : UInt<1>
connect _portsCOI_in_16_c_ready_WIRE, _portsCOI_in_16_c_ready_T_2
connect in[16].c.ready, _portsCOI_in_16_c_ready_WIRE
wire portsCOI_filtered_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_17[0].bits, in[17].c.bits
node _portsCOI_filtered_0_valid_T_34 = or(requestCIO_17_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_35 = and(in[17].c.valid, _portsCOI_filtered_0_valid_T_34)
connect portsCOI_filtered_17[0].valid, _portsCOI_filtered_0_valid_T_35
connect portsCOI_filtered_17[1].bits, in[17].c.bits
node _portsCOI_filtered_1_valid_T_34 = or(requestCIO_17_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_35 = and(in[17].c.valid, _portsCOI_filtered_1_valid_T_34)
connect portsCOI_filtered_17[1].valid, _portsCOI_filtered_1_valid_T_35
node _portsCOI_in_17_c_ready_T = mux(requestCIO_17_0, portsCOI_filtered_17[0].ready, UInt<1>(0h0))
node _portsCOI_in_17_c_ready_T_1 = mux(requestCIO_17_1, portsCOI_filtered_17[1].ready, UInt<1>(0h0))
node _portsCOI_in_17_c_ready_T_2 = or(_portsCOI_in_17_c_ready_T, _portsCOI_in_17_c_ready_T_1)
wire _portsCOI_in_17_c_ready_WIRE : UInt<1>
connect _portsCOI_in_17_c_ready_WIRE, _portsCOI_in_17_c_ready_T_2
connect in[17].c.ready, _portsCOI_in_17_c_ready_WIRE
wire portsCOI_filtered_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_18[0].bits, in[18].c.bits
node _portsCOI_filtered_0_valid_T_36 = or(requestCIO_18_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_37 = and(in[18].c.valid, _portsCOI_filtered_0_valid_T_36)
connect portsCOI_filtered_18[0].valid, _portsCOI_filtered_0_valid_T_37
connect portsCOI_filtered_18[1].bits, in[18].c.bits
node _portsCOI_filtered_1_valid_T_36 = or(requestCIO_18_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_37 = and(in[18].c.valid, _portsCOI_filtered_1_valid_T_36)
connect portsCOI_filtered_18[1].valid, _portsCOI_filtered_1_valid_T_37
node _portsCOI_in_18_c_ready_T = mux(requestCIO_18_0, portsCOI_filtered_18[0].ready, UInt<1>(0h0))
node _portsCOI_in_18_c_ready_T_1 = mux(requestCIO_18_1, portsCOI_filtered_18[1].ready, UInt<1>(0h0))
node _portsCOI_in_18_c_ready_T_2 = or(_portsCOI_in_18_c_ready_T, _portsCOI_in_18_c_ready_T_1)
wire _portsCOI_in_18_c_ready_WIRE : UInt<1>
connect _portsCOI_in_18_c_ready_WIRE, _portsCOI_in_18_c_ready_T_2
connect in[18].c.ready, _portsCOI_in_18_c_ready_WIRE
wire portsCOI_filtered_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_19[0].bits, in[19].c.bits
node _portsCOI_filtered_0_valid_T_38 = or(requestCIO_19_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_39 = and(in[19].c.valid, _portsCOI_filtered_0_valid_T_38)
connect portsCOI_filtered_19[0].valid, _portsCOI_filtered_0_valid_T_39
connect portsCOI_filtered_19[1].bits, in[19].c.bits
node _portsCOI_filtered_1_valid_T_38 = or(requestCIO_19_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_39 = and(in[19].c.valid, _portsCOI_filtered_1_valid_T_38)
connect portsCOI_filtered_19[1].valid, _portsCOI_filtered_1_valid_T_39
node _portsCOI_in_19_c_ready_T = mux(requestCIO_19_0, portsCOI_filtered_19[0].ready, UInt<1>(0h0))
node _portsCOI_in_19_c_ready_T_1 = mux(requestCIO_19_1, portsCOI_filtered_19[1].ready, UInt<1>(0h0))
node _portsCOI_in_19_c_ready_T_2 = or(_portsCOI_in_19_c_ready_T, _portsCOI_in_19_c_ready_T_1)
wire _portsCOI_in_19_c_ready_WIRE : UInt<1>
connect _portsCOI_in_19_c_ready_WIRE, _portsCOI_in_19_c_ready_T_2
connect in[19].c.ready, _portsCOI_in_19_c_ready_WIRE
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[20]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[2].bits.data, out[0].d.bits.data
connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[2].bits.source, out[0].d.bits.source
connect portsDIO_filtered[2].bits.size, out[0].d.bits.size
connect portsDIO_filtered[2].bits.param, out[0].d.bits.param
connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T)
connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1
connect portsDIO_filtered[3].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[3].bits.data, out[0].d.bits.data
connect portsDIO_filtered[3].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[3].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[3].bits.source, out[0].d.bits.source
connect portsDIO_filtered[3].bits.size, out[0].d.bits.size
connect portsDIO_filtered[3].bits.param, out[0].d.bits.param
connect portsDIO_filtered[3].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_3_valid_T = or(requestDOI_0_3, UInt<1>(0h0))
node _portsDIO_filtered_3_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_3_valid_T)
connect portsDIO_filtered[3].valid, _portsDIO_filtered_3_valid_T_1
connect portsDIO_filtered[4].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[4].bits.data, out[0].d.bits.data
connect portsDIO_filtered[4].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[4].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[4].bits.source, out[0].d.bits.source
connect portsDIO_filtered[4].bits.size, out[0].d.bits.size
connect portsDIO_filtered[4].bits.param, out[0].d.bits.param
connect portsDIO_filtered[4].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_4_valid_T = or(requestDOI_0_4, UInt<1>(0h0))
node _portsDIO_filtered_4_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_4_valid_T)
connect portsDIO_filtered[4].valid, _portsDIO_filtered_4_valid_T_1
connect portsDIO_filtered[5].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[5].bits.data, out[0].d.bits.data
connect portsDIO_filtered[5].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[5].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[5].bits.source, out[0].d.bits.source
connect portsDIO_filtered[5].bits.size, out[0].d.bits.size
connect portsDIO_filtered[5].bits.param, out[0].d.bits.param
connect portsDIO_filtered[5].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_5_valid_T = or(requestDOI_0_5, UInt<1>(0h0))
node _portsDIO_filtered_5_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_5_valid_T)
connect portsDIO_filtered[5].valid, _portsDIO_filtered_5_valid_T_1
connect portsDIO_filtered[6].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[6].bits.data, out[0].d.bits.data
connect portsDIO_filtered[6].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[6].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[6].bits.source, out[0].d.bits.source
connect portsDIO_filtered[6].bits.size, out[0].d.bits.size
connect portsDIO_filtered[6].bits.param, out[0].d.bits.param
connect portsDIO_filtered[6].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_6_valid_T = or(requestDOI_0_6, UInt<1>(0h0))
node _portsDIO_filtered_6_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_6_valid_T)
connect portsDIO_filtered[6].valid, _portsDIO_filtered_6_valid_T_1
connect portsDIO_filtered[7].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[7].bits.data, out[0].d.bits.data
connect portsDIO_filtered[7].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[7].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[7].bits.source, out[0].d.bits.source
connect portsDIO_filtered[7].bits.size, out[0].d.bits.size
connect portsDIO_filtered[7].bits.param, out[0].d.bits.param
connect portsDIO_filtered[7].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_7_valid_T = or(requestDOI_0_7, UInt<1>(0h0))
node _portsDIO_filtered_7_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_7_valid_T)
connect portsDIO_filtered[7].valid, _portsDIO_filtered_7_valid_T_1
connect portsDIO_filtered[8].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[8].bits.data, out[0].d.bits.data
connect portsDIO_filtered[8].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[8].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[8].bits.source, out[0].d.bits.source
connect portsDIO_filtered[8].bits.size, out[0].d.bits.size
connect portsDIO_filtered[8].bits.param, out[0].d.bits.param
connect portsDIO_filtered[8].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_8_valid_T = or(requestDOI_0_8, UInt<1>(0h0))
node _portsDIO_filtered_8_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_8_valid_T)
connect portsDIO_filtered[8].valid, _portsDIO_filtered_8_valid_T_1
connect portsDIO_filtered[9].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[9].bits.data, out[0].d.bits.data
connect portsDIO_filtered[9].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[9].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[9].bits.source, out[0].d.bits.source
connect portsDIO_filtered[9].bits.size, out[0].d.bits.size
connect portsDIO_filtered[9].bits.param, out[0].d.bits.param
connect portsDIO_filtered[9].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_9_valid_T = or(requestDOI_0_9, UInt<1>(0h0))
node _portsDIO_filtered_9_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_9_valid_T)
connect portsDIO_filtered[9].valid, _portsDIO_filtered_9_valid_T_1
connect portsDIO_filtered[10].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[10].bits.data, out[0].d.bits.data
connect portsDIO_filtered[10].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[10].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[10].bits.source, out[0].d.bits.source
connect portsDIO_filtered[10].bits.size, out[0].d.bits.size
connect portsDIO_filtered[10].bits.param, out[0].d.bits.param
connect portsDIO_filtered[10].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_10_valid_T = or(requestDOI_0_10, UInt<1>(0h0))
node _portsDIO_filtered_10_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_10_valid_T)
connect portsDIO_filtered[10].valid, _portsDIO_filtered_10_valid_T_1
connect portsDIO_filtered[11].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[11].bits.data, out[0].d.bits.data
connect portsDIO_filtered[11].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[11].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[11].bits.source, out[0].d.bits.source
connect portsDIO_filtered[11].bits.size, out[0].d.bits.size
connect portsDIO_filtered[11].bits.param, out[0].d.bits.param
connect portsDIO_filtered[11].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_11_valid_T = or(requestDOI_0_11, UInt<1>(0h0))
node _portsDIO_filtered_11_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_11_valid_T)
connect portsDIO_filtered[11].valid, _portsDIO_filtered_11_valid_T_1
connect portsDIO_filtered[12].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[12].bits.data, out[0].d.bits.data
connect portsDIO_filtered[12].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[12].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[12].bits.source, out[0].d.bits.source
connect portsDIO_filtered[12].bits.size, out[0].d.bits.size
connect portsDIO_filtered[12].bits.param, out[0].d.bits.param
connect portsDIO_filtered[12].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_12_valid_T = or(requestDOI_0_12, UInt<1>(0h0))
node _portsDIO_filtered_12_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_12_valid_T)
connect portsDIO_filtered[12].valid, _portsDIO_filtered_12_valid_T_1
connect portsDIO_filtered[13].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[13].bits.data, out[0].d.bits.data
connect portsDIO_filtered[13].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[13].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[13].bits.source, out[0].d.bits.source
connect portsDIO_filtered[13].bits.size, out[0].d.bits.size
connect portsDIO_filtered[13].bits.param, out[0].d.bits.param
connect portsDIO_filtered[13].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_13_valid_T = or(requestDOI_0_13, UInt<1>(0h0))
node _portsDIO_filtered_13_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_13_valid_T)
connect portsDIO_filtered[13].valid, _portsDIO_filtered_13_valid_T_1
connect portsDIO_filtered[14].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[14].bits.data, out[0].d.bits.data
connect portsDIO_filtered[14].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[14].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[14].bits.source, out[0].d.bits.source
connect portsDIO_filtered[14].bits.size, out[0].d.bits.size
connect portsDIO_filtered[14].bits.param, out[0].d.bits.param
connect portsDIO_filtered[14].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_14_valid_T = or(requestDOI_0_14, UInt<1>(0h0))
node _portsDIO_filtered_14_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_14_valid_T)
connect portsDIO_filtered[14].valid, _portsDIO_filtered_14_valid_T_1
connect portsDIO_filtered[15].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[15].bits.data, out[0].d.bits.data
connect portsDIO_filtered[15].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[15].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[15].bits.source, out[0].d.bits.source
connect portsDIO_filtered[15].bits.size, out[0].d.bits.size
connect portsDIO_filtered[15].bits.param, out[0].d.bits.param
connect portsDIO_filtered[15].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_15_valid_T = or(requestDOI_0_15, UInt<1>(0h0))
node _portsDIO_filtered_15_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_15_valid_T)
connect portsDIO_filtered[15].valid, _portsDIO_filtered_15_valid_T_1
connect portsDIO_filtered[16].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[16].bits.data, out[0].d.bits.data
connect portsDIO_filtered[16].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[16].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[16].bits.source, out[0].d.bits.source
connect portsDIO_filtered[16].bits.size, out[0].d.bits.size
connect portsDIO_filtered[16].bits.param, out[0].d.bits.param
connect portsDIO_filtered[16].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_16_valid_T = or(requestDOI_0_16, UInt<1>(0h0))
node _portsDIO_filtered_16_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_16_valid_T)
connect portsDIO_filtered[16].valid, _portsDIO_filtered_16_valid_T_1
connect portsDIO_filtered[17].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[17].bits.data, out[0].d.bits.data
connect portsDIO_filtered[17].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[17].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[17].bits.source, out[0].d.bits.source
connect portsDIO_filtered[17].bits.size, out[0].d.bits.size
connect portsDIO_filtered[17].bits.param, out[0].d.bits.param
connect portsDIO_filtered[17].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_17_valid_T = or(requestDOI_0_17, UInt<1>(0h0))
node _portsDIO_filtered_17_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_17_valid_T)
connect portsDIO_filtered[17].valid, _portsDIO_filtered_17_valid_T_1
connect portsDIO_filtered[18].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[18].bits.data, out[0].d.bits.data
connect portsDIO_filtered[18].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[18].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[18].bits.source, out[0].d.bits.source
connect portsDIO_filtered[18].bits.size, out[0].d.bits.size
connect portsDIO_filtered[18].bits.param, out[0].d.bits.param
connect portsDIO_filtered[18].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_18_valid_T = or(requestDOI_0_18, UInt<1>(0h0))
node _portsDIO_filtered_18_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_18_valid_T)
connect portsDIO_filtered[18].valid, _portsDIO_filtered_18_valid_T_1
connect portsDIO_filtered[19].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[19].bits.data, out[0].d.bits.data
connect portsDIO_filtered[19].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[19].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[19].bits.source, out[0].d.bits.source
connect portsDIO_filtered[19].bits.size, out[0].d.bits.size
connect portsDIO_filtered[19].bits.param, out[0].d.bits.param
connect portsDIO_filtered[19].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_19_valid_T = or(requestDOI_0_19, UInt<1>(0h0))
node _portsDIO_filtered_19_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_19_valid_T)
connect portsDIO_filtered[19].valid, _portsDIO_filtered_19_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_3 = mux(requestDOI_0_3, portsDIO_filtered[3].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_4 = mux(requestDOI_0_4, portsDIO_filtered[4].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_5 = mux(requestDOI_0_5, portsDIO_filtered[5].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_6 = mux(requestDOI_0_6, portsDIO_filtered[6].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_7 = mux(requestDOI_0_7, portsDIO_filtered[7].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_8 = mux(requestDOI_0_8, portsDIO_filtered[8].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_9 = mux(requestDOI_0_9, portsDIO_filtered[9].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_10 = mux(requestDOI_0_10, portsDIO_filtered[10].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_11 = mux(requestDOI_0_11, portsDIO_filtered[11].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_12 = mux(requestDOI_0_12, portsDIO_filtered[12].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_13 = mux(requestDOI_0_13, portsDIO_filtered[13].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_14 = mux(requestDOI_0_14, portsDIO_filtered[14].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_15 = mux(requestDOI_0_15, portsDIO_filtered[15].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_16 = mux(requestDOI_0_16, portsDIO_filtered[16].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_17 = mux(requestDOI_0_17, portsDIO_filtered[17].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_18 = mux(requestDOI_0_18, portsDIO_filtered[18].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_19 = mux(requestDOI_0_19, portsDIO_filtered[19].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_20 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
node _portsDIO_out_0_d_ready_T_21 = or(_portsDIO_out_0_d_ready_T_20, _portsDIO_out_0_d_ready_T_2)
node _portsDIO_out_0_d_ready_T_22 = or(_portsDIO_out_0_d_ready_T_21, _portsDIO_out_0_d_ready_T_3)
node _portsDIO_out_0_d_ready_T_23 = or(_portsDIO_out_0_d_ready_T_22, _portsDIO_out_0_d_ready_T_4)
node _portsDIO_out_0_d_ready_T_24 = or(_portsDIO_out_0_d_ready_T_23, _portsDIO_out_0_d_ready_T_5)
node _portsDIO_out_0_d_ready_T_25 = or(_portsDIO_out_0_d_ready_T_24, _portsDIO_out_0_d_ready_T_6)
node _portsDIO_out_0_d_ready_T_26 = or(_portsDIO_out_0_d_ready_T_25, _portsDIO_out_0_d_ready_T_7)
node _portsDIO_out_0_d_ready_T_27 = or(_portsDIO_out_0_d_ready_T_26, _portsDIO_out_0_d_ready_T_8)
node _portsDIO_out_0_d_ready_T_28 = or(_portsDIO_out_0_d_ready_T_27, _portsDIO_out_0_d_ready_T_9)
node _portsDIO_out_0_d_ready_T_29 = or(_portsDIO_out_0_d_ready_T_28, _portsDIO_out_0_d_ready_T_10)
node _portsDIO_out_0_d_ready_T_30 = or(_portsDIO_out_0_d_ready_T_29, _portsDIO_out_0_d_ready_T_11)
node _portsDIO_out_0_d_ready_T_31 = or(_portsDIO_out_0_d_ready_T_30, _portsDIO_out_0_d_ready_T_12)
node _portsDIO_out_0_d_ready_T_32 = or(_portsDIO_out_0_d_ready_T_31, _portsDIO_out_0_d_ready_T_13)
node _portsDIO_out_0_d_ready_T_33 = or(_portsDIO_out_0_d_ready_T_32, _portsDIO_out_0_d_ready_T_14)
node _portsDIO_out_0_d_ready_T_34 = or(_portsDIO_out_0_d_ready_T_33, _portsDIO_out_0_d_ready_T_15)
node _portsDIO_out_0_d_ready_T_35 = or(_portsDIO_out_0_d_ready_T_34, _portsDIO_out_0_d_ready_T_16)
node _portsDIO_out_0_d_ready_T_36 = or(_portsDIO_out_0_d_ready_T_35, _portsDIO_out_0_d_ready_T_17)
node _portsDIO_out_0_d_ready_T_37 = or(_portsDIO_out_0_d_ready_T_36, _portsDIO_out_0_d_ready_T_18)
node _portsDIO_out_0_d_ready_T_38 = or(_portsDIO_out_0_d_ready_T_37, _portsDIO_out_0_d_ready_T_19)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_38
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[20]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2)
connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3
connect portsDIO_filtered_1[2].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[2].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[2].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[2].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[2].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[2].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[2].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[2].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_2_valid_T_2 = or(requestDOI_1_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_2_valid_T_2)
connect portsDIO_filtered_1[2].valid, _portsDIO_filtered_2_valid_T_3
connect portsDIO_filtered_1[3].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[3].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[3].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[3].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[3].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[3].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[3].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[3].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_3_valid_T_2 = or(requestDOI_1_3, UInt<1>(0h0))
node _portsDIO_filtered_3_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_3_valid_T_2)
connect portsDIO_filtered_1[3].valid, _portsDIO_filtered_3_valid_T_3
connect portsDIO_filtered_1[4].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[4].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[4].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[4].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[4].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[4].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[4].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[4].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_4_valid_T_2 = or(requestDOI_1_4, UInt<1>(0h0))
node _portsDIO_filtered_4_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_4_valid_T_2)
connect portsDIO_filtered_1[4].valid, _portsDIO_filtered_4_valid_T_3
connect portsDIO_filtered_1[5].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[5].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[5].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[5].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[5].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[5].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[5].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[5].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_5_valid_T_2 = or(requestDOI_1_5, UInt<1>(0h0))
node _portsDIO_filtered_5_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_5_valid_T_2)
connect portsDIO_filtered_1[5].valid, _portsDIO_filtered_5_valid_T_3
connect portsDIO_filtered_1[6].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[6].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[6].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[6].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[6].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[6].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[6].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[6].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_6_valid_T_2 = or(requestDOI_1_6, UInt<1>(0h0))
node _portsDIO_filtered_6_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_6_valid_T_2)
connect portsDIO_filtered_1[6].valid, _portsDIO_filtered_6_valid_T_3
connect portsDIO_filtered_1[7].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[7].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[7].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[7].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[7].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[7].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[7].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[7].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_7_valid_T_2 = or(requestDOI_1_7, UInt<1>(0h0))
node _portsDIO_filtered_7_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_7_valid_T_2)
connect portsDIO_filtered_1[7].valid, _portsDIO_filtered_7_valid_T_3
connect portsDIO_filtered_1[8].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[8].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[8].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[8].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[8].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[8].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[8].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[8].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_8_valid_T_2 = or(requestDOI_1_8, UInt<1>(0h0))
node _portsDIO_filtered_8_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_8_valid_T_2)
connect portsDIO_filtered_1[8].valid, _portsDIO_filtered_8_valid_T_3
connect portsDIO_filtered_1[9].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[9].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[9].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[9].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[9].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[9].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[9].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[9].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_9_valid_T_2 = or(requestDOI_1_9, UInt<1>(0h0))
node _portsDIO_filtered_9_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_9_valid_T_2)
connect portsDIO_filtered_1[9].valid, _portsDIO_filtered_9_valid_T_3
connect portsDIO_filtered_1[10].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[10].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[10].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[10].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[10].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[10].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[10].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[10].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_10_valid_T_2 = or(requestDOI_1_10, UInt<1>(0h0))
node _portsDIO_filtered_10_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_10_valid_T_2)
connect portsDIO_filtered_1[10].valid, _portsDIO_filtered_10_valid_T_3
connect portsDIO_filtered_1[11].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[11].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[11].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[11].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[11].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[11].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[11].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[11].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_11_valid_T_2 = or(requestDOI_1_11, UInt<1>(0h0))
node _portsDIO_filtered_11_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_11_valid_T_2)
connect portsDIO_filtered_1[11].valid, _portsDIO_filtered_11_valid_T_3
connect portsDIO_filtered_1[12].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[12].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[12].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[12].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[12].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[12].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[12].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[12].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_12_valid_T_2 = or(requestDOI_1_12, UInt<1>(0h0))
node _portsDIO_filtered_12_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_12_valid_T_2)
connect portsDIO_filtered_1[12].valid, _portsDIO_filtered_12_valid_T_3
connect portsDIO_filtered_1[13].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[13].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[13].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[13].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[13].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[13].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[13].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[13].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_13_valid_T_2 = or(requestDOI_1_13, UInt<1>(0h0))
node _portsDIO_filtered_13_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_13_valid_T_2)
connect portsDIO_filtered_1[13].valid, _portsDIO_filtered_13_valid_T_3
connect portsDIO_filtered_1[14].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[14].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[14].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[14].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[14].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[14].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[14].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[14].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_14_valid_T_2 = or(requestDOI_1_14, UInt<1>(0h0))
node _portsDIO_filtered_14_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_14_valid_T_2)
connect portsDIO_filtered_1[14].valid, _portsDIO_filtered_14_valid_T_3
connect portsDIO_filtered_1[15].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[15].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[15].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[15].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[15].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[15].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[15].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[15].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_15_valid_T_2 = or(requestDOI_1_15, UInt<1>(0h0))
node _portsDIO_filtered_15_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_15_valid_T_2)
connect portsDIO_filtered_1[15].valid, _portsDIO_filtered_15_valid_T_3
connect portsDIO_filtered_1[16].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[16].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[16].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[16].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[16].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[16].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[16].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[16].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_16_valid_T_2 = or(requestDOI_1_16, UInt<1>(0h0))
node _portsDIO_filtered_16_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_16_valid_T_2)
connect portsDIO_filtered_1[16].valid, _portsDIO_filtered_16_valid_T_3
connect portsDIO_filtered_1[17].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[17].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[17].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[17].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[17].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[17].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[17].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[17].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_17_valid_T_2 = or(requestDOI_1_17, UInt<1>(0h0))
node _portsDIO_filtered_17_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_17_valid_T_2)
connect portsDIO_filtered_1[17].valid, _portsDIO_filtered_17_valid_T_3
connect portsDIO_filtered_1[18].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[18].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[18].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[18].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[18].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[18].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[18].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[18].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_18_valid_T_2 = or(requestDOI_1_18, UInt<1>(0h0))
node _portsDIO_filtered_18_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_18_valid_T_2)
connect portsDIO_filtered_1[18].valid, _portsDIO_filtered_18_valid_T_3
connect portsDIO_filtered_1[19].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[19].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[19].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[19].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[19].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[19].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[19].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[19].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_19_valid_T_2 = or(requestDOI_1_19, UInt<1>(0h0))
node _portsDIO_filtered_19_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_19_valid_T_2)
connect portsDIO_filtered_1[19].valid, _portsDIO_filtered_19_valid_T_3
node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_2 = mux(requestDOI_1_2, portsDIO_filtered_1[2].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_3 = mux(requestDOI_1_3, portsDIO_filtered_1[3].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_4 = mux(requestDOI_1_4, portsDIO_filtered_1[4].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_5 = mux(requestDOI_1_5, portsDIO_filtered_1[5].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_6 = mux(requestDOI_1_6, portsDIO_filtered_1[6].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_7 = mux(requestDOI_1_7, portsDIO_filtered_1[7].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_8 = mux(requestDOI_1_8, portsDIO_filtered_1[8].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_9 = mux(requestDOI_1_9, portsDIO_filtered_1[9].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_10 = mux(requestDOI_1_10, portsDIO_filtered_1[10].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_11 = mux(requestDOI_1_11, portsDIO_filtered_1[11].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_12 = mux(requestDOI_1_12, portsDIO_filtered_1[12].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_13 = mux(requestDOI_1_13, portsDIO_filtered_1[13].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_14 = mux(requestDOI_1_14, portsDIO_filtered_1[14].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_15 = mux(requestDOI_1_15, portsDIO_filtered_1[15].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_16 = mux(requestDOI_1_16, portsDIO_filtered_1[16].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_17 = mux(requestDOI_1_17, portsDIO_filtered_1[17].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_18 = mux(requestDOI_1_18, portsDIO_filtered_1[18].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_19 = mux(requestDOI_1_19, portsDIO_filtered_1[19].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_20 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1)
node _portsDIO_out_1_d_ready_T_21 = or(_portsDIO_out_1_d_ready_T_20, _portsDIO_out_1_d_ready_T_2)
node _portsDIO_out_1_d_ready_T_22 = or(_portsDIO_out_1_d_ready_T_21, _portsDIO_out_1_d_ready_T_3)
node _portsDIO_out_1_d_ready_T_23 = or(_portsDIO_out_1_d_ready_T_22, _portsDIO_out_1_d_ready_T_4)
node _portsDIO_out_1_d_ready_T_24 = or(_portsDIO_out_1_d_ready_T_23, _portsDIO_out_1_d_ready_T_5)
node _portsDIO_out_1_d_ready_T_25 = or(_portsDIO_out_1_d_ready_T_24, _portsDIO_out_1_d_ready_T_6)
node _portsDIO_out_1_d_ready_T_26 = or(_portsDIO_out_1_d_ready_T_25, _portsDIO_out_1_d_ready_T_7)
node _portsDIO_out_1_d_ready_T_27 = or(_portsDIO_out_1_d_ready_T_26, _portsDIO_out_1_d_ready_T_8)
node _portsDIO_out_1_d_ready_T_28 = or(_portsDIO_out_1_d_ready_T_27, _portsDIO_out_1_d_ready_T_9)
node _portsDIO_out_1_d_ready_T_29 = or(_portsDIO_out_1_d_ready_T_28, _portsDIO_out_1_d_ready_T_10)
node _portsDIO_out_1_d_ready_T_30 = or(_portsDIO_out_1_d_ready_T_29, _portsDIO_out_1_d_ready_T_11)
node _portsDIO_out_1_d_ready_T_31 = or(_portsDIO_out_1_d_ready_T_30, _portsDIO_out_1_d_ready_T_12)
node _portsDIO_out_1_d_ready_T_32 = or(_portsDIO_out_1_d_ready_T_31, _portsDIO_out_1_d_ready_T_13)
node _portsDIO_out_1_d_ready_T_33 = or(_portsDIO_out_1_d_ready_T_32, _portsDIO_out_1_d_ready_T_14)
node _portsDIO_out_1_d_ready_T_34 = or(_portsDIO_out_1_d_ready_T_33, _portsDIO_out_1_d_ready_T_15)
node _portsDIO_out_1_d_ready_T_35 = or(_portsDIO_out_1_d_ready_T_34, _portsDIO_out_1_d_ready_T_16)
node _portsDIO_out_1_d_ready_T_36 = or(_portsDIO_out_1_d_ready_T_35, _portsDIO_out_1_d_ready_T_17)
node _portsDIO_out_1_d_ready_T_37 = or(_portsDIO_out_1_d_ready_T_36, _portsDIO_out_1_d_ready_T_18)
node _portsDIO_out_1_d_ready_T_38 = or(_portsDIO_out_1_d_ready_T_37, _portsDIO_out_1_d_ready_T_19)
wire _portsDIO_out_1_d_ready_WIRE : UInt<1>
connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_38
connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, in[0].e.bits
node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1)
wire _portsEOI_in_0_e_ready_WIRE : UInt<1>
connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2
connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect portsEOI_filtered_1[1].bits, in[1].e.bits
node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2)
connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3
node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1)
wire _portsEOI_in_1_e_ready_WIRE : UInt<1>
connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2
connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE
wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_2[0].bits, in[2].e.bits
node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_0_valid_T_4)
connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5
connect portsEOI_filtered_2[1].bits, in[2].e.bits
node _portsEOI_filtered_1_valid_T_4 = or(requestEIO_2_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_1_valid_T_4)
connect portsEOI_filtered_2[1].valid, _portsEOI_filtered_1_valid_T_5
node _portsEOI_in_2_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsEOI_in_2_e_ready_T_1 = mux(requestEIO_2_1, portsEOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsEOI_in_2_e_ready_T_2 = or(_portsEOI_in_2_e_ready_T, _portsEOI_in_2_e_ready_T_1)
wire _portsEOI_in_2_e_ready_WIRE : UInt<1>
connect _portsEOI_in_2_e_ready_WIRE, _portsEOI_in_2_e_ready_T_2
connect in[2].e.ready, _portsEOI_in_2_e_ready_WIRE
wire portsEOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_3[0].bits, in[3].e.bits
node _portsEOI_filtered_0_valid_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_0_valid_T_6)
connect portsEOI_filtered_3[0].valid, _portsEOI_filtered_0_valid_T_7
connect portsEOI_filtered_3[1].bits, in[3].e.bits
node _portsEOI_filtered_1_valid_T_6 = or(requestEIO_3_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_1_valid_T_6)
connect portsEOI_filtered_3[1].valid, _portsEOI_filtered_1_valid_T_7
node _portsEOI_in_3_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsEOI_in_3_e_ready_T_1 = mux(requestEIO_3_1, portsEOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsEOI_in_3_e_ready_T_2 = or(_portsEOI_in_3_e_ready_T, _portsEOI_in_3_e_ready_T_1)
wire _portsEOI_in_3_e_ready_WIRE : UInt<1>
connect _portsEOI_in_3_e_ready_WIRE, _portsEOI_in_3_e_ready_T_2
connect in[3].e.ready, _portsEOI_in_3_e_ready_WIRE
wire portsEOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_4[0].bits, in[4].e.bits
node _portsEOI_filtered_0_valid_T_8 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_0_valid_T_8)
connect portsEOI_filtered_4[0].valid, _portsEOI_filtered_0_valid_T_9
connect portsEOI_filtered_4[1].bits, in[4].e.bits
node _portsEOI_filtered_1_valid_T_8 = or(requestEIO_4_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_1_valid_T_8)
connect portsEOI_filtered_4[1].valid, _portsEOI_filtered_1_valid_T_9
node _portsEOI_in_4_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_4[0].ready, UInt<1>(0h0))
node _portsEOI_in_4_e_ready_T_1 = mux(requestEIO_4_1, portsEOI_filtered_4[1].ready, UInt<1>(0h0))
node _portsEOI_in_4_e_ready_T_2 = or(_portsEOI_in_4_e_ready_T, _portsEOI_in_4_e_ready_T_1)
wire _portsEOI_in_4_e_ready_WIRE : UInt<1>
connect _portsEOI_in_4_e_ready_WIRE, _portsEOI_in_4_e_ready_T_2
connect in[4].e.ready, _portsEOI_in_4_e_ready_WIRE
wire portsEOI_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_5[0].bits, in[5].e.bits
node _portsEOI_filtered_0_valid_T_10 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_11 = and(in[5].e.valid, _portsEOI_filtered_0_valid_T_10)
connect portsEOI_filtered_5[0].valid, _portsEOI_filtered_0_valid_T_11
connect portsEOI_filtered_5[1].bits, in[5].e.bits
node _portsEOI_filtered_1_valid_T_10 = or(requestEIO_5_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_11 = and(in[5].e.valid, _portsEOI_filtered_1_valid_T_10)
connect portsEOI_filtered_5[1].valid, _portsEOI_filtered_1_valid_T_11
node _portsEOI_in_5_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_5[0].ready, UInt<1>(0h0))
node _portsEOI_in_5_e_ready_T_1 = mux(requestEIO_5_1, portsEOI_filtered_5[1].ready, UInt<1>(0h0))
node _portsEOI_in_5_e_ready_T_2 = or(_portsEOI_in_5_e_ready_T, _portsEOI_in_5_e_ready_T_1)
wire _portsEOI_in_5_e_ready_WIRE : UInt<1>
connect _portsEOI_in_5_e_ready_WIRE, _portsEOI_in_5_e_ready_T_2
connect in[5].e.ready, _portsEOI_in_5_e_ready_WIRE
wire portsEOI_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_6[0].bits, in[6].e.bits
node _portsEOI_filtered_0_valid_T_12 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_13 = and(in[6].e.valid, _portsEOI_filtered_0_valid_T_12)
connect portsEOI_filtered_6[0].valid, _portsEOI_filtered_0_valid_T_13
connect portsEOI_filtered_6[1].bits, in[6].e.bits
node _portsEOI_filtered_1_valid_T_12 = or(requestEIO_6_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_13 = and(in[6].e.valid, _portsEOI_filtered_1_valid_T_12)
connect portsEOI_filtered_6[1].valid, _portsEOI_filtered_1_valid_T_13
node _portsEOI_in_6_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_6[0].ready, UInt<1>(0h0))
node _portsEOI_in_6_e_ready_T_1 = mux(requestEIO_6_1, portsEOI_filtered_6[1].ready, UInt<1>(0h0))
node _portsEOI_in_6_e_ready_T_2 = or(_portsEOI_in_6_e_ready_T, _portsEOI_in_6_e_ready_T_1)
wire _portsEOI_in_6_e_ready_WIRE : UInt<1>
connect _portsEOI_in_6_e_ready_WIRE, _portsEOI_in_6_e_ready_T_2
connect in[6].e.ready, _portsEOI_in_6_e_ready_WIRE
wire portsEOI_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_7[0].bits, in[7].e.bits
node _portsEOI_filtered_0_valid_T_14 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_15 = and(in[7].e.valid, _portsEOI_filtered_0_valid_T_14)
connect portsEOI_filtered_7[0].valid, _portsEOI_filtered_0_valid_T_15
connect portsEOI_filtered_7[1].bits, in[7].e.bits
node _portsEOI_filtered_1_valid_T_14 = or(requestEIO_7_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_15 = and(in[7].e.valid, _portsEOI_filtered_1_valid_T_14)
connect portsEOI_filtered_7[1].valid, _portsEOI_filtered_1_valid_T_15
node _portsEOI_in_7_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_7[0].ready, UInt<1>(0h0))
node _portsEOI_in_7_e_ready_T_1 = mux(requestEIO_7_1, portsEOI_filtered_7[1].ready, UInt<1>(0h0))
node _portsEOI_in_7_e_ready_T_2 = or(_portsEOI_in_7_e_ready_T, _portsEOI_in_7_e_ready_T_1)
wire _portsEOI_in_7_e_ready_WIRE : UInt<1>
connect _portsEOI_in_7_e_ready_WIRE, _portsEOI_in_7_e_ready_T_2
connect in[7].e.ready, _portsEOI_in_7_e_ready_WIRE
wire portsEOI_filtered_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_8[0].bits, in[8].e.bits
node _portsEOI_filtered_0_valid_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_17 = and(in[8].e.valid, _portsEOI_filtered_0_valid_T_16)
connect portsEOI_filtered_8[0].valid, _portsEOI_filtered_0_valid_T_17
connect portsEOI_filtered_8[1].bits, in[8].e.bits
node _portsEOI_filtered_1_valid_T_16 = or(requestEIO_8_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_17 = and(in[8].e.valid, _portsEOI_filtered_1_valid_T_16)
connect portsEOI_filtered_8[1].valid, _portsEOI_filtered_1_valid_T_17
node _portsEOI_in_8_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_8[0].ready, UInt<1>(0h0))
node _portsEOI_in_8_e_ready_T_1 = mux(requestEIO_8_1, portsEOI_filtered_8[1].ready, UInt<1>(0h0))
node _portsEOI_in_8_e_ready_T_2 = or(_portsEOI_in_8_e_ready_T, _portsEOI_in_8_e_ready_T_1)
wire _portsEOI_in_8_e_ready_WIRE : UInt<1>
connect _portsEOI_in_8_e_ready_WIRE, _portsEOI_in_8_e_ready_T_2
connect in[8].e.ready, _portsEOI_in_8_e_ready_WIRE
wire portsEOI_filtered_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_9[0].bits, in[9].e.bits
node _portsEOI_filtered_0_valid_T_18 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_19 = and(in[9].e.valid, _portsEOI_filtered_0_valid_T_18)
connect portsEOI_filtered_9[0].valid, _portsEOI_filtered_0_valid_T_19
connect portsEOI_filtered_9[1].bits, in[9].e.bits
node _portsEOI_filtered_1_valid_T_18 = or(requestEIO_9_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_19 = and(in[9].e.valid, _portsEOI_filtered_1_valid_T_18)
connect portsEOI_filtered_9[1].valid, _portsEOI_filtered_1_valid_T_19
node _portsEOI_in_9_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_9[0].ready, UInt<1>(0h0))
node _portsEOI_in_9_e_ready_T_1 = mux(requestEIO_9_1, portsEOI_filtered_9[1].ready, UInt<1>(0h0))
node _portsEOI_in_9_e_ready_T_2 = or(_portsEOI_in_9_e_ready_T, _portsEOI_in_9_e_ready_T_1)
wire _portsEOI_in_9_e_ready_WIRE : UInt<1>
connect _portsEOI_in_9_e_ready_WIRE, _portsEOI_in_9_e_ready_T_2
connect in[9].e.ready, _portsEOI_in_9_e_ready_WIRE
wire portsEOI_filtered_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_10[0].bits, in[10].e.bits
node _portsEOI_filtered_0_valid_T_20 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_21 = and(in[10].e.valid, _portsEOI_filtered_0_valid_T_20)
connect portsEOI_filtered_10[0].valid, _portsEOI_filtered_0_valid_T_21
connect portsEOI_filtered_10[1].bits, in[10].e.bits
node _portsEOI_filtered_1_valid_T_20 = or(requestEIO_10_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_21 = and(in[10].e.valid, _portsEOI_filtered_1_valid_T_20)
connect portsEOI_filtered_10[1].valid, _portsEOI_filtered_1_valid_T_21
node _portsEOI_in_10_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_10[0].ready, UInt<1>(0h0))
node _portsEOI_in_10_e_ready_T_1 = mux(requestEIO_10_1, portsEOI_filtered_10[1].ready, UInt<1>(0h0))
node _portsEOI_in_10_e_ready_T_2 = or(_portsEOI_in_10_e_ready_T, _portsEOI_in_10_e_ready_T_1)
wire _portsEOI_in_10_e_ready_WIRE : UInt<1>
connect _portsEOI_in_10_e_ready_WIRE, _portsEOI_in_10_e_ready_T_2
connect in[10].e.ready, _portsEOI_in_10_e_ready_WIRE
wire portsEOI_filtered_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_11[0].bits, in[11].e.bits
node _portsEOI_filtered_0_valid_T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_23 = and(in[11].e.valid, _portsEOI_filtered_0_valid_T_22)
connect portsEOI_filtered_11[0].valid, _portsEOI_filtered_0_valid_T_23
connect portsEOI_filtered_11[1].bits, in[11].e.bits
node _portsEOI_filtered_1_valid_T_22 = or(requestEIO_11_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_23 = and(in[11].e.valid, _portsEOI_filtered_1_valid_T_22)
connect portsEOI_filtered_11[1].valid, _portsEOI_filtered_1_valid_T_23
node _portsEOI_in_11_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_11[0].ready, UInt<1>(0h0))
node _portsEOI_in_11_e_ready_T_1 = mux(requestEIO_11_1, portsEOI_filtered_11[1].ready, UInt<1>(0h0))
node _portsEOI_in_11_e_ready_T_2 = or(_portsEOI_in_11_e_ready_T, _portsEOI_in_11_e_ready_T_1)
wire _portsEOI_in_11_e_ready_WIRE : UInt<1>
connect _portsEOI_in_11_e_ready_WIRE, _portsEOI_in_11_e_ready_T_2
connect in[11].e.ready, _portsEOI_in_11_e_ready_WIRE
wire portsEOI_filtered_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_12[0].bits, in[12].e.bits
node _portsEOI_filtered_0_valid_T_24 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_25 = and(in[12].e.valid, _portsEOI_filtered_0_valid_T_24)
connect portsEOI_filtered_12[0].valid, _portsEOI_filtered_0_valid_T_25
connect portsEOI_filtered_12[1].bits, in[12].e.bits
node _portsEOI_filtered_1_valid_T_24 = or(requestEIO_12_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_25 = and(in[12].e.valid, _portsEOI_filtered_1_valid_T_24)
connect portsEOI_filtered_12[1].valid, _portsEOI_filtered_1_valid_T_25
node _portsEOI_in_12_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_12[0].ready, UInt<1>(0h0))
node _portsEOI_in_12_e_ready_T_1 = mux(requestEIO_12_1, portsEOI_filtered_12[1].ready, UInt<1>(0h0))
node _portsEOI_in_12_e_ready_T_2 = or(_portsEOI_in_12_e_ready_T, _portsEOI_in_12_e_ready_T_1)
wire _portsEOI_in_12_e_ready_WIRE : UInt<1>
connect _portsEOI_in_12_e_ready_WIRE, _portsEOI_in_12_e_ready_T_2
connect in[12].e.ready, _portsEOI_in_12_e_ready_WIRE
wire portsEOI_filtered_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_13[0].bits, in[13].e.bits
node _portsEOI_filtered_0_valid_T_26 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_27 = and(in[13].e.valid, _portsEOI_filtered_0_valid_T_26)
connect portsEOI_filtered_13[0].valid, _portsEOI_filtered_0_valid_T_27
connect portsEOI_filtered_13[1].bits, in[13].e.bits
node _portsEOI_filtered_1_valid_T_26 = or(requestEIO_13_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_27 = and(in[13].e.valid, _portsEOI_filtered_1_valid_T_26)
connect portsEOI_filtered_13[1].valid, _portsEOI_filtered_1_valid_T_27
node _portsEOI_in_13_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_13[0].ready, UInt<1>(0h0))
node _portsEOI_in_13_e_ready_T_1 = mux(requestEIO_13_1, portsEOI_filtered_13[1].ready, UInt<1>(0h0))
node _portsEOI_in_13_e_ready_T_2 = or(_portsEOI_in_13_e_ready_T, _portsEOI_in_13_e_ready_T_1)
wire _portsEOI_in_13_e_ready_WIRE : UInt<1>
connect _portsEOI_in_13_e_ready_WIRE, _portsEOI_in_13_e_ready_T_2
connect in[13].e.ready, _portsEOI_in_13_e_ready_WIRE
wire portsEOI_filtered_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_14[0].bits, in[14].e.bits
node _portsEOI_filtered_0_valid_T_28 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_29 = and(in[14].e.valid, _portsEOI_filtered_0_valid_T_28)
connect portsEOI_filtered_14[0].valid, _portsEOI_filtered_0_valid_T_29
connect portsEOI_filtered_14[1].bits, in[14].e.bits
node _portsEOI_filtered_1_valid_T_28 = or(requestEIO_14_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_29 = and(in[14].e.valid, _portsEOI_filtered_1_valid_T_28)
connect portsEOI_filtered_14[1].valid, _portsEOI_filtered_1_valid_T_29
node _portsEOI_in_14_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_14[0].ready, UInt<1>(0h0))
node _portsEOI_in_14_e_ready_T_1 = mux(requestEIO_14_1, portsEOI_filtered_14[1].ready, UInt<1>(0h0))
node _portsEOI_in_14_e_ready_T_2 = or(_portsEOI_in_14_e_ready_T, _portsEOI_in_14_e_ready_T_1)
wire _portsEOI_in_14_e_ready_WIRE : UInt<1>
connect _portsEOI_in_14_e_ready_WIRE, _portsEOI_in_14_e_ready_T_2
connect in[14].e.ready, _portsEOI_in_14_e_ready_WIRE
wire portsEOI_filtered_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_15[0].bits, in[15].e.bits
node _portsEOI_filtered_0_valid_T_30 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_31 = and(in[15].e.valid, _portsEOI_filtered_0_valid_T_30)
connect portsEOI_filtered_15[0].valid, _portsEOI_filtered_0_valid_T_31
connect portsEOI_filtered_15[1].bits, in[15].e.bits
node _portsEOI_filtered_1_valid_T_30 = or(requestEIO_15_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_31 = and(in[15].e.valid, _portsEOI_filtered_1_valid_T_30)
connect portsEOI_filtered_15[1].valid, _portsEOI_filtered_1_valid_T_31
node _portsEOI_in_15_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_15[0].ready, UInt<1>(0h0))
node _portsEOI_in_15_e_ready_T_1 = mux(requestEIO_15_1, portsEOI_filtered_15[1].ready, UInt<1>(0h0))
node _portsEOI_in_15_e_ready_T_2 = or(_portsEOI_in_15_e_ready_T, _portsEOI_in_15_e_ready_T_1)
wire _portsEOI_in_15_e_ready_WIRE : UInt<1>
connect _portsEOI_in_15_e_ready_WIRE, _portsEOI_in_15_e_ready_T_2
connect in[15].e.ready, _portsEOI_in_15_e_ready_WIRE
wire portsEOI_filtered_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_16[0].bits, in[16].e.bits
node _portsEOI_filtered_0_valid_T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_33 = and(in[16].e.valid, _portsEOI_filtered_0_valid_T_32)
connect portsEOI_filtered_16[0].valid, _portsEOI_filtered_0_valid_T_33
connect portsEOI_filtered_16[1].bits, in[16].e.bits
node _portsEOI_filtered_1_valid_T_32 = or(requestEIO_16_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_33 = and(in[16].e.valid, _portsEOI_filtered_1_valid_T_32)
connect portsEOI_filtered_16[1].valid, _portsEOI_filtered_1_valid_T_33
node _portsEOI_in_16_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_16[0].ready, UInt<1>(0h0))
node _portsEOI_in_16_e_ready_T_1 = mux(requestEIO_16_1, portsEOI_filtered_16[1].ready, UInt<1>(0h0))
node _portsEOI_in_16_e_ready_T_2 = or(_portsEOI_in_16_e_ready_T, _portsEOI_in_16_e_ready_T_1)
wire _portsEOI_in_16_e_ready_WIRE : UInt<1>
connect _portsEOI_in_16_e_ready_WIRE, _portsEOI_in_16_e_ready_T_2
connect in[16].e.ready, _portsEOI_in_16_e_ready_WIRE
wire portsEOI_filtered_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_17[0].bits, in[17].e.bits
node _portsEOI_filtered_0_valid_T_34 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_35 = and(in[17].e.valid, _portsEOI_filtered_0_valid_T_34)
connect portsEOI_filtered_17[0].valid, _portsEOI_filtered_0_valid_T_35
connect portsEOI_filtered_17[1].bits, in[17].e.bits
node _portsEOI_filtered_1_valid_T_34 = or(requestEIO_17_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_35 = and(in[17].e.valid, _portsEOI_filtered_1_valid_T_34)
connect portsEOI_filtered_17[1].valid, _portsEOI_filtered_1_valid_T_35
node _portsEOI_in_17_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_17[0].ready, UInt<1>(0h0))
node _portsEOI_in_17_e_ready_T_1 = mux(requestEIO_17_1, portsEOI_filtered_17[1].ready, UInt<1>(0h0))
node _portsEOI_in_17_e_ready_T_2 = or(_portsEOI_in_17_e_ready_T, _portsEOI_in_17_e_ready_T_1)
wire _portsEOI_in_17_e_ready_WIRE : UInt<1>
connect _portsEOI_in_17_e_ready_WIRE, _portsEOI_in_17_e_ready_T_2
connect in[17].e.ready, _portsEOI_in_17_e_ready_WIRE
wire portsEOI_filtered_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_18[0].bits, in[18].e.bits
node _portsEOI_filtered_0_valid_T_36 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_37 = and(in[18].e.valid, _portsEOI_filtered_0_valid_T_36)
connect portsEOI_filtered_18[0].valid, _portsEOI_filtered_0_valid_T_37
connect portsEOI_filtered_18[1].bits, in[18].e.bits
node _portsEOI_filtered_1_valid_T_36 = or(requestEIO_18_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_37 = and(in[18].e.valid, _portsEOI_filtered_1_valid_T_36)
connect portsEOI_filtered_18[1].valid, _portsEOI_filtered_1_valid_T_37
node _portsEOI_in_18_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_18[0].ready, UInt<1>(0h0))
node _portsEOI_in_18_e_ready_T_1 = mux(requestEIO_18_1, portsEOI_filtered_18[1].ready, UInt<1>(0h0))
node _portsEOI_in_18_e_ready_T_2 = or(_portsEOI_in_18_e_ready_T, _portsEOI_in_18_e_ready_T_1)
wire _portsEOI_in_18_e_ready_WIRE : UInt<1>
connect _portsEOI_in_18_e_ready_WIRE, _portsEOI_in_18_e_ready_T_2
connect in[18].e.ready, _portsEOI_in_18_e_ready_WIRE
wire portsEOI_filtered_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2]
connect portsEOI_filtered_19[0].bits, in[19].e.bits
node _portsEOI_filtered_0_valid_T_38 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_39 = and(in[19].e.valid, _portsEOI_filtered_0_valid_T_38)
connect portsEOI_filtered_19[0].valid, _portsEOI_filtered_0_valid_T_39
connect portsEOI_filtered_19[1].bits, in[19].e.bits
node _portsEOI_filtered_1_valid_T_38 = or(requestEIO_19_1, UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_39 = and(in[19].e.valid, _portsEOI_filtered_1_valid_T_38)
connect portsEOI_filtered_19[1].valid, _portsEOI_filtered_1_valid_T_39
node _portsEOI_in_19_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_19[0].ready, UInt<1>(0h0))
node _portsEOI_in_19_e_ready_T_1 = mux(requestEIO_19_1, portsEOI_filtered_19[1].ready, UInt<1>(0h0))
node _portsEOI_in_19_e_ready_T_2 = or(_portsEOI_in_19_e_ready_T, _portsEOI_in_19_e_ready_T_1)
wire _portsEOI_in_19_e_ready_WIRE : UInt<1>
connect _portsEOI_in_19_e_ready_WIRE, _portsEOI_in_19_e_ready_T_2
connect in[19].e.ready, _portsEOI_in_19_e_ready_WIRE
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node readys_lo_lo_lo = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_lo_lo_hi_hi = cat(portsAOI_filtered_4[0].valid, portsAOI_filtered_3[0].valid)
node readys_lo_lo_hi = cat(readys_lo_lo_hi_hi, portsAOI_filtered_2[0].valid)
node readys_lo_lo = cat(readys_lo_lo_hi, readys_lo_lo_lo)
node readys_lo_hi_lo = cat(portsAOI_filtered_6[0].valid, portsAOI_filtered_5[0].valid)
node readys_lo_hi_hi_hi = cat(portsAOI_filtered_9[0].valid, portsAOI_filtered_8[0].valid)
node readys_lo_hi_hi = cat(readys_lo_hi_hi_hi, portsAOI_filtered_7[0].valid)
node readys_lo_hi = cat(readys_lo_hi_hi, readys_lo_hi_lo)
node readys_lo = cat(readys_lo_hi, readys_lo_lo)
node readys_hi_lo_lo = cat(portsAOI_filtered_11[0].valid, portsAOI_filtered_10[0].valid)
node readys_hi_lo_hi_hi = cat(portsAOI_filtered_14[0].valid, portsAOI_filtered_13[0].valid)
node readys_hi_lo_hi = cat(readys_hi_lo_hi_hi, portsAOI_filtered_12[0].valid)
node readys_hi_lo = cat(readys_hi_lo_hi, readys_hi_lo_lo)
node readys_hi_hi_lo = cat(portsAOI_filtered_16[0].valid, portsAOI_filtered_15[0].valid)
node readys_hi_hi_hi_hi = cat(portsAOI_filtered_19[0].valid, portsAOI_filtered_18[0].valid)
node readys_hi_hi_hi = cat(readys_hi_hi_hi_hi, portsAOI_filtered_17[0].valid)
node readys_hi_hi = cat(readys_hi_hi_hi, readys_hi_hi_lo)
node readys_hi = cat(readys_hi_hi, readys_hi_lo)
node _readys_T = cat(readys_hi, readys_lo)
node readys_valid = bits(_readys_T, 19, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<20>, clock, reset, UInt<20>(0hfffff)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = shr(_readys_unready_T_3, 4)
node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_unready_T_6 = shr(_readys_unready_T_5, 8)
node _readys_unready_T_7 = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_unready_T_8 = shr(_readys_unready_T_7, 16)
node _readys_unready_T_9 = or(_readys_unready_T_7, _readys_unready_T_8)
node _readys_unready_T_10 = bits(_readys_unready_T_9, 39, 0)
node _readys_unready_T_11 = shr(_readys_unready_T_10, 1)
node _readys_unready_T_12 = shl(readys_mask, 20)
node readys_unready = or(_readys_unready_T_11, _readys_unready_T_12)
node _readys_readys_T = shr(readys_unready, 20)
node _readys_readys_T_1 = bits(readys_unready, 19, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 19, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 19, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = shl(_readys_mask_T_6, 4)
node _readys_mask_T_8 = bits(_readys_mask_T_7, 19, 0)
node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8)
node _readys_mask_T_10 = shl(_readys_mask_T_9, 8)
node _readys_mask_T_11 = bits(_readys_mask_T_10, 19, 0)
node _readys_mask_T_12 = or(_readys_mask_T_9, _readys_mask_T_11)
node _readys_mask_T_13 = shl(_readys_mask_T_12, 16)
node _readys_mask_T_14 = bits(_readys_mask_T_13, 19, 0)
node _readys_mask_T_15 = or(_readys_mask_T_12, _readys_mask_T_14)
node _readys_mask_T_16 = bits(_readys_mask_T_15, 19, 0)
connect readys_mask, _readys_mask_T_16
node _readys_T_7 = bits(readys_readys, 19, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
node _readys_T_11 = bits(_readys_T_7, 3, 3)
node _readys_T_12 = bits(_readys_T_7, 4, 4)
node _readys_T_13 = bits(_readys_T_7, 5, 5)
node _readys_T_14 = bits(_readys_T_7, 6, 6)
node _readys_T_15 = bits(_readys_T_7, 7, 7)
node _readys_T_16 = bits(_readys_T_7, 8, 8)
node _readys_T_17 = bits(_readys_T_7, 9, 9)
node _readys_T_18 = bits(_readys_T_7, 10, 10)
node _readys_T_19 = bits(_readys_T_7, 11, 11)
node _readys_T_20 = bits(_readys_T_7, 12, 12)
node _readys_T_21 = bits(_readys_T_7, 13, 13)
node _readys_T_22 = bits(_readys_T_7, 14, 14)
node _readys_T_23 = bits(_readys_T_7, 15, 15)
node _readys_T_24 = bits(_readys_T_7, 16, 16)
node _readys_T_25 = bits(_readys_T_7, 17, 17)
node _readys_T_26 = bits(_readys_T_7, 18, 18)
node _readys_T_27 = bits(_readys_T_7, 19, 19)
wire readys : UInt<1>[20]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
connect readys[3], _readys_T_11
connect readys[4], _readys_T_12
connect readys[5], _readys_T_13
connect readys[6], _readys_T_14
connect readys[7], _readys_T_15
connect readys[8], _readys_T_16
connect readys[9], _readys_T_17
connect readys[10], _readys_T_18
connect readys[11], _readys_T_19
connect readys[12], _readys_T_20
connect readys[13], _readys_T_21
connect readys[14], _readys_T_22
connect readys[15], _readys_T_23
connect readys[16], _readys_T_24
connect readys[17], _readys_T_25
connect readys[18], _readys_T_26
connect readys[19], _readys_T_27
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid)
node _winner_T_3 = and(readys[3], portsAOI_filtered_3[0].valid)
node _winner_T_4 = and(readys[4], portsAOI_filtered_4[0].valid)
node _winner_T_5 = and(readys[5], portsAOI_filtered_5[0].valid)
node _winner_T_6 = and(readys[6], portsAOI_filtered_6[0].valid)
node _winner_T_7 = and(readys[7], portsAOI_filtered_7[0].valid)
node _winner_T_8 = and(readys[8], portsAOI_filtered_8[0].valid)
node _winner_T_9 = and(readys[9], portsAOI_filtered_9[0].valid)
node _winner_T_10 = and(readys[10], portsAOI_filtered_10[0].valid)
node _winner_T_11 = and(readys[11], portsAOI_filtered_11[0].valid)
node _winner_T_12 = and(readys[12], portsAOI_filtered_12[0].valid)
node _winner_T_13 = and(readys[13], portsAOI_filtered_13[0].valid)
node _winner_T_14 = and(readys[14], portsAOI_filtered_14[0].valid)
node _winner_T_15 = and(readys[15], portsAOI_filtered_15[0].valid)
node _winner_T_16 = and(readys[16], portsAOI_filtered_16[0].valid)
node _winner_T_17 = and(readys[17], portsAOI_filtered_17[0].valid)
node _winner_T_18 = and(readys[18], portsAOI_filtered_18[0].valid)
node _winner_T_19 = and(readys[19], portsAOI_filtered_19[0].valid)
wire winner : UInt<1>[20]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
connect winner[3], _winner_T_3
connect winner[4], _winner_T_4
connect winner[5], _winner_T_5
connect winner[6], _winner_T_6
connect winner[7], _winner_T_7
connect winner[8], _winner_T_8
connect winner[9], _winner_T_9
connect winner[10], _winner_T_10
connect winner[11], _winner_T_11
connect winner[12], _winner_T_12
connect winner[13], _winner_T_13
connect winner[14], _winner_T_14
connect winner[15], _winner_T_15
connect winner[16], _winner_T_16
connect winner[17], _winner_T_17
connect winner[18], _winner_T_18
connect winner[19], _winner_T_19
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node prefixOR_3 = or(prefixOR_2, winner[2])
node prefixOR_4 = or(prefixOR_3, winner[3])
node prefixOR_5 = or(prefixOR_4, winner[4])
node prefixOR_6 = or(prefixOR_5, winner[5])
node prefixOR_7 = or(prefixOR_6, winner[6])
node prefixOR_8 = or(prefixOR_7, winner[7])
node prefixOR_9 = or(prefixOR_8, winner[8])
node prefixOR_10 = or(prefixOR_9, winner[9])
node prefixOR_11 = or(prefixOR_10, winner[10])
node prefixOR_12 = or(prefixOR_11, winner[11])
node prefixOR_13 = or(prefixOR_12, winner[12])
node prefixOR_14 = or(prefixOR_13, winner[13])
node prefixOR_15 = or(prefixOR_14, winner[14])
node prefixOR_16 = or(prefixOR_15, winner[15])
node prefixOR_17 = or(prefixOR_16, winner[16])
node prefixOR_18 = or(prefixOR_17, winner[17])
node prefixOR_19 = or(prefixOR_18, winner[18])
node _prefixOR_T = or(prefixOR_19, winner[19])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = eq(prefixOR_3, UInt<1>(0h0))
node _T_10 = eq(winner[3], UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = eq(prefixOR_4, UInt<1>(0h0))
node _T_13 = eq(winner[4], UInt<1>(0h0))
node _T_14 = or(_T_12, _T_13)
node _T_15 = eq(prefixOR_5, UInt<1>(0h0))
node _T_16 = eq(winner[5], UInt<1>(0h0))
node _T_17 = or(_T_15, _T_16)
node _T_18 = eq(prefixOR_6, UInt<1>(0h0))
node _T_19 = eq(winner[6], UInt<1>(0h0))
node _T_20 = or(_T_18, _T_19)
node _T_21 = eq(prefixOR_7, UInt<1>(0h0))
node _T_22 = eq(winner[7], UInt<1>(0h0))
node _T_23 = or(_T_21, _T_22)
node _T_24 = eq(prefixOR_8, UInt<1>(0h0))
node _T_25 = eq(winner[8], UInt<1>(0h0))
node _T_26 = or(_T_24, _T_25)
node _T_27 = eq(prefixOR_9, UInt<1>(0h0))
node _T_28 = eq(winner[9], UInt<1>(0h0))
node _T_29 = or(_T_27, _T_28)
node _T_30 = eq(prefixOR_10, UInt<1>(0h0))
node _T_31 = eq(winner[10], UInt<1>(0h0))
node _T_32 = or(_T_30, _T_31)
node _T_33 = eq(prefixOR_11, UInt<1>(0h0))
node _T_34 = eq(winner[11], UInt<1>(0h0))
node _T_35 = or(_T_33, _T_34)
node _T_36 = eq(prefixOR_12, UInt<1>(0h0))
node _T_37 = eq(winner[12], UInt<1>(0h0))
node _T_38 = or(_T_36, _T_37)
node _T_39 = eq(prefixOR_13, UInt<1>(0h0))
node _T_40 = eq(winner[13], UInt<1>(0h0))
node _T_41 = or(_T_39, _T_40)
node _T_42 = eq(prefixOR_14, UInt<1>(0h0))
node _T_43 = eq(winner[14], UInt<1>(0h0))
node _T_44 = or(_T_42, _T_43)
node _T_45 = eq(prefixOR_15, UInt<1>(0h0))
node _T_46 = eq(winner[15], UInt<1>(0h0))
node _T_47 = or(_T_45, _T_46)
node _T_48 = eq(prefixOR_16, UInt<1>(0h0))
node _T_49 = eq(winner[16], UInt<1>(0h0))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(prefixOR_17, UInt<1>(0h0))
node _T_52 = eq(winner[17], UInt<1>(0h0))
node _T_53 = or(_T_51, _T_52)
node _T_54 = eq(prefixOR_18, UInt<1>(0h0))
node _T_55 = eq(winner[18], UInt<1>(0h0))
node _T_56 = or(_T_54, _T_55)
node _T_57 = eq(prefixOR_19, UInt<1>(0h0))
node _T_58 = eq(winner[19], UInt<1>(0h0))
node _T_59 = or(_T_57, _T_58)
node _T_60 = and(_T_2, _T_5)
node _T_61 = and(_T_60, _T_8)
node _T_62 = and(_T_61, _T_11)
node _T_63 = and(_T_62, _T_14)
node _T_64 = and(_T_63, _T_17)
node _T_65 = and(_T_64, _T_20)
node _T_66 = and(_T_65, _T_23)
node _T_67 = and(_T_66, _T_26)
node _T_68 = and(_T_67, _T_29)
node _T_69 = and(_T_68, _T_32)
node _T_70 = and(_T_69, _T_35)
node _T_71 = and(_T_70, _T_38)
node _T_72 = and(_T_71, _T_41)
node _T_73 = and(_T_72, _T_44)
node _T_74 = and(_T_73, _T_47)
node _T_75 = and(_T_74, _T_50)
node _T_76 = and(_T_75, _T_53)
node _T_77 = and(_T_76, _T_56)
node _T_78 = and(_T_77, _T_59)
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_78, UInt<1>(0h1), "") : assert
node _T_82 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_83 = or(_T_82, portsAOI_filtered_2[0].valid)
node _T_84 = or(_T_83, portsAOI_filtered_3[0].valid)
node _T_85 = or(_T_84, portsAOI_filtered_4[0].valid)
node _T_86 = or(_T_85, portsAOI_filtered_5[0].valid)
node _T_87 = or(_T_86, portsAOI_filtered_6[0].valid)
node _T_88 = or(_T_87, portsAOI_filtered_7[0].valid)
node _T_89 = or(_T_88, portsAOI_filtered_8[0].valid)
node _T_90 = or(_T_89, portsAOI_filtered_9[0].valid)
node _T_91 = or(_T_90, portsAOI_filtered_10[0].valid)
node _T_92 = or(_T_91, portsAOI_filtered_11[0].valid)
node _T_93 = or(_T_92, portsAOI_filtered_12[0].valid)
node _T_94 = or(_T_93, portsAOI_filtered_13[0].valid)
node _T_95 = or(_T_94, portsAOI_filtered_14[0].valid)
node _T_96 = or(_T_95, portsAOI_filtered_15[0].valid)
node _T_97 = or(_T_96, portsAOI_filtered_16[0].valid)
node _T_98 = or(_T_97, portsAOI_filtered_17[0].valid)
node _T_99 = or(_T_98, portsAOI_filtered_18[0].valid)
node _T_100 = or(_T_99, portsAOI_filtered_19[0].valid)
node _T_101 = eq(_T_100, UInt<1>(0h0))
node _T_102 = or(winner[0], winner[1])
node _T_103 = or(_T_102, winner[2])
node _T_104 = or(_T_103, winner[3])
node _T_105 = or(_T_104, winner[4])
node _T_106 = or(_T_105, winner[5])
node _T_107 = or(_T_106, winner[6])
node _T_108 = or(_T_107, winner[7])
node _T_109 = or(_T_108, winner[8])
node _T_110 = or(_T_109, winner[9])
node _T_111 = or(_T_110, winner[10])
node _T_112 = or(_T_111, winner[11])
node _T_113 = or(_T_112, winner[12])
node _T_114 = or(_T_113, winner[13])
node _T_115 = or(_T_114, winner[14])
node _T_116 = or(_T_115, winner[15])
node _T_117 = or(_T_116, winner[16])
node _T_118 = or(_T_117, winner[17])
node _T_119 = or(_T_118, winner[18])
node _T_120 = or(_T_119, winner[19])
node _T_121 = or(_T_101, _T_120)
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_121, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0))
node maskedBeats_3 = mux(winner[3], beatsAI_3, UInt<1>(0h0))
node maskedBeats_4 = mux(winner[4], beatsAI_4, UInt<1>(0h0))
node maskedBeats_5 = mux(winner[5], beatsAI_5, UInt<1>(0h0))
node maskedBeats_6 = mux(winner[6], beatsAI_6, UInt<1>(0h0))
node maskedBeats_7 = mux(winner[7], beatsAI_7, UInt<1>(0h0))
node maskedBeats_8 = mux(winner[8], beatsAI_8, UInt<1>(0h0))
node maskedBeats_9 = mux(winner[9], beatsAI_9, UInt<1>(0h0))
node maskedBeats_10 = mux(winner[10], beatsAI_10, UInt<1>(0h0))
node maskedBeats_11 = mux(winner[11], beatsAI_11, UInt<1>(0h0))
node maskedBeats_12 = mux(winner[12], beatsAI_12, UInt<1>(0h0))
node maskedBeats_13 = mux(winner[13], beatsAI_13, UInt<1>(0h0))
node maskedBeats_14 = mux(winner[14], beatsAI_14, UInt<1>(0h0))
node maskedBeats_15 = mux(winner[15], beatsAI_15, UInt<1>(0h0))
node maskedBeats_16 = mux(winner[16], beatsAI_16, UInt<1>(0h0))
node maskedBeats_17 = mux(winner[17], beatsAI_17, UInt<1>(0h0))
node maskedBeats_18 = mux(winner[18], beatsAI_18, UInt<1>(0h0))
node maskedBeats_19 = mux(winner[19], beatsAI_19, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2)
node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3)
node _initBeats_T_3 = or(_initBeats_T_2, maskedBeats_4)
node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_5)
node _initBeats_T_5 = or(_initBeats_T_4, maskedBeats_6)
node _initBeats_T_6 = or(_initBeats_T_5, maskedBeats_7)
node _initBeats_T_7 = or(_initBeats_T_6, maskedBeats_8)
node _initBeats_T_8 = or(_initBeats_T_7, maskedBeats_9)
node _initBeats_T_9 = or(_initBeats_T_8, maskedBeats_10)
node _initBeats_T_10 = or(_initBeats_T_9, maskedBeats_11)
node _initBeats_T_11 = or(_initBeats_T_10, maskedBeats_12)
node _initBeats_T_12 = or(_initBeats_T_11, maskedBeats_13)
node _initBeats_T_13 = or(_initBeats_T_12, maskedBeats_14)
node _initBeats_T_14 = or(_initBeats_T_13, maskedBeats_15)
node _initBeats_T_15 = or(_initBeats_T_14, maskedBeats_16)
node _initBeats_T_16 = or(_initBeats_T_15, maskedBeats_17)
node _initBeats_T_17 = or(_initBeats_T_16, maskedBeats_18)
node initBeats = or(_initBeats_T_17, maskedBeats_19)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[20]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
connect _state_WIRE[3], UInt<1>(0h0)
connect _state_WIRE[4], UInt<1>(0h0)
connect _state_WIRE[5], UInt<1>(0h0)
connect _state_WIRE[6], UInt<1>(0h0)
connect _state_WIRE[7], UInt<1>(0h0)
connect _state_WIRE[8], UInt<1>(0h0)
connect _state_WIRE[9], UInt<1>(0h0)
connect _state_WIRE[10], UInt<1>(0h0)
connect _state_WIRE[11], UInt<1>(0h0)
connect _state_WIRE[12], UInt<1>(0h0)
connect _state_WIRE[13], UInt<1>(0h0)
connect _state_WIRE[14], UInt<1>(0h0)
connect _state_WIRE[15], UInt<1>(0h0)
connect _state_WIRE[16], UInt<1>(0h0)
connect _state_WIRE[17], UInt<1>(0h0)
connect _state_WIRE[18], UInt<1>(0h0)
connect _state_WIRE[19], UInt<1>(0h0)
regreset state : UInt<1>[20], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2])
connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(out[0].a.ready, allowed[3])
connect portsAOI_filtered_3[0].ready, _filtered_0_ready_T_3
node _filtered_0_ready_T_4 = and(out[0].a.ready, allowed[4])
connect portsAOI_filtered_4[0].ready, _filtered_0_ready_T_4
node _filtered_0_ready_T_5 = and(out[0].a.ready, allowed[5])
connect portsAOI_filtered_5[0].ready, _filtered_0_ready_T_5
node _filtered_0_ready_T_6 = and(out[0].a.ready, allowed[6])
connect portsAOI_filtered_6[0].ready, _filtered_0_ready_T_6
node _filtered_0_ready_T_7 = and(out[0].a.ready, allowed[7])
connect portsAOI_filtered_7[0].ready, _filtered_0_ready_T_7
node _filtered_0_ready_T_8 = and(out[0].a.ready, allowed[8])
connect portsAOI_filtered_8[0].ready, _filtered_0_ready_T_8
node _filtered_0_ready_T_9 = and(out[0].a.ready, allowed[9])
connect portsAOI_filtered_9[0].ready, _filtered_0_ready_T_9
node _filtered_0_ready_T_10 = and(out[0].a.ready, allowed[10])
connect portsAOI_filtered_10[0].ready, _filtered_0_ready_T_10
node _filtered_0_ready_T_11 = and(out[0].a.ready, allowed[11])
connect portsAOI_filtered_11[0].ready, _filtered_0_ready_T_11
node _filtered_0_ready_T_12 = and(out[0].a.ready, allowed[12])
connect portsAOI_filtered_12[0].ready, _filtered_0_ready_T_12
node _filtered_0_ready_T_13 = and(out[0].a.ready, allowed[13])
connect portsAOI_filtered_13[0].ready, _filtered_0_ready_T_13
node _filtered_0_ready_T_14 = and(out[0].a.ready, allowed[14])
connect portsAOI_filtered_14[0].ready, _filtered_0_ready_T_14
node _filtered_0_ready_T_15 = and(out[0].a.ready, allowed[15])
connect portsAOI_filtered_15[0].ready, _filtered_0_ready_T_15
node _filtered_0_ready_T_16 = and(out[0].a.ready, allowed[16])
connect portsAOI_filtered_16[0].ready, _filtered_0_ready_T_16
node _filtered_0_ready_T_17 = and(out[0].a.ready, allowed[17])
connect portsAOI_filtered_17[0].ready, _filtered_0_ready_T_17
node _filtered_0_ready_T_18 = and(out[0].a.ready, allowed[18])
connect portsAOI_filtered_18[0].ready, _filtered_0_ready_T_18
node _filtered_0_ready_T_19 = and(out[0].a.ready, allowed[19])
connect portsAOI_filtered_19[0].ready, _filtered_0_ready_T_19
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid)
node _out_0_a_valid_T_2 = or(_out_0_a_valid_T_1, portsAOI_filtered_3[0].valid)
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_2, portsAOI_filtered_4[0].valid)
node _out_0_a_valid_T_4 = or(_out_0_a_valid_T_3, portsAOI_filtered_5[0].valid)
node _out_0_a_valid_T_5 = or(_out_0_a_valid_T_4, portsAOI_filtered_6[0].valid)
node _out_0_a_valid_T_6 = or(_out_0_a_valid_T_5, portsAOI_filtered_7[0].valid)
node _out_0_a_valid_T_7 = or(_out_0_a_valid_T_6, portsAOI_filtered_8[0].valid)
node _out_0_a_valid_T_8 = or(_out_0_a_valid_T_7, portsAOI_filtered_9[0].valid)
node _out_0_a_valid_T_9 = or(_out_0_a_valid_T_8, portsAOI_filtered_10[0].valid)
node _out_0_a_valid_T_10 = or(_out_0_a_valid_T_9, portsAOI_filtered_11[0].valid)
node _out_0_a_valid_T_11 = or(_out_0_a_valid_T_10, portsAOI_filtered_12[0].valid)
node _out_0_a_valid_T_12 = or(_out_0_a_valid_T_11, portsAOI_filtered_13[0].valid)
node _out_0_a_valid_T_13 = or(_out_0_a_valid_T_12, portsAOI_filtered_14[0].valid)
node _out_0_a_valid_T_14 = or(_out_0_a_valid_T_13, portsAOI_filtered_15[0].valid)
node _out_0_a_valid_T_15 = or(_out_0_a_valid_T_14, portsAOI_filtered_16[0].valid)
node _out_0_a_valid_T_16 = or(_out_0_a_valid_T_15, portsAOI_filtered_17[0].valid)
node _out_0_a_valid_T_17 = or(_out_0_a_valid_T_16, portsAOI_filtered_18[0].valid)
node _out_0_a_valid_T_18 = or(_out_0_a_valid_T_17, portsAOI_filtered_19[0].valid)
node _out_0_a_valid_T_19 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_20 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_21 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_22 = mux(state[3], portsAOI_filtered_3[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_23 = mux(state[4], portsAOI_filtered_4[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_24 = mux(state[5], portsAOI_filtered_5[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_25 = mux(state[6], portsAOI_filtered_6[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_26 = mux(state[7], portsAOI_filtered_7[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_27 = mux(state[8], portsAOI_filtered_8[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_28 = mux(state[9], portsAOI_filtered_9[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_29 = mux(state[10], portsAOI_filtered_10[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_30 = mux(state[11], portsAOI_filtered_11[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_31 = mux(state[12], portsAOI_filtered_12[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_32 = mux(state[13], portsAOI_filtered_13[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_33 = mux(state[14], portsAOI_filtered_14[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_34 = mux(state[15], portsAOI_filtered_15[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_35 = mux(state[16], portsAOI_filtered_16[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_36 = mux(state[17], portsAOI_filtered_17[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_37 = mux(state[18], portsAOI_filtered_18[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_38 = mux(state[19], portsAOI_filtered_19[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_39 = or(_out_0_a_valid_T_19, _out_0_a_valid_T_20)
node _out_0_a_valid_T_40 = or(_out_0_a_valid_T_39, _out_0_a_valid_T_21)
node _out_0_a_valid_T_41 = or(_out_0_a_valid_T_40, _out_0_a_valid_T_22)
node _out_0_a_valid_T_42 = or(_out_0_a_valid_T_41, _out_0_a_valid_T_23)
node _out_0_a_valid_T_43 = or(_out_0_a_valid_T_42, _out_0_a_valid_T_24)
node _out_0_a_valid_T_44 = or(_out_0_a_valid_T_43, _out_0_a_valid_T_25)
node _out_0_a_valid_T_45 = or(_out_0_a_valid_T_44, _out_0_a_valid_T_26)
node _out_0_a_valid_T_46 = or(_out_0_a_valid_T_45, _out_0_a_valid_T_27)
node _out_0_a_valid_T_47 = or(_out_0_a_valid_T_46, _out_0_a_valid_T_28)
node _out_0_a_valid_T_48 = or(_out_0_a_valid_T_47, _out_0_a_valid_T_29)
node _out_0_a_valid_T_49 = or(_out_0_a_valid_T_48, _out_0_a_valid_T_30)
node _out_0_a_valid_T_50 = or(_out_0_a_valid_T_49, _out_0_a_valid_T_31)
node _out_0_a_valid_T_51 = or(_out_0_a_valid_T_50, _out_0_a_valid_T_32)
node _out_0_a_valid_T_52 = or(_out_0_a_valid_T_51, _out_0_a_valid_T_33)
node _out_0_a_valid_T_53 = or(_out_0_a_valid_T_52, _out_0_a_valid_T_34)
node _out_0_a_valid_T_54 = or(_out_0_a_valid_T_53, _out_0_a_valid_T_35)
node _out_0_a_valid_T_55 = or(_out_0_a_valid_T_54, _out_0_a_valid_T_36)
node _out_0_a_valid_T_56 = or(_out_0_a_valid_T_55, _out_0_a_valid_T_37)
node _out_0_a_valid_T_57 = or(_out_0_a_valid_T_56, _out_0_a_valid_T_38)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_57
node _out_0_a_valid_T_58 = mux(idle, _out_0_a_valid_T_18, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_58
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_3 = mux(muxState[3], portsAOI_filtered_3[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[4], portsAOI_filtered_4[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_5 = mux(muxState[5], portsAOI_filtered_5[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_6 = mux(muxState[6], portsAOI_filtered_6[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[7], portsAOI_filtered_7[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_8 = mux(muxState[8], portsAOI_filtered_8[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_9 = mux(muxState[9], portsAOI_filtered_9[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[10], portsAOI_filtered_10[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_11 = mux(muxState[11], portsAOI_filtered_11[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_12 = mux(muxState[12], portsAOI_filtered_12[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[13], portsAOI_filtered_13[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_14 = mux(muxState[14], portsAOI_filtered_14[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_15 = mux(muxState[15], portsAOI_filtered_15[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[16], portsAOI_filtered_16[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_17 = mux(muxState[17], portsAOI_filtered_17[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_18 = mux(muxState[18], portsAOI_filtered_18[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[19], portsAOI_filtered_19[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
node _out_0_a_bits_T_21 = or(_out_0_a_bits_T_20, _out_0_a_bits_T_2)
node _out_0_a_bits_T_22 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_3)
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_22, _out_0_a_bits_T_4)
node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_5)
node _out_0_a_bits_T_25 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_6)
node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_7)
node _out_0_a_bits_T_27 = or(_out_0_a_bits_T_26, _out_0_a_bits_T_8)
node _out_0_a_bits_T_28 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_9)
node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_28, _out_0_a_bits_T_10)
node _out_0_a_bits_T_30 = or(_out_0_a_bits_T_29, _out_0_a_bits_T_11)
node _out_0_a_bits_T_31 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_12)
node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_31, _out_0_a_bits_T_13)
node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_32, _out_0_a_bits_T_14)
node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_15)
node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_34, _out_0_a_bits_T_16)
node _out_0_a_bits_T_36 = or(_out_0_a_bits_T_35, _out_0_a_bits_T_17)
node _out_0_a_bits_T_37 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_18)
node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_37, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_38
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_41 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_42 = mux(muxState[3], portsAOI_filtered_3[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_43 = mux(muxState[4], portsAOI_filtered_4[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_44 = mux(muxState[5], portsAOI_filtered_5[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_45 = mux(muxState[6], portsAOI_filtered_6[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_46 = mux(muxState[7], portsAOI_filtered_7[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_47 = mux(muxState[8], portsAOI_filtered_8[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_48 = mux(muxState[9], portsAOI_filtered_9[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_49 = mux(muxState[10], portsAOI_filtered_10[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_50 = mux(muxState[11], portsAOI_filtered_11[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_51 = mux(muxState[12], portsAOI_filtered_12[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_52 = mux(muxState[13], portsAOI_filtered_13[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_53 = mux(muxState[14], portsAOI_filtered_14[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_54 = mux(muxState[15], portsAOI_filtered_15[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_55 = mux(muxState[16], portsAOI_filtered_16[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_56 = mux(muxState[17], portsAOI_filtered_17[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_57 = mux(muxState[18], portsAOI_filtered_18[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_58 = mux(muxState[19], portsAOI_filtered_19[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_59 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40)
node _out_0_a_bits_T_60 = or(_out_0_a_bits_T_59, _out_0_a_bits_T_41)
node _out_0_a_bits_T_61 = or(_out_0_a_bits_T_60, _out_0_a_bits_T_42)
node _out_0_a_bits_T_62 = or(_out_0_a_bits_T_61, _out_0_a_bits_T_43)
node _out_0_a_bits_T_63 = or(_out_0_a_bits_T_62, _out_0_a_bits_T_44)
node _out_0_a_bits_T_64 = or(_out_0_a_bits_T_63, _out_0_a_bits_T_45)
node _out_0_a_bits_T_65 = or(_out_0_a_bits_T_64, _out_0_a_bits_T_46)
node _out_0_a_bits_T_66 = or(_out_0_a_bits_T_65, _out_0_a_bits_T_47)
node _out_0_a_bits_T_67 = or(_out_0_a_bits_T_66, _out_0_a_bits_T_48)
node _out_0_a_bits_T_68 = or(_out_0_a_bits_T_67, _out_0_a_bits_T_49)
node _out_0_a_bits_T_69 = or(_out_0_a_bits_T_68, _out_0_a_bits_T_50)
node _out_0_a_bits_T_70 = or(_out_0_a_bits_T_69, _out_0_a_bits_T_51)
node _out_0_a_bits_T_71 = or(_out_0_a_bits_T_70, _out_0_a_bits_T_52)
node _out_0_a_bits_T_72 = or(_out_0_a_bits_T_71, _out_0_a_bits_T_53)
node _out_0_a_bits_T_73 = or(_out_0_a_bits_T_72, _out_0_a_bits_T_54)
node _out_0_a_bits_T_74 = or(_out_0_a_bits_T_73, _out_0_a_bits_T_55)
node _out_0_a_bits_T_75 = or(_out_0_a_bits_T_74, _out_0_a_bits_T_56)
node _out_0_a_bits_T_76 = or(_out_0_a_bits_T_75, _out_0_a_bits_T_57)
node _out_0_a_bits_T_77 = or(_out_0_a_bits_T_76, _out_0_a_bits_T_58)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_77
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_78 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_79 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_80 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_81 = mux(muxState[3], portsAOI_filtered_3[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_82 = mux(muxState[4], portsAOI_filtered_4[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_83 = mux(muxState[5], portsAOI_filtered_5[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_84 = mux(muxState[6], portsAOI_filtered_6[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_85 = mux(muxState[7], portsAOI_filtered_7[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_86 = mux(muxState[8], portsAOI_filtered_8[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_87 = mux(muxState[9], portsAOI_filtered_9[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_88 = mux(muxState[10], portsAOI_filtered_10[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_89 = mux(muxState[11], portsAOI_filtered_11[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_90 = mux(muxState[12], portsAOI_filtered_12[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_91 = mux(muxState[13], portsAOI_filtered_13[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_92 = mux(muxState[14], portsAOI_filtered_14[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_93 = mux(muxState[15], portsAOI_filtered_15[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_94 = mux(muxState[16], portsAOI_filtered_16[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_95 = mux(muxState[17], portsAOI_filtered_17[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_96 = mux(muxState[18], portsAOI_filtered_18[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_97 = mux(muxState[19], portsAOI_filtered_19[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_98 = or(_out_0_a_bits_T_78, _out_0_a_bits_T_79)
node _out_0_a_bits_T_99 = or(_out_0_a_bits_T_98, _out_0_a_bits_T_80)
node _out_0_a_bits_T_100 = or(_out_0_a_bits_T_99, _out_0_a_bits_T_81)
node _out_0_a_bits_T_101 = or(_out_0_a_bits_T_100, _out_0_a_bits_T_82)
node _out_0_a_bits_T_102 = or(_out_0_a_bits_T_101, _out_0_a_bits_T_83)
node _out_0_a_bits_T_103 = or(_out_0_a_bits_T_102, _out_0_a_bits_T_84)
node _out_0_a_bits_T_104 = or(_out_0_a_bits_T_103, _out_0_a_bits_T_85)
node _out_0_a_bits_T_105 = or(_out_0_a_bits_T_104, _out_0_a_bits_T_86)
node _out_0_a_bits_T_106 = or(_out_0_a_bits_T_105, _out_0_a_bits_T_87)
node _out_0_a_bits_T_107 = or(_out_0_a_bits_T_106, _out_0_a_bits_T_88)
node _out_0_a_bits_T_108 = or(_out_0_a_bits_T_107, _out_0_a_bits_T_89)
node _out_0_a_bits_T_109 = or(_out_0_a_bits_T_108, _out_0_a_bits_T_90)
node _out_0_a_bits_T_110 = or(_out_0_a_bits_T_109, _out_0_a_bits_T_91)
node _out_0_a_bits_T_111 = or(_out_0_a_bits_T_110, _out_0_a_bits_T_92)
node _out_0_a_bits_T_112 = or(_out_0_a_bits_T_111, _out_0_a_bits_T_93)
node _out_0_a_bits_T_113 = or(_out_0_a_bits_T_112, _out_0_a_bits_T_94)
node _out_0_a_bits_T_114 = or(_out_0_a_bits_T_113, _out_0_a_bits_T_95)
node _out_0_a_bits_T_115 = or(_out_0_a_bits_T_114, _out_0_a_bits_T_96)
node _out_0_a_bits_T_116 = or(_out_0_a_bits_T_115, _out_0_a_bits_T_97)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_116
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_117 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_118 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_119 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_120 = mux(muxState[3], portsAOI_filtered_3[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_121 = mux(muxState[4], portsAOI_filtered_4[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_122 = mux(muxState[5], portsAOI_filtered_5[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_123 = mux(muxState[6], portsAOI_filtered_6[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_124 = mux(muxState[7], portsAOI_filtered_7[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_125 = mux(muxState[8], portsAOI_filtered_8[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_126 = mux(muxState[9], portsAOI_filtered_9[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_127 = mux(muxState[10], portsAOI_filtered_10[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_128 = mux(muxState[11], portsAOI_filtered_11[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_129 = mux(muxState[12], portsAOI_filtered_12[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_130 = mux(muxState[13], portsAOI_filtered_13[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_131 = mux(muxState[14], portsAOI_filtered_14[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_132 = mux(muxState[15], portsAOI_filtered_15[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_133 = mux(muxState[16], portsAOI_filtered_16[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_134 = mux(muxState[17], portsAOI_filtered_17[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_135 = mux(muxState[18], portsAOI_filtered_18[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_136 = mux(muxState[19], portsAOI_filtered_19[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_137 = or(_out_0_a_bits_T_117, _out_0_a_bits_T_118)
node _out_0_a_bits_T_138 = or(_out_0_a_bits_T_137, _out_0_a_bits_T_119)
node _out_0_a_bits_T_139 = or(_out_0_a_bits_T_138, _out_0_a_bits_T_120)
node _out_0_a_bits_T_140 = or(_out_0_a_bits_T_139, _out_0_a_bits_T_121)
node _out_0_a_bits_T_141 = or(_out_0_a_bits_T_140, _out_0_a_bits_T_122)
node _out_0_a_bits_T_142 = or(_out_0_a_bits_T_141, _out_0_a_bits_T_123)
node _out_0_a_bits_T_143 = or(_out_0_a_bits_T_142, _out_0_a_bits_T_124)
node _out_0_a_bits_T_144 = or(_out_0_a_bits_T_143, _out_0_a_bits_T_125)
node _out_0_a_bits_T_145 = or(_out_0_a_bits_T_144, _out_0_a_bits_T_126)
node _out_0_a_bits_T_146 = or(_out_0_a_bits_T_145, _out_0_a_bits_T_127)
node _out_0_a_bits_T_147 = or(_out_0_a_bits_T_146, _out_0_a_bits_T_128)
node _out_0_a_bits_T_148 = or(_out_0_a_bits_T_147, _out_0_a_bits_T_129)
node _out_0_a_bits_T_149 = or(_out_0_a_bits_T_148, _out_0_a_bits_T_130)
node _out_0_a_bits_T_150 = or(_out_0_a_bits_T_149, _out_0_a_bits_T_131)
node _out_0_a_bits_T_151 = or(_out_0_a_bits_T_150, _out_0_a_bits_T_132)
node _out_0_a_bits_T_152 = or(_out_0_a_bits_T_151, _out_0_a_bits_T_133)
node _out_0_a_bits_T_153 = or(_out_0_a_bits_T_152, _out_0_a_bits_T_134)
node _out_0_a_bits_T_154 = or(_out_0_a_bits_T_153, _out_0_a_bits_T_135)
node _out_0_a_bits_T_155 = or(_out_0_a_bits_T_154, _out_0_a_bits_T_136)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_155
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_156 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_157 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_158 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_159 = mux(muxState[3], portsAOI_filtered_3[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_160 = mux(muxState[4], portsAOI_filtered_4[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_161 = mux(muxState[5], portsAOI_filtered_5[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_162 = mux(muxState[6], portsAOI_filtered_6[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_163 = mux(muxState[7], portsAOI_filtered_7[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_164 = mux(muxState[8], portsAOI_filtered_8[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_165 = mux(muxState[9], portsAOI_filtered_9[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_166 = mux(muxState[10], portsAOI_filtered_10[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_167 = mux(muxState[11], portsAOI_filtered_11[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_168 = mux(muxState[12], portsAOI_filtered_12[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_169 = mux(muxState[13], portsAOI_filtered_13[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_170 = mux(muxState[14], portsAOI_filtered_14[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_171 = mux(muxState[15], portsAOI_filtered_15[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_172 = mux(muxState[16], portsAOI_filtered_16[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_173 = mux(muxState[17], portsAOI_filtered_17[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_174 = mux(muxState[18], portsAOI_filtered_18[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_175 = mux(muxState[19], portsAOI_filtered_19[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_176 = or(_out_0_a_bits_T_156, _out_0_a_bits_T_157)
node _out_0_a_bits_T_177 = or(_out_0_a_bits_T_176, _out_0_a_bits_T_158)
node _out_0_a_bits_T_178 = or(_out_0_a_bits_T_177, _out_0_a_bits_T_159)
node _out_0_a_bits_T_179 = or(_out_0_a_bits_T_178, _out_0_a_bits_T_160)
node _out_0_a_bits_T_180 = or(_out_0_a_bits_T_179, _out_0_a_bits_T_161)
node _out_0_a_bits_T_181 = or(_out_0_a_bits_T_180, _out_0_a_bits_T_162)
node _out_0_a_bits_T_182 = or(_out_0_a_bits_T_181, _out_0_a_bits_T_163)
node _out_0_a_bits_T_183 = or(_out_0_a_bits_T_182, _out_0_a_bits_T_164)
node _out_0_a_bits_T_184 = or(_out_0_a_bits_T_183, _out_0_a_bits_T_165)
node _out_0_a_bits_T_185 = or(_out_0_a_bits_T_184, _out_0_a_bits_T_166)
node _out_0_a_bits_T_186 = or(_out_0_a_bits_T_185, _out_0_a_bits_T_167)
node _out_0_a_bits_T_187 = or(_out_0_a_bits_T_186, _out_0_a_bits_T_168)
node _out_0_a_bits_T_188 = or(_out_0_a_bits_T_187, _out_0_a_bits_T_169)
node _out_0_a_bits_T_189 = or(_out_0_a_bits_T_188, _out_0_a_bits_T_170)
node _out_0_a_bits_T_190 = or(_out_0_a_bits_T_189, _out_0_a_bits_T_171)
node _out_0_a_bits_T_191 = or(_out_0_a_bits_T_190, _out_0_a_bits_T_172)
node _out_0_a_bits_T_192 = or(_out_0_a_bits_T_191, _out_0_a_bits_T_173)
node _out_0_a_bits_T_193 = or(_out_0_a_bits_T_192, _out_0_a_bits_T_174)
node _out_0_a_bits_T_194 = or(_out_0_a_bits_T_193, _out_0_a_bits_T_175)
wire _out_0_a_bits_WIRE_7 : UInt<9>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_194
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_195 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_196 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_197 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_198 = mux(muxState[3], portsAOI_filtered_3[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_199 = mux(muxState[4], portsAOI_filtered_4[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_200 = mux(muxState[5], portsAOI_filtered_5[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_201 = mux(muxState[6], portsAOI_filtered_6[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_202 = mux(muxState[7], portsAOI_filtered_7[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_203 = mux(muxState[8], portsAOI_filtered_8[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_204 = mux(muxState[9], portsAOI_filtered_9[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_205 = mux(muxState[10], portsAOI_filtered_10[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_206 = mux(muxState[11], portsAOI_filtered_11[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_207 = mux(muxState[12], portsAOI_filtered_12[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_208 = mux(muxState[13], portsAOI_filtered_13[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_209 = mux(muxState[14], portsAOI_filtered_14[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_210 = mux(muxState[15], portsAOI_filtered_15[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_211 = mux(muxState[16], portsAOI_filtered_16[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_212 = mux(muxState[17], portsAOI_filtered_17[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_213 = mux(muxState[18], portsAOI_filtered_18[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_214 = mux(muxState[19], portsAOI_filtered_19[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_215 = or(_out_0_a_bits_T_195, _out_0_a_bits_T_196)
node _out_0_a_bits_T_216 = or(_out_0_a_bits_T_215, _out_0_a_bits_T_197)
node _out_0_a_bits_T_217 = or(_out_0_a_bits_T_216, _out_0_a_bits_T_198)
node _out_0_a_bits_T_218 = or(_out_0_a_bits_T_217, _out_0_a_bits_T_199)
node _out_0_a_bits_T_219 = or(_out_0_a_bits_T_218, _out_0_a_bits_T_200)
node _out_0_a_bits_T_220 = or(_out_0_a_bits_T_219, _out_0_a_bits_T_201)
node _out_0_a_bits_T_221 = or(_out_0_a_bits_T_220, _out_0_a_bits_T_202)
node _out_0_a_bits_T_222 = or(_out_0_a_bits_T_221, _out_0_a_bits_T_203)
node _out_0_a_bits_T_223 = or(_out_0_a_bits_T_222, _out_0_a_bits_T_204)
node _out_0_a_bits_T_224 = or(_out_0_a_bits_T_223, _out_0_a_bits_T_205)
node _out_0_a_bits_T_225 = or(_out_0_a_bits_T_224, _out_0_a_bits_T_206)
node _out_0_a_bits_T_226 = or(_out_0_a_bits_T_225, _out_0_a_bits_T_207)
node _out_0_a_bits_T_227 = or(_out_0_a_bits_T_226, _out_0_a_bits_T_208)
node _out_0_a_bits_T_228 = or(_out_0_a_bits_T_227, _out_0_a_bits_T_209)
node _out_0_a_bits_T_229 = or(_out_0_a_bits_T_228, _out_0_a_bits_T_210)
node _out_0_a_bits_T_230 = or(_out_0_a_bits_T_229, _out_0_a_bits_T_211)
node _out_0_a_bits_T_231 = or(_out_0_a_bits_T_230, _out_0_a_bits_T_212)
node _out_0_a_bits_T_232 = or(_out_0_a_bits_T_231, _out_0_a_bits_T_213)
node _out_0_a_bits_T_233 = or(_out_0_a_bits_T_232, _out_0_a_bits_T_214)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_233
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_234 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_235 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_236 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_237 = mux(muxState[3], portsAOI_filtered_3[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_238 = mux(muxState[4], portsAOI_filtered_4[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_239 = mux(muxState[5], portsAOI_filtered_5[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_240 = mux(muxState[6], portsAOI_filtered_6[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_241 = mux(muxState[7], portsAOI_filtered_7[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_242 = mux(muxState[8], portsAOI_filtered_8[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_243 = mux(muxState[9], portsAOI_filtered_9[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_244 = mux(muxState[10], portsAOI_filtered_10[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_245 = mux(muxState[11], portsAOI_filtered_11[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_246 = mux(muxState[12], portsAOI_filtered_12[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_247 = mux(muxState[13], portsAOI_filtered_13[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_248 = mux(muxState[14], portsAOI_filtered_14[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_249 = mux(muxState[15], portsAOI_filtered_15[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_250 = mux(muxState[16], portsAOI_filtered_16[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_251 = mux(muxState[17], portsAOI_filtered_17[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_252 = mux(muxState[18], portsAOI_filtered_18[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_253 = mux(muxState[19], portsAOI_filtered_19[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_254 = or(_out_0_a_bits_T_234, _out_0_a_bits_T_235)
node _out_0_a_bits_T_255 = or(_out_0_a_bits_T_254, _out_0_a_bits_T_236)
node _out_0_a_bits_T_256 = or(_out_0_a_bits_T_255, _out_0_a_bits_T_237)
node _out_0_a_bits_T_257 = or(_out_0_a_bits_T_256, _out_0_a_bits_T_238)
node _out_0_a_bits_T_258 = or(_out_0_a_bits_T_257, _out_0_a_bits_T_239)
node _out_0_a_bits_T_259 = or(_out_0_a_bits_T_258, _out_0_a_bits_T_240)
node _out_0_a_bits_T_260 = or(_out_0_a_bits_T_259, _out_0_a_bits_T_241)
node _out_0_a_bits_T_261 = or(_out_0_a_bits_T_260, _out_0_a_bits_T_242)
node _out_0_a_bits_T_262 = or(_out_0_a_bits_T_261, _out_0_a_bits_T_243)
node _out_0_a_bits_T_263 = or(_out_0_a_bits_T_262, _out_0_a_bits_T_244)
node _out_0_a_bits_T_264 = or(_out_0_a_bits_T_263, _out_0_a_bits_T_245)
node _out_0_a_bits_T_265 = or(_out_0_a_bits_T_264, _out_0_a_bits_T_246)
node _out_0_a_bits_T_266 = or(_out_0_a_bits_T_265, _out_0_a_bits_T_247)
node _out_0_a_bits_T_267 = or(_out_0_a_bits_T_266, _out_0_a_bits_T_248)
node _out_0_a_bits_T_268 = or(_out_0_a_bits_T_267, _out_0_a_bits_T_249)
node _out_0_a_bits_T_269 = or(_out_0_a_bits_T_268, _out_0_a_bits_T_250)
node _out_0_a_bits_T_270 = or(_out_0_a_bits_T_269, _out_0_a_bits_T_251)
node _out_0_a_bits_T_271 = or(_out_0_a_bits_T_270, _out_0_a_bits_T_252)
node _out_0_a_bits_T_272 = or(_out_0_a_bits_T_271, _out_0_a_bits_T_253)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_272
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_273 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_274 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_275 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_276 = mux(muxState[3], portsAOI_filtered_3[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_277 = mux(muxState[4], portsAOI_filtered_4[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_278 = mux(muxState[5], portsAOI_filtered_5[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_279 = mux(muxState[6], portsAOI_filtered_6[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_280 = mux(muxState[7], portsAOI_filtered_7[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_281 = mux(muxState[8], portsAOI_filtered_8[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_282 = mux(muxState[9], portsAOI_filtered_9[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_283 = mux(muxState[10], portsAOI_filtered_10[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_284 = mux(muxState[11], portsAOI_filtered_11[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_285 = mux(muxState[12], portsAOI_filtered_12[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_286 = mux(muxState[13], portsAOI_filtered_13[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_287 = mux(muxState[14], portsAOI_filtered_14[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_288 = mux(muxState[15], portsAOI_filtered_15[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_289 = mux(muxState[16], portsAOI_filtered_16[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_290 = mux(muxState[17], portsAOI_filtered_17[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_291 = mux(muxState[18], portsAOI_filtered_18[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_292 = mux(muxState[19], portsAOI_filtered_19[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_293 = or(_out_0_a_bits_T_273, _out_0_a_bits_T_274)
node _out_0_a_bits_T_294 = or(_out_0_a_bits_T_293, _out_0_a_bits_T_275)
node _out_0_a_bits_T_295 = or(_out_0_a_bits_T_294, _out_0_a_bits_T_276)
node _out_0_a_bits_T_296 = or(_out_0_a_bits_T_295, _out_0_a_bits_T_277)
node _out_0_a_bits_T_297 = or(_out_0_a_bits_T_296, _out_0_a_bits_T_278)
node _out_0_a_bits_T_298 = or(_out_0_a_bits_T_297, _out_0_a_bits_T_279)
node _out_0_a_bits_T_299 = or(_out_0_a_bits_T_298, _out_0_a_bits_T_280)
node _out_0_a_bits_T_300 = or(_out_0_a_bits_T_299, _out_0_a_bits_T_281)
node _out_0_a_bits_T_301 = or(_out_0_a_bits_T_300, _out_0_a_bits_T_282)
node _out_0_a_bits_T_302 = or(_out_0_a_bits_T_301, _out_0_a_bits_T_283)
node _out_0_a_bits_T_303 = or(_out_0_a_bits_T_302, _out_0_a_bits_T_284)
node _out_0_a_bits_T_304 = or(_out_0_a_bits_T_303, _out_0_a_bits_T_285)
node _out_0_a_bits_T_305 = or(_out_0_a_bits_T_304, _out_0_a_bits_T_286)
node _out_0_a_bits_T_306 = or(_out_0_a_bits_T_305, _out_0_a_bits_T_287)
node _out_0_a_bits_T_307 = or(_out_0_a_bits_T_306, _out_0_a_bits_T_288)
node _out_0_a_bits_T_308 = or(_out_0_a_bits_T_307, _out_0_a_bits_T_289)
node _out_0_a_bits_T_309 = or(_out_0_a_bits_T_308, _out_0_a_bits_T_290)
node _out_0_a_bits_T_310 = or(_out_0_a_bits_T_309, _out_0_a_bits_T_291)
node _out_0_a_bits_T_311 = or(_out_0_a_bits_T_310, _out_0_a_bits_T_292)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_311
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
invalidate out[0].c.bits.corrupt
invalidate out[0].c.bits.data
invalidate out[0].c.bits.address
invalidate out[0].c.bits.source
invalidate out[0].c.bits.size
invalidate out[0].c.bits.param
invalidate out[0].c.bits.opcode
invalidate out[0].e.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_3[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_4[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_5[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_6[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_7[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_8[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_9[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_10[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_11[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_12[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_13[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_14[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_15[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_16[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_17[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_18[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_19[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_3[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_4[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_5[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_6[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_7[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_8[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_9[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_10[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_11[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_12[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_13[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_14[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_15[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_16[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_17[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_18[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_19[0].ready, UInt<1>(0h0)
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, out[1].a.ready)
node readys_lo_lo_lo_1 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid)
node readys_lo_lo_hi_hi_1 = cat(portsAOI_filtered_4[1].valid, portsAOI_filtered_3[1].valid)
node readys_lo_lo_hi_1 = cat(readys_lo_lo_hi_hi_1, portsAOI_filtered_2[1].valid)
node readys_lo_lo_1 = cat(readys_lo_lo_hi_1, readys_lo_lo_lo_1)
node readys_lo_hi_lo_1 = cat(portsAOI_filtered_6[1].valid, portsAOI_filtered_5[1].valid)
node readys_lo_hi_hi_hi_1 = cat(portsAOI_filtered_9[1].valid, portsAOI_filtered_8[1].valid)
node readys_lo_hi_hi_1 = cat(readys_lo_hi_hi_hi_1, portsAOI_filtered_7[1].valid)
node readys_lo_hi_1 = cat(readys_lo_hi_hi_1, readys_lo_hi_lo_1)
node readys_lo_1 = cat(readys_lo_hi_1, readys_lo_lo_1)
node readys_hi_lo_lo_1 = cat(portsAOI_filtered_11[1].valid, portsAOI_filtered_10[1].valid)
node readys_hi_lo_hi_hi_1 = cat(portsAOI_filtered_14[1].valid, portsAOI_filtered_13[1].valid)
node readys_hi_lo_hi_1 = cat(readys_hi_lo_hi_hi_1, portsAOI_filtered_12[1].valid)
node readys_hi_lo_1 = cat(readys_hi_lo_hi_1, readys_hi_lo_lo_1)
node readys_hi_hi_lo_1 = cat(portsAOI_filtered_16[1].valid, portsAOI_filtered_15[1].valid)
node readys_hi_hi_hi_hi_1 = cat(portsAOI_filtered_19[1].valid, portsAOI_filtered_18[1].valid)
node readys_hi_hi_hi_1 = cat(readys_hi_hi_hi_hi_1, portsAOI_filtered_17[1].valid)
node readys_hi_hi_1 = cat(readys_hi_hi_hi_1, readys_hi_hi_lo_1)
node readys_hi_1 = cat(readys_hi_hi_1, readys_hi_lo_1)
node _readys_T_28 = cat(readys_hi_1, readys_lo_1)
node readys_valid_1 = bits(_readys_T_28, 19, 0)
node _readys_T_29 = eq(readys_valid_1, _readys_T_28)
node _readys_T_30 = asUInt(reset)
node _readys_T_31 = eq(_readys_T_30, UInt<1>(0h0))
when _readys_T_31 :
node _readys_T_32 = eq(_readys_T_29, UInt<1>(0h0))
when _readys_T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1
assert(clock, _readys_T_29, UInt<1>(0h1), "") : readys_assert_1
regreset readys_mask_1 : UInt<20>, clock, reset, UInt<20>(0hfffff)
node _readys_filter_T_2 = not(readys_mask_1)
node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2)
node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1)
node _readys_unready_T_13 = shr(readys_filter_1, 1)
node _readys_unready_T_14 = or(readys_filter_1, _readys_unready_T_13)
node _readys_unready_T_15 = shr(_readys_unready_T_14, 2)
node _readys_unready_T_16 = or(_readys_unready_T_14, _readys_unready_T_15)
node _readys_unready_T_17 = shr(_readys_unready_T_16, 4)
node _readys_unready_T_18 = or(_readys_unready_T_16, _readys_unready_T_17)
node _readys_unready_T_19 = shr(_readys_unready_T_18, 8)
node _readys_unready_T_20 = or(_readys_unready_T_18, _readys_unready_T_19)
node _readys_unready_T_21 = shr(_readys_unready_T_20, 16)
node _readys_unready_T_22 = or(_readys_unready_T_20, _readys_unready_T_21)
node _readys_unready_T_23 = bits(_readys_unready_T_22, 39, 0)
node _readys_unready_T_24 = shr(_readys_unready_T_23, 1)
node _readys_unready_T_25 = shl(readys_mask_1, 20)
node readys_unready_1 = or(_readys_unready_T_24, _readys_unready_T_25)
node _readys_readys_T_3 = shr(readys_unready_1, 20)
node _readys_readys_T_4 = bits(readys_unready_1, 19, 0)
node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4)
node readys_readys_1 = not(_readys_readys_T_5)
node _readys_T_33 = orr(readys_valid_1)
node _readys_T_34 = and(latch_1, _readys_T_33)
when _readys_T_34 :
node _readys_mask_T_17 = and(readys_readys_1, readys_valid_1)
node _readys_mask_T_18 = shl(_readys_mask_T_17, 1)
node _readys_mask_T_19 = bits(_readys_mask_T_18, 19, 0)
node _readys_mask_T_20 = or(_readys_mask_T_17, _readys_mask_T_19)
node _readys_mask_T_21 = shl(_readys_mask_T_20, 2)
node _readys_mask_T_22 = bits(_readys_mask_T_21, 19, 0)
node _readys_mask_T_23 = or(_readys_mask_T_20, _readys_mask_T_22)
node _readys_mask_T_24 = shl(_readys_mask_T_23, 4)
node _readys_mask_T_25 = bits(_readys_mask_T_24, 19, 0)
node _readys_mask_T_26 = or(_readys_mask_T_23, _readys_mask_T_25)
node _readys_mask_T_27 = shl(_readys_mask_T_26, 8)
node _readys_mask_T_28 = bits(_readys_mask_T_27, 19, 0)
node _readys_mask_T_29 = or(_readys_mask_T_26, _readys_mask_T_28)
node _readys_mask_T_30 = shl(_readys_mask_T_29, 16)
node _readys_mask_T_31 = bits(_readys_mask_T_30, 19, 0)
node _readys_mask_T_32 = or(_readys_mask_T_29, _readys_mask_T_31)
node _readys_mask_T_33 = bits(_readys_mask_T_32, 19, 0)
connect readys_mask_1, _readys_mask_T_33
node _readys_T_35 = bits(readys_readys_1, 19, 0)
node _readys_T_36 = bits(_readys_T_35, 0, 0)
node _readys_T_37 = bits(_readys_T_35, 1, 1)
node _readys_T_38 = bits(_readys_T_35, 2, 2)
node _readys_T_39 = bits(_readys_T_35, 3, 3)
node _readys_T_40 = bits(_readys_T_35, 4, 4)
node _readys_T_41 = bits(_readys_T_35, 5, 5)
node _readys_T_42 = bits(_readys_T_35, 6, 6)
node _readys_T_43 = bits(_readys_T_35, 7, 7)
node _readys_T_44 = bits(_readys_T_35, 8, 8)
node _readys_T_45 = bits(_readys_T_35, 9, 9)
node _readys_T_46 = bits(_readys_T_35, 10, 10)
node _readys_T_47 = bits(_readys_T_35, 11, 11)
node _readys_T_48 = bits(_readys_T_35, 12, 12)
node _readys_T_49 = bits(_readys_T_35, 13, 13)
node _readys_T_50 = bits(_readys_T_35, 14, 14)
node _readys_T_51 = bits(_readys_T_35, 15, 15)
node _readys_T_52 = bits(_readys_T_35, 16, 16)
node _readys_T_53 = bits(_readys_T_35, 17, 17)
node _readys_T_54 = bits(_readys_T_35, 18, 18)
node _readys_T_55 = bits(_readys_T_35, 19, 19)
wire readys_1 : UInt<1>[20]
connect readys_1[0], _readys_T_36
connect readys_1[1], _readys_T_37
connect readys_1[2], _readys_T_38
connect readys_1[3], _readys_T_39
connect readys_1[4], _readys_T_40
connect readys_1[5], _readys_T_41
connect readys_1[6], _readys_T_42
connect readys_1[7], _readys_T_43
connect readys_1[8], _readys_T_44
connect readys_1[9], _readys_T_45
connect readys_1[10], _readys_T_46
connect readys_1[11], _readys_T_47
connect readys_1[12], _readys_T_48
connect readys_1[13], _readys_T_49
connect readys_1[14], _readys_T_50
connect readys_1[15], _readys_T_51
connect readys_1[16], _readys_T_52
connect readys_1[17], _readys_T_53
connect readys_1[18], _readys_T_54
connect readys_1[19], _readys_T_55
node _winner_T_20 = and(readys_1[0], portsAOI_filtered[1].valid)
node _winner_T_21 = and(readys_1[1], portsAOI_filtered_1[1].valid)
node _winner_T_22 = and(readys_1[2], portsAOI_filtered_2[1].valid)
node _winner_T_23 = and(readys_1[3], portsAOI_filtered_3[1].valid)
node _winner_T_24 = and(readys_1[4], portsAOI_filtered_4[1].valid)
node _winner_T_25 = and(readys_1[5], portsAOI_filtered_5[1].valid)
node _winner_T_26 = and(readys_1[6], portsAOI_filtered_6[1].valid)
node _winner_T_27 = and(readys_1[7], portsAOI_filtered_7[1].valid)
node _winner_T_28 = and(readys_1[8], portsAOI_filtered_8[1].valid)
node _winner_T_29 = and(readys_1[9], portsAOI_filtered_9[1].valid)
node _winner_T_30 = and(readys_1[10], portsAOI_filtered_10[1].valid)
node _winner_T_31 = and(readys_1[11], portsAOI_filtered_11[1].valid)
node _winner_T_32 = and(readys_1[12], portsAOI_filtered_12[1].valid)
node _winner_T_33 = and(readys_1[13], portsAOI_filtered_13[1].valid)
node _winner_T_34 = and(readys_1[14], portsAOI_filtered_14[1].valid)
node _winner_T_35 = and(readys_1[15], portsAOI_filtered_15[1].valid)
node _winner_T_36 = and(readys_1[16], portsAOI_filtered_16[1].valid)
node _winner_T_37 = and(readys_1[17], portsAOI_filtered_17[1].valid)
node _winner_T_38 = and(readys_1[18], portsAOI_filtered_18[1].valid)
node _winner_T_39 = and(readys_1[19], portsAOI_filtered_19[1].valid)
wire winner_1 : UInt<1>[20]
connect winner_1[0], _winner_T_20
connect winner_1[1], _winner_T_21
connect winner_1[2], _winner_T_22
connect winner_1[3], _winner_T_23
connect winner_1[4], _winner_T_24
connect winner_1[5], _winner_T_25
connect winner_1[6], _winner_T_26
connect winner_1[7], _winner_T_27
connect winner_1[8], _winner_T_28
connect winner_1[9], _winner_T_29
connect winner_1[10], _winner_T_30
connect winner_1[11], _winner_T_31
connect winner_1[12], _winner_T_32
connect winner_1[13], _winner_T_33
connect winner_1[14], _winner_T_34
connect winner_1[15], _winner_T_35
connect winner_1[16], _winner_T_36
connect winner_1[17], _winner_T_37
connect winner_1[18], _winner_T_38
connect winner_1[19], _winner_T_39
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node prefixOR_2_1 = or(prefixOR_1_1, winner_1[1])
node prefixOR_3_1 = or(prefixOR_2_1, winner_1[2])
node prefixOR_4_1 = or(prefixOR_3_1, winner_1[3])
node prefixOR_5_1 = or(prefixOR_4_1, winner_1[4])
node prefixOR_6_1 = or(prefixOR_5_1, winner_1[5])
node prefixOR_7_1 = or(prefixOR_6_1, winner_1[6])
node prefixOR_8_1 = or(prefixOR_7_1, winner_1[7])
node prefixOR_9_1 = or(prefixOR_8_1, winner_1[8])
node prefixOR_10_1 = or(prefixOR_9_1, winner_1[9])
node prefixOR_11_1 = or(prefixOR_10_1, winner_1[10])
node prefixOR_12_1 = or(prefixOR_11_1, winner_1[11])
node prefixOR_13_1 = or(prefixOR_12_1, winner_1[12])
node prefixOR_14_1 = or(prefixOR_13_1, winner_1[13])
node prefixOR_15_1 = or(prefixOR_14_1, winner_1[14])
node prefixOR_16_1 = or(prefixOR_15_1, winner_1[15])
node prefixOR_17_1 = or(prefixOR_16_1, winner_1[16])
node prefixOR_18_1 = or(prefixOR_17_1, winner_1[17])
node prefixOR_19_1 = or(prefixOR_18_1, winner_1[18])
node _prefixOR_T_1 = or(prefixOR_19_1, winner_1[19])
node _T_125 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_126 = eq(winner_1[0], UInt<1>(0h0))
node _T_127 = or(_T_125, _T_126)
node _T_128 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_129 = eq(winner_1[1], UInt<1>(0h0))
node _T_130 = or(_T_128, _T_129)
node _T_131 = eq(prefixOR_2_1, UInt<1>(0h0))
node _T_132 = eq(winner_1[2], UInt<1>(0h0))
node _T_133 = or(_T_131, _T_132)
node _T_134 = eq(prefixOR_3_1, UInt<1>(0h0))
node _T_135 = eq(winner_1[3], UInt<1>(0h0))
node _T_136 = or(_T_134, _T_135)
node _T_137 = eq(prefixOR_4_1, UInt<1>(0h0))
node _T_138 = eq(winner_1[4], UInt<1>(0h0))
node _T_139 = or(_T_137, _T_138)
node _T_140 = eq(prefixOR_5_1, UInt<1>(0h0))
node _T_141 = eq(winner_1[5], UInt<1>(0h0))
node _T_142 = or(_T_140, _T_141)
node _T_143 = eq(prefixOR_6_1, UInt<1>(0h0))
node _T_144 = eq(winner_1[6], UInt<1>(0h0))
node _T_145 = or(_T_143, _T_144)
node _T_146 = eq(prefixOR_7_1, UInt<1>(0h0))
node _T_147 = eq(winner_1[7], UInt<1>(0h0))
node _T_148 = or(_T_146, _T_147)
node _T_149 = eq(prefixOR_8_1, UInt<1>(0h0))
node _T_150 = eq(winner_1[8], UInt<1>(0h0))
node _T_151 = or(_T_149, _T_150)
node _T_152 = eq(prefixOR_9_1, UInt<1>(0h0))
node _T_153 = eq(winner_1[9], UInt<1>(0h0))
node _T_154 = or(_T_152, _T_153)
node _T_155 = eq(prefixOR_10_1, UInt<1>(0h0))
node _T_156 = eq(winner_1[10], UInt<1>(0h0))
node _T_157 = or(_T_155, _T_156)
node _T_158 = eq(prefixOR_11_1, UInt<1>(0h0))
node _T_159 = eq(winner_1[11], UInt<1>(0h0))
node _T_160 = or(_T_158, _T_159)
node _T_161 = eq(prefixOR_12_1, UInt<1>(0h0))
node _T_162 = eq(winner_1[12], UInt<1>(0h0))
node _T_163 = or(_T_161, _T_162)
node _T_164 = eq(prefixOR_13_1, UInt<1>(0h0))
node _T_165 = eq(winner_1[13], UInt<1>(0h0))
node _T_166 = or(_T_164, _T_165)
node _T_167 = eq(prefixOR_14_1, UInt<1>(0h0))
node _T_168 = eq(winner_1[14], UInt<1>(0h0))
node _T_169 = or(_T_167, _T_168)
node _T_170 = eq(prefixOR_15_1, UInt<1>(0h0))
node _T_171 = eq(winner_1[15], UInt<1>(0h0))
node _T_172 = or(_T_170, _T_171)
node _T_173 = eq(prefixOR_16_1, UInt<1>(0h0))
node _T_174 = eq(winner_1[16], UInt<1>(0h0))
node _T_175 = or(_T_173, _T_174)
node _T_176 = eq(prefixOR_17_1, UInt<1>(0h0))
node _T_177 = eq(winner_1[17], UInt<1>(0h0))
node _T_178 = or(_T_176, _T_177)
node _T_179 = eq(prefixOR_18_1, UInt<1>(0h0))
node _T_180 = eq(winner_1[18], UInt<1>(0h0))
node _T_181 = or(_T_179, _T_180)
node _T_182 = eq(prefixOR_19_1, UInt<1>(0h0))
node _T_183 = eq(winner_1[19], UInt<1>(0h0))
node _T_184 = or(_T_182, _T_183)
node _T_185 = and(_T_127, _T_130)
node _T_186 = and(_T_185, _T_133)
node _T_187 = and(_T_186, _T_136)
node _T_188 = and(_T_187, _T_139)
node _T_189 = and(_T_188, _T_142)
node _T_190 = and(_T_189, _T_145)
node _T_191 = and(_T_190, _T_148)
node _T_192 = and(_T_191, _T_151)
node _T_193 = and(_T_192, _T_154)
node _T_194 = and(_T_193, _T_157)
node _T_195 = and(_T_194, _T_160)
node _T_196 = and(_T_195, _T_163)
node _T_197 = and(_T_196, _T_166)
node _T_198 = and(_T_197, _T_169)
node _T_199 = and(_T_198, _T_172)
node _T_200 = and(_T_199, _T_175)
node _T_201 = and(_T_200, _T_178)
node _T_202 = and(_T_201, _T_181)
node _T_203 = and(_T_202, _T_184)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_203, UInt<1>(0h1), "") : assert_2
node _T_207 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _T_208 = or(_T_207, portsAOI_filtered_2[1].valid)
node _T_209 = or(_T_208, portsAOI_filtered_3[1].valid)
node _T_210 = or(_T_209, portsAOI_filtered_4[1].valid)
node _T_211 = or(_T_210, portsAOI_filtered_5[1].valid)
node _T_212 = or(_T_211, portsAOI_filtered_6[1].valid)
node _T_213 = or(_T_212, portsAOI_filtered_7[1].valid)
node _T_214 = or(_T_213, portsAOI_filtered_8[1].valid)
node _T_215 = or(_T_214, portsAOI_filtered_9[1].valid)
node _T_216 = or(_T_215, portsAOI_filtered_10[1].valid)
node _T_217 = or(_T_216, portsAOI_filtered_11[1].valid)
node _T_218 = or(_T_217, portsAOI_filtered_12[1].valid)
node _T_219 = or(_T_218, portsAOI_filtered_13[1].valid)
node _T_220 = or(_T_219, portsAOI_filtered_14[1].valid)
node _T_221 = or(_T_220, portsAOI_filtered_15[1].valid)
node _T_222 = or(_T_221, portsAOI_filtered_16[1].valid)
node _T_223 = or(_T_222, portsAOI_filtered_17[1].valid)
node _T_224 = or(_T_223, portsAOI_filtered_18[1].valid)
node _T_225 = or(_T_224, portsAOI_filtered_19[1].valid)
node _T_226 = eq(_T_225, UInt<1>(0h0))
node _T_227 = or(winner_1[0], winner_1[1])
node _T_228 = or(_T_227, winner_1[2])
node _T_229 = or(_T_228, winner_1[3])
node _T_230 = or(_T_229, winner_1[4])
node _T_231 = or(_T_230, winner_1[5])
node _T_232 = or(_T_231, winner_1[6])
node _T_233 = or(_T_232, winner_1[7])
node _T_234 = or(_T_233, winner_1[8])
node _T_235 = or(_T_234, winner_1[9])
node _T_236 = or(_T_235, winner_1[10])
node _T_237 = or(_T_236, winner_1[11])
node _T_238 = or(_T_237, winner_1[12])
node _T_239 = or(_T_238, winner_1[13])
node _T_240 = or(_T_239, winner_1[14])
node _T_241 = or(_T_240, winner_1[15])
node _T_242 = or(_T_241, winner_1[16])
node _T_243 = or(_T_242, winner_1[17])
node _T_244 = or(_T_243, winner_1[18])
node _T_245 = or(_T_244, winner_1[19])
node _T_246 = or(_T_226, _T_245)
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_246, UInt<1>(0h1), "") : assert_3
node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2_1 = mux(winner_1[2], beatsAI_2, UInt<1>(0h0))
node maskedBeats_3_1 = mux(winner_1[3], beatsAI_3, UInt<1>(0h0))
node maskedBeats_4_1 = mux(winner_1[4], beatsAI_4, UInt<1>(0h0))
node maskedBeats_5_1 = mux(winner_1[5], beatsAI_5, UInt<1>(0h0))
node maskedBeats_6_1 = mux(winner_1[6], beatsAI_6, UInt<1>(0h0))
node maskedBeats_7_1 = mux(winner_1[7], beatsAI_7, UInt<1>(0h0))
node maskedBeats_8_1 = mux(winner_1[8], beatsAI_8, UInt<1>(0h0))
node maskedBeats_9_1 = mux(winner_1[9], beatsAI_9, UInt<1>(0h0))
node maskedBeats_10_1 = mux(winner_1[10], beatsAI_10, UInt<1>(0h0))
node maskedBeats_11_1 = mux(winner_1[11], beatsAI_11, UInt<1>(0h0))
node maskedBeats_12_1 = mux(winner_1[12], beatsAI_12, UInt<1>(0h0))
node maskedBeats_13_1 = mux(winner_1[13], beatsAI_13, UInt<1>(0h0))
node maskedBeats_14_1 = mux(winner_1[14], beatsAI_14, UInt<1>(0h0))
node maskedBeats_15_1 = mux(winner_1[15], beatsAI_15, UInt<1>(0h0))
node maskedBeats_16_1 = mux(winner_1[16], beatsAI_16, UInt<1>(0h0))
node maskedBeats_17_1 = mux(winner_1[17], beatsAI_17, UInt<1>(0h0))
node maskedBeats_18_1 = mux(winner_1[18], beatsAI_18, UInt<1>(0h0))
node maskedBeats_19_1 = mux(winner_1[19], beatsAI_19, UInt<1>(0h0))
node _initBeats_T_18 = or(maskedBeats_0_1, maskedBeats_1_1)
node _initBeats_T_19 = or(_initBeats_T_18, maskedBeats_2_1)
node _initBeats_T_20 = or(_initBeats_T_19, maskedBeats_3_1)
node _initBeats_T_21 = or(_initBeats_T_20, maskedBeats_4_1)
node _initBeats_T_22 = or(_initBeats_T_21, maskedBeats_5_1)
node _initBeats_T_23 = or(_initBeats_T_22, maskedBeats_6_1)
node _initBeats_T_24 = or(_initBeats_T_23, maskedBeats_7_1)
node _initBeats_T_25 = or(_initBeats_T_24, maskedBeats_8_1)
node _initBeats_T_26 = or(_initBeats_T_25, maskedBeats_9_1)
node _initBeats_T_27 = or(_initBeats_T_26, maskedBeats_10_1)
node _initBeats_T_28 = or(_initBeats_T_27, maskedBeats_11_1)
node _initBeats_T_29 = or(_initBeats_T_28, maskedBeats_12_1)
node _initBeats_T_30 = or(_initBeats_T_29, maskedBeats_13_1)
node _initBeats_T_31 = or(_initBeats_T_30, maskedBeats_14_1)
node _initBeats_T_32 = or(_initBeats_T_31, maskedBeats_15_1)
node _initBeats_T_33 = or(_initBeats_T_32, maskedBeats_16_1)
node _initBeats_T_34 = or(_initBeats_T_33, maskedBeats_17_1)
node _initBeats_T_35 = or(_initBeats_T_34, maskedBeats_18_1)
node initBeats_1 = or(_initBeats_T_35, maskedBeats_19_1)
node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[20]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
connect _state_WIRE_1[2], UInt<1>(0h0)
connect _state_WIRE_1[3], UInt<1>(0h0)
connect _state_WIRE_1[4], UInt<1>(0h0)
connect _state_WIRE_1[5], UInt<1>(0h0)
connect _state_WIRE_1[6], UInt<1>(0h0)
connect _state_WIRE_1[7], UInt<1>(0h0)
connect _state_WIRE_1[8], UInt<1>(0h0)
connect _state_WIRE_1[9], UInt<1>(0h0)
connect _state_WIRE_1[10], UInt<1>(0h0)
connect _state_WIRE_1[11], UInt<1>(0h0)
connect _state_WIRE_1[12], UInt<1>(0h0)
connect _state_WIRE_1[13], UInt<1>(0h0)
connect _state_WIRE_1[14], UInt<1>(0h0)
connect _state_WIRE_1[15], UInt<1>(0h0)
connect _state_WIRE_1[16], UInt<1>(0h0)
connect _state_WIRE_1[17], UInt<1>(0h0)
connect _state_WIRE_1[18], UInt<1>(0h0)
connect _state_WIRE_1[19], UInt<1>(0h0)
regreset state_1 : UInt<1>[20], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0])
connect portsAOI_filtered[1].ready, _filtered_1_ready_T
node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1])
connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1
node _filtered_1_ready_T_2 = and(out[1].a.ready, allowed_1[2])
connect portsAOI_filtered_2[1].ready, _filtered_1_ready_T_2
node _filtered_1_ready_T_3 = and(out[1].a.ready, allowed_1[3])
connect portsAOI_filtered_3[1].ready, _filtered_1_ready_T_3
node _filtered_1_ready_T_4 = and(out[1].a.ready, allowed_1[4])
connect portsAOI_filtered_4[1].ready, _filtered_1_ready_T_4
node _filtered_1_ready_T_5 = and(out[1].a.ready, allowed_1[5])
connect portsAOI_filtered_5[1].ready, _filtered_1_ready_T_5
node _filtered_1_ready_T_6 = and(out[1].a.ready, allowed_1[6])
connect portsAOI_filtered_6[1].ready, _filtered_1_ready_T_6
node _filtered_1_ready_T_7 = and(out[1].a.ready, allowed_1[7])
connect portsAOI_filtered_7[1].ready, _filtered_1_ready_T_7
node _filtered_1_ready_T_8 = and(out[1].a.ready, allowed_1[8])
connect portsAOI_filtered_8[1].ready, _filtered_1_ready_T_8
node _filtered_1_ready_T_9 = and(out[1].a.ready, allowed_1[9])
connect portsAOI_filtered_9[1].ready, _filtered_1_ready_T_9
node _filtered_1_ready_T_10 = and(out[1].a.ready, allowed_1[10])
connect portsAOI_filtered_10[1].ready, _filtered_1_ready_T_10
node _filtered_1_ready_T_11 = and(out[1].a.ready, allowed_1[11])
connect portsAOI_filtered_11[1].ready, _filtered_1_ready_T_11
node _filtered_1_ready_T_12 = and(out[1].a.ready, allowed_1[12])
connect portsAOI_filtered_12[1].ready, _filtered_1_ready_T_12
node _filtered_1_ready_T_13 = and(out[1].a.ready, allowed_1[13])
connect portsAOI_filtered_13[1].ready, _filtered_1_ready_T_13
node _filtered_1_ready_T_14 = and(out[1].a.ready, allowed_1[14])
connect portsAOI_filtered_14[1].ready, _filtered_1_ready_T_14
node _filtered_1_ready_T_15 = and(out[1].a.ready, allowed_1[15])
connect portsAOI_filtered_15[1].ready, _filtered_1_ready_T_15
node _filtered_1_ready_T_16 = and(out[1].a.ready, allowed_1[16])
connect portsAOI_filtered_16[1].ready, _filtered_1_ready_T_16
node _filtered_1_ready_T_17 = and(out[1].a.ready, allowed_1[17])
connect portsAOI_filtered_17[1].ready, _filtered_1_ready_T_17
node _filtered_1_ready_T_18 = and(out[1].a.ready, allowed_1[18])
connect portsAOI_filtered_18[1].ready, _filtered_1_ready_T_18
node _filtered_1_ready_T_19 = and(out[1].a.ready, allowed_1[19])
connect portsAOI_filtered_19[1].ready, _filtered_1_ready_T_19
node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _out_1_a_valid_T_1 = or(_out_1_a_valid_T, portsAOI_filtered_2[1].valid)
node _out_1_a_valid_T_2 = or(_out_1_a_valid_T_1, portsAOI_filtered_3[1].valid)
node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_2, portsAOI_filtered_4[1].valid)
node _out_1_a_valid_T_4 = or(_out_1_a_valid_T_3, portsAOI_filtered_5[1].valid)
node _out_1_a_valid_T_5 = or(_out_1_a_valid_T_4, portsAOI_filtered_6[1].valid)
node _out_1_a_valid_T_6 = or(_out_1_a_valid_T_5, portsAOI_filtered_7[1].valid)
node _out_1_a_valid_T_7 = or(_out_1_a_valid_T_6, portsAOI_filtered_8[1].valid)
node _out_1_a_valid_T_8 = or(_out_1_a_valid_T_7, portsAOI_filtered_9[1].valid)
node _out_1_a_valid_T_9 = or(_out_1_a_valid_T_8, portsAOI_filtered_10[1].valid)
node _out_1_a_valid_T_10 = or(_out_1_a_valid_T_9, portsAOI_filtered_11[1].valid)
node _out_1_a_valid_T_11 = or(_out_1_a_valid_T_10, portsAOI_filtered_12[1].valid)
node _out_1_a_valid_T_12 = or(_out_1_a_valid_T_11, portsAOI_filtered_13[1].valid)
node _out_1_a_valid_T_13 = or(_out_1_a_valid_T_12, portsAOI_filtered_14[1].valid)
node _out_1_a_valid_T_14 = or(_out_1_a_valid_T_13, portsAOI_filtered_15[1].valid)
node _out_1_a_valid_T_15 = or(_out_1_a_valid_T_14, portsAOI_filtered_16[1].valid)
node _out_1_a_valid_T_16 = or(_out_1_a_valid_T_15, portsAOI_filtered_17[1].valid)
node _out_1_a_valid_T_17 = or(_out_1_a_valid_T_16, portsAOI_filtered_18[1].valid)
node _out_1_a_valid_T_18 = or(_out_1_a_valid_T_17, portsAOI_filtered_19[1].valid)
node _out_1_a_valid_T_19 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_20 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_21 = mux(state_1[2], portsAOI_filtered_2[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_22 = mux(state_1[3], portsAOI_filtered_3[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_23 = mux(state_1[4], portsAOI_filtered_4[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_24 = mux(state_1[5], portsAOI_filtered_5[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_25 = mux(state_1[6], portsAOI_filtered_6[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_26 = mux(state_1[7], portsAOI_filtered_7[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_27 = mux(state_1[8], portsAOI_filtered_8[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_28 = mux(state_1[9], portsAOI_filtered_9[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_29 = mux(state_1[10], portsAOI_filtered_10[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_30 = mux(state_1[11], portsAOI_filtered_11[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_31 = mux(state_1[12], portsAOI_filtered_12[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_32 = mux(state_1[13], portsAOI_filtered_13[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_33 = mux(state_1[14], portsAOI_filtered_14[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_34 = mux(state_1[15], portsAOI_filtered_15[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_35 = mux(state_1[16], portsAOI_filtered_16[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_36 = mux(state_1[17], portsAOI_filtered_17[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_37 = mux(state_1[18], portsAOI_filtered_18[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_38 = mux(state_1[19], portsAOI_filtered_19[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_39 = or(_out_1_a_valid_T_19, _out_1_a_valid_T_20)
node _out_1_a_valid_T_40 = or(_out_1_a_valid_T_39, _out_1_a_valid_T_21)
node _out_1_a_valid_T_41 = or(_out_1_a_valid_T_40, _out_1_a_valid_T_22)
node _out_1_a_valid_T_42 = or(_out_1_a_valid_T_41, _out_1_a_valid_T_23)
node _out_1_a_valid_T_43 = or(_out_1_a_valid_T_42, _out_1_a_valid_T_24)
node _out_1_a_valid_T_44 = or(_out_1_a_valid_T_43, _out_1_a_valid_T_25)
node _out_1_a_valid_T_45 = or(_out_1_a_valid_T_44, _out_1_a_valid_T_26)
node _out_1_a_valid_T_46 = or(_out_1_a_valid_T_45, _out_1_a_valid_T_27)
node _out_1_a_valid_T_47 = or(_out_1_a_valid_T_46, _out_1_a_valid_T_28)
node _out_1_a_valid_T_48 = or(_out_1_a_valid_T_47, _out_1_a_valid_T_29)
node _out_1_a_valid_T_49 = or(_out_1_a_valid_T_48, _out_1_a_valid_T_30)
node _out_1_a_valid_T_50 = or(_out_1_a_valid_T_49, _out_1_a_valid_T_31)
node _out_1_a_valid_T_51 = or(_out_1_a_valid_T_50, _out_1_a_valid_T_32)
node _out_1_a_valid_T_52 = or(_out_1_a_valid_T_51, _out_1_a_valid_T_33)
node _out_1_a_valid_T_53 = or(_out_1_a_valid_T_52, _out_1_a_valid_T_34)
node _out_1_a_valid_T_54 = or(_out_1_a_valid_T_53, _out_1_a_valid_T_35)
node _out_1_a_valid_T_55 = or(_out_1_a_valid_T_54, _out_1_a_valid_T_36)
node _out_1_a_valid_T_56 = or(_out_1_a_valid_T_55, _out_1_a_valid_T_37)
node _out_1_a_valid_T_57 = or(_out_1_a_valid_T_56, _out_1_a_valid_T_38)
wire _out_1_a_valid_WIRE : UInt<1>
connect _out_1_a_valid_WIRE, _out_1_a_valid_T_57
node _out_1_a_valid_T_58 = mux(idle_1, _out_1_a_valid_T_18, _out_1_a_valid_WIRE)
connect out[1].a.valid, _out_1_a_valid_T_58
wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_2 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_3 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_4 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_5 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_6 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_7 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_8 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_9 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_10 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_11 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_12 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_13 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_14 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_15 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_16 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_17 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_18 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_19 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_20 = or(_out_1_a_bits_T, _out_1_a_bits_T_1)
node _out_1_a_bits_T_21 = or(_out_1_a_bits_T_20, _out_1_a_bits_T_2)
node _out_1_a_bits_T_22 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_3)
node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_22, _out_1_a_bits_T_4)
node _out_1_a_bits_T_24 = or(_out_1_a_bits_T_23, _out_1_a_bits_T_5)
node _out_1_a_bits_T_25 = or(_out_1_a_bits_T_24, _out_1_a_bits_T_6)
node _out_1_a_bits_T_26 = or(_out_1_a_bits_T_25, _out_1_a_bits_T_7)
node _out_1_a_bits_T_27 = or(_out_1_a_bits_T_26, _out_1_a_bits_T_8)
node _out_1_a_bits_T_28 = or(_out_1_a_bits_T_27, _out_1_a_bits_T_9)
node _out_1_a_bits_T_29 = or(_out_1_a_bits_T_28, _out_1_a_bits_T_10)
node _out_1_a_bits_T_30 = or(_out_1_a_bits_T_29, _out_1_a_bits_T_11)
node _out_1_a_bits_T_31 = or(_out_1_a_bits_T_30, _out_1_a_bits_T_12)
node _out_1_a_bits_T_32 = or(_out_1_a_bits_T_31, _out_1_a_bits_T_13)
node _out_1_a_bits_T_33 = or(_out_1_a_bits_T_32, _out_1_a_bits_T_14)
node _out_1_a_bits_T_34 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_15)
node _out_1_a_bits_T_35 = or(_out_1_a_bits_T_34, _out_1_a_bits_T_16)
node _out_1_a_bits_T_36 = or(_out_1_a_bits_T_35, _out_1_a_bits_T_17)
node _out_1_a_bits_T_37 = or(_out_1_a_bits_T_36, _out_1_a_bits_T_18)
node _out_1_a_bits_T_38 = or(_out_1_a_bits_T_37, _out_1_a_bits_T_19)
wire _out_1_a_bits_WIRE_1 : UInt<1>
connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_38
connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1
node _out_1_a_bits_T_39 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_40 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_41 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_42 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_43 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_44 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_45 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_46 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_47 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_48 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_49 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_50 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_51 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_52 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_53 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_54 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_55 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_56 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_57 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_58 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_59 = or(_out_1_a_bits_T_39, _out_1_a_bits_T_40)
node _out_1_a_bits_T_60 = or(_out_1_a_bits_T_59, _out_1_a_bits_T_41)
node _out_1_a_bits_T_61 = or(_out_1_a_bits_T_60, _out_1_a_bits_T_42)
node _out_1_a_bits_T_62 = or(_out_1_a_bits_T_61, _out_1_a_bits_T_43)
node _out_1_a_bits_T_63 = or(_out_1_a_bits_T_62, _out_1_a_bits_T_44)
node _out_1_a_bits_T_64 = or(_out_1_a_bits_T_63, _out_1_a_bits_T_45)
node _out_1_a_bits_T_65 = or(_out_1_a_bits_T_64, _out_1_a_bits_T_46)
node _out_1_a_bits_T_66 = or(_out_1_a_bits_T_65, _out_1_a_bits_T_47)
node _out_1_a_bits_T_67 = or(_out_1_a_bits_T_66, _out_1_a_bits_T_48)
node _out_1_a_bits_T_68 = or(_out_1_a_bits_T_67, _out_1_a_bits_T_49)
node _out_1_a_bits_T_69 = or(_out_1_a_bits_T_68, _out_1_a_bits_T_50)
node _out_1_a_bits_T_70 = or(_out_1_a_bits_T_69, _out_1_a_bits_T_51)
node _out_1_a_bits_T_71 = or(_out_1_a_bits_T_70, _out_1_a_bits_T_52)
node _out_1_a_bits_T_72 = or(_out_1_a_bits_T_71, _out_1_a_bits_T_53)
node _out_1_a_bits_T_73 = or(_out_1_a_bits_T_72, _out_1_a_bits_T_54)
node _out_1_a_bits_T_74 = or(_out_1_a_bits_T_73, _out_1_a_bits_T_55)
node _out_1_a_bits_T_75 = or(_out_1_a_bits_T_74, _out_1_a_bits_T_56)
node _out_1_a_bits_T_76 = or(_out_1_a_bits_T_75, _out_1_a_bits_T_57)
node _out_1_a_bits_T_77 = or(_out_1_a_bits_T_76, _out_1_a_bits_T_58)
wire _out_1_a_bits_WIRE_2 : UInt<64>
connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_77
connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2
node _out_1_a_bits_T_78 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_79 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_80 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_81 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_82 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_83 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_84 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_85 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_86 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_87 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_88 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_89 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_90 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_91 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_92 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_93 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_94 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_95 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_96 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_97 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_98 = or(_out_1_a_bits_T_78, _out_1_a_bits_T_79)
node _out_1_a_bits_T_99 = or(_out_1_a_bits_T_98, _out_1_a_bits_T_80)
node _out_1_a_bits_T_100 = or(_out_1_a_bits_T_99, _out_1_a_bits_T_81)
node _out_1_a_bits_T_101 = or(_out_1_a_bits_T_100, _out_1_a_bits_T_82)
node _out_1_a_bits_T_102 = or(_out_1_a_bits_T_101, _out_1_a_bits_T_83)
node _out_1_a_bits_T_103 = or(_out_1_a_bits_T_102, _out_1_a_bits_T_84)
node _out_1_a_bits_T_104 = or(_out_1_a_bits_T_103, _out_1_a_bits_T_85)
node _out_1_a_bits_T_105 = or(_out_1_a_bits_T_104, _out_1_a_bits_T_86)
node _out_1_a_bits_T_106 = or(_out_1_a_bits_T_105, _out_1_a_bits_T_87)
node _out_1_a_bits_T_107 = or(_out_1_a_bits_T_106, _out_1_a_bits_T_88)
node _out_1_a_bits_T_108 = or(_out_1_a_bits_T_107, _out_1_a_bits_T_89)
node _out_1_a_bits_T_109 = or(_out_1_a_bits_T_108, _out_1_a_bits_T_90)
node _out_1_a_bits_T_110 = or(_out_1_a_bits_T_109, _out_1_a_bits_T_91)
node _out_1_a_bits_T_111 = or(_out_1_a_bits_T_110, _out_1_a_bits_T_92)
node _out_1_a_bits_T_112 = or(_out_1_a_bits_T_111, _out_1_a_bits_T_93)
node _out_1_a_bits_T_113 = or(_out_1_a_bits_T_112, _out_1_a_bits_T_94)
node _out_1_a_bits_T_114 = or(_out_1_a_bits_T_113, _out_1_a_bits_T_95)
node _out_1_a_bits_T_115 = or(_out_1_a_bits_T_114, _out_1_a_bits_T_96)
node _out_1_a_bits_T_116 = or(_out_1_a_bits_T_115, _out_1_a_bits_T_97)
wire _out_1_a_bits_WIRE_3 : UInt<8>
connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_116
connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3
wire _out_1_a_bits_WIRE_4 : { }
connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4
wire _out_1_a_bits_WIRE_5 : { }
connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5
node _out_1_a_bits_T_117 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_118 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_119 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_120 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_121 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_122 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_123 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_124 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_125 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_126 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_127 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_128 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_129 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_130 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_131 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_132 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_133 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_134 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_135 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_136 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_137 = or(_out_1_a_bits_T_117, _out_1_a_bits_T_118)
node _out_1_a_bits_T_138 = or(_out_1_a_bits_T_137, _out_1_a_bits_T_119)
node _out_1_a_bits_T_139 = or(_out_1_a_bits_T_138, _out_1_a_bits_T_120)
node _out_1_a_bits_T_140 = or(_out_1_a_bits_T_139, _out_1_a_bits_T_121)
node _out_1_a_bits_T_141 = or(_out_1_a_bits_T_140, _out_1_a_bits_T_122)
node _out_1_a_bits_T_142 = or(_out_1_a_bits_T_141, _out_1_a_bits_T_123)
node _out_1_a_bits_T_143 = or(_out_1_a_bits_T_142, _out_1_a_bits_T_124)
node _out_1_a_bits_T_144 = or(_out_1_a_bits_T_143, _out_1_a_bits_T_125)
node _out_1_a_bits_T_145 = or(_out_1_a_bits_T_144, _out_1_a_bits_T_126)
node _out_1_a_bits_T_146 = or(_out_1_a_bits_T_145, _out_1_a_bits_T_127)
node _out_1_a_bits_T_147 = or(_out_1_a_bits_T_146, _out_1_a_bits_T_128)
node _out_1_a_bits_T_148 = or(_out_1_a_bits_T_147, _out_1_a_bits_T_129)
node _out_1_a_bits_T_149 = or(_out_1_a_bits_T_148, _out_1_a_bits_T_130)
node _out_1_a_bits_T_150 = or(_out_1_a_bits_T_149, _out_1_a_bits_T_131)
node _out_1_a_bits_T_151 = or(_out_1_a_bits_T_150, _out_1_a_bits_T_132)
node _out_1_a_bits_T_152 = or(_out_1_a_bits_T_151, _out_1_a_bits_T_133)
node _out_1_a_bits_T_153 = or(_out_1_a_bits_T_152, _out_1_a_bits_T_134)
node _out_1_a_bits_T_154 = or(_out_1_a_bits_T_153, _out_1_a_bits_T_135)
node _out_1_a_bits_T_155 = or(_out_1_a_bits_T_154, _out_1_a_bits_T_136)
wire _out_1_a_bits_WIRE_6 : UInt<32>
connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_155
connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6
node _out_1_a_bits_T_156 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_157 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_158 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_159 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_160 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_161 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_162 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_163 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_164 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_165 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_166 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_167 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_168 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_169 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_170 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_171 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_172 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_173 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_174 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_175 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_176 = or(_out_1_a_bits_T_156, _out_1_a_bits_T_157)
node _out_1_a_bits_T_177 = or(_out_1_a_bits_T_176, _out_1_a_bits_T_158)
node _out_1_a_bits_T_178 = or(_out_1_a_bits_T_177, _out_1_a_bits_T_159)
node _out_1_a_bits_T_179 = or(_out_1_a_bits_T_178, _out_1_a_bits_T_160)
node _out_1_a_bits_T_180 = or(_out_1_a_bits_T_179, _out_1_a_bits_T_161)
node _out_1_a_bits_T_181 = or(_out_1_a_bits_T_180, _out_1_a_bits_T_162)
node _out_1_a_bits_T_182 = or(_out_1_a_bits_T_181, _out_1_a_bits_T_163)
node _out_1_a_bits_T_183 = or(_out_1_a_bits_T_182, _out_1_a_bits_T_164)
node _out_1_a_bits_T_184 = or(_out_1_a_bits_T_183, _out_1_a_bits_T_165)
node _out_1_a_bits_T_185 = or(_out_1_a_bits_T_184, _out_1_a_bits_T_166)
node _out_1_a_bits_T_186 = or(_out_1_a_bits_T_185, _out_1_a_bits_T_167)
node _out_1_a_bits_T_187 = or(_out_1_a_bits_T_186, _out_1_a_bits_T_168)
node _out_1_a_bits_T_188 = or(_out_1_a_bits_T_187, _out_1_a_bits_T_169)
node _out_1_a_bits_T_189 = or(_out_1_a_bits_T_188, _out_1_a_bits_T_170)
node _out_1_a_bits_T_190 = or(_out_1_a_bits_T_189, _out_1_a_bits_T_171)
node _out_1_a_bits_T_191 = or(_out_1_a_bits_T_190, _out_1_a_bits_T_172)
node _out_1_a_bits_T_192 = or(_out_1_a_bits_T_191, _out_1_a_bits_T_173)
node _out_1_a_bits_T_193 = or(_out_1_a_bits_T_192, _out_1_a_bits_T_174)
node _out_1_a_bits_T_194 = or(_out_1_a_bits_T_193, _out_1_a_bits_T_175)
wire _out_1_a_bits_WIRE_7 : UInt<9>
connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_194
connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7
node _out_1_a_bits_T_195 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_196 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_197 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_198 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_199 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_200 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_201 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_202 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_203 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_204 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_205 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_206 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_207 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_208 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_209 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_210 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_211 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_212 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_213 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_214 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_215 = or(_out_1_a_bits_T_195, _out_1_a_bits_T_196)
node _out_1_a_bits_T_216 = or(_out_1_a_bits_T_215, _out_1_a_bits_T_197)
node _out_1_a_bits_T_217 = or(_out_1_a_bits_T_216, _out_1_a_bits_T_198)
node _out_1_a_bits_T_218 = or(_out_1_a_bits_T_217, _out_1_a_bits_T_199)
node _out_1_a_bits_T_219 = or(_out_1_a_bits_T_218, _out_1_a_bits_T_200)
node _out_1_a_bits_T_220 = or(_out_1_a_bits_T_219, _out_1_a_bits_T_201)
node _out_1_a_bits_T_221 = or(_out_1_a_bits_T_220, _out_1_a_bits_T_202)
node _out_1_a_bits_T_222 = or(_out_1_a_bits_T_221, _out_1_a_bits_T_203)
node _out_1_a_bits_T_223 = or(_out_1_a_bits_T_222, _out_1_a_bits_T_204)
node _out_1_a_bits_T_224 = or(_out_1_a_bits_T_223, _out_1_a_bits_T_205)
node _out_1_a_bits_T_225 = or(_out_1_a_bits_T_224, _out_1_a_bits_T_206)
node _out_1_a_bits_T_226 = or(_out_1_a_bits_T_225, _out_1_a_bits_T_207)
node _out_1_a_bits_T_227 = or(_out_1_a_bits_T_226, _out_1_a_bits_T_208)
node _out_1_a_bits_T_228 = or(_out_1_a_bits_T_227, _out_1_a_bits_T_209)
node _out_1_a_bits_T_229 = or(_out_1_a_bits_T_228, _out_1_a_bits_T_210)
node _out_1_a_bits_T_230 = or(_out_1_a_bits_T_229, _out_1_a_bits_T_211)
node _out_1_a_bits_T_231 = or(_out_1_a_bits_T_230, _out_1_a_bits_T_212)
node _out_1_a_bits_T_232 = or(_out_1_a_bits_T_231, _out_1_a_bits_T_213)
node _out_1_a_bits_T_233 = or(_out_1_a_bits_T_232, _out_1_a_bits_T_214)
wire _out_1_a_bits_WIRE_8 : UInt<4>
connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_233
connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8
node _out_1_a_bits_T_234 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_235 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_236 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_237 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_238 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_239 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_240 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_241 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_242 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_243 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_244 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_245 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_246 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_247 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_248 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_249 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_250 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_251 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_252 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_253 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_254 = or(_out_1_a_bits_T_234, _out_1_a_bits_T_235)
node _out_1_a_bits_T_255 = or(_out_1_a_bits_T_254, _out_1_a_bits_T_236)
node _out_1_a_bits_T_256 = or(_out_1_a_bits_T_255, _out_1_a_bits_T_237)
node _out_1_a_bits_T_257 = or(_out_1_a_bits_T_256, _out_1_a_bits_T_238)
node _out_1_a_bits_T_258 = or(_out_1_a_bits_T_257, _out_1_a_bits_T_239)
node _out_1_a_bits_T_259 = or(_out_1_a_bits_T_258, _out_1_a_bits_T_240)
node _out_1_a_bits_T_260 = or(_out_1_a_bits_T_259, _out_1_a_bits_T_241)
node _out_1_a_bits_T_261 = or(_out_1_a_bits_T_260, _out_1_a_bits_T_242)
node _out_1_a_bits_T_262 = or(_out_1_a_bits_T_261, _out_1_a_bits_T_243)
node _out_1_a_bits_T_263 = or(_out_1_a_bits_T_262, _out_1_a_bits_T_244)
node _out_1_a_bits_T_264 = or(_out_1_a_bits_T_263, _out_1_a_bits_T_245)
node _out_1_a_bits_T_265 = or(_out_1_a_bits_T_264, _out_1_a_bits_T_246)
node _out_1_a_bits_T_266 = or(_out_1_a_bits_T_265, _out_1_a_bits_T_247)
node _out_1_a_bits_T_267 = or(_out_1_a_bits_T_266, _out_1_a_bits_T_248)
node _out_1_a_bits_T_268 = or(_out_1_a_bits_T_267, _out_1_a_bits_T_249)
node _out_1_a_bits_T_269 = or(_out_1_a_bits_T_268, _out_1_a_bits_T_250)
node _out_1_a_bits_T_270 = or(_out_1_a_bits_T_269, _out_1_a_bits_T_251)
node _out_1_a_bits_T_271 = or(_out_1_a_bits_T_270, _out_1_a_bits_T_252)
node _out_1_a_bits_T_272 = or(_out_1_a_bits_T_271, _out_1_a_bits_T_253)
wire _out_1_a_bits_WIRE_9 : UInt<3>
connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_272
connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9
node _out_1_a_bits_T_273 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_274 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_275 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_276 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_277 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_278 = mux(muxState_1[5], portsAOI_filtered_5[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_279 = mux(muxState_1[6], portsAOI_filtered_6[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_280 = mux(muxState_1[7], portsAOI_filtered_7[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_281 = mux(muxState_1[8], portsAOI_filtered_8[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_282 = mux(muxState_1[9], portsAOI_filtered_9[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_283 = mux(muxState_1[10], portsAOI_filtered_10[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_284 = mux(muxState_1[11], portsAOI_filtered_11[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_285 = mux(muxState_1[12], portsAOI_filtered_12[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_286 = mux(muxState_1[13], portsAOI_filtered_13[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_287 = mux(muxState_1[14], portsAOI_filtered_14[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_288 = mux(muxState_1[15], portsAOI_filtered_15[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_289 = mux(muxState_1[16], portsAOI_filtered_16[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_290 = mux(muxState_1[17], portsAOI_filtered_17[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_291 = mux(muxState_1[18], portsAOI_filtered_18[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_292 = mux(muxState_1[19], portsAOI_filtered_19[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_293 = or(_out_1_a_bits_T_273, _out_1_a_bits_T_274)
node _out_1_a_bits_T_294 = or(_out_1_a_bits_T_293, _out_1_a_bits_T_275)
node _out_1_a_bits_T_295 = or(_out_1_a_bits_T_294, _out_1_a_bits_T_276)
node _out_1_a_bits_T_296 = or(_out_1_a_bits_T_295, _out_1_a_bits_T_277)
node _out_1_a_bits_T_297 = or(_out_1_a_bits_T_296, _out_1_a_bits_T_278)
node _out_1_a_bits_T_298 = or(_out_1_a_bits_T_297, _out_1_a_bits_T_279)
node _out_1_a_bits_T_299 = or(_out_1_a_bits_T_298, _out_1_a_bits_T_280)
node _out_1_a_bits_T_300 = or(_out_1_a_bits_T_299, _out_1_a_bits_T_281)
node _out_1_a_bits_T_301 = or(_out_1_a_bits_T_300, _out_1_a_bits_T_282)
node _out_1_a_bits_T_302 = or(_out_1_a_bits_T_301, _out_1_a_bits_T_283)
node _out_1_a_bits_T_303 = or(_out_1_a_bits_T_302, _out_1_a_bits_T_284)
node _out_1_a_bits_T_304 = or(_out_1_a_bits_T_303, _out_1_a_bits_T_285)
node _out_1_a_bits_T_305 = or(_out_1_a_bits_T_304, _out_1_a_bits_T_286)
node _out_1_a_bits_T_306 = or(_out_1_a_bits_T_305, _out_1_a_bits_T_287)
node _out_1_a_bits_T_307 = or(_out_1_a_bits_T_306, _out_1_a_bits_T_288)
node _out_1_a_bits_T_308 = or(_out_1_a_bits_T_307, _out_1_a_bits_T_289)
node _out_1_a_bits_T_309 = or(_out_1_a_bits_T_308, _out_1_a_bits_T_290)
node _out_1_a_bits_T_310 = or(_out_1_a_bits_T_309, _out_1_a_bits_T_291)
node _out_1_a_bits_T_311 = or(_out_1_a_bits_T_310, _out_1_a_bits_T_292)
wire _out_1_a_bits_WIRE_10 : UInt<3>
connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_311
connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10
connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt
connect out[1].a.bits.data, _out_1_a_bits_WIRE.data
connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask
connect out[1].a.bits.address, _out_1_a_bits_WIRE.address
connect out[1].a.bits.source, _out_1_a_bits_WIRE.source
connect out[1].a.bits.size, _out_1_a_bits_WIRE.size
connect out[1].a.bits.param, _out_1_a_bits_WIRE.param
connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode
connect out[1].c, portsCOI_filtered_19[1]
connect out[1].e, portsEOI_filtered_19[1]
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_3[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_4[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_5[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_6[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_7[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_8[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_9[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_10[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_11[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_12[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_13[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_14[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_15[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_16[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_17[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_18[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_3[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_4[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_5[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_6[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_7[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_8[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_9[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_10[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_11[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_12[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_13[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_14[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_15[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_16[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_17[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_18[1].ready, UInt<1>(0h0)
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, in[0].d.ready)
node _readys_T_56 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid_2 = bits(_readys_T_56, 1, 0)
node _readys_T_57 = eq(readys_valid_2, _readys_T_56)
node _readys_T_58 = asUInt(reset)
node _readys_T_59 = eq(_readys_T_58, UInt<1>(0h0))
when _readys_T_59 :
node _readys_T_60 = eq(_readys_T_57, UInt<1>(0h0))
when _readys_T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2
assert(clock, _readys_T_57, UInt<1>(0h1), "") : readys_assert_2
regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_4 = not(readys_mask_2)
node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4)
node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2)
node _readys_unready_T_26 = shr(readys_filter_2, 1)
node _readys_unready_T_27 = or(readys_filter_2, _readys_unready_T_26)
node _readys_unready_T_28 = bits(_readys_unready_T_27, 3, 0)
node _readys_unready_T_29 = shr(_readys_unready_T_28, 1)
node _readys_unready_T_30 = shl(readys_mask_2, 2)
node readys_unready_2 = or(_readys_unready_T_29, _readys_unready_T_30)
node _readys_readys_T_6 = shr(readys_unready_2, 2)
node _readys_readys_T_7 = bits(readys_unready_2, 1, 0)
node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7)
node readys_readys_2 = not(_readys_readys_T_8)
node _readys_T_61 = orr(readys_valid_2)
node _readys_T_62 = and(latch_2, _readys_T_61)
when _readys_T_62 :
node _readys_mask_T_34 = and(readys_readys_2, readys_valid_2)
node _readys_mask_T_35 = shl(_readys_mask_T_34, 1)
node _readys_mask_T_36 = bits(_readys_mask_T_35, 1, 0)
node _readys_mask_T_37 = or(_readys_mask_T_34, _readys_mask_T_36)
node _readys_mask_T_38 = bits(_readys_mask_T_37, 1, 0)
connect readys_mask_2, _readys_mask_T_38
node _readys_T_63 = bits(readys_readys_2, 1, 0)
node _readys_T_64 = bits(_readys_T_63, 0, 0)
node _readys_T_65 = bits(_readys_T_63, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_64
connect readys_2[1], _readys_T_65
node _winner_T_40 = and(readys_2[0], portsDIO_filtered[0].valid)
node _winner_T_41 = and(readys_2[1], portsDIO_filtered_1[0].valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_40
connect winner_2[1], _winner_T_41
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_250 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = eq(winner_2[0], UInt<1>(0h0))
node _T_252 = or(_T_250, _T_251)
node _T_253 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_254 = eq(winner_2[1], UInt<1>(0h0))
node _T_255 = or(_T_253, _T_254)
node _T_256 = and(_T_252, _T_255)
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(_T_256, UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_256, UInt<1>(0h1), "") : assert_4
node _T_260 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = or(winner_2[0], winner_2[1])
node _T_263 = or(_T_261, _T_262)
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_263, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _filtered_0_ready_T_20 = and(in[0].d.ready, allowed_2[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T_20
node _filtered_0_ready_T_21 = and(in[0].d.ready, allowed_2[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_21
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<3>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<9>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<4>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in[1].d.ready)
node _readys_T_66 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid)
node readys_valid_3 = bits(_readys_T_66, 1, 0)
node _readys_T_67 = eq(readys_valid_3, _readys_T_66)
node _readys_T_68 = asUInt(reset)
node _readys_T_69 = eq(_readys_T_68, UInt<1>(0h0))
when _readys_T_69 :
node _readys_T_70 = eq(_readys_T_67, UInt<1>(0h0))
when _readys_T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3
assert(clock, _readys_T_67, UInt<1>(0h1), "") : readys_assert_3
regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_6 = not(readys_mask_3)
node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6)
node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3)
node _readys_unready_T_31 = shr(readys_filter_3, 1)
node _readys_unready_T_32 = or(readys_filter_3, _readys_unready_T_31)
node _readys_unready_T_33 = bits(_readys_unready_T_32, 3, 0)
node _readys_unready_T_34 = shr(_readys_unready_T_33, 1)
node _readys_unready_T_35 = shl(readys_mask_3, 2)
node readys_unready_3 = or(_readys_unready_T_34, _readys_unready_T_35)
node _readys_readys_T_9 = shr(readys_unready_3, 2)
node _readys_readys_T_10 = bits(readys_unready_3, 1, 0)
node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10)
node readys_readys_3 = not(_readys_readys_T_11)
node _readys_T_71 = orr(readys_valid_3)
node _readys_T_72 = and(latch_3, _readys_T_71)
when _readys_T_72 :
node _readys_mask_T_39 = and(readys_readys_3, readys_valid_3)
node _readys_mask_T_40 = shl(_readys_mask_T_39, 1)
node _readys_mask_T_41 = bits(_readys_mask_T_40, 1, 0)
node _readys_mask_T_42 = or(_readys_mask_T_39, _readys_mask_T_41)
node _readys_mask_T_43 = bits(_readys_mask_T_42, 1, 0)
connect readys_mask_3, _readys_mask_T_43
node _readys_T_73 = bits(readys_readys_3, 1, 0)
node _readys_T_74 = bits(_readys_T_73, 0, 0)
node _readys_T_75 = bits(_readys_T_73, 1, 1)
wire readys_3 : UInt<1>[2]
connect readys_3[0], _readys_T_74
connect readys_3[1], _readys_T_75
node _winner_T_42 = and(readys_3[0], portsDIO_filtered[1].valid)
node _winner_T_43 = and(readys_3[1], portsDIO_filtered_1[1].valid)
wire winner_3 : UInt<1>[2]
connect winner_3[0], _winner_T_42
connect winner_3[1], _winner_T_43
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1])
node _T_267 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_268 = eq(winner_3[0], UInt<1>(0h0))
node _T_269 = or(_T_267, _T_268)
node _T_270 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_271 = eq(winner_3[1], UInt<1>(0h0))
node _T_272 = or(_T_270, _T_271)
node _T_273 = and(_T_269, _T_272)
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(_T_273, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6
assert(clock, _T_273, UInt<1>(0h1), "") : assert_6
node _T_277 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = or(winner_3[0], winner_3[1])
node _T_280 = or(_T_278, _T_279)
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(_T_280, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7
assert(clock, _T_280, UInt<1>(0h1), "") : assert_7
node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0))
node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3)
node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[2]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _filtered_1_ready_T_20 = and(in[1].d.ready, allowed_3[0])
connect portsDIO_filtered[1].ready, _filtered_1_ready_T_20
node _filtered_1_ready_T_21 = and(in[1].d.ready, allowed_3[1])
connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_21
node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2)
wire _in_1_d_valid_WIRE : UInt<1>
connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3
node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE)
connect in[1].d.valid, _in_1_d_valid_T_4
wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1)
wire _in_1_d_bits_WIRE_1 : UInt<1>
connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2
connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1
node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4)
wire _in_1_d_bits_WIRE_2 : UInt<64>
connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5
connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2
wire _in_1_d_bits_WIRE_3 : { }
connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3
wire _in_1_d_bits_WIRE_4 : { }
connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4
node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7)
wire _in_1_d_bits_WIRE_5 : UInt<1>
connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8
connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5
node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10)
wire _in_1_d_bits_WIRE_6 : UInt<3>
connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11
connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6
node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13)
wire _in_1_d_bits_WIRE_7 : UInt<9>
connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14
connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7
node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16)
wire _in_1_d_bits_WIRE_8 : UInt<4>
connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17
connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8
node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19)
wire _in_1_d_bits_WIRE_9 : UInt<2>
connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20
connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9
node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22)
wire _in_1_d_bits_WIRE_10 : UInt<3>
connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23
connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10
connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt
connect in[1].d.bits.data, _in_1_d_bits_WIRE.data
connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied
connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink
connect in[1].d.bits.source, _in_1_d_bits_WIRE.source
connect in[1].d.bits.size, _in_1_d_bits_WIRE.size
connect in[1].d.bits.param, _in_1_d_bits_WIRE.param
connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[1].ready, UInt<1>(0h0)
invalidate in[2].b.bits.corrupt
invalidate in[2].b.bits.data
invalidate in[2].b.bits.mask
invalidate in[2].b.bits.address
invalidate in[2].b.bits.source
invalidate in[2].b.bits.size
invalidate in[2].b.bits.param
invalidate in[2].b.bits.opcode
regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0)
node idle_4 = eq(beatsLeft_4, UInt<1>(0h0))
node latch_4 = and(idle_4, in[2].d.ready)
node _readys_T_76 = cat(portsDIO_filtered_1[2].valid, portsDIO_filtered[2].valid)
node readys_valid_4 = bits(_readys_T_76, 1, 0)
node _readys_T_77 = eq(readys_valid_4, _readys_T_76)
node _readys_T_78 = asUInt(reset)
node _readys_T_79 = eq(_readys_T_78, UInt<1>(0h0))
when _readys_T_79 :
node _readys_T_80 = eq(_readys_T_77, UInt<1>(0h0))
when _readys_T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_4
assert(clock, _readys_T_77, UInt<1>(0h1), "") : readys_assert_4
regreset readys_mask_4 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_8 = not(readys_mask_4)
node _readys_filter_T_9 = and(readys_valid_4, _readys_filter_T_8)
node readys_filter_4 = cat(_readys_filter_T_9, readys_valid_4)
node _readys_unready_T_36 = shr(readys_filter_4, 1)
node _readys_unready_T_37 = or(readys_filter_4, _readys_unready_T_36)
node _readys_unready_T_38 = bits(_readys_unready_T_37, 3, 0)
node _readys_unready_T_39 = shr(_readys_unready_T_38, 1)
node _readys_unready_T_40 = shl(readys_mask_4, 2)
node readys_unready_4 = or(_readys_unready_T_39, _readys_unready_T_40)
node _readys_readys_T_12 = shr(readys_unready_4, 2)
node _readys_readys_T_13 = bits(readys_unready_4, 1, 0)
node _readys_readys_T_14 = and(_readys_readys_T_12, _readys_readys_T_13)
node readys_readys_4 = not(_readys_readys_T_14)
node _readys_T_81 = orr(readys_valid_4)
node _readys_T_82 = and(latch_4, _readys_T_81)
when _readys_T_82 :
node _readys_mask_T_44 = and(readys_readys_4, readys_valid_4)
node _readys_mask_T_45 = shl(_readys_mask_T_44, 1)
node _readys_mask_T_46 = bits(_readys_mask_T_45, 1, 0)
node _readys_mask_T_47 = or(_readys_mask_T_44, _readys_mask_T_46)
node _readys_mask_T_48 = bits(_readys_mask_T_47, 1, 0)
connect readys_mask_4, _readys_mask_T_48
node _readys_T_83 = bits(readys_readys_4, 1, 0)
node _readys_T_84 = bits(_readys_T_83, 0, 0)
node _readys_T_85 = bits(_readys_T_83, 1, 1)
wire readys_4 : UInt<1>[2]
connect readys_4[0], _readys_T_84
connect readys_4[1], _readys_T_85
node _winner_T_44 = and(readys_4[0], portsDIO_filtered[2].valid)
node _winner_T_45 = and(readys_4[1], portsDIO_filtered_1[2].valid)
wire winner_4 : UInt<1>[2]
connect winner_4[0], _winner_T_44
connect winner_4[1], _winner_T_45
node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0])
node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1])
node _T_284 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_285 = eq(winner_4[0], UInt<1>(0h0))
node _T_286 = or(_T_284, _T_285)
node _T_287 = eq(prefixOR_1_4, UInt<1>(0h0))
node _T_288 = eq(winner_4[1], UInt<1>(0h0))
node _T_289 = or(_T_287, _T_288)
node _T_290 = and(_T_286, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8
assert(clock, _T_290, UInt<1>(0h1), "") : assert_8
node _T_294 = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid)
node _T_295 = eq(_T_294, UInt<1>(0h0))
node _T_296 = or(winner_4[0], winner_4[1])
node _T_297 = or(_T_295, _T_296)
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9
assert(clock, _T_297, UInt<1>(0h1), "") : assert_9
node maskedBeats_0_4 = mux(winner_4[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_4 = mux(winner_4[1], beatsDO_1, UInt<1>(0h0))
node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4)
node _beatsLeft_T_16 = and(in[2].d.ready, in[2].d.valid)
node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16)
node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1)
node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18)
connect beatsLeft_4, _beatsLeft_T_19
wire _state_WIRE_4 : UInt<1>[2]
connect _state_WIRE_4[0], UInt<1>(0h0)
connect _state_WIRE_4[1], UInt<1>(0h0)
regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4
node muxState_4 = mux(idle_4, winner_4, state_4)
connect state_4, muxState_4
node allowed_4 = mux(idle_4, readys_4, state_4)
node _filtered_2_ready_T = and(in[2].d.ready, allowed_4[0])
connect portsDIO_filtered[2].ready, _filtered_2_ready_T
node _filtered_2_ready_T_1 = and(in[2].d.ready, allowed_4[1])
connect portsDIO_filtered_1[2].ready, _filtered_2_ready_T_1
node _in_2_d_valid_T = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid)
node _in_2_d_valid_T_1 = mux(state_4[0], portsDIO_filtered[2].valid, UInt<1>(0h0))
node _in_2_d_valid_T_2 = mux(state_4[1], portsDIO_filtered_1[2].valid, UInt<1>(0h0))
node _in_2_d_valid_T_3 = or(_in_2_d_valid_T_1, _in_2_d_valid_T_2)
wire _in_2_d_valid_WIRE : UInt<1>
connect _in_2_d_valid_WIRE, _in_2_d_valid_T_3
node _in_2_d_valid_T_4 = mux(idle_4, _in_2_d_valid_T, _in_2_d_valid_WIRE)
connect in[2].d.valid, _in_2_d_valid_T_4
wire _in_2_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_2_d_bits_T = mux(muxState_4[0], portsDIO_filtered[2].bits.corrupt, UInt<1>(0h0))
node _in_2_d_bits_T_1 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.corrupt, UInt<1>(0h0))
node _in_2_d_bits_T_2 = or(_in_2_d_bits_T, _in_2_d_bits_T_1)
wire _in_2_d_bits_WIRE_1 : UInt<1>
connect _in_2_d_bits_WIRE_1, _in_2_d_bits_T_2
connect _in_2_d_bits_WIRE.corrupt, _in_2_d_bits_WIRE_1
node _in_2_d_bits_T_3 = mux(muxState_4[0], portsDIO_filtered[2].bits.data, UInt<1>(0h0))
node _in_2_d_bits_T_4 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.data, UInt<1>(0h0))
node _in_2_d_bits_T_5 = or(_in_2_d_bits_T_3, _in_2_d_bits_T_4)
wire _in_2_d_bits_WIRE_2 : UInt<64>
connect _in_2_d_bits_WIRE_2, _in_2_d_bits_T_5
connect _in_2_d_bits_WIRE.data, _in_2_d_bits_WIRE_2
wire _in_2_d_bits_WIRE_3 : { }
connect _in_2_d_bits_WIRE.echo, _in_2_d_bits_WIRE_3
wire _in_2_d_bits_WIRE_4 : { }
connect _in_2_d_bits_WIRE.user, _in_2_d_bits_WIRE_4
node _in_2_d_bits_T_6 = mux(muxState_4[0], portsDIO_filtered[2].bits.denied, UInt<1>(0h0))
node _in_2_d_bits_T_7 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.denied, UInt<1>(0h0))
node _in_2_d_bits_T_8 = or(_in_2_d_bits_T_6, _in_2_d_bits_T_7)
wire _in_2_d_bits_WIRE_5 : UInt<1>
connect _in_2_d_bits_WIRE_5, _in_2_d_bits_T_8
connect _in_2_d_bits_WIRE.denied, _in_2_d_bits_WIRE_5
node _in_2_d_bits_T_9 = mux(muxState_4[0], portsDIO_filtered[2].bits.sink, UInt<1>(0h0))
node _in_2_d_bits_T_10 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.sink, UInt<1>(0h0))
node _in_2_d_bits_T_11 = or(_in_2_d_bits_T_9, _in_2_d_bits_T_10)
wire _in_2_d_bits_WIRE_6 : UInt<3>
connect _in_2_d_bits_WIRE_6, _in_2_d_bits_T_11
connect _in_2_d_bits_WIRE.sink, _in_2_d_bits_WIRE_6
node _in_2_d_bits_T_12 = mux(muxState_4[0], portsDIO_filtered[2].bits.source, UInt<1>(0h0))
node _in_2_d_bits_T_13 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.source, UInt<1>(0h0))
node _in_2_d_bits_T_14 = or(_in_2_d_bits_T_12, _in_2_d_bits_T_13)
wire _in_2_d_bits_WIRE_7 : UInt<9>
connect _in_2_d_bits_WIRE_7, _in_2_d_bits_T_14
connect _in_2_d_bits_WIRE.source, _in_2_d_bits_WIRE_7
node _in_2_d_bits_T_15 = mux(muxState_4[0], portsDIO_filtered[2].bits.size, UInt<1>(0h0))
node _in_2_d_bits_T_16 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.size, UInt<1>(0h0))
node _in_2_d_bits_T_17 = or(_in_2_d_bits_T_15, _in_2_d_bits_T_16)
wire _in_2_d_bits_WIRE_8 : UInt<4>
connect _in_2_d_bits_WIRE_8, _in_2_d_bits_T_17
connect _in_2_d_bits_WIRE.size, _in_2_d_bits_WIRE_8
node _in_2_d_bits_T_18 = mux(muxState_4[0], portsDIO_filtered[2].bits.param, UInt<1>(0h0))
node _in_2_d_bits_T_19 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.param, UInt<1>(0h0))
node _in_2_d_bits_T_20 = or(_in_2_d_bits_T_18, _in_2_d_bits_T_19)
wire _in_2_d_bits_WIRE_9 : UInt<2>
connect _in_2_d_bits_WIRE_9, _in_2_d_bits_T_20
connect _in_2_d_bits_WIRE.param, _in_2_d_bits_WIRE_9
node _in_2_d_bits_T_21 = mux(muxState_4[0], portsDIO_filtered[2].bits.opcode, UInt<1>(0h0))
node _in_2_d_bits_T_22 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.opcode, UInt<1>(0h0))
node _in_2_d_bits_T_23 = or(_in_2_d_bits_T_21, _in_2_d_bits_T_22)
wire _in_2_d_bits_WIRE_10 : UInt<3>
connect _in_2_d_bits_WIRE_10, _in_2_d_bits_T_23
connect _in_2_d_bits_WIRE.opcode, _in_2_d_bits_WIRE_10
connect in[2].d.bits.corrupt, _in_2_d_bits_WIRE.corrupt
connect in[2].d.bits.data, _in_2_d_bits_WIRE.data
connect in[2].d.bits.denied, _in_2_d_bits_WIRE.denied
connect in[2].d.bits.sink, _in_2_d_bits_WIRE.sink
connect in[2].d.bits.source, _in_2_d_bits_WIRE.source
connect in[2].d.bits.size, _in_2_d_bits_WIRE.size
connect in[2].d.bits.param, _in_2_d_bits_WIRE.param
connect in[2].d.bits.opcode, _in_2_d_bits_WIRE.opcode
connect portsBIO_filtered[2].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[2].ready, UInt<1>(0h0)
invalidate in[3].b.bits.corrupt
invalidate in[3].b.bits.data
invalidate in[3].b.bits.mask
invalidate in[3].b.bits.address
invalidate in[3].b.bits.source
invalidate in[3].b.bits.size
invalidate in[3].b.bits.param
invalidate in[3].b.bits.opcode
regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0)
node idle_5 = eq(beatsLeft_5, UInt<1>(0h0))
node latch_5 = and(idle_5, in[3].d.ready)
node _readys_T_86 = cat(portsDIO_filtered_1[3].valid, portsDIO_filtered[3].valid)
node readys_valid_5 = bits(_readys_T_86, 1, 0)
node _readys_T_87 = eq(readys_valid_5, _readys_T_86)
node _readys_T_88 = asUInt(reset)
node _readys_T_89 = eq(_readys_T_88, UInt<1>(0h0))
when _readys_T_89 :
node _readys_T_90 = eq(_readys_T_87, UInt<1>(0h0))
when _readys_T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_5
assert(clock, _readys_T_87, UInt<1>(0h1), "") : readys_assert_5
regreset readys_mask_5 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_10 = not(readys_mask_5)
node _readys_filter_T_11 = and(readys_valid_5, _readys_filter_T_10)
node readys_filter_5 = cat(_readys_filter_T_11, readys_valid_5)
node _readys_unready_T_41 = shr(readys_filter_5, 1)
node _readys_unready_T_42 = or(readys_filter_5, _readys_unready_T_41)
node _readys_unready_T_43 = bits(_readys_unready_T_42, 3, 0)
node _readys_unready_T_44 = shr(_readys_unready_T_43, 1)
node _readys_unready_T_45 = shl(readys_mask_5, 2)
node readys_unready_5 = or(_readys_unready_T_44, _readys_unready_T_45)
node _readys_readys_T_15 = shr(readys_unready_5, 2)
node _readys_readys_T_16 = bits(readys_unready_5, 1, 0)
node _readys_readys_T_17 = and(_readys_readys_T_15, _readys_readys_T_16)
node readys_readys_5 = not(_readys_readys_T_17)
node _readys_T_91 = orr(readys_valid_5)
node _readys_T_92 = and(latch_5, _readys_T_91)
when _readys_T_92 :
node _readys_mask_T_49 = and(readys_readys_5, readys_valid_5)
node _readys_mask_T_50 = shl(_readys_mask_T_49, 1)
node _readys_mask_T_51 = bits(_readys_mask_T_50, 1, 0)
node _readys_mask_T_52 = or(_readys_mask_T_49, _readys_mask_T_51)
node _readys_mask_T_53 = bits(_readys_mask_T_52, 1, 0)
connect readys_mask_5, _readys_mask_T_53
node _readys_T_93 = bits(readys_readys_5, 1, 0)
node _readys_T_94 = bits(_readys_T_93, 0, 0)
node _readys_T_95 = bits(_readys_T_93, 1, 1)
wire readys_5 : UInt<1>[2]
connect readys_5[0], _readys_T_94
connect readys_5[1], _readys_T_95
node _winner_T_46 = and(readys_5[0], portsDIO_filtered[3].valid)
node _winner_T_47 = and(readys_5[1], portsDIO_filtered_1[3].valid)
wire winner_5 : UInt<1>[2]
connect winner_5[0], _winner_T_46
connect winner_5[1], _winner_T_47
node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0])
node _prefixOR_T_5 = or(prefixOR_1_5, winner_5[1])
node _T_301 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = eq(winner_5[0], UInt<1>(0h0))
node _T_303 = or(_T_301, _T_302)
node _T_304 = eq(prefixOR_1_5, UInt<1>(0h0))
node _T_305 = eq(winner_5[1], UInt<1>(0h0))
node _T_306 = or(_T_304, _T_305)
node _T_307 = and(_T_303, _T_306)
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_10
assert(clock, _T_307, UInt<1>(0h1), "") : assert_10
node _T_311 = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid)
node _T_312 = eq(_T_311, UInt<1>(0h0))
node _T_313 = or(winner_5[0], winner_5[1])
node _T_314 = or(_T_312, _T_313)
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(_T_314, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_11
assert(clock, _T_314, UInt<1>(0h1), "") : assert_11
node maskedBeats_0_5 = mux(winner_5[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_5 = mux(winner_5[1], beatsDO_1, UInt<1>(0h0))
node initBeats_5 = or(maskedBeats_0_5, maskedBeats_1_5)
node _beatsLeft_T_20 = and(in[3].d.ready, in[3].d.valid)
node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20)
node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1)
node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22)
connect beatsLeft_5, _beatsLeft_T_23
wire _state_WIRE_5 : UInt<1>[2]
connect _state_WIRE_5[0], UInt<1>(0h0)
connect _state_WIRE_5[1], UInt<1>(0h0)
regreset state_5 : UInt<1>[2], clock, reset, _state_WIRE_5
node muxState_5 = mux(idle_5, winner_5, state_5)
connect state_5, muxState_5
node allowed_5 = mux(idle_5, readys_5, state_5)
node _filtered_3_ready_T = and(in[3].d.ready, allowed_5[0])
connect portsDIO_filtered[3].ready, _filtered_3_ready_T
node _filtered_3_ready_T_1 = and(in[3].d.ready, allowed_5[1])
connect portsDIO_filtered_1[3].ready, _filtered_3_ready_T_1
node _in_3_d_valid_T = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid)
node _in_3_d_valid_T_1 = mux(state_5[0], portsDIO_filtered[3].valid, UInt<1>(0h0))
node _in_3_d_valid_T_2 = mux(state_5[1], portsDIO_filtered_1[3].valid, UInt<1>(0h0))
node _in_3_d_valid_T_3 = or(_in_3_d_valid_T_1, _in_3_d_valid_T_2)
wire _in_3_d_valid_WIRE : UInt<1>
connect _in_3_d_valid_WIRE, _in_3_d_valid_T_3
node _in_3_d_valid_T_4 = mux(idle_5, _in_3_d_valid_T, _in_3_d_valid_WIRE)
connect in[3].d.valid, _in_3_d_valid_T_4
wire _in_3_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_3_d_bits_T = mux(muxState_5[0], portsDIO_filtered[3].bits.corrupt, UInt<1>(0h0))
node _in_3_d_bits_T_1 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.corrupt, UInt<1>(0h0))
node _in_3_d_bits_T_2 = or(_in_3_d_bits_T, _in_3_d_bits_T_1)
wire _in_3_d_bits_WIRE_1 : UInt<1>
connect _in_3_d_bits_WIRE_1, _in_3_d_bits_T_2
connect _in_3_d_bits_WIRE.corrupt, _in_3_d_bits_WIRE_1
node _in_3_d_bits_T_3 = mux(muxState_5[0], portsDIO_filtered[3].bits.data, UInt<1>(0h0))
node _in_3_d_bits_T_4 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.data, UInt<1>(0h0))
node _in_3_d_bits_T_5 = or(_in_3_d_bits_T_3, _in_3_d_bits_T_4)
wire _in_3_d_bits_WIRE_2 : UInt<64>
connect _in_3_d_bits_WIRE_2, _in_3_d_bits_T_5
connect _in_3_d_bits_WIRE.data, _in_3_d_bits_WIRE_2
wire _in_3_d_bits_WIRE_3 : { }
connect _in_3_d_bits_WIRE.echo, _in_3_d_bits_WIRE_3
wire _in_3_d_bits_WIRE_4 : { }
connect _in_3_d_bits_WIRE.user, _in_3_d_bits_WIRE_4
node _in_3_d_bits_T_6 = mux(muxState_5[0], portsDIO_filtered[3].bits.denied, UInt<1>(0h0))
node _in_3_d_bits_T_7 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.denied, UInt<1>(0h0))
node _in_3_d_bits_T_8 = or(_in_3_d_bits_T_6, _in_3_d_bits_T_7)
wire _in_3_d_bits_WIRE_5 : UInt<1>
connect _in_3_d_bits_WIRE_5, _in_3_d_bits_T_8
connect _in_3_d_bits_WIRE.denied, _in_3_d_bits_WIRE_5
node _in_3_d_bits_T_9 = mux(muxState_5[0], portsDIO_filtered[3].bits.sink, UInt<1>(0h0))
node _in_3_d_bits_T_10 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.sink, UInt<1>(0h0))
node _in_3_d_bits_T_11 = or(_in_3_d_bits_T_9, _in_3_d_bits_T_10)
wire _in_3_d_bits_WIRE_6 : UInt<3>
connect _in_3_d_bits_WIRE_6, _in_3_d_bits_T_11
connect _in_3_d_bits_WIRE.sink, _in_3_d_bits_WIRE_6
node _in_3_d_bits_T_12 = mux(muxState_5[0], portsDIO_filtered[3].bits.source, UInt<1>(0h0))
node _in_3_d_bits_T_13 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.source, UInt<1>(0h0))
node _in_3_d_bits_T_14 = or(_in_3_d_bits_T_12, _in_3_d_bits_T_13)
wire _in_3_d_bits_WIRE_7 : UInt<9>
connect _in_3_d_bits_WIRE_7, _in_3_d_bits_T_14
connect _in_3_d_bits_WIRE.source, _in_3_d_bits_WIRE_7
node _in_3_d_bits_T_15 = mux(muxState_5[0], portsDIO_filtered[3].bits.size, UInt<1>(0h0))
node _in_3_d_bits_T_16 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.size, UInt<1>(0h0))
node _in_3_d_bits_T_17 = or(_in_3_d_bits_T_15, _in_3_d_bits_T_16)
wire _in_3_d_bits_WIRE_8 : UInt<4>
connect _in_3_d_bits_WIRE_8, _in_3_d_bits_T_17
connect _in_3_d_bits_WIRE.size, _in_3_d_bits_WIRE_8
node _in_3_d_bits_T_18 = mux(muxState_5[0], portsDIO_filtered[3].bits.param, UInt<1>(0h0))
node _in_3_d_bits_T_19 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.param, UInt<1>(0h0))
node _in_3_d_bits_T_20 = or(_in_3_d_bits_T_18, _in_3_d_bits_T_19)
wire _in_3_d_bits_WIRE_9 : UInt<2>
connect _in_3_d_bits_WIRE_9, _in_3_d_bits_T_20
connect _in_3_d_bits_WIRE.param, _in_3_d_bits_WIRE_9
node _in_3_d_bits_T_21 = mux(muxState_5[0], portsDIO_filtered[3].bits.opcode, UInt<1>(0h0))
node _in_3_d_bits_T_22 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.opcode, UInt<1>(0h0))
node _in_3_d_bits_T_23 = or(_in_3_d_bits_T_21, _in_3_d_bits_T_22)
wire _in_3_d_bits_WIRE_10 : UInt<3>
connect _in_3_d_bits_WIRE_10, _in_3_d_bits_T_23
connect _in_3_d_bits_WIRE.opcode, _in_3_d_bits_WIRE_10
connect in[3].d.bits.corrupt, _in_3_d_bits_WIRE.corrupt
connect in[3].d.bits.data, _in_3_d_bits_WIRE.data
connect in[3].d.bits.denied, _in_3_d_bits_WIRE.denied
connect in[3].d.bits.sink, _in_3_d_bits_WIRE.sink
connect in[3].d.bits.source, _in_3_d_bits_WIRE.source
connect in[3].d.bits.size, _in_3_d_bits_WIRE.size
connect in[3].d.bits.param, _in_3_d_bits_WIRE.param
connect in[3].d.bits.opcode, _in_3_d_bits_WIRE.opcode
connect portsBIO_filtered[3].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[3].ready, UInt<1>(0h0)
invalidate in[4].b.bits.corrupt
invalidate in[4].b.bits.data
invalidate in[4].b.bits.mask
invalidate in[4].b.bits.address
invalidate in[4].b.bits.source
invalidate in[4].b.bits.size
invalidate in[4].b.bits.param
invalidate in[4].b.bits.opcode
regreset beatsLeft_6 : UInt, clock, reset, UInt<1>(0h0)
node idle_6 = eq(beatsLeft_6, UInt<1>(0h0))
node latch_6 = and(idle_6, in[4].d.ready)
node _readys_T_96 = cat(portsDIO_filtered_1[4].valid, portsDIO_filtered[4].valid)
node readys_valid_6 = bits(_readys_T_96, 1, 0)
node _readys_T_97 = eq(readys_valid_6, _readys_T_96)
node _readys_T_98 = asUInt(reset)
node _readys_T_99 = eq(_readys_T_98, UInt<1>(0h0))
when _readys_T_99 :
node _readys_T_100 = eq(_readys_T_97, UInt<1>(0h0))
when _readys_T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_6
assert(clock, _readys_T_97, UInt<1>(0h1), "") : readys_assert_6
regreset readys_mask_6 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_12 = not(readys_mask_6)
node _readys_filter_T_13 = and(readys_valid_6, _readys_filter_T_12)
node readys_filter_6 = cat(_readys_filter_T_13, readys_valid_6)
node _readys_unready_T_46 = shr(readys_filter_6, 1)
node _readys_unready_T_47 = or(readys_filter_6, _readys_unready_T_46)
node _readys_unready_T_48 = bits(_readys_unready_T_47, 3, 0)
node _readys_unready_T_49 = shr(_readys_unready_T_48, 1)
node _readys_unready_T_50 = shl(readys_mask_6, 2)
node readys_unready_6 = or(_readys_unready_T_49, _readys_unready_T_50)
node _readys_readys_T_18 = shr(readys_unready_6, 2)
node _readys_readys_T_19 = bits(readys_unready_6, 1, 0)
node _readys_readys_T_20 = and(_readys_readys_T_18, _readys_readys_T_19)
node readys_readys_6 = not(_readys_readys_T_20)
node _readys_T_101 = orr(readys_valid_6)
node _readys_T_102 = and(latch_6, _readys_T_101)
when _readys_T_102 :
node _readys_mask_T_54 = and(readys_readys_6, readys_valid_6)
node _readys_mask_T_55 = shl(_readys_mask_T_54, 1)
node _readys_mask_T_56 = bits(_readys_mask_T_55, 1, 0)
node _readys_mask_T_57 = or(_readys_mask_T_54, _readys_mask_T_56)
node _readys_mask_T_58 = bits(_readys_mask_T_57, 1, 0)
connect readys_mask_6, _readys_mask_T_58
node _readys_T_103 = bits(readys_readys_6, 1, 0)
node _readys_T_104 = bits(_readys_T_103, 0, 0)
node _readys_T_105 = bits(_readys_T_103, 1, 1)
wire readys_6 : UInt<1>[2]
connect readys_6[0], _readys_T_104
connect readys_6[1], _readys_T_105
node _winner_T_48 = and(readys_6[0], portsDIO_filtered[4].valid)
node _winner_T_49 = and(readys_6[1], portsDIO_filtered_1[4].valid)
wire winner_6 : UInt<1>[2]
connect winner_6[0], _winner_T_48
connect winner_6[1], _winner_T_49
node prefixOR_1_6 = or(UInt<1>(0h0), winner_6[0])
node _prefixOR_T_6 = or(prefixOR_1_6, winner_6[1])
node _T_318 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = eq(winner_6[0], UInt<1>(0h0))
node _T_320 = or(_T_318, _T_319)
node _T_321 = eq(prefixOR_1_6, UInt<1>(0h0))
node _T_322 = eq(winner_6[1], UInt<1>(0h0))
node _T_323 = or(_T_321, _T_322)
node _T_324 = and(_T_320, _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_12
assert(clock, _T_324, UInt<1>(0h1), "") : assert_12
node _T_328 = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid)
node _T_329 = eq(_T_328, UInt<1>(0h0))
node _T_330 = or(winner_6[0], winner_6[1])
node _T_331 = or(_T_329, _T_330)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node maskedBeats_0_6 = mux(winner_6[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_6 = mux(winner_6[1], beatsDO_1, UInt<1>(0h0))
node initBeats_6 = or(maskedBeats_0_6, maskedBeats_1_6)
node _beatsLeft_T_24 = and(in[4].d.ready, in[4].d.valid)
node _beatsLeft_T_25 = sub(beatsLeft_6, _beatsLeft_T_24)
node _beatsLeft_T_26 = tail(_beatsLeft_T_25, 1)
node _beatsLeft_T_27 = mux(latch_6, initBeats_6, _beatsLeft_T_26)
connect beatsLeft_6, _beatsLeft_T_27
wire _state_WIRE_6 : UInt<1>[2]
connect _state_WIRE_6[0], UInt<1>(0h0)
connect _state_WIRE_6[1], UInt<1>(0h0)
regreset state_6 : UInt<1>[2], clock, reset, _state_WIRE_6
node muxState_6 = mux(idle_6, winner_6, state_6)
connect state_6, muxState_6
node allowed_6 = mux(idle_6, readys_6, state_6)
node _filtered_4_ready_T = and(in[4].d.ready, allowed_6[0])
connect portsDIO_filtered[4].ready, _filtered_4_ready_T
node _filtered_4_ready_T_1 = and(in[4].d.ready, allowed_6[1])
connect portsDIO_filtered_1[4].ready, _filtered_4_ready_T_1
node _in_4_d_valid_T = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid)
node _in_4_d_valid_T_1 = mux(state_6[0], portsDIO_filtered[4].valid, UInt<1>(0h0))
node _in_4_d_valid_T_2 = mux(state_6[1], portsDIO_filtered_1[4].valid, UInt<1>(0h0))
node _in_4_d_valid_T_3 = or(_in_4_d_valid_T_1, _in_4_d_valid_T_2)
wire _in_4_d_valid_WIRE : UInt<1>
connect _in_4_d_valid_WIRE, _in_4_d_valid_T_3
node _in_4_d_valid_T_4 = mux(idle_6, _in_4_d_valid_T, _in_4_d_valid_WIRE)
connect in[4].d.valid, _in_4_d_valid_T_4
wire _in_4_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_4_d_bits_T = mux(muxState_6[0], portsDIO_filtered[4].bits.corrupt, UInt<1>(0h0))
node _in_4_d_bits_T_1 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.corrupt, UInt<1>(0h0))
node _in_4_d_bits_T_2 = or(_in_4_d_bits_T, _in_4_d_bits_T_1)
wire _in_4_d_bits_WIRE_1 : UInt<1>
connect _in_4_d_bits_WIRE_1, _in_4_d_bits_T_2
connect _in_4_d_bits_WIRE.corrupt, _in_4_d_bits_WIRE_1
node _in_4_d_bits_T_3 = mux(muxState_6[0], portsDIO_filtered[4].bits.data, UInt<1>(0h0))
node _in_4_d_bits_T_4 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.data, UInt<1>(0h0))
node _in_4_d_bits_T_5 = or(_in_4_d_bits_T_3, _in_4_d_bits_T_4)
wire _in_4_d_bits_WIRE_2 : UInt<64>
connect _in_4_d_bits_WIRE_2, _in_4_d_bits_T_5
connect _in_4_d_bits_WIRE.data, _in_4_d_bits_WIRE_2
wire _in_4_d_bits_WIRE_3 : { }
connect _in_4_d_bits_WIRE.echo, _in_4_d_bits_WIRE_3
wire _in_4_d_bits_WIRE_4 : { }
connect _in_4_d_bits_WIRE.user, _in_4_d_bits_WIRE_4
node _in_4_d_bits_T_6 = mux(muxState_6[0], portsDIO_filtered[4].bits.denied, UInt<1>(0h0))
node _in_4_d_bits_T_7 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.denied, UInt<1>(0h0))
node _in_4_d_bits_T_8 = or(_in_4_d_bits_T_6, _in_4_d_bits_T_7)
wire _in_4_d_bits_WIRE_5 : UInt<1>
connect _in_4_d_bits_WIRE_5, _in_4_d_bits_T_8
connect _in_4_d_bits_WIRE.denied, _in_4_d_bits_WIRE_5
node _in_4_d_bits_T_9 = mux(muxState_6[0], portsDIO_filtered[4].bits.sink, UInt<1>(0h0))
node _in_4_d_bits_T_10 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.sink, UInt<1>(0h0))
node _in_4_d_bits_T_11 = or(_in_4_d_bits_T_9, _in_4_d_bits_T_10)
wire _in_4_d_bits_WIRE_6 : UInt<3>
connect _in_4_d_bits_WIRE_6, _in_4_d_bits_T_11
connect _in_4_d_bits_WIRE.sink, _in_4_d_bits_WIRE_6
node _in_4_d_bits_T_12 = mux(muxState_6[0], portsDIO_filtered[4].bits.source, UInt<1>(0h0))
node _in_4_d_bits_T_13 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.source, UInt<1>(0h0))
node _in_4_d_bits_T_14 = or(_in_4_d_bits_T_12, _in_4_d_bits_T_13)
wire _in_4_d_bits_WIRE_7 : UInt<9>
connect _in_4_d_bits_WIRE_7, _in_4_d_bits_T_14
connect _in_4_d_bits_WIRE.source, _in_4_d_bits_WIRE_7
node _in_4_d_bits_T_15 = mux(muxState_6[0], portsDIO_filtered[4].bits.size, UInt<1>(0h0))
node _in_4_d_bits_T_16 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.size, UInt<1>(0h0))
node _in_4_d_bits_T_17 = or(_in_4_d_bits_T_15, _in_4_d_bits_T_16)
wire _in_4_d_bits_WIRE_8 : UInt<4>
connect _in_4_d_bits_WIRE_8, _in_4_d_bits_T_17
connect _in_4_d_bits_WIRE.size, _in_4_d_bits_WIRE_8
node _in_4_d_bits_T_18 = mux(muxState_6[0], portsDIO_filtered[4].bits.param, UInt<1>(0h0))
node _in_4_d_bits_T_19 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.param, UInt<1>(0h0))
node _in_4_d_bits_T_20 = or(_in_4_d_bits_T_18, _in_4_d_bits_T_19)
wire _in_4_d_bits_WIRE_9 : UInt<2>
connect _in_4_d_bits_WIRE_9, _in_4_d_bits_T_20
connect _in_4_d_bits_WIRE.param, _in_4_d_bits_WIRE_9
node _in_4_d_bits_T_21 = mux(muxState_6[0], portsDIO_filtered[4].bits.opcode, UInt<1>(0h0))
node _in_4_d_bits_T_22 = mux(muxState_6[1], portsDIO_filtered_1[4].bits.opcode, UInt<1>(0h0))
node _in_4_d_bits_T_23 = or(_in_4_d_bits_T_21, _in_4_d_bits_T_22)
wire _in_4_d_bits_WIRE_10 : UInt<3>
connect _in_4_d_bits_WIRE_10, _in_4_d_bits_T_23
connect _in_4_d_bits_WIRE.opcode, _in_4_d_bits_WIRE_10
connect in[4].d.bits.corrupt, _in_4_d_bits_WIRE.corrupt
connect in[4].d.bits.data, _in_4_d_bits_WIRE.data
connect in[4].d.bits.denied, _in_4_d_bits_WIRE.denied
connect in[4].d.bits.sink, _in_4_d_bits_WIRE.sink
connect in[4].d.bits.source, _in_4_d_bits_WIRE.source
connect in[4].d.bits.size, _in_4_d_bits_WIRE.size
connect in[4].d.bits.param, _in_4_d_bits_WIRE.param
connect in[4].d.bits.opcode, _in_4_d_bits_WIRE.opcode
connect portsBIO_filtered[4].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[4].ready, UInt<1>(0h0)
invalidate in[5].b.bits.corrupt
invalidate in[5].b.bits.data
invalidate in[5].b.bits.mask
invalidate in[5].b.bits.address
invalidate in[5].b.bits.source
invalidate in[5].b.bits.size
invalidate in[5].b.bits.param
invalidate in[5].b.bits.opcode
regreset beatsLeft_7 : UInt, clock, reset, UInt<1>(0h0)
node idle_7 = eq(beatsLeft_7, UInt<1>(0h0))
node latch_7 = and(idle_7, in[5].d.ready)
node _readys_T_106 = cat(portsDIO_filtered_1[5].valid, portsDIO_filtered[5].valid)
node readys_valid_7 = bits(_readys_T_106, 1, 0)
node _readys_T_107 = eq(readys_valid_7, _readys_T_106)
node _readys_T_108 = asUInt(reset)
node _readys_T_109 = eq(_readys_T_108, UInt<1>(0h0))
when _readys_T_109 :
node _readys_T_110 = eq(_readys_T_107, UInt<1>(0h0))
when _readys_T_110 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_7
assert(clock, _readys_T_107, UInt<1>(0h1), "") : readys_assert_7
regreset readys_mask_7 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_14 = not(readys_mask_7)
node _readys_filter_T_15 = and(readys_valid_7, _readys_filter_T_14)
node readys_filter_7 = cat(_readys_filter_T_15, readys_valid_7)
node _readys_unready_T_51 = shr(readys_filter_7, 1)
node _readys_unready_T_52 = or(readys_filter_7, _readys_unready_T_51)
node _readys_unready_T_53 = bits(_readys_unready_T_52, 3, 0)
node _readys_unready_T_54 = shr(_readys_unready_T_53, 1)
node _readys_unready_T_55 = shl(readys_mask_7, 2)
node readys_unready_7 = or(_readys_unready_T_54, _readys_unready_T_55)
node _readys_readys_T_21 = shr(readys_unready_7, 2)
node _readys_readys_T_22 = bits(readys_unready_7, 1, 0)
node _readys_readys_T_23 = and(_readys_readys_T_21, _readys_readys_T_22)
node readys_readys_7 = not(_readys_readys_T_23)
node _readys_T_111 = orr(readys_valid_7)
node _readys_T_112 = and(latch_7, _readys_T_111)
when _readys_T_112 :
node _readys_mask_T_59 = and(readys_readys_7, readys_valid_7)
node _readys_mask_T_60 = shl(_readys_mask_T_59, 1)
node _readys_mask_T_61 = bits(_readys_mask_T_60, 1, 0)
node _readys_mask_T_62 = or(_readys_mask_T_59, _readys_mask_T_61)
node _readys_mask_T_63 = bits(_readys_mask_T_62, 1, 0)
connect readys_mask_7, _readys_mask_T_63
node _readys_T_113 = bits(readys_readys_7, 1, 0)
node _readys_T_114 = bits(_readys_T_113, 0, 0)
node _readys_T_115 = bits(_readys_T_113, 1, 1)
wire readys_7 : UInt<1>[2]
connect readys_7[0], _readys_T_114
connect readys_7[1], _readys_T_115
node _winner_T_50 = and(readys_7[0], portsDIO_filtered[5].valid)
node _winner_T_51 = and(readys_7[1], portsDIO_filtered_1[5].valid)
wire winner_7 : UInt<1>[2]
connect winner_7[0], _winner_T_50
connect winner_7[1], _winner_T_51
node prefixOR_1_7 = or(UInt<1>(0h0), winner_7[0])
node _prefixOR_T_7 = or(prefixOR_1_7, winner_7[1])
node _T_335 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = eq(winner_7[0], UInt<1>(0h0))
node _T_337 = or(_T_335, _T_336)
node _T_338 = eq(prefixOR_1_7, UInt<1>(0h0))
node _T_339 = eq(winner_7[1], UInt<1>(0h0))
node _T_340 = or(_T_338, _T_339)
node _T_341 = and(_T_337, _T_340)
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_14
assert(clock, _T_341, UInt<1>(0h1), "") : assert_14
node _T_345 = or(portsDIO_filtered[5].valid, portsDIO_filtered_1[5].valid)
node _T_346 = eq(_T_345, UInt<1>(0h0))
node _T_347 = or(winner_7[0], winner_7[1])
node _T_348 = or(_T_346, _T_347)
node _T_349 = asUInt(reset)
node _T_350 = eq(_T_349, UInt<1>(0h0))
when _T_350 :
node _T_351 = eq(_T_348, UInt<1>(0h0))
when _T_351 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_15
assert(clock, _T_348, UInt<1>(0h1), "") : assert_15
node maskedBeats_0_7 = mux(winner_7[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_7 = mux(winner_7[1], beatsDO_1, UInt<1>(0h0))
node initBeats_7 = or(maskedBeats_0_7, maskedBeats_1_7)
node _beatsLeft_T_28 = and(in[5].d.ready, in[5].d.valid)
node _beatsLeft_T_29 = sub(beatsLeft_7, _beatsLeft_T_28)
node _beatsLeft_T_30 = tail(_beatsLeft_T_29, 1)
node _beatsLeft_T_31 = mux(latch_7, initBeats_7, _beatsLeft_T_30)
connect beatsLeft_7, _beatsLeft_T_31
wire _state_WIRE_7 : UInt<1>[2]
connect _state_WIRE_7[0], UInt<1>(0h0)
connect _state_WIRE_7[1], UInt<1>(0h0)
regreset state_7 : UInt<1>[2], clock, reset, _state_WIRE_7
node muxState_7 = mux(idle_7, winner_7, state_7)
connect state_7, muxState_7
node allowed_7 = mux(idle_7, readys_7, state_7)
node _filtered_5_ready_T = and(in[5].d.ready, allowed_7[0])
connect portsDIO_filtered[5].ready, _filtered_5_ready_T
node _filtered_5_ready_T_1 = and(in[5].d.ready, allowed_7[1])
connect portsDIO_filtered_1[5].ready, _filtered_5_ready_T_1
node _in_5_d_valid_T = or(portsDIO_filtered[5].valid, portsDIO_filtered_1[5].valid)
node _in_5_d_valid_T_1 = mux(state_7[0], portsDIO_filtered[5].valid, UInt<1>(0h0))
node _in_5_d_valid_T_2 = mux(state_7[1], portsDIO_filtered_1[5].valid, UInt<1>(0h0))
node _in_5_d_valid_T_3 = or(_in_5_d_valid_T_1, _in_5_d_valid_T_2)
wire _in_5_d_valid_WIRE : UInt<1>
connect _in_5_d_valid_WIRE, _in_5_d_valid_T_3
node _in_5_d_valid_T_4 = mux(idle_7, _in_5_d_valid_T, _in_5_d_valid_WIRE)
connect in[5].d.valid, _in_5_d_valid_T_4
wire _in_5_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_5_d_bits_T = mux(muxState_7[0], portsDIO_filtered[5].bits.corrupt, UInt<1>(0h0))
node _in_5_d_bits_T_1 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.corrupt, UInt<1>(0h0))
node _in_5_d_bits_T_2 = or(_in_5_d_bits_T, _in_5_d_bits_T_1)
wire _in_5_d_bits_WIRE_1 : UInt<1>
connect _in_5_d_bits_WIRE_1, _in_5_d_bits_T_2
connect _in_5_d_bits_WIRE.corrupt, _in_5_d_bits_WIRE_1
node _in_5_d_bits_T_3 = mux(muxState_7[0], portsDIO_filtered[5].bits.data, UInt<1>(0h0))
node _in_5_d_bits_T_4 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.data, UInt<1>(0h0))
node _in_5_d_bits_T_5 = or(_in_5_d_bits_T_3, _in_5_d_bits_T_4)
wire _in_5_d_bits_WIRE_2 : UInt<64>
connect _in_5_d_bits_WIRE_2, _in_5_d_bits_T_5
connect _in_5_d_bits_WIRE.data, _in_5_d_bits_WIRE_2
wire _in_5_d_bits_WIRE_3 : { }
connect _in_5_d_bits_WIRE.echo, _in_5_d_bits_WIRE_3
wire _in_5_d_bits_WIRE_4 : { }
connect _in_5_d_bits_WIRE.user, _in_5_d_bits_WIRE_4
node _in_5_d_bits_T_6 = mux(muxState_7[0], portsDIO_filtered[5].bits.denied, UInt<1>(0h0))
node _in_5_d_bits_T_7 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.denied, UInt<1>(0h0))
node _in_5_d_bits_T_8 = or(_in_5_d_bits_T_6, _in_5_d_bits_T_7)
wire _in_5_d_bits_WIRE_5 : UInt<1>
connect _in_5_d_bits_WIRE_5, _in_5_d_bits_T_8
connect _in_5_d_bits_WIRE.denied, _in_5_d_bits_WIRE_5
node _in_5_d_bits_T_9 = mux(muxState_7[0], portsDIO_filtered[5].bits.sink, UInt<1>(0h0))
node _in_5_d_bits_T_10 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.sink, UInt<1>(0h0))
node _in_5_d_bits_T_11 = or(_in_5_d_bits_T_9, _in_5_d_bits_T_10)
wire _in_5_d_bits_WIRE_6 : UInt<3>
connect _in_5_d_bits_WIRE_6, _in_5_d_bits_T_11
connect _in_5_d_bits_WIRE.sink, _in_5_d_bits_WIRE_6
node _in_5_d_bits_T_12 = mux(muxState_7[0], portsDIO_filtered[5].bits.source, UInt<1>(0h0))
node _in_5_d_bits_T_13 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.source, UInt<1>(0h0))
node _in_5_d_bits_T_14 = or(_in_5_d_bits_T_12, _in_5_d_bits_T_13)
wire _in_5_d_bits_WIRE_7 : UInt<9>
connect _in_5_d_bits_WIRE_7, _in_5_d_bits_T_14
connect _in_5_d_bits_WIRE.source, _in_5_d_bits_WIRE_7
node _in_5_d_bits_T_15 = mux(muxState_7[0], portsDIO_filtered[5].bits.size, UInt<1>(0h0))
node _in_5_d_bits_T_16 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.size, UInt<1>(0h0))
node _in_5_d_bits_T_17 = or(_in_5_d_bits_T_15, _in_5_d_bits_T_16)
wire _in_5_d_bits_WIRE_8 : UInt<4>
connect _in_5_d_bits_WIRE_8, _in_5_d_bits_T_17
connect _in_5_d_bits_WIRE.size, _in_5_d_bits_WIRE_8
node _in_5_d_bits_T_18 = mux(muxState_7[0], portsDIO_filtered[5].bits.param, UInt<1>(0h0))
node _in_5_d_bits_T_19 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.param, UInt<1>(0h0))
node _in_5_d_bits_T_20 = or(_in_5_d_bits_T_18, _in_5_d_bits_T_19)
wire _in_5_d_bits_WIRE_9 : UInt<2>
connect _in_5_d_bits_WIRE_9, _in_5_d_bits_T_20
connect _in_5_d_bits_WIRE.param, _in_5_d_bits_WIRE_9
node _in_5_d_bits_T_21 = mux(muxState_7[0], portsDIO_filtered[5].bits.opcode, UInt<1>(0h0))
node _in_5_d_bits_T_22 = mux(muxState_7[1], portsDIO_filtered_1[5].bits.opcode, UInt<1>(0h0))
node _in_5_d_bits_T_23 = or(_in_5_d_bits_T_21, _in_5_d_bits_T_22)
wire _in_5_d_bits_WIRE_10 : UInt<3>
connect _in_5_d_bits_WIRE_10, _in_5_d_bits_T_23
connect _in_5_d_bits_WIRE.opcode, _in_5_d_bits_WIRE_10
connect in[5].d.bits.corrupt, _in_5_d_bits_WIRE.corrupt
connect in[5].d.bits.data, _in_5_d_bits_WIRE.data
connect in[5].d.bits.denied, _in_5_d_bits_WIRE.denied
connect in[5].d.bits.sink, _in_5_d_bits_WIRE.sink
connect in[5].d.bits.source, _in_5_d_bits_WIRE.source
connect in[5].d.bits.size, _in_5_d_bits_WIRE.size
connect in[5].d.bits.param, _in_5_d_bits_WIRE.param
connect in[5].d.bits.opcode, _in_5_d_bits_WIRE.opcode
connect portsBIO_filtered[5].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[5].ready, UInt<1>(0h0)
invalidate in[6].b.bits.corrupt
invalidate in[6].b.bits.data
invalidate in[6].b.bits.mask
invalidate in[6].b.bits.address
invalidate in[6].b.bits.source
invalidate in[6].b.bits.size
invalidate in[6].b.bits.param
invalidate in[6].b.bits.opcode
regreset beatsLeft_8 : UInt, clock, reset, UInt<1>(0h0)
node idle_8 = eq(beatsLeft_8, UInt<1>(0h0))
node latch_8 = and(idle_8, in[6].d.ready)
node _readys_T_116 = cat(portsDIO_filtered_1[6].valid, portsDIO_filtered[6].valid)
node readys_valid_8 = bits(_readys_T_116, 1, 0)
node _readys_T_117 = eq(readys_valid_8, _readys_T_116)
node _readys_T_118 = asUInt(reset)
node _readys_T_119 = eq(_readys_T_118, UInt<1>(0h0))
when _readys_T_119 :
node _readys_T_120 = eq(_readys_T_117, UInt<1>(0h0))
when _readys_T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_8
assert(clock, _readys_T_117, UInt<1>(0h1), "") : readys_assert_8
regreset readys_mask_8 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_16 = not(readys_mask_8)
node _readys_filter_T_17 = and(readys_valid_8, _readys_filter_T_16)
node readys_filter_8 = cat(_readys_filter_T_17, readys_valid_8)
node _readys_unready_T_56 = shr(readys_filter_8, 1)
node _readys_unready_T_57 = or(readys_filter_8, _readys_unready_T_56)
node _readys_unready_T_58 = bits(_readys_unready_T_57, 3, 0)
node _readys_unready_T_59 = shr(_readys_unready_T_58, 1)
node _readys_unready_T_60 = shl(readys_mask_8, 2)
node readys_unready_8 = or(_readys_unready_T_59, _readys_unready_T_60)
node _readys_readys_T_24 = shr(readys_unready_8, 2)
node _readys_readys_T_25 = bits(readys_unready_8, 1, 0)
node _readys_readys_T_26 = and(_readys_readys_T_24, _readys_readys_T_25)
node readys_readys_8 = not(_readys_readys_T_26)
node _readys_T_121 = orr(readys_valid_8)
node _readys_T_122 = and(latch_8, _readys_T_121)
when _readys_T_122 :
node _readys_mask_T_64 = and(readys_readys_8, readys_valid_8)
node _readys_mask_T_65 = shl(_readys_mask_T_64, 1)
node _readys_mask_T_66 = bits(_readys_mask_T_65, 1, 0)
node _readys_mask_T_67 = or(_readys_mask_T_64, _readys_mask_T_66)
node _readys_mask_T_68 = bits(_readys_mask_T_67, 1, 0)
connect readys_mask_8, _readys_mask_T_68
node _readys_T_123 = bits(readys_readys_8, 1, 0)
node _readys_T_124 = bits(_readys_T_123, 0, 0)
node _readys_T_125 = bits(_readys_T_123, 1, 1)
wire readys_8 : UInt<1>[2]
connect readys_8[0], _readys_T_124
connect readys_8[1], _readys_T_125
node _winner_T_52 = and(readys_8[0], portsDIO_filtered[6].valid)
node _winner_T_53 = and(readys_8[1], portsDIO_filtered_1[6].valid)
wire winner_8 : UInt<1>[2]
connect winner_8[0], _winner_T_52
connect winner_8[1], _winner_T_53
node prefixOR_1_8 = or(UInt<1>(0h0), winner_8[0])
node _prefixOR_T_8 = or(prefixOR_1_8, winner_8[1])
node _T_352 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_353 = eq(winner_8[0], UInt<1>(0h0))
node _T_354 = or(_T_352, _T_353)
node _T_355 = eq(prefixOR_1_8, UInt<1>(0h0))
node _T_356 = eq(winner_8[1], UInt<1>(0h0))
node _T_357 = or(_T_355, _T_356)
node _T_358 = and(_T_354, _T_357)
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_T_358, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_16
assert(clock, _T_358, UInt<1>(0h1), "") : assert_16
node _T_362 = or(portsDIO_filtered[6].valid, portsDIO_filtered_1[6].valid)
node _T_363 = eq(_T_362, UInt<1>(0h0))
node _T_364 = or(winner_8[0], winner_8[1])
node _T_365 = or(_T_363, _T_364)
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_17
assert(clock, _T_365, UInt<1>(0h1), "") : assert_17
node maskedBeats_0_8 = mux(winner_8[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_8 = mux(winner_8[1], beatsDO_1, UInt<1>(0h0))
node initBeats_8 = or(maskedBeats_0_8, maskedBeats_1_8)
node _beatsLeft_T_32 = and(in[6].d.ready, in[6].d.valid)
node _beatsLeft_T_33 = sub(beatsLeft_8, _beatsLeft_T_32)
node _beatsLeft_T_34 = tail(_beatsLeft_T_33, 1)
node _beatsLeft_T_35 = mux(latch_8, initBeats_8, _beatsLeft_T_34)
connect beatsLeft_8, _beatsLeft_T_35
wire _state_WIRE_8 : UInt<1>[2]
connect _state_WIRE_8[0], UInt<1>(0h0)
connect _state_WIRE_8[1], UInt<1>(0h0)
regreset state_8 : UInt<1>[2], clock, reset, _state_WIRE_8
node muxState_8 = mux(idle_8, winner_8, state_8)
connect state_8, muxState_8
node allowed_8 = mux(idle_8, readys_8, state_8)
node _filtered_6_ready_T = and(in[6].d.ready, allowed_8[0])
connect portsDIO_filtered[6].ready, _filtered_6_ready_T
node _filtered_6_ready_T_1 = and(in[6].d.ready, allowed_8[1])
connect portsDIO_filtered_1[6].ready, _filtered_6_ready_T_1
node _in_6_d_valid_T = or(portsDIO_filtered[6].valid, portsDIO_filtered_1[6].valid)
node _in_6_d_valid_T_1 = mux(state_8[0], portsDIO_filtered[6].valid, UInt<1>(0h0))
node _in_6_d_valid_T_2 = mux(state_8[1], portsDIO_filtered_1[6].valid, UInt<1>(0h0))
node _in_6_d_valid_T_3 = or(_in_6_d_valid_T_1, _in_6_d_valid_T_2)
wire _in_6_d_valid_WIRE : UInt<1>
connect _in_6_d_valid_WIRE, _in_6_d_valid_T_3
node _in_6_d_valid_T_4 = mux(idle_8, _in_6_d_valid_T, _in_6_d_valid_WIRE)
connect in[6].d.valid, _in_6_d_valid_T_4
wire _in_6_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_6_d_bits_T = mux(muxState_8[0], portsDIO_filtered[6].bits.corrupt, UInt<1>(0h0))
node _in_6_d_bits_T_1 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.corrupt, UInt<1>(0h0))
node _in_6_d_bits_T_2 = or(_in_6_d_bits_T, _in_6_d_bits_T_1)
wire _in_6_d_bits_WIRE_1 : UInt<1>
connect _in_6_d_bits_WIRE_1, _in_6_d_bits_T_2
connect _in_6_d_bits_WIRE.corrupt, _in_6_d_bits_WIRE_1
node _in_6_d_bits_T_3 = mux(muxState_8[0], portsDIO_filtered[6].bits.data, UInt<1>(0h0))
node _in_6_d_bits_T_4 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.data, UInt<1>(0h0))
node _in_6_d_bits_T_5 = or(_in_6_d_bits_T_3, _in_6_d_bits_T_4)
wire _in_6_d_bits_WIRE_2 : UInt<64>
connect _in_6_d_bits_WIRE_2, _in_6_d_bits_T_5
connect _in_6_d_bits_WIRE.data, _in_6_d_bits_WIRE_2
wire _in_6_d_bits_WIRE_3 : { }
connect _in_6_d_bits_WIRE.echo, _in_6_d_bits_WIRE_3
wire _in_6_d_bits_WIRE_4 : { }
connect _in_6_d_bits_WIRE.user, _in_6_d_bits_WIRE_4
node _in_6_d_bits_T_6 = mux(muxState_8[0], portsDIO_filtered[6].bits.denied, UInt<1>(0h0))
node _in_6_d_bits_T_7 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.denied, UInt<1>(0h0))
node _in_6_d_bits_T_8 = or(_in_6_d_bits_T_6, _in_6_d_bits_T_7)
wire _in_6_d_bits_WIRE_5 : UInt<1>
connect _in_6_d_bits_WIRE_5, _in_6_d_bits_T_8
connect _in_6_d_bits_WIRE.denied, _in_6_d_bits_WIRE_5
node _in_6_d_bits_T_9 = mux(muxState_8[0], portsDIO_filtered[6].bits.sink, UInt<1>(0h0))
node _in_6_d_bits_T_10 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.sink, UInt<1>(0h0))
node _in_6_d_bits_T_11 = or(_in_6_d_bits_T_9, _in_6_d_bits_T_10)
wire _in_6_d_bits_WIRE_6 : UInt<3>
connect _in_6_d_bits_WIRE_6, _in_6_d_bits_T_11
connect _in_6_d_bits_WIRE.sink, _in_6_d_bits_WIRE_6
node _in_6_d_bits_T_12 = mux(muxState_8[0], portsDIO_filtered[6].bits.source, UInt<1>(0h0))
node _in_6_d_bits_T_13 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.source, UInt<1>(0h0))
node _in_6_d_bits_T_14 = or(_in_6_d_bits_T_12, _in_6_d_bits_T_13)
wire _in_6_d_bits_WIRE_7 : UInt<9>
connect _in_6_d_bits_WIRE_7, _in_6_d_bits_T_14
connect _in_6_d_bits_WIRE.source, _in_6_d_bits_WIRE_7
node _in_6_d_bits_T_15 = mux(muxState_8[0], portsDIO_filtered[6].bits.size, UInt<1>(0h0))
node _in_6_d_bits_T_16 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.size, UInt<1>(0h0))
node _in_6_d_bits_T_17 = or(_in_6_d_bits_T_15, _in_6_d_bits_T_16)
wire _in_6_d_bits_WIRE_8 : UInt<4>
connect _in_6_d_bits_WIRE_8, _in_6_d_bits_T_17
connect _in_6_d_bits_WIRE.size, _in_6_d_bits_WIRE_8
node _in_6_d_bits_T_18 = mux(muxState_8[0], portsDIO_filtered[6].bits.param, UInt<1>(0h0))
node _in_6_d_bits_T_19 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.param, UInt<1>(0h0))
node _in_6_d_bits_T_20 = or(_in_6_d_bits_T_18, _in_6_d_bits_T_19)
wire _in_6_d_bits_WIRE_9 : UInt<2>
connect _in_6_d_bits_WIRE_9, _in_6_d_bits_T_20
connect _in_6_d_bits_WIRE.param, _in_6_d_bits_WIRE_9
node _in_6_d_bits_T_21 = mux(muxState_8[0], portsDIO_filtered[6].bits.opcode, UInt<1>(0h0))
node _in_6_d_bits_T_22 = mux(muxState_8[1], portsDIO_filtered_1[6].bits.opcode, UInt<1>(0h0))
node _in_6_d_bits_T_23 = or(_in_6_d_bits_T_21, _in_6_d_bits_T_22)
wire _in_6_d_bits_WIRE_10 : UInt<3>
connect _in_6_d_bits_WIRE_10, _in_6_d_bits_T_23
connect _in_6_d_bits_WIRE.opcode, _in_6_d_bits_WIRE_10
connect in[6].d.bits.corrupt, _in_6_d_bits_WIRE.corrupt
connect in[6].d.bits.data, _in_6_d_bits_WIRE.data
connect in[6].d.bits.denied, _in_6_d_bits_WIRE.denied
connect in[6].d.bits.sink, _in_6_d_bits_WIRE.sink
connect in[6].d.bits.source, _in_6_d_bits_WIRE.source
connect in[6].d.bits.size, _in_6_d_bits_WIRE.size
connect in[6].d.bits.param, _in_6_d_bits_WIRE.param
connect in[6].d.bits.opcode, _in_6_d_bits_WIRE.opcode
connect portsBIO_filtered[6].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[6].ready, UInt<1>(0h0)
invalidate in[7].b.bits.corrupt
invalidate in[7].b.bits.data
invalidate in[7].b.bits.mask
invalidate in[7].b.bits.address
invalidate in[7].b.bits.source
invalidate in[7].b.bits.size
invalidate in[7].b.bits.param
invalidate in[7].b.bits.opcode
regreset beatsLeft_9 : UInt, clock, reset, UInt<1>(0h0)
node idle_9 = eq(beatsLeft_9, UInt<1>(0h0))
node latch_9 = and(idle_9, in[7].d.ready)
node _readys_T_126 = cat(portsDIO_filtered_1[7].valid, portsDIO_filtered[7].valid)
node readys_valid_9 = bits(_readys_T_126, 1, 0)
node _readys_T_127 = eq(readys_valid_9, _readys_T_126)
node _readys_T_128 = asUInt(reset)
node _readys_T_129 = eq(_readys_T_128, UInt<1>(0h0))
when _readys_T_129 :
node _readys_T_130 = eq(_readys_T_127, UInt<1>(0h0))
when _readys_T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_9
assert(clock, _readys_T_127, UInt<1>(0h1), "") : readys_assert_9
regreset readys_mask_9 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_18 = not(readys_mask_9)
node _readys_filter_T_19 = and(readys_valid_9, _readys_filter_T_18)
node readys_filter_9 = cat(_readys_filter_T_19, readys_valid_9)
node _readys_unready_T_61 = shr(readys_filter_9, 1)
node _readys_unready_T_62 = or(readys_filter_9, _readys_unready_T_61)
node _readys_unready_T_63 = bits(_readys_unready_T_62, 3, 0)
node _readys_unready_T_64 = shr(_readys_unready_T_63, 1)
node _readys_unready_T_65 = shl(readys_mask_9, 2)
node readys_unready_9 = or(_readys_unready_T_64, _readys_unready_T_65)
node _readys_readys_T_27 = shr(readys_unready_9, 2)
node _readys_readys_T_28 = bits(readys_unready_9, 1, 0)
node _readys_readys_T_29 = and(_readys_readys_T_27, _readys_readys_T_28)
node readys_readys_9 = not(_readys_readys_T_29)
node _readys_T_131 = orr(readys_valid_9)
node _readys_T_132 = and(latch_9, _readys_T_131)
when _readys_T_132 :
node _readys_mask_T_69 = and(readys_readys_9, readys_valid_9)
node _readys_mask_T_70 = shl(_readys_mask_T_69, 1)
node _readys_mask_T_71 = bits(_readys_mask_T_70, 1, 0)
node _readys_mask_T_72 = or(_readys_mask_T_69, _readys_mask_T_71)
node _readys_mask_T_73 = bits(_readys_mask_T_72, 1, 0)
connect readys_mask_9, _readys_mask_T_73
node _readys_T_133 = bits(readys_readys_9, 1, 0)
node _readys_T_134 = bits(_readys_T_133, 0, 0)
node _readys_T_135 = bits(_readys_T_133, 1, 1)
wire readys_9 : UInt<1>[2]
connect readys_9[0], _readys_T_134
connect readys_9[1], _readys_T_135
node _winner_T_54 = and(readys_9[0], portsDIO_filtered[7].valid)
node _winner_T_55 = and(readys_9[1], portsDIO_filtered_1[7].valid)
wire winner_9 : UInt<1>[2]
connect winner_9[0], _winner_T_54
connect winner_9[1], _winner_T_55
node prefixOR_1_9 = or(UInt<1>(0h0), winner_9[0])
node _prefixOR_T_9 = or(prefixOR_1_9, winner_9[1])
node _T_369 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_370 = eq(winner_9[0], UInt<1>(0h0))
node _T_371 = or(_T_369, _T_370)
node _T_372 = eq(prefixOR_1_9, UInt<1>(0h0))
node _T_373 = eq(winner_9[1], UInt<1>(0h0))
node _T_374 = or(_T_372, _T_373)
node _T_375 = and(_T_371, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_18
assert(clock, _T_375, UInt<1>(0h1), "") : assert_18
node _T_379 = or(portsDIO_filtered[7].valid, portsDIO_filtered_1[7].valid)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = or(winner_9[0], winner_9[1])
node _T_382 = or(_T_380, _T_381)
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_19
assert(clock, _T_382, UInt<1>(0h1), "") : assert_19
node maskedBeats_0_9 = mux(winner_9[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_9 = mux(winner_9[1], beatsDO_1, UInt<1>(0h0))
node initBeats_9 = or(maskedBeats_0_9, maskedBeats_1_9)
node _beatsLeft_T_36 = and(in[7].d.ready, in[7].d.valid)
node _beatsLeft_T_37 = sub(beatsLeft_9, _beatsLeft_T_36)
node _beatsLeft_T_38 = tail(_beatsLeft_T_37, 1)
node _beatsLeft_T_39 = mux(latch_9, initBeats_9, _beatsLeft_T_38)
connect beatsLeft_9, _beatsLeft_T_39
wire _state_WIRE_9 : UInt<1>[2]
connect _state_WIRE_9[0], UInt<1>(0h0)
connect _state_WIRE_9[1], UInt<1>(0h0)
regreset state_9 : UInt<1>[2], clock, reset, _state_WIRE_9
node muxState_9 = mux(idle_9, winner_9, state_9)
connect state_9, muxState_9
node allowed_9 = mux(idle_9, readys_9, state_9)
node _filtered_7_ready_T = and(in[7].d.ready, allowed_9[0])
connect portsDIO_filtered[7].ready, _filtered_7_ready_T
node _filtered_7_ready_T_1 = and(in[7].d.ready, allowed_9[1])
connect portsDIO_filtered_1[7].ready, _filtered_7_ready_T_1
node _in_7_d_valid_T = or(portsDIO_filtered[7].valid, portsDIO_filtered_1[7].valid)
node _in_7_d_valid_T_1 = mux(state_9[0], portsDIO_filtered[7].valid, UInt<1>(0h0))
node _in_7_d_valid_T_2 = mux(state_9[1], portsDIO_filtered_1[7].valid, UInt<1>(0h0))
node _in_7_d_valid_T_3 = or(_in_7_d_valid_T_1, _in_7_d_valid_T_2)
wire _in_7_d_valid_WIRE : UInt<1>
connect _in_7_d_valid_WIRE, _in_7_d_valid_T_3
node _in_7_d_valid_T_4 = mux(idle_9, _in_7_d_valid_T, _in_7_d_valid_WIRE)
connect in[7].d.valid, _in_7_d_valid_T_4
wire _in_7_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_7_d_bits_T = mux(muxState_9[0], portsDIO_filtered[7].bits.corrupt, UInt<1>(0h0))
node _in_7_d_bits_T_1 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.corrupt, UInt<1>(0h0))
node _in_7_d_bits_T_2 = or(_in_7_d_bits_T, _in_7_d_bits_T_1)
wire _in_7_d_bits_WIRE_1 : UInt<1>
connect _in_7_d_bits_WIRE_1, _in_7_d_bits_T_2
connect _in_7_d_bits_WIRE.corrupt, _in_7_d_bits_WIRE_1
node _in_7_d_bits_T_3 = mux(muxState_9[0], portsDIO_filtered[7].bits.data, UInt<1>(0h0))
node _in_7_d_bits_T_4 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.data, UInt<1>(0h0))
node _in_7_d_bits_T_5 = or(_in_7_d_bits_T_3, _in_7_d_bits_T_4)
wire _in_7_d_bits_WIRE_2 : UInt<64>
connect _in_7_d_bits_WIRE_2, _in_7_d_bits_T_5
connect _in_7_d_bits_WIRE.data, _in_7_d_bits_WIRE_2
wire _in_7_d_bits_WIRE_3 : { }
connect _in_7_d_bits_WIRE.echo, _in_7_d_bits_WIRE_3
wire _in_7_d_bits_WIRE_4 : { }
connect _in_7_d_bits_WIRE.user, _in_7_d_bits_WIRE_4
node _in_7_d_bits_T_6 = mux(muxState_9[0], portsDIO_filtered[7].bits.denied, UInt<1>(0h0))
node _in_7_d_bits_T_7 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.denied, UInt<1>(0h0))
node _in_7_d_bits_T_8 = or(_in_7_d_bits_T_6, _in_7_d_bits_T_7)
wire _in_7_d_bits_WIRE_5 : UInt<1>
connect _in_7_d_bits_WIRE_5, _in_7_d_bits_T_8
connect _in_7_d_bits_WIRE.denied, _in_7_d_bits_WIRE_5
node _in_7_d_bits_T_9 = mux(muxState_9[0], portsDIO_filtered[7].bits.sink, UInt<1>(0h0))
node _in_7_d_bits_T_10 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.sink, UInt<1>(0h0))
node _in_7_d_bits_T_11 = or(_in_7_d_bits_T_9, _in_7_d_bits_T_10)
wire _in_7_d_bits_WIRE_6 : UInt<3>
connect _in_7_d_bits_WIRE_6, _in_7_d_bits_T_11
connect _in_7_d_bits_WIRE.sink, _in_7_d_bits_WIRE_6
node _in_7_d_bits_T_12 = mux(muxState_9[0], portsDIO_filtered[7].bits.source, UInt<1>(0h0))
node _in_7_d_bits_T_13 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.source, UInt<1>(0h0))
node _in_7_d_bits_T_14 = or(_in_7_d_bits_T_12, _in_7_d_bits_T_13)
wire _in_7_d_bits_WIRE_7 : UInt<9>
connect _in_7_d_bits_WIRE_7, _in_7_d_bits_T_14
connect _in_7_d_bits_WIRE.source, _in_7_d_bits_WIRE_7
node _in_7_d_bits_T_15 = mux(muxState_9[0], portsDIO_filtered[7].bits.size, UInt<1>(0h0))
node _in_7_d_bits_T_16 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.size, UInt<1>(0h0))
node _in_7_d_bits_T_17 = or(_in_7_d_bits_T_15, _in_7_d_bits_T_16)
wire _in_7_d_bits_WIRE_8 : UInt<4>
connect _in_7_d_bits_WIRE_8, _in_7_d_bits_T_17
connect _in_7_d_bits_WIRE.size, _in_7_d_bits_WIRE_8
node _in_7_d_bits_T_18 = mux(muxState_9[0], portsDIO_filtered[7].bits.param, UInt<1>(0h0))
node _in_7_d_bits_T_19 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.param, UInt<1>(0h0))
node _in_7_d_bits_T_20 = or(_in_7_d_bits_T_18, _in_7_d_bits_T_19)
wire _in_7_d_bits_WIRE_9 : UInt<2>
connect _in_7_d_bits_WIRE_9, _in_7_d_bits_T_20
connect _in_7_d_bits_WIRE.param, _in_7_d_bits_WIRE_9
node _in_7_d_bits_T_21 = mux(muxState_9[0], portsDIO_filtered[7].bits.opcode, UInt<1>(0h0))
node _in_7_d_bits_T_22 = mux(muxState_9[1], portsDIO_filtered_1[7].bits.opcode, UInt<1>(0h0))
node _in_7_d_bits_T_23 = or(_in_7_d_bits_T_21, _in_7_d_bits_T_22)
wire _in_7_d_bits_WIRE_10 : UInt<3>
connect _in_7_d_bits_WIRE_10, _in_7_d_bits_T_23
connect _in_7_d_bits_WIRE.opcode, _in_7_d_bits_WIRE_10
connect in[7].d.bits.corrupt, _in_7_d_bits_WIRE.corrupt
connect in[7].d.bits.data, _in_7_d_bits_WIRE.data
connect in[7].d.bits.denied, _in_7_d_bits_WIRE.denied
connect in[7].d.bits.sink, _in_7_d_bits_WIRE.sink
connect in[7].d.bits.source, _in_7_d_bits_WIRE.source
connect in[7].d.bits.size, _in_7_d_bits_WIRE.size
connect in[7].d.bits.param, _in_7_d_bits_WIRE.param
connect in[7].d.bits.opcode, _in_7_d_bits_WIRE.opcode
connect portsBIO_filtered[7].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[7].ready, UInt<1>(0h0)
invalidate in[8].b.bits.corrupt
invalidate in[8].b.bits.data
invalidate in[8].b.bits.mask
invalidate in[8].b.bits.address
invalidate in[8].b.bits.source
invalidate in[8].b.bits.size
invalidate in[8].b.bits.param
invalidate in[8].b.bits.opcode
regreset beatsLeft_10 : UInt, clock, reset, UInt<1>(0h0)
node idle_10 = eq(beatsLeft_10, UInt<1>(0h0))
node latch_10 = and(idle_10, in[8].d.ready)
node _readys_T_136 = cat(portsDIO_filtered_1[8].valid, portsDIO_filtered[8].valid)
node readys_valid_10 = bits(_readys_T_136, 1, 0)
node _readys_T_137 = eq(readys_valid_10, _readys_T_136)
node _readys_T_138 = asUInt(reset)
node _readys_T_139 = eq(_readys_T_138, UInt<1>(0h0))
when _readys_T_139 :
node _readys_T_140 = eq(_readys_T_137, UInt<1>(0h0))
when _readys_T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_10
assert(clock, _readys_T_137, UInt<1>(0h1), "") : readys_assert_10
regreset readys_mask_10 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_20 = not(readys_mask_10)
node _readys_filter_T_21 = and(readys_valid_10, _readys_filter_T_20)
node readys_filter_10 = cat(_readys_filter_T_21, readys_valid_10)
node _readys_unready_T_66 = shr(readys_filter_10, 1)
node _readys_unready_T_67 = or(readys_filter_10, _readys_unready_T_66)
node _readys_unready_T_68 = bits(_readys_unready_T_67, 3, 0)
node _readys_unready_T_69 = shr(_readys_unready_T_68, 1)
node _readys_unready_T_70 = shl(readys_mask_10, 2)
node readys_unready_10 = or(_readys_unready_T_69, _readys_unready_T_70)
node _readys_readys_T_30 = shr(readys_unready_10, 2)
node _readys_readys_T_31 = bits(readys_unready_10, 1, 0)
node _readys_readys_T_32 = and(_readys_readys_T_30, _readys_readys_T_31)
node readys_readys_10 = not(_readys_readys_T_32)
node _readys_T_141 = orr(readys_valid_10)
node _readys_T_142 = and(latch_10, _readys_T_141)
when _readys_T_142 :
node _readys_mask_T_74 = and(readys_readys_10, readys_valid_10)
node _readys_mask_T_75 = shl(_readys_mask_T_74, 1)
node _readys_mask_T_76 = bits(_readys_mask_T_75, 1, 0)
node _readys_mask_T_77 = or(_readys_mask_T_74, _readys_mask_T_76)
node _readys_mask_T_78 = bits(_readys_mask_T_77, 1, 0)
connect readys_mask_10, _readys_mask_T_78
node _readys_T_143 = bits(readys_readys_10, 1, 0)
node _readys_T_144 = bits(_readys_T_143, 0, 0)
node _readys_T_145 = bits(_readys_T_143, 1, 1)
wire readys_10 : UInt<1>[2]
connect readys_10[0], _readys_T_144
connect readys_10[1], _readys_T_145
node _winner_T_56 = and(readys_10[0], portsDIO_filtered[8].valid)
node _winner_T_57 = and(readys_10[1], portsDIO_filtered_1[8].valid)
wire winner_10 : UInt<1>[2]
connect winner_10[0], _winner_T_56
connect winner_10[1], _winner_T_57
node prefixOR_1_10 = or(UInt<1>(0h0), winner_10[0])
node _prefixOR_T_10 = or(prefixOR_1_10, winner_10[1])
node _T_386 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_387 = eq(winner_10[0], UInt<1>(0h0))
node _T_388 = or(_T_386, _T_387)
node _T_389 = eq(prefixOR_1_10, UInt<1>(0h0))
node _T_390 = eq(winner_10[1], UInt<1>(0h0))
node _T_391 = or(_T_389, _T_390)
node _T_392 = and(_T_388, _T_391)
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_20
assert(clock, _T_392, UInt<1>(0h1), "") : assert_20
node _T_396 = or(portsDIO_filtered[8].valid, portsDIO_filtered_1[8].valid)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = or(winner_10[0], winner_10[1])
node _T_399 = or(_T_397, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_21
assert(clock, _T_399, UInt<1>(0h1), "") : assert_21
node maskedBeats_0_10 = mux(winner_10[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_10 = mux(winner_10[1], beatsDO_1, UInt<1>(0h0))
node initBeats_10 = or(maskedBeats_0_10, maskedBeats_1_10)
node _beatsLeft_T_40 = and(in[8].d.ready, in[8].d.valid)
node _beatsLeft_T_41 = sub(beatsLeft_10, _beatsLeft_T_40)
node _beatsLeft_T_42 = tail(_beatsLeft_T_41, 1)
node _beatsLeft_T_43 = mux(latch_10, initBeats_10, _beatsLeft_T_42)
connect beatsLeft_10, _beatsLeft_T_43
wire _state_WIRE_10 : UInt<1>[2]
connect _state_WIRE_10[0], UInt<1>(0h0)
connect _state_WIRE_10[1], UInt<1>(0h0)
regreset state_10 : UInt<1>[2], clock, reset, _state_WIRE_10
node muxState_10 = mux(idle_10, winner_10, state_10)
connect state_10, muxState_10
node allowed_10 = mux(idle_10, readys_10, state_10)
node _filtered_8_ready_T = and(in[8].d.ready, allowed_10[0])
connect portsDIO_filtered[8].ready, _filtered_8_ready_T
node _filtered_8_ready_T_1 = and(in[8].d.ready, allowed_10[1])
connect portsDIO_filtered_1[8].ready, _filtered_8_ready_T_1
node _in_8_d_valid_T = or(portsDIO_filtered[8].valid, portsDIO_filtered_1[8].valid)
node _in_8_d_valid_T_1 = mux(state_10[0], portsDIO_filtered[8].valid, UInt<1>(0h0))
node _in_8_d_valid_T_2 = mux(state_10[1], portsDIO_filtered_1[8].valid, UInt<1>(0h0))
node _in_8_d_valid_T_3 = or(_in_8_d_valid_T_1, _in_8_d_valid_T_2)
wire _in_8_d_valid_WIRE : UInt<1>
connect _in_8_d_valid_WIRE, _in_8_d_valid_T_3
node _in_8_d_valid_T_4 = mux(idle_10, _in_8_d_valid_T, _in_8_d_valid_WIRE)
connect in[8].d.valid, _in_8_d_valid_T_4
wire _in_8_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_8_d_bits_T = mux(muxState_10[0], portsDIO_filtered[8].bits.corrupt, UInt<1>(0h0))
node _in_8_d_bits_T_1 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.corrupt, UInt<1>(0h0))
node _in_8_d_bits_T_2 = or(_in_8_d_bits_T, _in_8_d_bits_T_1)
wire _in_8_d_bits_WIRE_1 : UInt<1>
connect _in_8_d_bits_WIRE_1, _in_8_d_bits_T_2
connect _in_8_d_bits_WIRE.corrupt, _in_8_d_bits_WIRE_1
node _in_8_d_bits_T_3 = mux(muxState_10[0], portsDIO_filtered[8].bits.data, UInt<1>(0h0))
node _in_8_d_bits_T_4 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.data, UInt<1>(0h0))
node _in_8_d_bits_T_5 = or(_in_8_d_bits_T_3, _in_8_d_bits_T_4)
wire _in_8_d_bits_WIRE_2 : UInt<64>
connect _in_8_d_bits_WIRE_2, _in_8_d_bits_T_5
connect _in_8_d_bits_WIRE.data, _in_8_d_bits_WIRE_2
wire _in_8_d_bits_WIRE_3 : { }
connect _in_8_d_bits_WIRE.echo, _in_8_d_bits_WIRE_3
wire _in_8_d_bits_WIRE_4 : { }
connect _in_8_d_bits_WIRE.user, _in_8_d_bits_WIRE_4
node _in_8_d_bits_T_6 = mux(muxState_10[0], portsDIO_filtered[8].bits.denied, UInt<1>(0h0))
node _in_8_d_bits_T_7 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.denied, UInt<1>(0h0))
node _in_8_d_bits_T_8 = or(_in_8_d_bits_T_6, _in_8_d_bits_T_7)
wire _in_8_d_bits_WIRE_5 : UInt<1>
connect _in_8_d_bits_WIRE_5, _in_8_d_bits_T_8
connect _in_8_d_bits_WIRE.denied, _in_8_d_bits_WIRE_5
node _in_8_d_bits_T_9 = mux(muxState_10[0], portsDIO_filtered[8].bits.sink, UInt<1>(0h0))
node _in_8_d_bits_T_10 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.sink, UInt<1>(0h0))
node _in_8_d_bits_T_11 = or(_in_8_d_bits_T_9, _in_8_d_bits_T_10)
wire _in_8_d_bits_WIRE_6 : UInt<3>
connect _in_8_d_bits_WIRE_6, _in_8_d_bits_T_11
connect _in_8_d_bits_WIRE.sink, _in_8_d_bits_WIRE_6
node _in_8_d_bits_T_12 = mux(muxState_10[0], portsDIO_filtered[8].bits.source, UInt<1>(0h0))
node _in_8_d_bits_T_13 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.source, UInt<1>(0h0))
node _in_8_d_bits_T_14 = or(_in_8_d_bits_T_12, _in_8_d_bits_T_13)
wire _in_8_d_bits_WIRE_7 : UInt<9>
connect _in_8_d_bits_WIRE_7, _in_8_d_bits_T_14
connect _in_8_d_bits_WIRE.source, _in_8_d_bits_WIRE_7
node _in_8_d_bits_T_15 = mux(muxState_10[0], portsDIO_filtered[8].bits.size, UInt<1>(0h0))
node _in_8_d_bits_T_16 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.size, UInt<1>(0h0))
node _in_8_d_bits_T_17 = or(_in_8_d_bits_T_15, _in_8_d_bits_T_16)
wire _in_8_d_bits_WIRE_8 : UInt<4>
connect _in_8_d_bits_WIRE_8, _in_8_d_bits_T_17
connect _in_8_d_bits_WIRE.size, _in_8_d_bits_WIRE_8
node _in_8_d_bits_T_18 = mux(muxState_10[0], portsDIO_filtered[8].bits.param, UInt<1>(0h0))
node _in_8_d_bits_T_19 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.param, UInt<1>(0h0))
node _in_8_d_bits_T_20 = or(_in_8_d_bits_T_18, _in_8_d_bits_T_19)
wire _in_8_d_bits_WIRE_9 : UInt<2>
connect _in_8_d_bits_WIRE_9, _in_8_d_bits_T_20
connect _in_8_d_bits_WIRE.param, _in_8_d_bits_WIRE_9
node _in_8_d_bits_T_21 = mux(muxState_10[0], portsDIO_filtered[8].bits.opcode, UInt<1>(0h0))
node _in_8_d_bits_T_22 = mux(muxState_10[1], portsDIO_filtered_1[8].bits.opcode, UInt<1>(0h0))
node _in_8_d_bits_T_23 = or(_in_8_d_bits_T_21, _in_8_d_bits_T_22)
wire _in_8_d_bits_WIRE_10 : UInt<3>
connect _in_8_d_bits_WIRE_10, _in_8_d_bits_T_23
connect _in_8_d_bits_WIRE.opcode, _in_8_d_bits_WIRE_10
connect in[8].d.bits.corrupt, _in_8_d_bits_WIRE.corrupt
connect in[8].d.bits.data, _in_8_d_bits_WIRE.data
connect in[8].d.bits.denied, _in_8_d_bits_WIRE.denied
connect in[8].d.bits.sink, _in_8_d_bits_WIRE.sink
connect in[8].d.bits.source, _in_8_d_bits_WIRE.source
connect in[8].d.bits.size, _in_8_d_bits_WIRE.size
connect in[8].d.bits.param, _in_8_d_bits_WIRE.param
connect in[8].d.bits.opcode, _in_8_d_bits_WIRE.opcode
connect portsBIO_filtered[8].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[8].ready, UInt<1>(0h0)
invalidate in[9].b.bits.corrupt
invalidate in[9].b.bits.data
invalidate in[9].b.bits.mask
invalidate in[9].b.bits.address
invalidate in[9].b.bits.source
invalidate in[9].b.bits.size
invalidate in[9].b.bits.param
invalidate in[9].b.bits.opcode
regreset beatsLeft_11 : UInt, clock, reset, UInt<1>(0h0)
node idle_11 = eq(beatsLeft_11, UInt<1>(0h0))
node latch_11 = and(idle_11, in[9].d.ready)
node _readys_T_146 = cat(portsDIO_filtered_1[9].valid, portsDIO_filtered[9].valid)
node readys_valid_11 = bits(_readys_T_146, 1, 0)
node _readys_T_147 = eq(readys_valid_11, _readys_T_146)
node _readys_T_148 = asUInt(reset)
node _readys_T_149 = eq(_readys_T_148, UInt<1>(0h0))
when _readys_T_149 :
node _readys_T_150 = eq(_readys_T_147, UInt<1>(0h0))
when _readys_T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_11
assert(clock, _readys_T_147, UInt<1>(0h1), "") : readys_assert_11
regreset readys_mask_11 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_22 = not(readys_mask_11)
node _readys_filter_T_23 = and(readys_valid_11, _readys_filter_T_22)
node readys_filter_11 = cat(_readys_filter_T_23, readys_valid_11)
node _readys_unready_T_71 = shr(readys_filter_11, 1)
node _readys_unready_T_72 = or(readys_filter_11, _readys_unready_T_71)
node _readys_unready_T_73 = bits(_readys_unready_T_72, 3, 0)
node _readys_unready_T_74 = shr(_readys_unready_T_73, 1)
node _readys_unready_T_75 = shl(readys_mask_11, 2)
node readys_unready_11 = or(_readys_unready_T_74, _readys_unready_T_75)
node _readys_readys_T_33 = shr(readys_unready_11, 2)
node _readys_readys_T_34 = bits(readys_unready_11, 1, 0)
node _readys_readys_T_35 = and(_readys_readys_T_33, _readys_readys_T_34)
node readys_readys_11 = not(_readys_readys_T_35)
node _readys_T_151 = orr(readys_valid_11)
node _readys_T_152 = and(latch_11, _readys_T_151)
when _readys_T_152 :
node _readys_mask_T_79 = and(readys_readys_11, readys_valid_11)
node _readys_mask_T_80 = shl(_readys_mask_T_79, 1)
node _readys_mask_T_81 = bits(_readys_mask_T_80, 1, 0)
node _readys_mask_T_82 = or(_readys_mask_T_79, _readys_mask_T_81)
node _readys_mask_T_83 = bits(_readys_mask_T_82, 1, 0)
connect readys_mask_11, _readys_mask_T_83
node _readys_T_153 = bits(readys_readys_11, 1, 0)
node _readys_T_154 = bits(_readys_T_153, 0, 0)
node _readys_T_155 = bits(_readys_T_153, 1, 1)
wire readys_11 : UInt<1>[2]
connect readys_11[0], _readys_T_154
connect readys_11[1], _readys_T_155
node _winner_T_58 = and(readys_11[0], portsDIO_filtered[9].valid)
node _winner_T_59 = and(readys_11[1], portsDIO_filtered_1[9].valid)
wire winner_11 : UInt<1>[2]
connect winner_11[0], _winner_T_58
connect winner_11[1], _winner_T_59
node prefixOR_1_11 = or(UInt<1>(0h0), winner_11[0])
node _prefixOR_T_11 = or(prefixOR_1_11, winner_11[1])
node _T_403 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_404 = eq(winner_11[0], UInt<1>(0h0))
node _T_405 = or(_T_403, _T_404)
node _T_406 = eq(prefixOR_1_11, UInt<1>(0h0))
node _T_407 = eq(winner_11[1], UInt<1>(0h0))
node _T_408 = or(_T_406, _T_407)
node _T_409 = and(_T_405, _T_408)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_22
assert(clock, _T_409, UInt<1>(0h1), "") : assert_22
node _T_413 = or(portsDIO_filtered[9].valid, portsDIO_filtered_1[9].valid)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = or(winner_11[0], winner_11[1])
node _T_416 = or(_T_414, _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_23
assert(clock, _T_416, UInt<1>(0h1), "") : assert_23
node maskedBeats_0_11 = mux(winner_11[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_11 = mux(winner_11[1], beatsDO_1, UInt<1>(0h0))
node initBeats_11 = or(maskedBeats_0_11, maskedBeats_1_11)
node _beatsLeft_T_44 = and(in[9].d.ready, in[9].d.valid)
node _beatsLeft_T_45 = sub(beatsLeft_11, _beatsLeft_T_44)
node _beatsLeft_T_46 = tail(_beatsLeft_T_45, 1)
node _beatsLeft_T_47 = mux(latch_11, initBeats_11, _beatsLeft_T_46)
connect beatsLeft_11, _beatsLeft_T_47
wire _state_WIRE_11 : UInt<1>[2]
connect _state_WIRE_11[0], UInt<1>(0h0)
connect _state_WIRE_11[1], UInt<1>(0h0)
regreset state_11 : UInt<1>[2], clock, reset, _state_WIRE_11
node muxState_11 = mux(idle_11, winner_11, state_11)
connect state_11, muxState_11
node allowed_11 = mux(idle_11, readys_11, state_11)
node _filtered_9_ready_T = and(in[9].d.ready, allowed_11[0])
connect portsDIO_filtered[9].ready, _filtered_9_ready_T
node _filtered_9_ready_T_1 = and(in[9].d.ready, allowed_11[1])
connect portsDIO_filtered_1[9].ready, _filtered_9_ready_T_1
node _in_9_d_valid_T = or(portsDIO_filtered[9].valid, portsDIO_filtered_1[9].valid)
node _in_9_d_valid_T_1 = mux(state_11[0], portsDIO_filtered[9].valid, UInt<1>(0h0))
node _in_9_d_valid_T_2 = mux(state_11[1], portsDIO_filtered_1[9].valid, UInt<1>(0h0))
node _in_9_d_valid_T_3 = or(_in_9_d_valid_T_1, _in_9_d_valid_T_2)
wire _in_9_d_valid_WIRE : UInt<1>
connect _in_9_d_valid_WIRE, _in_9_d_valid_T_3
node _in_9_d_valid_T_4 = mux(idle_11, _in_9_d_valid_T, _in_9_d_valid_WIRE)
connect in[9].d.valid, _in_9_d_valid_T_4
wire _in_9_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_9_d_bits_T = mux(muxState_11[0], portsDIO_filtered[9].bits.corrupt, UInt<1>(0h0))
node _in_9_d_bits_T_1 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.corrupt, UInt<1>(0h0))
node _in_9_d_bits_T_2 = or(_in_9_d_bits_T, _in_9_d_bits_T_1)
wire _in_9_d_bits_WIRE_1 : UInt<1>
connect _in_9_d_bits_WIRE_1, _in_9_d_bits_T_2
connect _in_9_d_bits_WIRE.corrupt, _in_9_d_bits_WIRE_1
node _in_9_d_bits_T_3 = mux(muxState_11[0], portsDIO_filtered[9].bits.data, UInt<1>(0h0))
node _in_9_d_bits_T_4 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.data, UInt<1>(0h0))
node _in_9_d_bits_T_5 = or(_in_9_d_bits_T_3, _in_9_d_bits_T_4)
wire _in_9_d_bits_WIRE_2 : UInt<64>
connect _in_9_d_bits_WIRE_2, _in_9_d_bits_T_5
connect _in_9_d_bits_WIRE.data, _in_9_d_bits_WIRE_2
wire _in_9_d_bits_WIRE_3 : { }
connect _in_9_d_bits_WIRE.echo, _in_9_d_bits_WIRE_3
wire _in_9_d_bits_WIRE_4 : { }
connect _in_9_d_bits_WIRE.user, _in_9_d_bits_WIRE_4
node _in_9_d_bits_T_6 = mux(muxState_11[0], portsDIO_filtered[9].bits.denied, UInt<1>(0h0))
node _in_9_d_bits_T_7 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.denied, UInt<1>(0h0))
node _in_9_d_bits_T_8 = or(_in_9_d_bits_T_6, _in_9_d_bits_T_7)
wire _in_9_d_bits_WIRE_5 : UInt<1>
connect _in_9_d_bits_WIRE_5, _in_9_d_bits_T_8
connect _in_9_d_bits_WIRE.denied, _in_9_d_bits_WIRE_5
node _in_9_d_bits_T_9 = mux(muxState_11[0], portsDIO_filtered[9].bits.sink, UInt<1>(0h0))
node _in_9_d_bits_T_10 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.sink, UInt<1>(0h0))
node _in_9_d_bits_T_11 = or(_in_9_d_bits_T_9, _in_9_d_bits_T_10)
wire _in_9_d_bits_WIRE_6 : UInt<3>
connect _in_9_d_bits_WIRE_6, _in_9_d_bits_T_11
connect _in_9_d_bits_WIRE.sink, _in_9_d_bits_WIRE_6
node _in_9_d_bits_T_12 = mux(muxState_11[0], portsDIO_filtered[9].bits.source, UInt<1>(0h0))
node _in_9_d_bits_T_13 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.source, UInt<1>(0h0))
node _in_9_d_bits_T_14 = or(_in_9_d_bits_T_12, _in_9_d_bits_T_13)
wire _in_9_d_bits_WIRE_7 : UInt<9>
connect _in_9_d_bits_WIRE_7, _in_9_d_bits_T_14
connect _in_9_d_bits_WIRE.source, _in_9_d_bits_WIRE_7
node _in_9_d_bits_T_15 = mux(muxState_11[0], portsDIO_filtered[9].bits.size, UInt<1>(0h0))
node _in_9_d_bits_T_16 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.size, UInt<1>(0h0))
node _in_9_d_bits_T_17 = or(_in_9_d_bits_T_15, _in_9_d_bits_T_16)
wire _in_9_d_bits_WIRE_8 : UInt<4>
connect _in_9_d_bits_WIRE_8, _in_9_d_bits_T_17
connect _in_9_d_bits_WIRE.size, _in_9_d_bits_WIRE_8
node _in_9_d_bits_T_18 = mux(muxState_11[0], portsDIO_filtered[9].bits.param, UInt<1>(0h0))
node _in_9_d_bits_T_19 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.param, UInt<1>(0h0))
node _in_9_d_bits_T_20 = or(_in_9_d_bits_T_18, _in_9_d_bits_T_19)
wire _in_9_d_bits_WIRE_9 : UInt<2>
connect _in_9_d_bits_WIRE_9, _in_9_d_bits_T_20
connect _in_9_d_bits_WIRE.param, _in_9_d_bits_WIRE_9
node _in_9_d_bits_T_21 = mux(muxState_11[0], portsDIO_filtered[9].bits.opcode, UInt<1>(0h0))
node _in_9_d_bits_T_22 = mux(muxState_11[1], portsDIO_filtered_1[9].bits.opcode, UInt<1>(0h0))
node _in_9_d_bits_T_23 = or(_in_9_d_bits_T_21, _in_9_d_bits_T_22)
wire _in_9_d_bits_WIRE_10 : UInt<3>
connect _in_9_d_bits_WIRE_10, _in_9_d_bits_T_23
connect _in_9_d_bits_WIRE.opcode, _in_9_d_bits_WIRE_10
connect in[9].d.bits.corrupt, _in_9_d_bits_WIRE.corrupt
connect in[9].d.bits.data, _in_9_d_bits_WIRE.data
connect in[9].d.bits.denied, _in_9_d_bits_WIRE.denied
connect in[9].d.bits.sink, _in_9_d_bits_WIRE.sink
connect in[9].d.bits.source, _in_9_d_bits_WIRE.source
connect in[9].d.bits.size, _in_9_d_bits_WIRE.size
connect in[9].d.bits.param, _in_9_d_bits_WIRE.param
connect in[9].d.bits.opcode, _in_9_d_bits_WIRE.opcode
connect portsBIO_filtered[9].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[9].ready, UInt<1>(0h0)
invalidate in[10].b.bits.corrupt
invalidate in[10].b.bits.data
invalidate in[10].b.bits.mask
invalidate in[10].b.bits.address
invalidate in[10].b.bits.source
invalidate in[10].b.bits.size
invalidate in[10].b.bits.param
invalidate in[10].b.bits.opcode
regreset beatsLeft_12 : UInt, clock, reset, UInt<1>(0h0)
node idle_12 = eq(beatsLeft_12, UInt<1>(0h0))
node latch_12 = and(idle_12, in[10].d.ready)
node _readys_T_156 = cat(portsDIO_filtered_1[10].valid, portsDIO_filtered[10].valid)
node readys_valid_12 = bits(_readys_T_156, 1, 0)
node _readys_T_157 = eq(readys_valid_12, _readys_T_156)
node _readys_T_158 = asUInt(reset)
node _readys_T_159 = eq(_readys_T_158, UInt<1>(0h0))
when _readys_T_159 :
node _readys_T_160 = eq(_readys_T_157, UInt<1>(0h0))
when _readys_T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_12
assert(clock, _readys_T_157, UInt<1>(0h1), "") : readys_assert_12
regreset readys_mask_12 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_24 = not(readys_mask_12)
node _readys_filter_T_25 = and(readys_valid_12, _readys_filter_T_24)
node readys_filter_12 = cat(_readys_filter_T_25, readys_valid_12)
node _readys_unready_T_76 = shr(readys_filter_12, 1)
node _readys_unready_T_77 = or(readys_filter_12, _readys_unready_T_76)
node _readys_unready_T_78 = bits(_readys_unready_T_77, 3, 0)
node _readys_unready_T_79 = shr(_readys_unready_T_78, 1)
node _readys_unready_T_80 = shl(readys_mask_12, 2)
node readys_unready_12 = or(_readys_unready_T_79, _readys_unready_T_80)
node _readys_readys_T_36 = shr(readys_unready_12, 2)
node _readys_readys_T_37 = bits(readys_unready_12, 1, 0)
node _readys_readys_T_38 = and(_readys_readys_T_36, _readys_readys_T_37)
node readys_readys_12 = not(_readys_readys_T_38)
node _readys_T_161 = orr(readys_valid_12)
node _readys_T_162 = and(latch_12, _readys_T_161)
when _readys_T_162 :
node _readys_mask_T_84 = and(readys_readys_12, readys_valid_12)
node _readys_mask_T_85 = shl(_readys_mask_T_84, 1)
node _readys_mask_T_86 = bits(_readys_mask_T_85, 1, 0)
node _readys_mask_T_87 = or(_readys_mask_T_84, _readys_mask_T_86)
node _readys_mask_T_88 = bits(_readys_mask_T_87, 1, 0)
connect readys_mask_12, _readys_mask_T_88
node _readys_T_163 = bits(readys_readys_12, 1, 0)
node _readys_T_164 = bits(_readys_T_163, 0, 0)
node _readys_T_165 = bits(_readys_T_163, 1, 1)
wire readys_12 : UInt<1>[2]
connect readys_12[0], _readys_T_164
connect readys_12[1], _readys_T_165
node _winner_T_60 = and(readys_12[0], portsDIO_filtered[10].valid)
node _winner_T_61 = and(readys_12[1], portsDIO_filtered_1[10].valid)
wire winner_12 : UInt<1>[2]
connect winner_12[0], _winner_T_60
connect winner_12[1], _winner_T_61
node prefixOR_1_12 = or(UInt<1>(0h0), winner_12[0])
node _prefixOR_T_12 = or(prefixOR_1_12, winner_12[1])
node _T_420 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = eq(winner_12[0], UInt<1>(0h0))
node _T_422 = or(_T_420, _T_421)
node _T_423 = eq(prefixOR_1_12, UInt<1>(0h0))
node _T_424 = eq(winner_12[1], UInt<1>(0h0))
node _T_425 = or(_T_423, _T_424)
node _T_426 = and(_T_422, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_24
assert(clock, _T_426, UInt<1>(0h1), "") : assert_24
node _T_430 = or(portsDIO_filtered[10].valid, portsDIO_filtered_1[10].valid)
node _T_431 = eq(_T_430, UInt<1>(0h0))
node _T_432 = or(winner_12[0], winner_12[1])
node _T_433 = or(_T_431, _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_25
assert(clock, _T_433, UInt<1>(0h1), "") : assert_25
node maskedBeats_0_12 = mux(winner_12[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_12 = mux(winner_12[1], beatsDO_1, UInt<1>(0h0))
node initBeats_12 = or(maskedBeats_0_12, maskedBeats_1_12)
node _beatsLeft_T_48 = and(in[10].d.ready, in[10].d.valid)
node _beatsLeft_T_49 = sub(beatsLeft_12, _beatsLeft_T_48)
node _beatsLeft_T_50 = tail(_beatsLeft_T_49, 1)
node _beatsLeft_T_51 = mux(latch_12, initBeats_12, _beatsLeft_T_50)
connect beatsLeft_12, _beatsLeft_T_51
wire _state_WIRE_12 : UInt<1>[2]
connect _state_WIRE_12[0], UInt<1>(0h0)
connect _state_WIRE_12[1], UInt<1>(0h0)
regreset state_12 : UInt<1>[2], clock, reset, _state_WIRE_12
node muxState_12 = mux(idle_12, winner_12, state_12)
connect state_12, muxState_12
node allowed_12 = mux(idle_12, readys_12, state_12)
node _filtered_10_ready_T = and(in[10].d.ready, allowed_12[0])
connect portsDIO_filtered[10].ready, _filtered_10_ready_T
node _filtered_10_ready_T_1 = and(in[10].d.ready, allowed_12[1])
connect portsDIO_filtered_1[10].ready, _filtered_10_ready_T_1
node _in_10_d_valid_T = or(portsDIO_filtered[10].valid, portsDIO_filtered_1[10].valid)
node _in_10_d_valid_T_1 = mux(state_12[0], portsDIO_filtered[10].valid, UInt<1>(0h0))
node _in_10_d_valid_T_2 = mux(state_12[1], portsDIO_filtered_1[10].valid, UInt<1>(0h0))
node _in_10_d_valid_T_3 = or(_in_10_d_valid_T_1, _in_10_d_valid_T_2)
wire _in_10_d_valid_WIRE : UInt<1>
connect _in_10_d_valid_WIRE, _in_10_d_valid_T_3
node _in_10_d_valid_T_4 = mux(idle_12, _in_10_d_valid_T, _in_10_d_valid_WIRE)
connect in[10].d.valid, _in_10_d_valid_T_4
wire _in_10_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_10_d_bits_T = mux(muxState_12[0], portsDIO_filtered[10].bits.corrupt, UInt<1>(0h0))
node _in_10_d_bits_T_1 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.corrupt, UInt<1>(0h0))
node _in_10_d_bits_T_2 = or(_in_10_d_bits_T, _in_10_d_bits_T_1)
wire _in_10_d_bits_WIRE_1 : UInt<1>
connect _in_10_d_bits_WIRE_1, _in_10_d_bits_T_2
connect _in_10_d_bits_WIRE.corrupt, _in_10_d_bits_WIRE_1
node _in_10_d_bits_T_3 = mux(muxState_12[0], portsDIO_filtered[10].bits.data, UInt<1>(0h0))
node _in_10_d_bits_T_4 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.data, UInt<1>(0h0))
node _in_10_d_bits_T_5 = or(_in_10_d_bits_T_3, _in_10_d_bits_T_4)
wire _in_10_d_bits_WIRE_2 : UInt<64>
connect _in_10_d_bits_WIRE_2, _in_10_d_bits_T_5
connect _in_10_d_bits_WIRE.data, _in_10_d_bits_WIRE_2
wire _in_10_d_bits_WIRE_3 : { }
connect _in_10_d_bits_WIRE.echo, _in_10_d_bits_WIRE_3
wire _in_10_d_bits_WIRE_4 : { }
connect _in_10_d_bits_WIRE.user, _in_10_d_bits_WIRE_4
node _in_10_d_bits_T_6 = mux(muxState_12[0], portsDIO_filtered[10].bits.denied, UInt<1>(0h0))
node _in_10_d_bits_T_7 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.denied, UInt<1>(0h0))
node _in_10_d_bits_T_8 = or(_in_10_d_bits_T_6, _in_10_d_bits_T_7)
wire _in_10_d_bits_WIRE_5 : UInt<1>
connect _in_10_d_bits_WIRE_5, _in_10_d_bits_T_8
connect _in_10_d_bits_WIRE.denied, _in_10_d_bits_WIRE_5
node _in_10_d_bits_T_9 = mux(muxState_12[0], portsDIO_filtered[10].bits.sink, UInt<1>(0h0))
node _in_10_d_bits_T_10 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.sink, UInt<1>(0h0))
node _in_10_d_bits_T_11 = or(_in_10_d_bits_T_9, _in_10_d_bits_T_10)
wire _in_10_d_bits_WIRE_6 : UInt<3>
connect _in_10_d_bits_WIRE_6, _in_10_d_bits_T_11
connect _in_10_d_bits_WIRE.sink, _in_10_d_bits_WIRE_6
node _in_10_d_bits_T_12 = mux(muxState_12[0], portsDIO_filtered[10].bits.source, UInt<1>(0h0))
node _in_10_d_bits_T_13 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.source, UInt<1>(0h0))
node _in_10_d_bits_T_14 = or(_in_10_d_bits_T_12, _in_10_d_bits_T_13)
wire _in_10_d_bits_WIRE_7 : UInt<9>
connect _in_10_d_bits_WIRE_7, _in_10_d_bits_T_14
connect _in_10_d_bits_WIRE.source, _in_10_d_bits_WIRE_7
node _in_10_d_bits_T_15 = mux(muxState_12[0], portsDIO_filtered[10].bits.size, UInt<1>(0h0))
node _in_10_d_bits_T_16 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.size, UInt<1>(0h0))
node _in_10_d_bits_T_17 = or(_in_10_d_bits_T_15, _in_10_d_bits_T_16)
wire _in_10_d_bits_WIRE_8 : UInt<4>
connect _in_10_d_bits_WIRE_8, _in_10_d_bits_T_17
connect _in_10_d_bits_WIRE.size, _in_10_d_bits_WIRE_8
node _in_10_d_bits_T_18 = mux(muxState_12[0], portsDIO_filtered[10].bits.param, UInt<1>(0h0))
node _in_10_d_bits_T_19 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.param, UInt<1>(0h0))
node _in_10_d_bits_T_20 = or(_in_10_d_bits_T_18, _in_10_d_bits_T_19)
wire _in_10_d_bits_WIRE_9 : UInt<2>
connect _in_10_d_bits_WIRE_9, _in_10_d_bits_T_20
connect _in_10_d_bits_WIRE.param, _in_10_d_bits_WIRE_9
node _in_10_d_bits_T_21 = mux(muxState_12[0], portsDIO_filtered[10].bits.opcode, UInt<1>(0h0))
node _in_10_d_bits_T_22 = mux(muxState_12[1], portsDIO_filtered_1[10].bits.opcode, UInt<1>(0h0))
node _in_10_d_bits_T_23 = or(_in_10_d_bits_T_21, _in_10_d_bits_T_22)
wire _in_10_d_bits_WIRE_10 : UInt<3>
connect _in_10_d_bits_WIRE_10, _in_10_d_bits_T_23
connect _in_10_d_bits_WIRE.opcode, _in_10_d_bits_WIRE_10
connect in[10].d.bits.corrupt, _in_10_d_bits_WIRE.corrupt
connect in[10].d.bits.data, _in_10_d_bits_WIRE.data
connect in[10].d.bits.denied, _in_10_d_bits_WIRE.denied
connect in[10].d.bits.sink, _in_10_d_bits_WIRE.sink
connect in[10].d.bits.source, _in_10_d_bits_WIRE.source
connect in[10].d.bits.size, _in_10_d_bits_WIRE.size
connect in[10].d.bits.param, _in_10_d_bits_WIRE.param
connect in[10].d.bits.opcode, _in_10_d_bits_WIRE.opcode
connect portsBIO_filtered[10].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[10].ready, UInt<1>(0h0)
invalidate in[11].b.bits.corrupt
invalidate in[11].b.bits.data
invalidate in[11].b.bits.mask
invalidate in[11].b.bits.address
invalidate in[11].b.bits.source
invalidate in[11].b.bits.size
invalidate in[11].b.bits.param
invalidate in[11].b.bits.opcode
regreset beatsLeft_13 : UInt, clock, reset, UInt<1>(0h0)
node idle_13 = eq(beatsLeft_13, UInt<1>(0h0))
node latch_13 = and(idle_13, in[11].d.ready)
node _readys_T_166 = cat(portsDIO_filtered_1[11].valid, portsDIO_filtered[11].valid)
node readys_valid_13 = bits(_readys_T_166, 1, 0)
node _readys_T_167 = eq(readys_valid_13, _readys_T_166)
node _readys_T_168 = asUInt(reset)
node _readys_T_169 = eq(_readys_T_168, UInt<1>(0h0))
when _readys_T_169 :
node _readys_T_170 = eq(_readys_T_167, UInt<1>(0h0))
when _readys_T_170 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_13
assert(clock, _readys_T_167, UInt<1>(0h1), "") : readys_assert_13
regreset readys_mask_13 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_26 = not(readys_mask_13)
node _readys_filter_T_27 = and(readys_valid_13, _readys_filter_T_26)
node readys_filter_13 = cat(_readys_filter_T_27, readys_valid_13)
node _readys_unready_T_81 = shr(readys_filter_13, 1)
node _readys_unready_T_82 = or(readys_filter_13, _readys_unready_T_81)
node _readys_unready_T_83 = bits(_readys_unready_T_82, 3, 0)
node _readys_unready_T_84 = shr(_readys_unready_T_83, 1)
node _readys_unready_T_85 = shl(readys_mask_13, 2)
node readys_unready_13 = or(_readys_unready_T_84, _readys_unready_T_85)
node _readys_readys_T_39 = shr(readys_unready_13, 2)
node _readys_readys_T_40 = bits(readys_unready_13, 1, 0)
node _readys_readys_T_41 = and(_readys_readys_T_39, _readys_readys_T_40)
node readys_readys_13 = not(_readys_readys_T_41)
node _readys_T_171 = orr(readys_valid_13)
node _readys_T_172 = and(latch_13, _readys_T_171)
when _readys_T_172 :
node _readys_mask_T_89 = and(readys_readys_13, readys_valid_13)
node _readys_mask_T_90 = shl(_readys_mask_T_89, 1)
node _readys_mask_T_91 = bits(_readys_mask_T_90, 1, 0)
node _readys_mask_T_92 = or(_readys_mask_T_89, _readys_mask_T_91)
node _readys_mask_T_93 = bits(_readys_mask_T_92, 1, 0)
connect readys_mask_13, _readys_mask_T_93
node _readys_T_173 = bits(readys_readys_13, 1, 0)
node _readys_T_174 = bits(_readys_T_173, 0, 0)
node _readys_T_175 = bits(_readys_T_173, 1, 1)
wire readys_13 : UInt<1>[2]
connect readys_13[0], _readys_T_174
connect readys_13[1], _readys_T_175
node _winner_T_62 = and(readys_13[0], portsDIO_filtered[11].valid)
node _winner_T_63 = and(readys_13[1], portsDIO_filtered_1[11].valid)
wire winner_13 : UInt<1>[2]
connect winner_13[0], _winner_T_62
connect winner_13[1], _winner_T_63
node prefixOR_1_13 = or(UInt<1>(0h0), winner_13[0])
node _prefixOR_T_13 = or(prefixOR_1_13, winner_13[1])
node _T_437 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = eq(winner_13[0], UInt<1>(0h0))
node _T_439 = or(_T_437, _T_438)
node _T_440 = eq(prefixOR_1_13, UInt<1>(0h0))
node _T_441 = eq(winner_13[1], UInt<1>(0h0))
node _T_442 = or(_T_440, _T_441)
node _T_443 = and(_T_439, _T_442)
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_26
assert(clock, _T_443, UInt<1>(0h1), "") : assert_26
node _T_447 = or(portsDIO_filtered[11].valid, portsDIO_filtered_1[11].valid)
node _T_448 = eq(_T_447, UInt<1>(0h0))
node _T_449 = or(winner_13[0], winner_13[1])
node _T_450 = or(_T_448, _T_449)
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_27
assert(clock, _T_450, UInt<1>(0h1), "") : assert_27
node maskedBeats_0_13 = mux(winner_13[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_13 = mux(winner_13[1], beatsDO_1, UInt<1>(0h0))
node initBeats_13 = or(maskedBeats_0_13, maskedBeats_1_13)
node _beatsLeft_T_52 = and(in[11].d.ready, in[11].d.valid)
node _beatsLeft_T_53 = sub(beatsLeft_13, _beatsLeft_T_52)
node _beatsLeft_T_54 = tail(_beatsLeft_T_53, 1)
node _beatsLeft_T_55 = mux(latch_13, initBeats_13, _beatsLeft_T_54)
connect beatsLeft_13, _beatsLeft_T_55
wire _state_WIRE_13 : UInt<1>[2]
connect _state_WIRE_13[0], UInt<1>(0h0)
connect _state_WIRE_13[1], UInt<1>(0h0)
regreset state_13 : UInt<1>[2], clock, reset, _state_WIRE_13
node muxState_13 = mux(idle_13, winner_13, state_13)
connect state_13, muxState_13
node allowed_13 = mux(idle_13, readys_13, state_13)
node _filtered_11_ready_T = and(in[11].d.ready, allowed_13[0])
connect portsDIO_filtered[11].ready, _filtered_11_ready_T
node _filtered_11_ready_T_1 = and(in[11].d.ready, allowed_13[1])
connect portsDIO_filtered_1[11].ready, _filtered_11_ready_T_1
node _in_11_d_valid_T = or(portsDIO_filtered[11].valid, portsDIO_filtered_1[11].valid)
node _in_11_d_valid_T_1 = mux(state_13[0], portsDIO_filtered[11].valid, UInt<1>(0h0))
node _in_11_d_valid_T_2 = mux(state_13[1], portsDIO_filtered_1[11].valid, UInt<1>(0h0))
node _in_11_d_valid_T_3 = or(_in_11_d_valid_T_1, _in_11_d_valid_T_2)
wire _in_11_d_valid_WIRE : UInt<1>
connect _in_11_d_valid_WIRE, _in_11_d_valid_T_3
node _in_11_d_valid_T_4 = mux(idle_13, _in_11_d_valid_T, _in_11_d_valid_WIRE)
connect in[11].d.valid, _in_11_d_valid_T_4
wire _in_11_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_11_d_bits_T = mux(muxState_13[0], portsDIO_filtered[11].bits.corrupt, UInt<1>(0h0))
node _in_11_d_bits_T_1 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.corrupt, UInt<1>(0h0))
node _in_11_d_bits_T_2 = or(_in_11_d_bits_T, _in_11_d_bits_T_1)
wire _in_11_d_bits_WIRE_1 : UInt<1>
connect _in_11_d_bits_WIRE_1, _in_11_d_bits_T_2
connect _in_11_d_bits_WIRE.corrupt, _in_11_d_bits_WIRE_1
node _in_11_d_bits_T_3 = mux(muxState_13[0], portsDIO_filtered[11].bits.data, UInt<1>(0h0))
node _in_11_d_bits_T_4 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.data, UInt<1>(0h0))
node _in_11_d_bits_T_5 = or(_in_11_d_bits_T_3, _in_11_d_bits_T_4)
wire _in_11_d_bits_WIRE_2 : UInt<64>
connect _in_11_d_bits_WIRE_2, _in_11_d_bits_T_5
connect _in_11_d_bits_WIRE.data, _in_11_d_bits_WIRE_2
wire _in_11_d_bits_WIRE_3 : { }
connect _in_11_d_bits_WIRE.echo, _in_11_d_bits_WIRE_3
wire _in_11_d_bits_WIRE_4 : { }
connect _in_11_d_bits_WIRE.user, _in_11_d_bits_WIRE_4
node _in_11_d_bits_T_6 = mux(muxState_13[0], portsDIO_filtered[11].bits.denied, UInt<1>(0h0))
node _in_11_d_bits_T_7 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.denied, UInt<1>(0h0))
node _in_11_d_bits_T_8 = or(_in_11_d_bits_T_6, _in_11_d_bits_T_7)
wire _in_11_d_bits_WIRE_5 : UInt<1>
connect _in_11_d_bits_WIRE_5, _in_11_d_bits_T_8
connect _in_11_d_bits_WIRE.denied, _in_11_d_bits_WIRE_5
node _in_11_d_bits_T_9 = mux(muxState_13[0], portsDIO_filtered[11].bits.sink, UInt<1>(0h0))
node _in_11_d_bits_T_10 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.sink, UInt<1>(0h0))
node _in_11_d_bits_T_11 = or(_in_11_d_bits_T_9, _in_11_d_bits_T_10)
wire _in_11_d_bits_WIRE_6 : UInt<3>
connect _in_11_d_bits_WIRE_6, _in_11_d_bits_T_11
connect _in_11_d_bits_WIRE.sink, _in_11_d_bits_WIRE_6
node _in_11_d_bits_T_12 = mux(muxState_13[0], portsDIO_filtered[11].bits.source, UInt<1>(0h0))
node _in_11_d_bits_T_13 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.source, UInt<1>(0h0))
node _in_11_d_bits_T_14 = or(_in_11_d_bits_T_12, _in_11_d_bits_T_13)
wire _in_11_d_bits_WIRE_7 : UInt<9>
connect _in_11_d_bits_WIRE_7, _in_11_d_bits_T_14
connect _in_11_d_bits_WIRE.source, _in_11_d_bits_WIRE_7
node _in_11_d_bits_T_15 = mux(muxState_13[0], portsDIO_filtered[11].bits.size, UInt<1>(0h0))
node _in_11_d_bits_T_16 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.size, UInt<1>(0h0))
node _in_11_d_bits_T_17 = or(_in_11_d_bits_T_15, _in_11_d_bits_T_16)
wire _in_11_d_bits_WIRE_8 : UInt<4>
connect _in_11_d_bits_WIRE_8, _in_11_d_bits_T_17
connect _in_11_d_bits_WIRE.size, _in_11_d_bits_WIRE_8
node _in_11_d_bits_T_18 = mux(muxState_13[0], portsDIO_filtered[11].bits.param, UInt<1>(0h0))
node _in_11_d_bits_T_19 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.param, UInt<1>(0h0))
node _in_11_d_bits_T_20 = or(_in_11_d_bits_T_18, _in_11_d_bits_T_19)
wire _in_11_d_bits_WIRE_9 : UInt<2>
connect _in_11_d_bits_WIRE_9, _in_11_d_bits_T_20
connect _in_11_d_bits_WIRE.param, _in_11_d_bits_WIRE_9
node _in_11_d_bits_T_21 = mux(muxState_13[0], portsDIO_filtered[11].bits.opcode, UInt<1>(0h0))
node _in_11_d_bits_T_22 = mux(muxState_13[1], portsDIO_filtered_1[11].bits.opcode, UInt<1>(0h0))
node _in_11_d_bits_T_23 = or(_in_11_d_bits_T_21, _in_11_d_bits_T_22)
wire _in_11_d_bits_WIRE_10 : UInt<3>
connect _in_11_d_bits_WIRE_10, _in_11_d_bits_T_23
connect _in_11_d_bits_WIRE.opcode, _in_11_d_bits_WIRE_10
connect in[11].d.bits.corrupt, _in_11_d_bits_WIRE.corrupt
connect in[11].d.bits.data, _in_11_d_bits_WIRE.data
connect in[11].d.bits.denied, _in_11_d_bits_WIRE.denied
connect in[11].d.bits.sink, _in_11_d_bits_WIRE.sink
connect in[11].d.bits.source, _in_11_d_bits_WIRE.source
connect in[11].d.bits.size, _in_11_d_bits_WIRE.size
connect in[11].d.bits.param, _in_11_d_bits_WIRE.param
connect in[11].d.bits.opcode, _in_11_d_bits_WIRE.opcode
connect portsBIO_filtered[11].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[11].ready, UInt<1>(0h0)
invalidate in[12].b.bits.corrupt
invalidate in[12].b.bits.data
invalidate in[12].b.bits.mask
invalidate in[12].b.bits.address
invalidate in[12].b.bits.source
invalidate in[12].b.bits.size
invalidate in[12].b.bits.param
invalidate in[12].b.bits.opcode
regreset beatsLeft_14 : UInt, clock, reset, UInt<1>(0h0)
node idle_14 = eq(beatsLeft_14, UInt<1>(0h0))
node latch_14 = and(idle_14, in[12].d.ready)
node _readys_T_176 = cat(portsDIO_filtered_1[12].valid, portsDIO_filtered[12].valid)
node readys_valid_14 = bits(_readys_T_176, 1, 0)
node _readys_T_177 = eq(readys_valid_14, _readys_T_176)
node _readys_T_178 = asUInt(reset)
node _readys_T_179 = eq(_readys_T_178, UInt<1>(0h0))
when _readys_T_179 :
node _readys_T_180 = eq(_readys_T_177, UInt<1>(0h0))
when _readys_T_180 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_14
assert(clock, _readys_T_177, UInt<1>(0h1), "") : readys_assert_14
regreset readys_mask_14 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_28 = not(readys_mask_14)
node _readys_filter_T_29 = and(readys_valid_14, _readys_filter_T_28)
node readys_filter_14 = cat(_readys_filter_T_29, readys_valid_14)
node _readys_unready_T_86 = shr(readys_filter_14, 1)
node _readys_unready_T_87 = or(readys_filter_14, _readys_unready_T_86)
node _readys_unready_T_88 = bits(_readys_unready_T_87, 3, 0)
node _readys_unready_T_89 = shr(_readys_unready_T_88, 1)
node _readys_unready_T_90 = shl(readys_mask_14, 2)
node readys_unready_14 = or(_readys_unready_T_89, _readys_unready_T_90)
node _readys_readys_T_42 = shr(readys_unready_14, 2)
node _readys_readys_T_43 = bits(readys_unready_14, 1, 0)
node _readys_readys_T_44 = and(_readys_readys_T_42, _readys_readys_T_43)
node readys_readys_14 = not(_readys_readys_T_44)
node _readys_T_181 = orr(readys_valid_14)
node _readys_T_182 = and(latch_14, _readys_T_181)
when _readys_T_182 :
node _readys_mask_T_94 = and(readys_readys_14, readys_valid_14)
node _readys_mask_T_95 = shl(_readys_mask_T_94, 1)
node _readys_mask_T_96 = bits(_readys_mask_T_95, 1, 0)
node _readys_mask_T_97 = or(_readys_mask_T_94, _readys_mask_T_96)
node _readys_mask_T_98 = bits(_readys_mask_T_97, 1, 0)
connect readys_mask_14, _readys_mask_T_98
node _readys_T_183 = bits(readys_readys_14, 1, 0)
node _readys_T_184 = bits(_readys_T_183, 0, 0)
node _readys_T_185 = bits(_readys_T_183, 1, 1)
wire readys_14 : UInt<1>[2]
connect readys_14[0], _readys_T_184
connect readys_14[1], _readys_T_185
node _winner_T_64 = and(readys_14[0], portsDIO_filtered[12].valid)
node _winner_T_65 = and(readys_14[1], portsDIO_filtered_1[12].valid)
wire winner_14 : UInt<1>[2]
connect winner_14[0], _winner_T_64
connect winner_14[1], _winner_T_65
node prefixOR_1_14 = or(UInt<1>(0h0), winner_14[0])
node _prefixOR_T_14 = or(prefixOR_1_14, winner_14[1])
node _T_454 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_455 = eq(winner_14[0], UInt<1>(0h0))
node _T_456 = or(_T_454, _T_455)
node _T_457 = eq(prefixOR_1_14, UInt<1>(0h0))
node _T_458 = eq(winner_14[1], UInt<1>(0h0))
node _T_459 = or(_T_457, _T_458)
node _T_460 = and(_T_456, _T_459)
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_28
assert(clock, _T_460, UInt<1>(0h1), "") : assert_28
node _T_464 = or(portsDIO_filtered[12].valid, portsDIO_filtered_1[12].valid)
node _T_465 = eq(_T_464, UInt<1>(0h0))
node _T_466 = or(winner_14[0], winner_14[1])
node _T_467 = or(_T_465, _T_466)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_29
assert(clock, _T_467, UInt<1>(0h1), "") : assert_29
node maskedBeats_0_14 = mux(winner_14[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_14 = mux(winner_14[1], beatsDO_1, UInt<1>(0h0))
node initBeats_14 = or(maskedBeats_0_14, maskedBeats_1_14)
node _beatsLeft_T_56 = and(in[12].d.ready, in[12].d.valid)
node _beatsLeft_T_57 = sub(beatsLeft_14, _beatsLeft_T_56)
node _beatsLeft_T_58 = tail(_beatsLeft_T_57, 1)
node _beatsLeft_T_59 = mux(latch_14, initBeats_14, _beatsLeft_T_58)
connect beatsLeft_14, _beatsLeft_T_59
wire _state_WIRE_14 : UInt<1>[2]
connect _state_WIRE_14[0], UInt<1>(0h0)
connect _state_WIRE_14[1], UInt<1>(0h0)
regreset state_14 : UInt<1>[2], clock, reset, _state_WIRE_14
node muxState_14 = mux(idle_14, winner_14, state_14)
connect state_14, muxState_14
node allowed_14 = mux(idle_14, readys_14, state_14)
node _filtered_12_ready_T = and(in[12].d.ready, allowed_14[0])
connect portsDIO_filtered[12].ready, _filtered_12_ready_T
node _filtered_12_ready_T_1 = and(in[12].d.ready, allowed_14[1])
connect portsDIO_filtered_1[12].ready, _filtered_12_ready_T_1
node _in_12_d_valid_T = or(portsDIO_filtered[12].valid, portsDIO_filtered_1[12].valid)
node _in_12_d_valid_T_1 = mux(state_14[0], portsDIO_filtered[12].valid, UInt<1>(0h0))
node _in_12_d_valid_T_2 = mux(state_14[1], portsDIO_filtered_1[12].valid, UInt<1>(0h0))
node _in_12_d_valid_T_3 = or(_in_12_d_valid_T_1, _in_12_d_valid_T_2)
wire _in_12_d_valid_WIRE : UInt<1>
connect _in_12_d_valid_WIRE, _in_12_d_valid_T_3
node _in_12_d_valid_T_4 = mux(idle_14, _in_12_d_valid_T, _in_12_d_valid_WIRE)
connect in[12].d.valid, _in_12_d_valid_T_4
wire _in_12_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_12_d_bits_T = mux(muxState_14[0], portsDIO_filtered[12].bits.corrupt, UInt<1>(0h0))
node _in_12_d_bits_T_1 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.corrupt, UInt<1>(0h0))
node _in_12_d_bits_T_2 = or(_in_12_d_bits_T, _in_12_d_bits_T_1)
wire _in_12_d_bits_WIRE_1 : UInt<1>
connect _in_12_d_bits_WIRE_1, _in_12_d_bits_T_2
connect _in_12_d_bits_WIRE.corrupt, _in_12_d_bits_WIRE_1
node _in_12_d_bits_T_3 = mux(muxState_14[0], portsDIO_filtered[12].bits.data, UInt<1>(0h0))
node _in_12_d_bits_T_4 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.data, UInt<1>(0h0))
node _in_12_d_bits_T_5 = or(_in_12_d_bits_T_3, _in_12_d_bits_T_4)
wire _in_12_d_bits_WIRE_2 : UInt<64>
connect _in_12_d_bits_WIRE_2, _in_12_d_bits_T_5
connect _in_12_d_bits_WIRE.data, _in_12_d_bits_WIRE_2
wire _in_12_d_bits_WIRE_3 : { }
connect _in_12_d_bits_WIRE.echo, _in_12_d_bits_WIRE_3
wire _in_12_d_bits_WIRE_4 : { }
connect _in_12_d_bits_WIRE.user, _in_12_d_bits_WIRE_4
node _in_12_d_bits_T_6 = mux(muxState_14[0], portsDIO_filtered[12].bits.denied, UInt<1>(0h0))
node _in_12_d_bits_T_7 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.denied, UInt<1>(0h0))
node _in_12_d_bits_T_8 = or(_in_12_d_bits_T_6, _in_12_d_bits_T_7)
wire _in_12_d_bits_WIRE_5 : UInt<1>
connect _in_12_d_bits_WIRE_5, _in_12_d_bits_T_8
connect _in_12_d_bits_WIRE.denied, _in_12_d_bits_WIRE_5
node _in_12_d_bits_T_9 = mux(muxState_14[0], portsDIO_filtered[12].bits.sink, UInt<1>(0h0))
node _in_12_d_bits_T_10 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.sink, UInt<1>(0h0))
node _in_12_d_bits_T_11 = or(_in_12_d_bits_T_9, _in_12_d_bits_T_10)
wire _in_12_d_bits_WIRE_6 : UInt<3>
connect _in_12_d_bits_WIRE_6, _in_12_d_bits_T_11
connect _in_12_d_bits_WIRE.sink, _in_12_d_bits_WIRE_6
node _in_12_d_bits_T_12 = mux(muxState_14[0], portsDIO_filtered[12].bits.source, UInt<1>(0h0))
node _in_12_d_bits_T_13 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.source, UInt<1>(0h0))
node _in_12_d_bits_T_14 = or(_in_12_d_bits_T_12, _in_12_d_bits_T_13)
wire _in_12_d_bits_WIRE_7 : UInt<9>
connect _in_12_d_bits_WIRE_7, _in_12_d_bits_T_14
connect _in_12_d_bits_WIRE.source, _in_12_d_bits_WIRE_7
node _in_12_d_bits_T_15 = mux(muxState_14[0], portsDIO_filtered[12].bits.size, UInt<1>(0h0))
node _in_12_d_bits_T_16 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.size, UInt<1>(0h0))
node _in_12_d_bits_T_17 = or(_in_12_d_bits_T_15, _in_12_d_bits_T_16)
wire _in_12_d_bits_WIRE_8 : UInt<4>
connect _in_12_d_bits_WIRE_8, _in_12_d_bits_T_17
connect _in_12_d_bits_WIRE.size, _in_12_d_bits_WIRE_8
node _in_12_d_bits_T_18 = mux(muxState_14[0], portsDIO_filtered[12].bits.param, UInt<1>(0h0))
node _in_12_d_bits_T_19 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.param, UInt<1>(0h0))
node _in_12_d_bits_T_20 = or(_in_12_d_bits_T_18, _in_12_d_bits_T_19)
wire _in_12_d_bits_WIRE_9 : UInt<2>
connect _in_12_d_bits_WIRE_9, _in_12_d_bits_T_20
connect _in_12_d_bits_WIRE.param, _in_12_d_bits_WIRE_9
node _in_12_d_bits_T_21 = mux(muxState_14[0], portsDIO_filtered[12].bits.opcode, UInt<1>(0h0))
node _in_12_d_bits_T_22 = mux(muxState_14[1], portsDIO_filtered_1[12].bits.opcode, UInt<1>(0h0))
node _in_12_d_bits_T_23 = or(_in_12_d_bits_T_21, _in_12_d_bits_T_22)
wire _in_12_d_bits_WIRE_10 : UInt<3>
connect _in_12_d_bits_WIRE_10, _in_12_d_bits_T_23
connect _in_12_d_bits_WIRE.opcode, _in_12_d_bits_WIRE_10
connect in[12].d.bits.corrupt, _in_12_d_bits_WIRE.corrupt
connect in[12].d.bits.data, _in_12_d_bits_WIRE.data
connect in[12].d.bits.denied, _in_12_d_bits_WIRE.denied
connect in[12].d.bits.sink, _in_12_d_bits_WIRE.sink
connect in[12].d.bits.source, _in_12_d_bits_WIRE.source
connect in[12].d.bits.size, _in_12_d_bits_WIRE.size
connect in[12].d.bits.param, _in_12_d_bits_WIRE.param
connect in[12].d.bits.opcode, _in_12_d_bits_WIRE.opcode
connect portsBIO_filtered[12].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[12].ready, UInt<1>(0h0)
invalidate in[13].b.bits.corrupt
invalidate in[13].b.bits.data
invalidate in[13].b.bits.mask
invalidate in[13].b.bits.address
invalidate in[13].b.bits.source
invalidate in[13].b.bits.size
invalidate in[13].b.bits.param
invalidate in[13].b.bits.opcode
regreset beatsLeft_15 : UInt, clock, reset, UInt<1>(0h0)
node idle_15 = eq(beatsLeft_15, UInt<1>(0h0))
node latch_15 = and(idle_15, in[13].d.ready)
node _readys_T_186 = cat(portsDIO_filtered_1[13].valid, portsDIO_filtered[13].valid)
node readys_valid_15 = bits(_readys_T_186, 1, 0)
node _readys_T_187 = eq(readys_valid_15, _readys_T_186)
node _readys_T_188 = asUInt(reset)
node _readys_T_189 = eq(_readys_T_188, UInt<1>(0h0))
when _readys_T_189 :
node _readys_T_190 = eq(_readys_T_187, UInt<1>(0h0))
when _readys_T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_15
assert(clock, _readys_T_187, UInt<1>(0h1), "") : readys_assert_15
regreset readys_mask_15 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_30 = not(readys_mask_15)
node _readys_filter_T_31 = and(readys_valid_15, _readys_filter_T_30)
node readys_filter_15 = cat(_readys_filter_T_31, readys_valid_15)
node _readys_unready_T_91 = shr(readys_filter_15, 1)
node _readys_unready_T_92 = or(readys_filter_15, _readys_unready_T_91)
node _readys_unready_T_93 = bits(_readys_unready_T_92, 3, 0)
node _readys_unready_T_94 = shr(_readys_unready_T_93, 1)
node _readys_unready_T_95 = shl(readys_mask_15, 2)
node readys_unready_15 = or(_readys_unready_T_94, _readys_unready_T_95)
node _readys_readys_T_45 = shr(readys_unready_15, 2)
node _readys_readys_T_46 = bits(readys_unready_15, 1, 0)
node _readys_readys_T_47 = and(_readys_readys_T_45, _readys_readys_T_46)
node readys_readys_15 = not(_readys_readys_T_47)
node _readys_T_191 = orr(readys_valid_15)
node _readys_T_192 = and(latch_15, _readys_T_191)
when _readys_T_192 :
node _readys_mask_T_99 = and(readys_readys_15, readys_valid_15)
node _readys_mask_T_100 = shl(_readys_mask_T_99, 1)
node _readys_mask_T_101 = bits(_readys_mask_T_100, 1, 0)
node _readys_mask_T_102 = or(_readys_mask_T_99, _readys_mask_T_101)
node _readys_mask_T_103 = bits(_readys_mask_T_102, 1, 0)
connect readys_mask_15, _readys_mask_T_103
node _readys_T_193 = bits(readys_readys_15, 1, 0)
node _readys_T_194 = bits(_readys_T_193, 0, 0)
node _readys_T_195 = bits(_readys_T_193, 1, 1)
wire readys_15 : UInt<1>[2]
connect readys_15[0], _readys_T_194
connect readys_15[1], _readys_T_195
node _winner_T_66 = and(readys_15[0], portsDIO_filtered[13].valid)
node _winner_T_67 = and(readys_15[1], portsDIO_filtered_1[13].valid)
wire winner_15 : UInt<1>[2]
connect winner_15[0], _winner_T_66
connect winner_15[1], _winner_T_67
node prefixOR_1_15 = or(UInt<1>(0h0), winner_15[0])
node _prefixOR_T_15 = or(prefixOR_1_15, winner_15[1])
node _T_471 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_472 = eq(winner_15[0], UInt<1>(0h0))
node _T_473 = or(_T_471, _T_472)
node _T_474 = eq(prefixOR_1_15, UInt<1>(0h0))
node _T_475 = eq(winner_15[1], UInt<1>(0h0))
node _T_476 = or(_T_474, _T_475)
node _T_477 = and(_T_473, _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_30
assert(clock, _T_477, UInt<1>(0h1), "") : assert_30
node _T_481 = or(portsDIO_filtered[13].valid, portsDIO_filtered_1[13].valid)
node _T_482 = eq(_T_481, UInt<1>(0h0))
node _T_483 = or(winner_15[0], winner_15[1])
node _T_484 = or(_T_482, _T_483)
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_31
assert(clock, _T_484, UInt<1>(0h1), "") : assert_31
node maskedBeats_0_15 = mux(winner_15[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_15 = mux(winner_15[1], beatsDO_1, UInt<1>(0h0))
node initBeats_15 = or(maskedBeats_0_15, maskedBeats_1_15)
node _beatsLeft_T_60 = and(in[13].d.ready, in[13].d.valid)
node _beatsLeft_T_61 = sub(beatsLeft_15, _beatsLeft_T_60)
node _beatsLeft_T_62 = tail(_beatsLeft_T_61, 1)
node _beatsLeft_T_63 = mux(latch_15, initBeats_15, _beatsLeft_T_62)
connect beatsLeft_15, _beatsLeft_T_63
wire _state_WIRE_15 : UInt<1>[2]
connect _state_WIRE_15[0], UInt<1>(0h0)
connect _state_WIRE_15[1], UInt<1>(0h0)
regreset state_15 : UInt<1>[2], clock, reset, _state_WIRE_15
node muxState_15 = mux(idle_15, winner_15, state_15)
connect state_15, muxState_15
node allowed_15 = mux(idle_15, readys_15, state_15)
node _filtered_13_ready_T = and(in[13].d.ready, allowed_15[0])
connect portsDIO_filtered[13].ready, _filtered_13_ready_T
node _filtered_13_ready_T_1 = and(in[13].d.ready, allowed_15[1])
connect portsDIO_filtered_1[13].ready, _filtered_13_ready_T_1
node _in_13_d_valid_T = or(portsDIO_filtered[13].valid, portsDIO_filtered_1[13].valid)
node _in_13_d_valid_T_1 = mux(state_15[0], portsDIO_filtered[13].valid, UInt<1>(0h0))
node _in_13_d_valid_T_2 = mux(state_15[1], portsDIO_filtered_1[13].valid, UInt<1>(0h0))
node _in_13_d_valid_T_3 = or(_in_13_d_valid_T_1, _in_13_d_valid_T_2)
wire _in_13_d_valid_WIRE : UInt<1>
connect _in_13_d_valid_WIRE, _in_13_d_valid_T_3
node _in_13_d_valid_T_4 = mux(idle_15, _in_13_d_valid_T, _in_13_d_valid_WIRE)
connect in[13].d.valid, _in_13_d_valid_T_4
wire _in_13_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_13_d_bits_T = mux(muxState_15[0], portsDIO_filtered[13].bits.corrupt, UInt<1>(0h0))
node _in_13_d_bits_T_1 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.corrupt, UInt<1>(0h0))
node _in_13_d_bits_T_2 = or(_in_13_d_bits_T, _in_13_d_bits_T_1)
wire _in_13_d_bits_WIRE_1 : UInt<1>
connect _in_13_d_bits_WIRE_1, _in_13_d_bits_T_2
connect _in_13_d_bits_WIRE.corrupt, _in_13_d_bits_WIRE_1
node _in_13_d_bits_T_3 = mux(muxState_15[0], portsDIO_filtered[13].bits.data, UInt<1>(0h0))
node _in_13_d_bits_T_4 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.data, UInt<1>(0h0))
node _in_13_d_bits_T_5 = or(_in_13_d_bits_T_3, _in_13_d_bits_T_4)
wire _in_13_d_bits_WIRE_2 : UInt<64>
connect _in_13_d_bits_WIRE_2, _in_13_d_bits_T_5
connect _in_13_d_bits_WIRE.data, _in_13_d_bits_WIRE_2
wire _in_13_d_bits_WIRE_3 : { }
connect _in_13_d_bits_WIRE.echo, _in_13_d_bits_WIRE_3
wire _in_13_d_bits_WIRE_4 : { }
connect _in_13_d_bits_WIRE.user, _in_13_d_bits_WIRE_4
node _in_13_d_bits_T_6 = mux(muxState_15[0], portsDIO_filtered[13].bits.denied, UInt<1>(0h0))
node _in_13_d_bits_T_7 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.denied, UInt<1>(0h0))
node _in_13_d_bits_T_8 = or(_in_13_d_bits_T_6, _in_13_d_bits_T_7)
wire _in_13_d_bits_WIRE_5 : UInt<1>
connect _in_13_d_bits_WIRE_5, _in_13_d_bits_T_8
connect _in_13_d_bits_WIRE.denied, _in_13_d_bits_WIRE_5
node _in_13_d_bits_T_9 = mux(muxState_15[0], portsDIO_filtered[13].bits.sink, UInt<1>(0h0))
node _in_13_d_bits_T_10 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.sink, UInt<1>(0h0))
node _in_13_d_bits_T_11 = or(_in_13_d_bits_T_9, _in_13_d_bits_T_10)
wire _in_13_d_bits_WIRE_6 : UInt<3>
connect _in_13_d_bits_WIRE_6, _in_13_d_bits_T_11
connect _in_13_d_bits_WIRE.sink, _in_13_d_bits_WIRE_6
node _in_13_d_bits_T_12 = mux(muxState_15[0], portsDIO_filtered[13].bits.source, UInt<1>(0h0))
node _in_13_d_bits_T_13 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.source, UInt<1>(0h0))
node _in_13_d_bits_T_14 = or(_in_13_d_bits_T_12, _in_13_d_bits_T_13)
wire _in_13_d_bits_WIRE_7 : UInt<9>
connect _in_13_d_bits_WIRE_7, _in_13_d_bits_T_14
connect _in_13_d_bits_WIRE.source, _in_13_d_bits_WIRE_7
node _in_13_d_bits_T_15 = mux(muxState_15[0], portsDIO_filtered[13].bits.size, UInt<1>(0h0))
node _in_13_d_bits_T_16 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.size, UInt<1>(0h0))
node _in_13_d_bits_T_17 = or(_in_13_d_bits_T_15, _in_13_d_bits_T_16)
wire _in_13_d_bits_WIRE_8 : UInt<4>
connect _in_13_d_bits_WIRE_8, _in_13_d_bits_T_17
connect _in_13_d_bits_WIRE.size, _in_13_d_bits_WIRE_8
node _in_13_d_bits_T_18 = mux(muxState_15[0], portsDIO_filtered[13].bits.param, UInt<1>(0h0))
node _in_13_d_bits_T_19 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.param, UInt<1>(0h0))
node _in_13_d_bits_T_20 = or(_in_13_d_bits_T_18, _in_13_d_bits_T_19)
wire _in_13_d_bits_WIRE_9 : UInt<2>
connect _in_13_d_bits_WIRE_9, _in_13_d_bits_T_20
connect _in_13_d_bits_WIRE.param, _in_13_d_bits_WIRE_9
node _in_13_d_bits_T_21 = mux(muxState_15[0], portsDIO_filtered[13].bits.opcode, UInt<1>(0h0))
node _in_13_d_bits_T_22 = mux(muxState_15[1], portsDIO_filtered_1[13].bits.opcode, UInt<1>(0h0))
node _in_13_d_bits_T_23 = or(_in_13_d_bits_T_21, _in_13_d_bits_T_22)
wire _in_13_d_bits_WIRE_10 : UInt<3>
connect _in_13_d_bits_WIRE_10, _in_13_d_bits_T_23
connect _in_13_d_bits_WIRE.opcode, _in_13_d_bits_WIRE_10
connect in[13].d.bits.corrupt, _in_13_d_bits_WIRE.corrupt
connect in[13].d.bits.data, _in_13_d_bits_WIRE.data
connect in[13].d.bits.denied, _in_13_d_bits_WIRE.denied
connect in[13].d.bits.sink, _in_13_d_bits_WIRE.sink
connect in[13].d.bits.source, _in_13_d_bits_WIRE.source
connect in[13].d.bits.size, _in_13_d_bits_WIRE.size
connect in[13].d.bits.param, _in_13_d_bits_WIRE.param
connect in[13].d.bits.opcode, _in_13_d_bits_WIRE.opcode
connect portsBIO_filtered[13].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[13].ready, UInt<1>(0h0)
invalidate in[14].b.bits.corrupt
invalidate in[14].b.bits.data
invalidate in[14].b.bits.mask
invalidate in[14].b.bits.address
invalidate in[14].b.bits.source
invalidate in[14].b.bits.size
invalidate in[14].b.bits.param
invalidate in[14].b.bits.opcode
regreset beatsLeft_16 : UInt, clock, reset, UInt<1>(0h0)
node idle_16 = eq(beatsLeft_16, UInt<1>(0h0))
node latch_16 = and(idle_16, in[14].d.ready)
node _readys_T_196 = cat(portsDIO_filtered_1[14].valid, portsDIO_filtered[14].valid)
node readys_valid_16 = bits(_readys_T_196, 1, 0)
node _readys_T_197 = eq(readys_valid_16, _readys_T_196)
node _readys_T_198 = asUInt(reset)
node _readys_T_199 = eq(_readys_T_198, UInt<1>(0h0))
when _readys_T_199 :
node _readys_T_200 = eq(_readys_T_197, UInt<1>(0h0))
when _readys_T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_16
assert(clock, _readys_T_197, UInt<1>(0h1), "") : readys_assert_16
regreset readys_mask_16 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_32 = not(readys_mask_16)
node _readys_filter_T_33 = and(readys_valid_16, _readys_filter_T_32)
node readys_filter_16 = cat(_readys_filter_T_33, readys_valid_16)
node _readys_unready_T_96 = shr(readys_filter_16, 1)
node _readys_unready_T_97 = or(readys_filter_16, _readys_unready_T_96)
node _readys_unready_T_98 = bits(_readys_unready_T_97, 3, 0)
node _readys_unready_T_99 = shr(_readys_unready_T_98, 1)
node _readys_unready_T_100 = shl(readys_mask_16, 2)
node readys_unready_16 = or(_readys_unready_T_99, _readys_unready_T_100)
node _readys_readys_T_48 = shr(readys_unready_16, 2)
node _readys_readys_T_49 = bits(readys_unready_16, 1, 0)
node _readys_readys_T_50 = and(_readys_readys_T_48, _readys_readys_T_49)
node readys_readys_16 = not(_readys_readys_T_50)
node _readys_T_201 = orr(readys_valid_16)
node _readys_T_202 = and(latch_16, _readys_T_201)
when _readys_T_202 :
node _readys_mask_T_104 = and(readys_readys_16, readys_valid_16)
node _readys_mask_T_105 = shl(_readys_mask_T_104, 1)
node _readys_mask_T_106 = bits(_readys_mask_T_105, 1, 0)
node _readys_mask_T_107 = or(_readys_mask_T_104, _readys_mask_T_106)
node _readys_mask_T_108 = bits(_readys_mask_T_107, 1, 0)
connect readys_mask_16, _readys_mask_T_108
node _readys_T_203 = bits(readys_readys_16, 1, 0)
node _readys_T_204 = bits(_readys_T_203, 0, 0)
node _readys_T_205 = bits(_readys_T_203, 1, 1)
wire readys_16 : UInt<1>[2]
connect readys_16[0], _readys_T_204
connect readys_16[1], _readys_T_205
node _winner_T_68 = and(readys_16[0], portsDIO_filtered[14].valid)
node _winner_T_69 = and(readys_16[1], portsDIO_filtered_1[14].valid)
wire winner_16 : UInt<1>[2]
connect winner_16[0], _winner_T_68
connect winner_16[1], _winner_T_69
node prefixOR_1_16 = or(UInt<1>(0h0), winner_16[0])
node _prefixOR_T_16 = or(prefixOR_1_16, winner_16[1])
node _T_488 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_489 = eq(winner_16[0], UInt<1>(0h0))
node _T_490 = or(_T_488, _T_489)
node _T_491 = eq(prefixOR_1_16, UInt<1>(0h0))
node _T_492 = eq(winner_16[1], UInt<1>(0h0))
node _T_493 = or(_T_491, _T_492)
node _T_494 = and(_T_490, _T_493)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_32
assert(clock, _T_494, UInt<1>(0h1), "") : assert_32
node _T_498 = or(portsDIO_filtered[14].valid, portsDIO_filtered_1[14].valid)
node _T_499 = eq(_T_498, UInt<1>(0h0))
node _T_500 = or(winner_16[0], winner_16[1])
node _T_501 = or(_T_499, _T_500)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_33
assert(clock, _T_501, UInt<1>(0h1), "") : assert_33
node maskedBeats_0_16 = mux(winner_16[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_16 = mux(winner_16[1], beatsDO_1, UInt<1>(0h0))
node initBeats_16 = or(maskedBeats_0_16, maskedBeats_1_16)
node _beatsLeft_T_64 = and(in[14].d.ready, in[14].d.valid)
node _beatsLeft_T_65 = sub(beatsLeft_16, _beatsLeft_T_64)
node _beatsLeft_T_66 = tail(_beatsLeft_T_65, 1)
node _beatsLeft_T_67 = mux(latch_16, initBeats_16, _beatsLeft_T_66)
connect beatsLeft_16, _beatsLeft_T_67
wire _state_WIRE_16 : UInt<1>[2]
connect _state_WIRE_16[0], UInt<1>(0h0)
connect _state_WIRE_16[1], UInt<1>(0h0)
regreset state_16 : UInt<1>[2], clock, reset, _state_WIRE_16
node muxState_16 = mux(idle_16, winner_16, state_16)
connect state_16, muxState_16
node allowed_16 = mux(idle_16, readys_16, state_16)
node _filtered_14_ready_T = and(in[14].d.ready, allowed_16[0])
connect portsDIO_filtered[14].ready, _filtered_14_ready_T
node _filtered_14_ready_T_1 = and(in[14].d.ready, allowed_16[1])
connect portsDIO_filtered_1[14].ready, _filtered_14_ready_T_1
node _in_14_d_valid_T = or(portsDIO_filtered[14].valid, portsDIO_filtered_1[14].valid)
node _in_14_d_valid_T_1 = mux(state_16[0], portsDIO_filtered[14].valid, UInt<1>(0h0))
node _in_14_d_valid_T_2 = mux(state_16[1], portsDIO_filtered_1[14].valid, UInt<1>(0h0))
node _in_14_d_valid_T_3 = or(_in_14_d_valid_T_1, _in_14_d_valid_T_2)
wire _in_14_d_valid_WIRE : UInt<1>
connect _in_14_d_valid_WIRE, _in_14_d_valid_T_3
node _in_14_d_valid_T_4 = mux(idle_16, _in_14_d_valid_T, _in_14_d_valid_WIRE)
connect in[14].d.valid, _in_14_d_valid_T_4
wire _in_14_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_14_d_bits_T = mux(muxState_16[0], portsDIO_filtered[14].bits.corrupt, UInt<1>(0h0))
node _in_14_d_bits_T_1 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.corrupt, UInt<1>(0h0))
node _in_14_d_bits_T_2 = or(_in_14_d_bits_T, _in_14_d_bits_T_1)
wire _in_14_d_bits_WIRE_1 : UInt<1>
connect _in_14_d_bits_WIRE_1, _in_14_d_bits_T_2
connect _in_14_d_bits_WIRE.corrupt, _in_14_d_bits_WIRE_1
node _in_14_d_bits_T_3 = mux(muxState_16[0], portsDIO_filtered[14].bits.data, UInt<1>(0h0))
node _in_14_d_bits_T_4 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.data, UInt<1>(0h0))
node _in_14_d_bits_T_5 = or(_in_14_d_bits_T_3, _in_14_d_bits_T_4)
wire _in_14_d_bits_WIRE_2 : UInt<64>
connect _in_14_d_bits_WIRE_2, _in_14_d_bits_T_5
connect _in_14_d_bits_WIRE.data, _in_14_d_bits_WIRE_2
wire _in_14_d_bits_WIRE_3 : { }
connect _in_14_d_bits_WIRE.echo, _in_14_d_bits_WIRE_3
wire _in_14_d_bits_WIRE_4 : { }
connect _in_14_d_bits_WIRE.user, _in_14_d_bits_WIRE_4
node _in_14_d_bits_T_6 = mux(muxState_16[0], portsDIO_filtered[14].bits.denied, UInt<1>(0h0))
node _in_14_d_bits_T_7 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.denied, UInt<1>(0h0))
node _in_14_d_bits_T_8 = or(_in_14_d_bits_T_6, _in_14_d_bits_T_7)
wire _in_14_d_bits_WIRE_5 : UInt<1>
connect _in_14_d_bits_WIRE_5, _in_14_d_bits_T_8
connect _in_14_d_bits_WIRE.denied, _in_14_d_bits_WIRE_5
node _in_14_d_bits_T_9 = mux(muxState_16[0], portsDIO_filtered[14].bits.sink, UInt<1>(0h0))
node _in_14_d_bits_T_10 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.sink, UInt<1>(0h0))
node _in_14_d_bits_T_11 = or(_in_14_d_bits_T_9, _in_14_d_bits_T_10)
wire _in_14_d_bits_WIRE_6 : UInt<3>
connect _in_14_d_bits_WIRE_6, _in_14_d_bits_T_11
connect _in_14_d_bits_WIRE.sink, _in_14_d_bits_WIRE_6
node _in_14_d_bits_T_12 = mux(muxState_16[0], portsDIO_filtered[14].bits.source, UInt<1>(0h0))
node _in_14_d_bits_T_13 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.source, UInt<1>(0h0))
node _in_14_d_bits_T_14 = or(_in_14_d_bits_T_12, _in_14_d_bits_T_13)
wire _in_14_d_bits_WIRE_7 : UInt<9>
connect _in_14_d_bits_WIRE_7, _in_14_d_bits_T_14
connect _in_14_d_bits_WIRE.source, _in_14_d_bits_WIRE_7
node _in_14_d_bits_T_15 = mux(muxState_16[0], portsDIO_filtered[14].bits.size, UInt<1>(0h0))
node _in_14_d_bits_T_16 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.size, UInt<1>(0h0))
node _in_14_d_bits_T_17 = or(_in_14_d_bits_T_15, _in_14_d_bits_T_16)
wire _in_14_d_bits_WIRE_8 : UInt<4>
connect _in_14_d_bits_WIRE_8, _in_14_d_bits_T_17
connect _in_14_d_bits_WIRE.size, _in_14_d_bits_WIRE_8
node _in_14_d_bits_T_18 = mux(muxState_16[0], portsDIO_filtered[14].bits.param, UInt<1>(0h0))
node _in_14_d_bits_T_19 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.param, UInt<1>(0h0))
node _in_14_d_bits_T_20 = or(_in_14_d_bits_T_18, _in_14_d_bits_T_19)
wire _in_14_d_bits_WIRE_9 : UInt<2>
connect _in_14_d_bits_WIRE_9, _in_14_d_bits_T_20
connect _in_14_d_bits_WIRE.param, _in_14_d_bits_WIRE_9
node _in_14_d_bits_T_21 = mux(muxState_16[0], portsDIO_filtered[14].bits.opcode, UInt<1>(0h0))
node _in_14_d_bits_T_22 = mux(muxState_16[1], portsDIO_filtered_1[14].bits.opcode, UInt<1>(0h0))
node _in_14_d_bits_T_23 = or(_in_14_d_bits_T_21, _in_14_d_bits_T_22)
wire _in_14_d_bits_WIRE_10 : UInt<3>
connect _in_14_d_bits_WIRE_10, _in_14_d_bits_T_23
connect _in_14_d_bits_WIRE.opcode, _in_14_d_bits_WIRE_10
connect in[14].d.bits.corrupt, _in_14_d_bits_WIRE.corrupt
connect in[14].d.bits.data, _in_14_d_bits_WIRE.data
connect in[14].d.bits.denied, _in_14_d_bits_WIRE.denied
connect in[14].d.bits.sink, _in_14_d_bits_WIRE.sink
connect in[14].d.bits.source, _in_14_d_bits_WIRE.source
connect in[14].d.bits.size, _in_14_d_bits_WIRE.size
connect in[14].d.bits.param, _in_14_d_bits_WIRE.param
connect in[14].d.bits.opcode, _in_14_d_bits_WIRE.opcode
connect portsBIO_filtered[14].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[14].ready, UInt<1>(0h0)
invalidate in[15].b.bits.corrupt
invalidate in[15].b.bits.data
invalidate in[15].b.bits.mask
invalidate in[15].b.bits.address
invalidate in[15].b.bits.source
invalidate in[15].b.bits.size
invalidate in[15].b.bits.param
invalidate in[15].b.bits.opcode
regreset beatsLeft_17 : UInt, clock, reset, UInt<1>(0h0)
node idle_17 = eq(beatsLeft_17, UInt<1>(0h0))
node latch_17 = and(idle_17, in[15].d.ready)
node _readys_T_206 = cat(portsDIO_filtered_1[15].valid, portsDIO_filtered[15].valid)
node readys_valid_17 = bits(_readys_T_206, 1, 0)
node _readys_T_207 = eq(readys_valid_17, _readys_T_206)
node _readys_T_208 = asUInt(reset)
node _readys_T_209 = eq(_readys_T_208, UInt<1>(0h0))
when _readys_T_209 :
node _readys_T_210 = eq(_readys_T_207, UInt<1>(0h0))
when _readys_T_210 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_17
assert(clock, _readys_T_207, UInt<1>(0h1), "") : readys_assert_17
regreset readys_mask_17 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_34 = not(readys_mask_17)
node _readys_filter_T_35 = and(readys_valid_17, _readys_filter_T_34)
node readys_filter_17 = cat(_readys_filter_T_35, readys_valid_17)
node _readys_unready_T_101 = shr(readys_filter_17, 1)
node _readys_unready_T_102 = or(readys_filter_17, _readys_unready_T_101)
node _readys_unready_T_103 = bits(_readys_unready_T_102, 3, 0)
node _readys_unready_T_104 = shr(_readys_unready_T_103, 1)
node _readys_unready_T_105 = shl(readys_mask_17, 2)
node readys_unready_17 = or(_readys_unready_T_104, _readys_unready_T_105)
node _readys_readys_T_51 = shr(readys_unready_17, 2)
node _readys_readys_T_52 = bits(readys_unready_17, 1, 0)
node _readys_readys_T_53 = and(_readys_readys_T_51, _readys_readys_T_52)
node readys_readys_17 = not(_readys_readys_T_53)
node _readys_T_211 = orr(readys_valid_17)
node _readys_T_212 = and(latch_17, _readys_T_211)
when _readys_T_212 :
node _readys_mask_T_109 = and(readys_readys_17, readys_valid_17)
node _readys_mask_T_110 = shl(_readys_mask_T_109, 1)
node _readys_mask_T_111 = bits(_readys_mask_T_110, 1, 0)
node _readys_mask_T_112 = or(_readys_mask_T_109, _readys_mask_T_111)
node _readys_mask_T_113 = bits(_readys_mask_T_112, 1, 0)
connect readys_mask_17, _readys_mask_T_113
node _readys_T_213 = bits(readys_readys_17, 1, 0)
node _readys_T_214 = bits(_readys_T_213, 0, 0)
node _readys_T_215 = bits(_readys_T_213, 1, 1)
wire readys_17 : UInt<1>[2]
connect readys_17[0], _readys_T_214
connect readys_17[1], _readys_T_215
node _winner_T_70 = and(readys_17[0], portsDIO_filtered[15].valid)
node _winner_T_71 = and(readys_17[1], portsDIO_filtered_1[15].valid)
wire winner_17 : UInt<1>[2]
connect winner_17[0], _winner_T_70
connect winner_17[1], _winner_T_71
node prefixOR_1_17 = or(UInt<1>(0h0), winner_17[0])
node _prefixOR_T_17 = or(prefixOR_1_17, winner_17[1])
node _T_505 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_506 = eq(winner_17[0], UInt<1>(0h0))
node _T_507 = or(_T_505, _T_506)
node _T_508 = eq(prefixOR_1_17, UInt<1>(0h0))
node _T_509 = eq(winner_17[1], UInt<1>(0h0))
node _T_510 = or(_T_508, _T_509)
node _T_511 = and(_T_507, _T_510)
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(_T_511, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_34
assert(clock, _T_511, UInt<1>(0h1), "") : assert_34
node _T_515 = or(portsDIO_filtered[15].valid, portsDIO_filtered_1[15].valid)
node _T_516 = eq(_T_515, UInt<1>(0h0))
node _T_517 = or(winner_17[0], winner_17[1])
node _T_518 = or(_T_516, _T_517)
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_35
assert(clock, _T_518, UInt<1>(0h1), "") : assert_35
node maskedBeats_0_17 = mux(winner_17[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_17 = mux(winner_17[1], beatsDO_1, UInt<1>(0h0))
node initBeats_17 = or(maskedBeats_0_17, maskedBeats_1_17)
node _beatsLeft_T_68 = and(in[15].d.ready, in[15].d.valid)
node _beatsLeft_T_69 = sub(beatsLeft_17, _beatsLeft_T_68)
node _beatsLeft_T_70 = tail(_beatsLeft_T_69, 1)
node _beatsLeft_T_71 = mux(latch_17, initBeats_17, _beatsLeft_T_70)
connect beatsLeft_17, _beatsLeft_T_71
wire _state_WIRE_17 : UInt<1>[2]
connect _state_WIRE_17[0], UInt<1>(0h0)
connect _state_WIRE_17[1], UInt<1>(0h0)
regreset state_17 : UInt<1>[2], clock, reset, _state_WIRE_17
node muxState_17 = mux(idle_17, winner_17, state_17)
connect state_17, muxState_17
node allowed_17 = mux(idle_17, readys_17, state_17)
node _filtered_15_ready_T = and(in[15].d.ready, allowed_17[0])
connect portsDIO_filtered[15].ready, _filtered_15_ready_T
node _filtered_15_ready_T_1 = and(in[15].d.ready, allowed_17[1])
connect portsDIO_filtered_1[15].ready, _filtered_15_ready_T_1
node _in_15_d_valid_T = or(portsDIO_filtered[15].valid, portsDIO_filtered_1[15].valid)
node _in_15_d_valid_T_1 = mux(state_17[0], portsDIO_filtered[15].valid, UInt<1>(0h0))
node _in_15_d_valid_T_2 = mux(state_17[1], portsDIO_filtered_1[15].valid, UInt<1>(0h0))
node _in_15_d_valid_T_3 = or(_in_15_d_valid_T_1, _in_15_d_valid_T_2)
wire _in_15_d_valid_WIRE : UInt<1>
connect _in_15_d_valid_WIRE, _in_15_d_valid_T_3
node _in_15_d_valid_T_4 = mux(idle_17, _in_15_d_valid_T, _in_15_d_valid_WIRE)
connect in[15].d.valid, _in_15_d_valid_T_4
wire _in_15_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_15_d_bits_T = mux(muxState_17[0], portsDIO_filtered[15].bits.corrupt, UInt<1>(0h0))
node _in_15_d_bits_T_1 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.corrupt, UInt<1>(0h0))
node _in_15_d_bits_T_2 = or(_in_15_d_bits_T, _in_15_d_bits_T_1)
wire _in_15_d_bits_WIRE_1 : UInt<1>
connect _in_15_d_bits_WIRE_1, _in_15_d_bits_T_2
connect _in_15_d_bits_WIRE.corrupt, _in_15_d_bits_WIRE_1
node _in_15_d_bits_T_3 = mux(muxState_17[0], portsDIO_filtered[15].bits.data, UInt<1>(0h0))
node _in_15_d_bits_T_4 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.data, UInt<1>(0h0))
node _in_15_d_bits_T_5 = or(_in_15_d_bits_T_3, _in_15_d_bits_T_4)
wire _in_15_d_bits_WIRE_2 : UInt<64>
connect _in_15_d_bits_WIRE_2, _in_15_d_bits_T_5
connect _in_15_d_bits_WIRE.data, _in_15_d_bits_WIRE_2
wire _in_15_d_bits_WIRE_3 : { }
connect _in_15_d_bits_WIRE.echo, _in_15_d_bits_WIRE_3
wire _in_15_d_bits_WIRE_4 : { }
connect _in_15_d_bits_WIRE.user, _in_15_d_bits_WIRE_4
node _in_15_d_bits_T_6 = mux(muxState_17[0], portsDIO_filtered[15].bits.denied, UInt<1>(0h0))
node _in_15_d_bits_T_7 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.denied, UInt<1>(0h0))
node _in_15_d_bits_T_8 = or(_in_15_d_bits_T_6, _in_15_d_bits_T_7)
wire _in_15_d_bits_WIRE_5 : UInt<1>
connect _in_15_d_bits_WIRE_5, _in_15_d_bits_T_8
connect _in_15_d_bits_WIRE.denied, _in_15_d_bits_WIRE_5
node _in_15_d_bits_T_9 = mux(muxState_17[0], portsDIO_filtered[15].bits.sink, UInt<1>(0h0))
node _in_15_d_bits_T_10 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.sink, UInt<1>(0h0))
node _in_15_d_bits_T_11 = or(_in_15_d_bits_T_9, _in_15_d_bits_T_10)
wire _in_15_d_bits_WIRE_6 : UInt<3>
connect _in_15_d_bits_WIRE_6, _in_15_d_bits_T_11
connect _in_15_d_bits_WIRE.sink, _in_15_d_bits_WIRE_6
node _in_15_d_bits_T_12 = mux(muxState_17[0], portsDIO_filtered[15].bits.source, UInt<1>(0h0))
node _in_15_d_bits_T_13 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.source, UInt<1>(0h0))
node _in_15_d_bits_T_14 = or(_in_15_d_bits_T_12, _in_15_d_bits_T_13)
wire _in_15_d_bits_WIRE_7 : UInt<9>
connect _in_15_d_bits_WIRE_7, _in_15_d_bits_T_14
connect _in_15_d_bits_WIRE.source, _in_15_d_bits_WIRE_7
node _in_15_d_bits_T_15 = mux(muxState_17[0], portsDIO_filtered[15].bits.size, UInt<1>(0h0))
node _in_15_d_bits_T_16 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.size, UInt<1>(0h0))
node _in_15_d_bits_T_17 = or(_in_15_d_bits_T_15, _in_15_d_bits_T_16)
wire _in_15_d_bits_WIRE_8 : UInt<4>
connect _in_15_d_bits_WIRE_8, _in_15_d_bits_T_17
connect _in_15_d_bits_WIRE.size, _in_15_d_bits_WIRE_8
node _in_15_d_bits_T_18 = mux(muxState_17[0], portsDIO_filtered[15].bits.param, UInt<1>(0h0))
node _in_15_d_bits_T_19 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.param, UInt<1>(0h0))
node _in_15_d_bits_T_20 = or(_in_15_d_bits_T_18, _in_15_d_bits_T_19)
wire _in_15_d_bits_WIRE_9 : UInt<2>
connect _in_15_d_bits_WIRE_9, _in_15_d_bits_T_20
connect _in_15_d_bits_WIRE.param, _in_15_d_bits_WIRE_9
node _in_15_d_bits_T_21 = mux(muxState_17[0], portsDIO_filtered[15].bits.opcode, UInt<1>(0h0))
node _in_15_d_bits_T_22 = mux(muxState_17[1], portsDIO_filtered_1[15].bits.opcode, UInt<1>(0h0))
node _in_15_d_bits_T_23 = or(_in_15_d_bits_T_21, _in_15_d_bits_T_22)
wire _in_15_d_bits_WIRE_10 : UInt<3>
connect _in_15_d_bits_WIRE_10, _in_15_d_bits_T_23
connect _in_15_d_bits_WIRE.opcode, _in_15_d_bits_WIRE_10
connect in[15].d.bits.corrupt, _in_15_d_bits_WIRE.corrupt
connect in[15].d.bits.data, _in_15_d_bits_WIRE.data
connect in[15].d.bits.denied, _in_15_d_bits_WIRE.denied
connect in[15].d.bits.sink, _in_15_d_bits_WIRE.sink
connect in[15].d.bits.source, _in_15_d_bits_WIRE.source
connect in[15].d.bits.size, _in_15_d_bits_WIRE.size
connect in[15].d.bits.param, _in_15_d_bits_WIRE.param
connect in[15].d.bits.opcode, _in_15_d_bits_WIRE.opcode
connect portsBIO_filtered[15].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[15].ready, UInt<1>(0h0)
invalidate in[16].b.bits.corrupt
invalidate in[16].b.bits.data
invalidate in[16].b.bits.mask
invalidate in[16].b.bits.address
invalidate in[16].b.bits.source
invalidate in[16].b.bits.size
invalidate in[16].b.bits.param
invalidate in[16].b.bits.opcode
regreset beatsLeft_18 : UInt, clock, reset, UInt<1>(0h0)
node idle_18 = eq(beatsLeft_18, UInt<1>(0h0))
node latch_18 = and(idle_18, in[16].d.ready)
node _readys_T_216 = cat(portsDIO_filtered_1[16].valid, portsDIO_filtered[16].valid)
node readys_valid_18 = bits(_readys_T_216, 1, 0)
node _readys_T_217 = eq(readys_valid_18, _readys_T_216)
node _readys_T_218 = asUInt(reset)
node _readys_T_219 = eq(_readys_T_218, UInt<1>(0h0))
when _readys_T_219 :
node _readys_T_220 = eq(_readys_T_217, UInt<1>(0h0))
when _readys_T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_18
assert(clock, _readys_T_217, UInt<1>(0h1), "") : readys_assert_18
regreset readys_mask_18 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_36 = not(readys_mask_18)
node _readys_filter_T_37 = and(readys_valid_18, _readys_filter_T_36)
node readys_filter_18 = cat(_readys_filter_T_37, readys_valid_18)
node _readys_unready_T_106 = shr(readys_filter_18, 1)
node _readys_unready_T_107 = or(readys_filter_18, _readys_unready_T_106)
node _readys_unready_T_108 = bits(_readys_unready_T_107, 3, 0)
node _readys_unready_T_109 = shr(_readys_unready_T_108, 1)
node _readys_unready_T_110 = shl(readys_mask_18, 2)
node readys_unready_18 = or(_readys_unready_T_109, _readys_unready_T_110)
node _readys_readys_T_54 = shr(readys_unready_18, 2)
node _readys_readys_T_55 = bits(readys_unready_18, 1, 0)
node _readys_readys_T_56 = and(_readys_readys_T_54, _readys_readys_T_55)
node readys_readys_18 = not(_readys_readys_T_56)
node _readys_T_221 = orr(readys_valid_18)
node _readys_T_222 = and(latch_18, _readys_T_221)
when _readys_T_222 :
node _readys_mask_T_114 = and(readys_readys_18, readys_valid_18)
node _readys_mask_T_115 = shl(_readys_mask_T_114, 1)
node _readys_mask_T_116 = bits(_readys_mask_T_115, 1, 0)
node _readys_mask_T_117 = or(_readys_mask_T_114, _readys_mask_T_116)
node _readys_mask_T_118 = bits(_readys_mask_T_117, 1, 0)
connect readys_mask_18, _readys_mask_T_118
node _readys_T_223 = bits(readys_readys_18, 1, 0)
node _readys_T_224 = bits(_readys_T_223, 0, 0)
node _readys_T_225 = bits(_readys_T_223, 1, 1)
wire readys_18 : UInt<1>[2]
connect readys_18[0], _readys_T_224
connect readys_18[1], _readys_T_225
node _winner_T_72 = and(readys_18[0], portsDIO_filtered[16].valid)
node _winner_T_73 = and(readys_18[1], portsDIO_filtered_1[16].valid)
wire winner_18 : UInt<1>[2]
connect winner_18[0], _winner_T_72
connect winner_18[1], _winner_T_73
node prefixOR_1_18 = or(UInt<1>(0h0), winner_18[0])
node _prefixOR_T_18 = or(prefixOR_1_18, winner_18[1])
node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = eq(winner_18[0], UInt<1>(0h0))
node _T_524 = or(_T_522, _T_523)
node _T_525 = eq(prefixOR_1_18, UInt<1>(0h0))
node _T_526 = eq(winner_18[1], UInt<1>(0h0))
node _T_527 = or(_T_525, _T_526)
node _T_528 = and(_T_524, _T_527)
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_36
assert(clock, _T_528, UInt<1>(0h1), "") : assert_36
node _T_532 = or(portsDIO_filtered[16].valid, portsDIO_filtered_1[16].valid)
node _T_533 = eq(_T_532, UInt<1>(0h0))
node _T_534 = or(winner_18[0], winner_18[1])
node _T_535 = or(_T_533, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_37
assert(clock, _T_535, UInt<1>(0h1), "") : assert_37
node maskedBeats_0_18 = mux(winner_18[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_18 = mux(winner_18[1], beatsDO_1, UInt<1>(0h0))
node initBeats_18 = or(maskedBeats_0_18, maskedBeats_1_18)
node _beatsLeft_T_72 = and(in[16].d.ready, in[16].d.valid)
node _beatsLeft_T_73 = sub(beatsLeft_18, _beatsLeft_T_72)
node _beatsLeft_T_74 = tail(_beatsLeft_T_73, 1)
node _beatsLeft_T_75 = mux(latch_18, initBeats_18, _beatsLeft_T_74)
connect beatsLeft_18, _beatsLeft_T_75
wire _state_WIRE_18 : UInt<1>[2]
connect _state_WIRE_18[0], UInt<1>(0h0)
connect _state_WIRE_18[1], UInt<1>(0h0)
regreset state_18 : UInt<1>[2], clock, reset, _state_WIRE_18
node muxState_18 = mux(idle_18, winner_18, state_18)
connect state_18, muxState_18
node allowed_18 = mux(idle_18, readys_18, state_18)
node _filtered_16_ready_T = and(in[16].d.ready, allowed_18[0])
connect portsDIO_filtered[16].ready, _filtered_16_ready_T
node _filtered_16_ready_T_1 = and(in[16].d.ready, allowed_18[1])
connect portsDIO_filtered_1[16].ready, _filtered_16_ready_T_1
node _in_16_d_valid_T = or(portsDIO_filtered[16].valid, portsDIO_filtered_1[16].valid)
node _in_16_d_valid_T_1 = mux(state_18[0], portsDIO_filtered[16].valid, UInt<1>(0h0))
node _in_16_d_valid_T_2 = mux(state_18[1], portsDIO_filtered_1[16].valid, UInt<1>(0h0))
node _in_16_d_valid_T_3 = or(_in_16_d_valid_T_1, _in_16_d_valid_T_2)
wire _in_16_d_valid_WIRE : UInt<1>
connect _in_16_d_valid_WIRE, _in_16_d_valid_T_3
node _in_16_d_valid_T_4 = mux(idle_18, _in_16_d_valid_T, _in_16_d_valid_WIRE)
connect in[16].d.valid, _in_16_d_valid_T_4
wire _in_16_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_16_d_bits_T = mux(muxState_18[0], portsDIO_filtered[16].bits.corrupt, UInt<1>(0h0))
node _in_16_d_bits_T_1 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.corrupt, UInt<1>(0h0))
node _in_16_d_bits_T_2 = or(_in_16_d_bits_T, _in_16_d_bits_T_1)
wire _in_16_d_bits_WIRE_1 : UInt<1>
connect _in_16_d_bits_WIRE_1, _in_16_d_bits_T_2
connect _in_16_d_bits_WIRE.corrupt, _in_16_d_bits_WIRE_1
node _in_16_d_bits_T_3 = mux(muxState_18[0], portsDIO_filtered[16].bits.data, UInt<1>(0h0))
node _in_16_d_bits_T_4 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.data, UInt<1>(0h0))
node _in_16_d_bits_T_5 = or(_in_16_d_bits_T_3, _in_16_d_bits_T_4)
wire _in_16_d_bits_WIRE_2 : UInt<64>
connect _in_16_d_bits_WIRE_2, _in_16_d_bits_T_5
connect _in_16_d_bits_WIRE.data, _in_16_d_bits_WIRE_2
wire _in_16_d_bits_WIRE_3 : { }
connect _in_16_d_bits_WIRE.echo, _in_16_d_bits_WIRE_3
wire _in_16_d_bits_WIRE_4 : { }
connect _in_16_d_bits_WIRE.user, _in_16_d_bits_WIRE_4
node _in_16_d_bits_T_6 = mux(muxState_18[0], portsDIO_filtered[16].bits.denied, UInt<1>(0h0))
node _in_16_d_bits_T_7 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.denied, UInt<1>(0h0))
node _in_16_d_bits_T_8 = or(_in_16_d_bits_T_6, _in_16_d_bits_T_7)
wire _in_16_d_bits_WIRE_5 : UInt<1>
connect _in_16_d_bits_WIRE_5, _in_16_d_bits_T_8
connect _in_16_d_bits_WIRE.denied, _in_16_d_bits_WIRE_5
node _in_16_d_bits_T_9 = mux(muxState_18[0], portsDIO_filtered[16].bits.sink, UInt<1>(0h0))
node _in_16_d_bits_T_10 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.sink, UInt<1>(0h0))
node _in_16_d_bits_T_11 = or(_in_16_d_bits_T_9, _in_16_d_bits_T_10)
wire _in_16_d_bits_WIRE_6 : UInt<3>
connect _in_16_d_bits_WIRE_6, _in_16_d_bits_T_11
connect _in_16_d_bits_WIRE.sink, _in_16_d_bits_WIRE_6
node _in_16_d_bits_T_12 = mux(muxState_18[0], portsDIO_filtered[16].bits.source, UInt<1>(0h0))
node _in_16_d_bits_T_13 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.source, UInt<1>(0h0))
node _in_16_d_bits_T_14 = or(_in_16_d_bits_T_12, _in_16_d_bits_T_13)
wire _in_16_d_bits_WIRE_7 : UInt<9>
connect _in_16_d_bits_WIRE_7, _in_16_d_bits_T_14
connect _in_16_d_bits_WIRE.source, _in_16_d_bits_WIRE_7
node _in_16_d_bits_T_15 = mux(muxState_18[0], portsDIO_filtered[16].bits.size, UInt<1>(0h0))
node _in_16_d_bits_T_16 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.size, UInt<1>(0h0))
node _in_16_d_bits_T_17 = or(_in_16_d_bits_T_15, _in_16_d_bits_T_16)
wire _in_16_d_bits_WIRE_8 : UInt<4>
connect _in_16_d_bits_WIRE_8, _in_16_d_bits_T_17
connect _in_16_d_bits_WIRE.size, _in_16_d_bits_WIRE_8
node _in_16_d_bits_T_18 = mux(muxState_18[0], portsDIO_filtered[16].bits.param, UInt<1>(0h0))
node _in_16_d_bits_T_19 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.param, UInt<1>(0h0))
node _in_16_d_bits_T_20 = or(_in_16_d_bits_T_18, _in_16_d_bits_T_19)
wire _in_16_d_bits_WIRE_9 : UInt<2>
connect _in_16_d_bits_WIRE_9, _in_16_d_bits_T_20
connect _in_16_d_bits_WIRE.param, _in_16_d_bits_WIRE_9
node _in_16_d_bits_T_21 = mux(muxState_18[0], portsDIO_filtered[16].bits.opcode, UInt<1>(0h0))
node _in_16_d_bits_T_22 = mux(muxState_18[1], portsDIO_filtered_1[16].bits.opcode, UInt<1>(0h0))
node _in_16_d_bits_T_23 = or(_in_16_d_bits_T_21, _in_16_d_bits_T_22)
wire _in_16_d_bits_WIRE_10 : UInt<3>
connect _in_16_d_bits_WIRE_10, _in_16_d_bits_T_23
connect _in_16_d_bits_WIRE.opcode, _in_16_d_bits_WIRE_10
connect in[16].d.bits.corrupt, _in_16_d_bits_WIRE.corrupt
connect in[16].d.bits.data, _in_16_d_bits_WIRE.data
connect in[16].d.bits.denied, _in_16_d_bits_WIRE.denied
connect in[16].d.bits.sink, _in_16_d_bits_WIRE.sink
connect in[16].d.bits.source, _in_16_d_bits_WIRE.source
connect in[16].d.bits.size, _in_16_d_bits_WIRE.size
connect in[16].d.bits.param, _in_16_d_bits_WIRE.param
connect in[16].d.bits.opcode, _in_16_d_bits_WIRE.opcode
connect portsBIO_filtered[16].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[16].ready, UInt<1>(0h0)
invalidate in[17].b.bits.corrupt
invalidate in[17].b.bits.data
invalidate in[17].b.bits.mask
invalidate in[17].b.bits.address
invalidate in[17].b.bits.source
invalidate in[17].b.bits.size
invalidate in[17].b.bits.param
invalidate in[17].b.bits.opcode
regreset beatsLeft_19 : UInt, clock, reset, UInt<1>(0h0)
node idle_19 = eq(beatsLeft_19, UInt<1>(0h0))
node latch_19 = and(idle_19, in[17].d.ready)
node _readys_T_226 = cat(portsDIO_filtered_1[17].valid, portsDIO_filtered[17].valid)
node readys_valid_19 = bits(_readys_T_226, 1, 0)
node _readys_T_227 = eq(readys_valid_19, _readys_T_226)
node _readys_T_228 = asUInt(reset)
node _readys_T_229 = eq(_readys_T_228, UInt<1>(0h0))
when _readys_T_229 :
node _readys_T_230 = eq(_readys_T_227, UInt<1>(0h0))
when _readys_T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_19
assert(clock, _readys_T_227, UInt<1>(0h1), "") : readys_assert_19
regreset readys_mask_19 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_38 = not(readys_mask_19)
node _readys_filter_T_39 = and(readys_valid_19, _readys_filter_T_38)
node readys_filter_19 = cat(_readys_filter_T_39, readys_valid_19)
node _readys_unready_T_111 = shr(readys_filter_19, 1)
node _readys_unready_T_112 = or(readys_filter_19, _readys_unready_T_111)
node _readys_unready_T_113 = bits(_readys_unready_T_112, 3, 0)
node _readys_unready_T_114 = shr(_readys_unready_T_113, 1)
node _readys_unready_T_115 = shl(readys_mask_19, 2)
node readys_unready_19 = or(_readys_unready_T_114, _readys_unready_T_115)
node _readys_readys_T_57 = shr(readys_unready_19, 2)
node _readys_readys_T_58 = bits(readys_unready_19, 1, 0)
node _readys_readys_T_59 = and(_readys_readys_T_57, _readys_readys_T_58)
node readys_readys_19 = not(_readys_readys_T_59)
node _readys_T_231 = orr(readys_valid_19)
node _readys_T_232 = and(latch_19, _readys_T_231)
when _readys_T_232 :
node _readys_mask_T_119 = and(readys_readys_19, readys_valid_19)
node _readys_mask_T_120 = shl(_readys_mask_T_119, 1)
node _readys_mask_T_121 = bits(_readys_mask_T_120, 1, 0)
node _readys_mask_T_122 = or(_readys_mask_T_119, _readys_mask_T_121)
node _readys_mask_T_123 = bits(_readys_mask_T_122, 1, 0)
connect readys_mask_19, _readys_mask_T_123
node _readys_T_233 = bits(readys_readys_19, 1, 0)
node _readys_T_234 = bits(_readys_T_233, 0, 0)
node _readys_T_235 = bits(_readys_T_233, 1, 1)
wire readys_19 : UInt<1>[2]
connect readys_19[0], _readys_T_234
connect readys_19[1], _readys_T_235
node _winner_T_74 = and(readys_19[0], portsDIO_filtered[17].valid)
node _winner_T_75 = and(readys_19[1], portsDIO_filtered_1[17].valid)
wire winner_19 : UInt<1>[2]
connect winner_19[0], _winner_T_74
connect winner_19[1], _winner_T_75
node prefixOR_1_19 = or(UInt<1>(0h0), winner_19[0])
node _prefixOR_T_19 = or(prefixOR_1_19, winner_19[1])
node _T_539 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_540 = eq(winner_19[0], UInt<1>(0h0))
node _T_541 = or(_T_539, _T_540)
node _T_542 = eq(prefixOR_1_19, UInt<1>(0h0))
node _T_543 = eq(winner_19[1], UInt<1>(0h0))
node _T_544 = or(_T_542, _T_543)
node _T_545 = and(_T_541, _T_544)
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_38
assert(clock, _T_545, UInt<1>(0h1), "") : assert_38
node _T_549 = or(portsDIO_filtered[17].valid, portsDIO_filtered_1[17].valid)
node _T_550 = eq(_T_549, UInt<1>(0h0))
node _T_551 = or(winner_19[0], winner_19[1])
node _T_552 = or(_T_550, _T_551)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_39
assert(clock, _T_552, UInt<1>(0h1), "") : assert_39
node maskedBeats_0_19 = mux(winner_19[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_19 = mux(winner_19[1], beatsDO_1, UInt<1>(0h0))
node initBeats_19 = or(maskedBeats_0_19, maskedBeats_1_19)
node _beatsLeft_T_76 = and(in[17].d.ready, in[17].d.valid)
node _beatsLeft_T_77 = sub(beatsLeft_19, _beatsLeft_T_76)
node _beatsLeft_T_78 = tail(_beatsLeft_T_77, 1)
node _beatsLeft_T_79 = mux(latch_19, initBeats_19, _beatsLeft_T_78)
connect beatsLeft_19, _beatsLeft_T_79
wire _state_WIRE_19 : UInt<1>[2]
connect _state_WIRE_19[0], UInt<1>(0h0)
connect _state_WIRE_19[1], UInt<1>(0h0)
regreset state_19 : UInt<1>[2], clock, reset, _state_WIRE_19
node muxState_19 = mux(idle_19, winner_19, state_19)
connect state_19, muxState_19
node allowed_19 = mux(idle_19, readys_19, state_19)
node _filtered_17_ready_T = and(in[17].d.ready, allowed_19[0])
connect portsDIO_filtered[17].ready, _filtered_17_ready_T
node _filtered_17_ready_T_1 = and(in[17].d.ready, allowed_19[1])
connect portsDIO_filtered_1[17].ready, _filtered_17_ready_T_1
node _in_17_d_valid_T = or(portsDIO_filtered[17].valid, portsDIO_filtered_1[17].valid)
node _in_17_d_valid_T_1 = mux(state_19[0], portsDIO_filtered[17].valid, UInt<1>(0h0))
node _in_17_d_valid_T_2 = mux(state_19[1], portsDIO_filtered_1[17].valid, UInt<1>(0h0))
node _in_17_d_valid_T_3 = or(_in_17_d_valid_T_1, _in_17_d_valid_T_2)
wire _in_17_d_valid_WIRE : UInt<1>
connect _in_17_d_valid_WIRE, _in_17_d_valid_T_3
node _in_17_d_valid_T_4 = mux(idle_19, _in_17_d_valid_T, _in_17_d_valid_WIRE)
connect in[17].d.valid, _in_17_d_valid_T_4
wire _in_17_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_17_d_bits_T = mux(muxState_19[0], portsDIO_filtered[17].bits.corrupt, UInt<1>(0h0))
node _in_17_d_bits_T_1 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.corrupt, UInt<1>(0h0))
node _in_17_d_bits_T_2 = or(_in_17_d_bits_T, _in_17_d_bits_T_1)
wire _in_17_d_bits_WIRE_1 : UInt<1>
connect _in_17_d_bits_WIRE_1, _in_17_d_bits_T_2
connect _in_17_d_bits_WIRE.corrupt, _in_17_d_bits_WIRE_1
node _in_17_d_bits_T_3 = mux(muxState_19[0], portsDIO_filtered[17].bits.data, UInt<1>(0h0))
node _in_17_d_bits_T_4 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.data, UInt<1>(0h0))
node _in_17_d_bits_T_5 = or(_in_17_d_bits_T_3, _in_17_d_bits_T_4)
wire _in_17_d_bits_WIRE_2 : UInt<64>
connect _in_17_d_bits_WIRE_2, _in_17_d_bits_T_5
connect _in_17_d_bits_WIRE.data, _in_17_d_bits_WIRE_2
wire _in_17_d_bits_WIRE_3 : { }
connect _in_17_d_bits_WIRE.echo, _in_17_d_bits_WIRE_3
wire _in_17_d_bits_WIRE_4 : { }
connect _in_17_d_bits_WIRE.user, _in_17_d_bits_WIRE_4
node _in_17_d_bits_T_6 = mux(muxState_19[0], portsDIO_filtered[17].bits.denied, UInt<1>(0h0))
node _in_17_d_bits_T_7 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.denied, UInt<1>(0h0))
node _in_17_d_bits_T_8 = or(_in_17_d_bits_T_6, _in_17_d_bits_T_7)
wire _in_17_d_bits_WIRE_5 : UInt<1>
connect _in_17_d_bits_WIRE_5, _in_17_d_bits_T_8
connect _in_17_d_bits_WIRE.denied, _in_17_d_bits_WIRE_5
node _in_17_d_bits_T_9 = mux(muxState_19[0], portsDIO_filtered[17].bits.sink, UInt<1>(0h0))
node _in_17_d_bits_T_10 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.sink, UInt<1>(0h0))
node _in_17_d_bits_T_11 = or(_in_17_d_bits_T_9, _in_17_d_bits_T_10)
wire _in_17_d_bits_WIRE_6 : UInt<3>
connect _in_17_d_bits_WIRE_6, _in_17_d_bits_T_11
connect _in_17_d_bits_WIRE.sink, _in_17_d_bits_WIRE_6
node _in_17_d_bits_T_12 = mux(muxState_19[0], portsDIO_filtered[17].bits.source, UInt<1>(0h0))
node _in_17_d_bits_T_13 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.source, UInt<1>(0h0))
node _in_17_d_bits_T_14 = or(_in_17_d_bits_T_12, _in_17_d_bits_T_13)
wire _in_17_d_bits_WIRE_7 : UInt<9>
connect _in_17_d_bits_WIRE_7, _in_17_d_bits_T_14
connect _in_17_d_bits_WIRE.source, _in_17_d_bits_WIRE_7
node _in_17_d_bits_T_15 = mux(muxState_19[0], portsDIO_filtered[17].bits.size, UInt<1>(0h0))
node _in_17_d_bits_T_16 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.size, UInt<1>(0h0))
node _in_17_d_bits_T_17 = or(_in_17_d_bits_T_15, _in_17_d_bits_T_16)
wire _in_17_d_bits_WIRE_8 : UInt<4>
connect _in_17_d_bits_WIRE_8, _in_17_d_bits_T_17
connect _in_17_d_bits_WIRE.size, _in_17_d_bits_WIRE_8
node _in_17_d_bits_T_18 = mux(muxState_19[0], portsDIO_filtered[17].bits.param, UInt<1>(0h0))
node _in_17_d_bits_T_19 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.param, UInt<1>(0h0))
node _in_17_d_bits_T_20 = or(_in_17_d_bits_T_18, _in_17_d_bits_T_19)
wire _in_17_d_bits_WIRE_9 : UInt<2>
connect _in_17_d_bits_WIRE_9, _in_17_d_bits_T_20
connect _in_17_d_bits_WIRE.param, _in_17_d_bits_WIRE_9
node _in_17_d_bits_T_21 = mux(muxState_19[0], portsDIO_filtered[17].bits.opcode, UInt<1>(0h0))
node _in_17_d_bits_T_22 = mux(muxState_19[1], portsDIO_filtered_1[17].bits.opcode, UInt<1>(0h0))
node _in_17_d_bits_T_23 = or(_in_17_d_bits_T_21, _in_17_d_bits_T_22)
wire _in_17_d_bits_WIRE_10 : UInt<3>
connect _in_17_d_bits_WIRE_10, _in_17_d_bits_T_23
connect _in_17_d_bits_WIRE.opcode, _in_17_d_bits_WIRE_10
connect in[17].d.bits.corrupt, _in_17_d_bits_WIRE.corrupt
connect in[17].d.bits.data, _in_17_d_bits_WIRE.data
connect in[17].d.bits.denied, _in_17_d_bits_WIRE.denied
connect in[17].d.bits.sink, _in_17_d_bits_WIRE.sink
connect in[17].d.bits.source, _in_17_d_bits_WIRE.source
connect in[17].d.bits.size, _in_17_d_bits_WIRE.size
connect in[17].d.bits.param, _in_17_d_bits_WIRE.param
connect in[17].d.bits.opcode, _in_17_d_bits_WIRE.opcode
connect portsBIO_filtered[17].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[17].ready, UInt<1>(0h0)
invalidate in[18].b.bits.corrupt
invalidate in[18].b.bits.data
invalidate in[18].b.bits.mask
invalidate in[18].b.bits.address
invalidate in[18].b.bits.source
invalidate in[18].b.bits.size
invalidate in[18].b.bits.param
invalidate in[18].b.bits.opcode
regreset beatsLeft_20 : UInt, clock, reset, UInt<1>(0h0)
node idle_20 = eq(beatsLeft_20, UInt<1>(0h0))
node latch_20 = and(idle_20, in[18].d.ready)
node _readys_T_236 = cat(portsDIO_filtered_1[18].valid, portsDIO_filtered[18].valid)
node readys_valid_20 = bits(_readys_T_236, 1, 0)
node _readys_T_237 = eq(readys_valid_20, _readys_T_236)
node _readys_T_238 = asUInt(reset)
node _readys_T_239 = eq(_readys_T_238, UInt<1>(0h0))
when _readys_T_239 :
node _readys_T_240 = eq(_readys_T_237, UInt<1>(0h0))
when _readys_T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_20
assert(clock, _readys_T_237, UInt<1>(0h1), "") : readys_assert_20
regreset readys_mask_20 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_40 = not(readys_mask_20)
node _readys_filter_T_41 = and(readys_valid_20, _readys_filter_T_40)
node readys_filter_20 = cat(_readys_filter_T_41, readys_valid_20)
node _readys_unready_T_116 = shr(readys_filter_20, 1)
node _readys_unready_T_117 = or(readys_filter_20, _readys_unready_T_116)
node _readys_unready_T_118 = bits(_readys_unready_T_117, 3, 0)
node _readys_unready_T_119 = shr(_readys_unready_T_118, 1)
node _readys_unready_T_120 = shl(readys_mask_20, 2)
node readys_unready_20 = or(_readys_unready_T_119, _readys_unready_T_120)
node _readys_readys_T_60 = shr(readys_unready_20, 2)
node _readys_readys_T_61 = bits(readys_unready_20, 1, 0)
node _readys_readys_T_62 = and(_readys_readys_T_60, _readys_readys_T_61)
node readys_readys_20 = not(_readys_readys_T_62)
node _readys_T_241 = orr(readys_valid_20)
node _readys_T_242 = and(latch_20, _readys_T_241)
when _readys_T_242 :
node _readys_mask_T_124 = and(readys_readys_20, readys_valid_20)
node _readys_mask_T_125 = shl(_readys_mask_T_124, 1)
node _readys_mask_T_126 = bits(_readys_mask_T_125, 1, 0)
node _readys_mask_T_127 = or(_readys_mask_T_124, _readys_mask_T_126)
node _readys_mask_T_128 = bits(_readys_mask_T_127, 1, 0)
connect readys_mask_20, _readys_mask_T_128
node _readys_T_243 = bits(readys_readys_20, 1, 0)
node _readys_T_244 = bits(_readys_T_243, 0, 0)
node _readys_T_245 = bits(_readys_T_243, 1, 1)
wire readys_20 : UInt<1>[2]
connect readys_20[0], _readys_T_244
connect readys_20[1], _readys_T_245
node _winner_T_76 = and(readys_20[0], portsDIO_filtered[18].valid)
node _winner_T_77 = and(readys_20[1], portsDIO_filtered_1[18].valid)
wire winner_20 : UInt<1>[2]
connect winner_20[0], _winner_T_76
connect winner_20[1], _winner_T_77
node prefixOR_1_20 = or(UInt<1>(0h0), winner_20[0])
node _prefixOR_T_20 = or(prefixOR_1_20, winner_20[1])
node _T_556 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_557 = eq(winner_20[0], UInt<1>(0h0))
node _T_558 = or(_T_556, _T_557)
node _T_559 = eq(prefixOR_1_20, UInt<1>(0h0))
node _T_560 = eq(winner_20[1], UInt<1>(0h0))
node _T_561 = or(_T_559, _T_560)
node _T_562 = and(_T_558, _T_561)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_40
assert(clock, _T_562, UInt<1>(0h1), "") : assert_40
node _T_566 = or(portsDIO_filtered[18].valid, portsDIO_filtered_1[18].valid)
node _T_567 = eq(_T_566, UInt<1>(0h0))
node _T_568 = or(winner_20[0], winner_20[1])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_41
assert(clock, _T_569, UInt<1>(0h1), "") : assert_41
node maskedBeats_0_20 = mux(winner_20[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_20 = mux(winner_20[1], beatsDO_1, UInt<1>(0h0))
node initBeats_20 = or(maskedBeats_0_20, maskedBeats_1_20)
node _beatsLeft_T_80 = and(in[18].d.ready, in[18].d.valid)
node _beatsLeft_T_81 = sub(beatsLeft_20, _beatsLeft_T_80)
node _beatsLeft_T_82 = tail(_beatsLeft_T_81, 1)
node _beatsLeft_T_83 = mux(latch_20, initBeats_20, _beatsLeft_T_82)
connect beatsLeft_20, _beatsLeft_T_83
wire _state_WIRE_20 : UInt<1>[2]
connect _state_WIRE_20[0], UInt<1>(0h0)
connect _state_WIRE_20[1], UInt<1>(0h0)
regreset state_20 : UInt<1>[2], clock, reset, _state_WIRE_20
node muxState_20 = mux(idle_20, winner_20, state_20)
connect state_20, muxState_20
node allowed_20 = mux(idle_20, readys_20, state_20)
node _filtered_18_ready_T = and(in[18].d.ready, allowed_20[0])
connect portsDIO_filtered[18].ready, _filtered_18_ready_T
node _filtered_18_ready_T_1 = and(in[18].d.ready, allowed_20[1])
connect portsDIO_filtered_1[18].ready, _filtered_18_ready_T_1
node _in_18_d_valid_T = or(portsDIO_filtered[18].valid, portsDIO_filtered_1[18].valid)
node _in_18_d_valid_T_1 = mux(state_20[0], portsDIO_filtered[18].valid, UInt<1>(0h0))
node _in_18_d_valid_T_2 = mux(state_20[1], portsDIO_filtered_1[18].valid, UInt<1>(0h0))
node _in_18_d_valid_T_3 = or(_in_18_d_valid_T_1, _in_18_d_valid_T_2)
wire _in_18_d_valid_WIRE : UInt<1>
connect _in_18_d_valid_WIRE, _in_18_d_valid_T_3
node _in_18_d_valid_T_4 = mux(idle_20, _in_18_d_valid_T, _in_18_d_valid_WIRE)
connect in[18].d.valid, _in_18_d_valid_T_4
wire _in_18_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_18_d_bits_T = mux(muxState_20[0], portsDIO_filtered[18].bits.corrupt, UInt<1>(0h0))
node _in_18_d_bits_T_1 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.corrupt, UInt<1>(0h0))
node _in_18_d_bits_T_2 = or(_in_18_d_bits_T, _in_18_d_bits_T_1)
wire _in_18_d_bits_WIRE_1 : UInt<1>
connect _in_18_d_bits_WIRE_1, _in_18_d_bits_T_2
connect _in_18_d_bits_WIRE.corrupt, _in_18_d_bits_WIRE_1
node _in_18_d_bits_T_3 = mux(muxState_20[0], portsDIO_filtered[18].bits.data, UInt<1>(0h0))
node _in_18_d_bits_T_4 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.data, UInt<1>(0h0))
node _in_18_d_bits_T_5 = or(_in_18_d_bits_T_3, _in_18_d_bits_T_4)
wire _in_18_d_bits_WIRE_2 : UInt<64>
connect _in_18_d_bits_WIRE_2, _in_18_d_bits_T_5
connect _in_18_d_bits_WIRE.data, _in_18_d_bits_WIRE_2
wire _in_18_d_bits_WIRE_3 : { }
connect _in_18_d_bits_WIRE.echo, _in_18_d_bits_WIRE_3
wire _in_18_d_bits_WIRE_4 : { }
connect _in_18_d_bits_WIRE.user, _in_18_d_bits_WIRE_4
node _in_18_d_bits_T_6 = mux(muxState_20[0], portsDIO_filtered[18].bits.denied, UInt<1>(0h0))
node _in_18_d_bits_T_7 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.denied, UInt<1>(0h0))
node _in_18_d_bits_T_8 = or(_in_18_d_bits_T_6, _in_18_d_bits_T_7)
wire _in_18_d_bits_WIRE_5 : UInt<1>
connect _in_18_d_bits_WIRE_5, _in_18_d_bits_T_8
connect _in_18_d_bits_WIRE.denied, _in_18_d_bits_WIRE_5
node _in_18_d_bits_T_9 = mux(muxState_20[0], portsDIO_filtered[18].bits.sink, UInt<1>(0h0))
node _in_18_d_bits_T_10 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.sink, UInt<1>(0h0))
node _in_18_d_bits_T_11 = or(_in_18_d_bits_T_9, _in_18_d_bits_T_10)
wire _in_18_d_bits_WIRE_6 : UInt<3>
connect _in_18_d_bits_WIRE_6, _in_18_d_bits_T_11
connect _in_18_d_bits_WIRE.sink, _in_18_d_bits_WIRE_6
node _in_18_d_bits_T_12 = mux(muxState_20[0], portsDIO_filtered[18].bits.source, UInt<1>(0h0))
node _in_18_d_bits_T_13 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.source, UInt<1>(0h0))
node _in_18_d_bits_T_14 = or(_in_18_d_bits_T_12, _in_18_d_bits_T_13)
wire _in_18_d_bits_WIRE_7 : UInt<9>
connect _in_18_d_bits_WIRE_7, _in_18_d_bits_T_14
connect _in_18_d_bits_WIRE.source, _in_18_d_bits_WIRE_7
node _in_18_d_bits_T_15 = mux(muxState_20[0], portsDIO_filtered[18].bits.size, UInt<1>(0h0))
node _in_18_d_bits_T_16 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.size, UInt<1>(0h0))
node _in_18_d_bits_T_17 = or(_in_18_d_bits_T_15, _in_18_d_bits_T_16)
wire _in_18_d_bits_WIRE_8 : UInt<4>
connect _in_18_d_bits_WIRE_8, _in_18_d_bits_T_17
connect _in_18_d_bits_WIRE.size, _in_18_d_bits_WIRE_8
node _in_18_d_bits_T_18 = mux(muxState_20[0], portsDIO_filtered[18].bits.param, UInt<1>(0h0))
node _in_18_d_bits_T_19 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.param, UInt<1>(0h0))
node _in_18_d_bits_T_20 = or(_in_18_d_bits_T_18, _in_18_d_bits_T_19)
wire _in_18_d_bits_WIRE_9 : UInt<2>
connect _in_18_d_bits_WIRE_9, _in_18_d_bits_T_20
connect _in_18_d_bits_WIRE.param, _in_18_d_bits_WIRE_9
node _in_18_d_bits_T_21 = mux(muxState_20[0], portsDIO_filtered[18].bits.opcode, UInt<1>(0h0))
node _in_18_d_bits_T_22 = mux(muxState_20[1], portsDIO_filtered_1[18].bits.opcode, UInt<1>(0h0))
node _in_18_d_bits_T_23 = or(_in_18_d_bits_T_21, _in_18_d_bits_T_22)
wire _in_18_d_bits_WIRE_10 : UInt<3>
connect _in_18_d_bits_WIRE_10, _in_18_d_bits_T_23
connect _in_18_d_bits_WIRE.opcode, _in_18_d_bits_WIRE_10
connect in[18].d.bits.corrupt, _in_18_d_bits_WIRE.corrupt
connect in[18].d.bits.data, _in_18_d_bits_WIRE.data
connect in[18].d.bits.denied, _in_18_d_bits_WIRE.denied
connect in[18].d.bits.sink, _in_18_d_bits_WIRE.sink
connect in[18].d.bits.source, _in_18_d_bits_WIRE.source
connect in[18].d.bits.size, _in_18_d_bits_WIRE.size
connect in[18].d.bits.param, _in_18_d_bits_WIRE.param
connect in[18].d.bits.opcode, _in_18_d_bits_WIRE.opcode
connect portsBIO_filtered[18].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[18].ready, UInt<1>(0h0)
connect in[19].b, portsBIO_filtered_1[19]
regreset beatsLeft_21 : UInt, clock, reset, UInt<1>(0h0)
node idle_21 = eq(beatsLeft_21, UInt<1>(0h0))
node latch_21 = and(idle_21, in[19].d.ready)
node _readys_T_246 = cat(portsDIO_filtered_1[19].valid, portsDIO_filtered[19].valid)
node readys_valid_21 = bits(_readys_T_246, 1, 0)
node _readys_T_247 = eq(readys_valid_21, _readys_T_246)
node _readys_T_248 = asUInt(reset)
node _readys_T_249 = eq(_readys_T_248, UInt<1>(0h0))
when _readys_T_249 :
node _readys_T_250 = eq(_readys_T_247, UInt<1>(0h0))
when _readys_T_250 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_21
assert(clock, _readys_T_247, UInt<1>(0h1), "") : readys_assert_21
regreset readys_mask_21 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_42 = not(readys_mask_21)
node _readys_filter_T_43 = and(readys_valid_21, _readys_filter_T_42)
node readys_filter_21 = cat(_readys_filter_T_43, readys_valid_21)
node _readys_unready_T_121 = shr(readys_filter_21, 1)
node _readys_unready_T_122 = or(readys_filter_21, _readys_unready_T_121)
node _readys_unready_T_123 = bits(_readys_unready_T_122, 3, 0)
node _readys_unready_T_124 = shr(_readys_unready_T_123, 1)
node _readys_unready_T_125 = shl(readys_mask_21, 2)
node readys_unready_21 = or(_readys_unready_T_124, _readys_unready_T_125)
node _readys_readys_T_63 = shr(readys_unready_21, 2)
node _readys_readys_T_64 = bits(readys_unready_21, 1, 0)
node _readys_readys_T_65 = and(_readys_readys_T_63, _readys_readys_T_64)
node readys_readys_21 = not(_readys_readys_T_65)
node _readys_T_251 = orr(readys_valid_21)
node _readys_T_252 = and(latch_21, _readys_T_251)
when _readys_T_252 :
node _readys_mask_T_129 = and(readys_readys_21, readys_valid_21)
node _readys_mask_T_130 = shl(_readys_mask_T_129, 1)
node _readys_mask_T_131 = bits(_readys_mask_T_130, 1, 0)
node _readys_mask_T_132 = or(_readys_mask_T_129, _readys_mask_T_131)
node _readys_mask_T_133 = bits(_readys_mask_T_132, 1, 0)
connect readys_mask_21, _readys_mask_T_133
node _readys_T_253 = bits(readys_readys_21, 1, 0)
node _readys_T_254 = bits(_readys_T_253, 0, 0)
node _readys_T_255 = bits(_readys_T_253, 1, 1)
wire readys_21 : UInt<1>[2]
connect readys_21[0], _readys_T_254
connect readys_21[1], _readys_T_255
node _winner_T_78 = and(readys_21[0], portsDIO_filtered[19].valid)
node _winner_T_79 = and(readys_21[1], portsDIO_filtered_1[19].valid)
wire winner_21 : UInt<1>[2]
connect winner_21[0], _winner_T_78
connect winner_21[1], _winner_T_79
node prefixOR_1_21 = or(UInt<1>(0h0), winner_21[0])
node _prefixOR_T_21 = or(prefixOR_1_21, winner_21[1])
node _T_573 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_574 = eq(winner_21[0], UInt<1>(0h0))
node _T_575 = or(_T_573, _T_574)
node _T_576 = eq(prefixOR_1_21, UInt<1>(0h0))
node _T_577 = eq(winner_21[1], UInt<1>(0h0))
node _T_578 = or(_T_576, _T_577)
node _T_579 = and(_T_575, _T_578)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_42
assert(clock, _T_579, UInt<1>(0h1), "") : assert_42
node _T_583 = or(portsDIO_filtered[19].valid, portsDIO_filtered_1[19].valid)
node _T_584 = eq(_T_583, UInt<1>(0h0))
node _T_585 = or(winner_21[0], winner_21[1])
node _T_586 = or(_T_584, _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_43
assert(clock, _T_586, UInt<1>(0h1), "") : assert_43
node maskedBeats_0_21 = mux(winner_21[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_21 = mux(winner_21[1], beatsDO_1, UInt<1>(0h0))
node initBeats_21 = or(maskedBeats_0_21, maskedBeats_1_21)
node _beatsLeft_T_84 = and(in[19].d.ready, in[19].d.valid)
node _beatsLeft_T_85 = sub(beatsLeft_21, _beatsLeft_T_84)
node _beatsLeft_T_86 = tail(_beatsLeft_T_85, 1)
node _beatsLeft_T_87 = mux(latch_21, initBeats_21, _beatsLeft_T_86)
connect beatsLeft_21, _beatsLeft_T_87
wire _state_WIRE_21 : UInt<1>[2]
connect _state_WIRE_21[0], UInt<1>(0h0)
connect _state_WIRE_21[1], UInt<1>(0h0)
regreset state_21 : UInt<1>[2], clock, reset, _state_WIRE_21
node muxState_21 = mux(idle_21, winner_21, state_21)
connect state_21, muxState_21
node allowed_21 = mux(idle_21, readys_21, state_21)
node _filtered_19_ready_T = and(in[19].d.ready, allowed_21[0])
connect portsDIO_filtered[19].ready, _filtered_19_ready_T
node _filtered_19_ready_T_1 = and(in[19].d.ready, allowed_21[1])
connect portsDIO_filtered_1[19].ready, _filtered_19_ready_T_1
node _in_19_d_valid_T = or(portsDIO_filtered[19].valid, portsDIO_filtered_1[19].valid)
node _in_19_d_valid_T_1 = mux(state_21[0], portsDIO_filtered[19].valid, UInt<1>(0h0))
node _in_19_d_valid_T_2 = mux(state_21[1], portsDIO_filtered_1[19].valid, UInt<1>(0h0))
node _in_19_d_valid_T_3 = or(_in_19_d_valid_T_1, _in_19_d_valid_T_2)
wire _in_19_d_valid_WIRE : UInt<1>
connect _in_19_d_valid_WIRE, _in_19_d_valid_T_3
node _in_19_d_valid_T_4 = mux(idle_21, _in_19_d_valid_T, _in_19_d_valid_WIRE)
connect in[19].d.valid, _in_19_d_valid_T_4
wire _in_19_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_19_d_bits_T = mux(muxState_21[0], portsDIO_filtered[19].bits.corrupt, UInt<1>(0h0))
node _in_19_d_bits_T_1 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.corrupt, UInt<1>(0h0))
node _in_19_d_bits_T_2 = or(_in_19_d_bits_T, _in_19_d_bits_T_1)
wire _in_19_d_bits_WIRE_1 : UInt<1>
connect _in_19_d_bits_WIRE_1, _in_19_d_bits_T_2
connect _in_19_d_bits_WIRE.corrupt, _in_19_d_bits_WIRE_1
node _in_19_d_bits_T_3 = mux(muxState_21[0], portsDIO_filtered[19].bits.data, UInt<1>(0h0))
node _in_19_d_bits_T_4 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.data, UInt<1>(0h0))
node _in_19_d_bits_T_5 = or(_in_19_d_bits_T_3, _in_19_d_bits_T_4)
wire _in_19_d_bits_WIRE_2 : UInt<64>
connect _in_19_d_bits_WIRE_2, _in_19_d_bits_T_5
connect _in_19_d_bits_WIRE.data, _in_19_d_bits_WIRE_2
wire _in_19_d_bits_WIRE_3 : { }
connect _in_19_d_bits_WIRE.echo, _in_19_d_bits_WIRE_3
wire _in_19_d_bits_WIRE_4 : { }
connect _in_19_d_bits_WIRE.user, _in_19_d_bits_WIRE_4
node _in_19_d_bits_T_6 = mux(muxState_21[0], portsDIO_filtered[19].bits.denied, UInt<1>(0h0))
node _in_19_d_bits_T_7 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.denied, UInt<1>(0h0))
node _in_19_d_bits_T_8 = or(_in_19_d_bits_T_6, _in_19_d_bits_T_7)
wire _in_19_d_bits_WIRE_5 : UInt<1>
connect _in_19_d_bits_WIRE_5, _in_19_d_bits_T_8
connect _in_19_d_bits_WIRE.denied, _in_19_d_bits_WIRE_5
node _in_19_d_bits_T_9 = mux(muxState_21[0], portsDIO_filtered[19].bits.sink, UInt<1>(0h0))
node _in_19_d_bits_T_10 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.sink, UInt<1>(0h0))
node _in_19_d_bits_T_11 = or(_in_19_d_bits_T_9, _in_19_d_bits_T_10)
wire _in_19_d_bits_WIRE_6 : UInt<3>
connect _in_19_d_bits_WIRE_6, _in_19_d_bits_T_11
connect _in_19_d_bits_WIRE.sink, _in_19_d_bits_WIRE_6
node _in_19_d_bits_T_12 = mux(muxState_21[0], portsDIO_filtered[19].bits.source, UInt<1>(0h0))
node _in_19_d_bits_T_13 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.source, UInt<1>(0h0))
node _in_19_d_bits_T_14 = or(_in_19_d_bits_T_12, _in_19_d_bits_T_13)
wire _in_19_d_bits_WIRE_7 : UInt<9>
connect _in_19_d_bits_WIRE_7, _in_19_d_bits_T_14
connect _in_19_d_bits_WIRE.source, _in_19_d_bits_WIRE_7
node _in_19_d_bits_T_15 = mux(muxState_21[0], portsDIO_filtered[19].bits.size, UInt<1>(0h0))
node _in_19_d_bits_T_16 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.size, UInt<1>(0h0))
node _in_19_d_bits_T_17 = or(_in_19_d_bits_T_15, _in_19_d_bits_T_16)
wire _in_19_d_bits_WIRE_8 : UInt<4>
connect _in_19_d_bits_WIRE_8, _in_19_d_bits_T_17
connect _in_19_d_bits_WIRE.size, _in_19_d_bits_WIRE_8
node _in_19_d_bits_T_18 = mux(muxState_21[0], portsDIO_filtered[19].bits.param, UInt<1>(0h0))
node _in_19_d_bits_T_19 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.param, UInt<1>(0h0))
node _in_19_d_bits_T_20 = or(_in_19_d_bits_T_18, _in_19_d_bits_T_19)
wire _in_19_d_bits_WIRE_9 : UInt<2>
connect _in_19_d_bits_WIRE_9, _in_19_d_bits_T_20
connect _in_19_d_bits_WIRE.param, _in_19_d_bits_WIRE_9
node _in_19_d_bits_T_21 = mux(muxState_21[0], portsDIO_filtered[19].bits.opcode, UInt<1>(0h0))
node _in_19_d_bits_T_22 = mux(muxState_21[1], portsDIO_filtered_1[19].bits.opcode, UInt<1>(0h0))
node _in_19_d_bits_T_23 = or(_in_19_d_bits_T_21, _in_19_d_bits_T_22)
wire _in_19_d_bits_WIRE_10 : UInt<3>
connect _in_19_d_bits_WIRE_10, _in_19_d_bits_T_23
connect _in_19_d_bits_WIRE.opcode, _in_19_d_bits_WIRE_10
connect in[19].d.bits.corrupt, _in_19_d_bits_WIRE.corrupt
connect in[19].d.bits.data, _in_19_d_bits_WIRE.data
connect in[19].d.bits.denied, _in_19_d_bits_WIRE.denied
connect in[19].d.bits.sink, _in_19_d_bits_WIRE.sink
connect in[19].d.bits.source, _in_19_d_bits_WIRE.source
connect in[19].d.bits.size, _in_19_d_bits_WIRE.size
connect in[19].d.bits.param, _in_19_d_bits_WIRE.param
connect in[19].d.bits.opcode, _in_19_d_bits_WIRE.opcode
connect portsBIO_filtered[19].ready, UInt<1>(0h0) | module TLXbar_sbus_i20_o2_a32d64s9k3z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_19_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_19_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_19_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_19_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_19_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_19_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_19_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_19_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_19_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_19_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_19_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_19_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_19_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_19_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_19_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_19_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_19_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_19_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_19_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_19_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_19_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_19_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_19_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_19_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_19_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_19_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_19_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_19_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_19_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_18_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_18_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_18_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_18_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_18_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_18_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_18_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_18_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_18_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_18_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_18_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_18_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_18_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_18_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_18_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_18_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_18_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_17_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_17_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_17_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_17_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_17_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_17_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_17_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_17_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_17_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_17_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_17_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_17_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_17_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_17_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_17_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_17_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_16_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_16_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_16_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_16_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_16_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_16_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_16_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_16_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_16_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_16_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_16_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_16_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_16_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_16_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_16_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_16_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_15_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_15_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_15_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_15_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_15_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_15_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_15_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_15_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_15_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_15_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_15_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_15_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_15_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_15_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_15_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_15_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_14_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_14_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_14_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_14_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_14_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_14_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_14_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_14_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_14_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_14_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_14_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_14_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_14_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_14_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_14_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_14_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_13_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_13_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_13_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_13_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_13_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_13_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_13_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_13_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_13_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_13_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_13_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_13_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_13_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_13_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_13_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_13_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_12_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_12_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_12_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_12_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_12_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_12_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_12_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_12_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_12_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_12_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_12_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_12_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_12_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_12_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_12_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_12_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_11_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_11_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_11_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_11_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_11_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_11_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_11_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_11_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_11_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_11_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_11_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_11_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_11_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_11_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_11_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_11_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_10_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_10_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_10_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_10_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_10_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_10_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_10_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_10_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_10_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_10_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_10_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_10_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_10_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_10_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_10_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_10_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_9_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_9_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_9_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_9_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_9_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_9_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_9_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_9_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_9_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_9_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_9_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_9_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_9_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_9_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_9_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_9_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_8_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_8_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_8_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_8_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_8_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_8_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_8_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_8_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_8_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_8_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_8_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_8_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_8_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_8_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_8_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_8_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_7_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_7_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_7_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_7_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_6_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_6_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_6_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_6_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_6_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_6_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_6_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_5_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_5_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_5_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_5_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_5_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_5_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_5_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_4_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_4_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_4_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_4_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [2:0] out_1_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [8:0] in_19_c_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_19_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_18_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_17_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_16_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_15_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_14_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_13_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_12_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_11_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_10_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_9_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_8_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_7_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_6_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_5_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_4_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_3_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_2_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_19_a_valid_0 = auto_anon_in_19_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_a_bits_opcode_0 = auto_anon_in_19_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_a_bits_param_0 = auto_anon_in_19_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_19_a_bits_size_0 = auto_anon_in_19_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_19_a_bits_source_0 = auto_anon_in_19_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_19_a_bits_address_0 = auto_anon_in_19_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_19_a_bits_mask_0 = auto_anon_in_19_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_19_a_bits_data_0 = auto_anon_in_19_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_19_a_bits_corrupt_0 = auto_anon_in_19_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_19_b_ready_0 = auto_anon_in_19_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_19_c_valid_0 = auto_anon_in_19_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_c_bits_opcode_0 = auto_anon_in_19_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_c_bits_param_0 = auto_anon_in_19_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_19_c_bits_size_0 = auto_anon_in_19_c_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_19_c_bits_source_0 = auto_anon_in_19_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_19_c_bits_address_0 = auto_anon_in_19_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_19_c_bits_data_0 = auto_anon_in_19_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_19_c_bits_corrupt_0 = auto_anon_in_19_c_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_19_d_ready_0 = auto_anon_in_19_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_19_e_valid_0 = auto_anon_in_19_e_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_e_bits_sink_0 = auto_anon_in_19_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_in_18_a_valid_0 = auto_anon_in_18_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_18_a_bits_opcode_0 = auto_anon_in_18_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_18_a_bits_param_0 = auto_anon_in_18_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_18_a_bits_size_0 = auto_anon_in_18_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_18_a_bits_source_0 = auto_anon_in_18_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_18_a_bits_address_0 = auto_anon_in_18_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_18_a_bits_mask_0 = auto_anon_in_18_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_18_a_bits_data_0 = auto_anon_in_18_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_18_a_bits_corrupt_0 = auto_anon_in_18_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_18_d_ready_0 = auto_anon_in_18_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_17_a_valid_0 = auto_anon_in_17_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_17_a_bits_opcode_0 = auto_anon_in_17_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_17_a_bits_param_0 = auto_anon_in_17_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_17_a_bits_size_0 = auto_anon_in_17_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_17_a_bits_source_0 = auto_anon_in_17_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_17_a_bits_address_0 = auto_anon_in_17_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_17_a_bits_mask_0 = auto_anon_in_17_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_17_a_bits_data_0 = auto_anon_in_17_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_17_a_bits_corrupt_0 = auto_anon_in_17_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_17_d_ready_0 = auto_anon_in_17_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_16_a_valid_0 = auto_anon_in_16_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_16_a_bits_opcode_0 = auto_anon_in_16_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_16_a_bits_param_0 = auto_anon_in_16_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_16_a_bits_size_0 = auto_anon_in_16_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_16_a_bits_source_0 = auto_anon_in_16_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_16_a_bits_address_0 = auto_anon_in_16_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_16_a_bits_mask_0 = auto_anon_in_16_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_16_a_bits_data_0 = auto_anon_in_16_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_16_a_bits_corrupt_0 = auto_anon_in_16_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_16_d_ready_0 = auto_anon_in_16_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_15_a_valid_0 = auto_anon_in_15_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_15_a_bits_opcode_0 = auto_anon_in_15_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_15_a_bits_param_0 = auto_anon_in_15_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_15_a_bits_size_0 = auto_anon_in_15_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_15_a_bits_source_0 = auto_anon_in_15_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_15_a_bits_address_0 = auto_anon_in_15_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_15_a_bits_mask_0 = auto_anon_in_15_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_15_a_bits_data_0 = auto_anon_in_15_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_15_a_bits_corrupt_0 = auto_anon_in_15_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_15_d_ready_0 = auto_anon_in_15_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_14_a_valid_0 = auto_anon_in_14_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_14_a_bits_opcode_0 = auto_anon_in_14_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_14_a_bits_param_0 = auto_anon_in_14_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_14_a_bits_size_0 = auto_anon_in_14_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_14_a_bits_source_0 = auto_anon_in_14_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_14_a_bits_address_0 = auto_anon_in_14_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_14_a_bits_mask_0 = auto_anon_in_14_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_14_a_bits_data_0 = auto_anon_in_14_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_14_a_bits_corrupt_0 = auto_anon_in_14_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_14_d_ready_0 = auto_anon_in_14_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_13_a_valid_0 = auto_anon_in_13_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_13_a_bits_opcode_0 = auto_anon_in_13_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_13_a_bits_param_0 = auto_anon_in_13_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_13_a_bits_size_0 = auto_anon_in_13_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_13_a_bits_source_0 = auto_anon_in_13_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_13_a_bits_address_0 = auto_anon_in_13_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_13_a_bits_mask_0 = auto_anon_in_13_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_13_a_bits_data_0 = auto_anon_in_13_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_13_a_bits_corrupt_0 = auto_anon_in_13_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_13_d_ready_0 = auto_anon_in_13_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_12_a_valid_0 = auto_anon_in_12_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_12_a_bits_opcode_0 = auto_anon_in_12_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_12_a_bits_param_0 = auto_anon_in_12_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_12_a_bits_size_0 = auto_anon_in_12_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_12_a_bits_source_0 = auto_anon_in_12_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_12_a_bits_address_0 = auto_anon_in_12_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_12_a_bits_mask_0 = auto_anon_in_12_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_12_a_bits_data_0 = auto_anon_in_12_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_12_a_bits_corrupt_0 = auto_anon_in_12_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_12_d_ready_0 = auto_anon_in_12_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_11_a_valid_0 = auto_anon_in_11_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_11_a_bits_opcode_0 = auto_anon_in_11_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_11_a_bits_param_0 = auto_anon_in_11_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_11_a_bits_size_0 = auto_anon_in_11_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_11_a_bits_source_0 = auto_anon_in_11_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_11_a_bits_address_0 = auto_anon_in_11_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_11_a_bits_mask_0 = auto_anon_in_11_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_11_a_bits_data_0 = auto_anon_in_11_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_11_a_bits_corrupt_0 = auto_anon_in_11_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_11_d_ready_0 = auto_anon_in_11_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_10_a_valid_0 = auto_anon_in_10_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_10_a_bits_opcode_0 = auto_anon_in_10_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_10_a_bits_param_0 = auto_anon_in_10_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_10_a_bits_size_0 = auto_anon_in_10_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_10_a_bits_source_0 = auto_anon_in_10_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_10_a_bits_address_0 = auto_anon_in_10_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_10_a_bits_mask_0 = auto_anon_in_10_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_10_a_bits_data_0 = auto_anon_in_10_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_10_a_bits_corrupt_0 = auto_anon_in_10_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_10_d_ready_0 = auto_anon_in_10_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_9_a_valid_0 = auto_anon_in_9_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_9_a_bits_opcode_0 = auto_anon_in_9_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_9_a_bits_param_0 = auto_anon_in_9_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_9_a_bits_size_0 = auto_anon_in_9_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_9_a_bits_source_0 = auto_anon_in_9_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_9_a_bits_address_0 = auto_anon_in_9_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_9_a_bits_mask_0 = auto_anon_in_9_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_9_a_bits_data_0 = auto_anon_in_9_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_9_a_bits_corrupt_0 = auto_anon_in_9_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_9_d_ready_0 = auto_anon_in_9_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_8_a_valid_0 = auto_anon_in_8_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_8_a_bits_opcode_0 = auto_anon_in_8_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_8_a_bits_param_0 = auto_anon_in_8_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_8_a_bits_size_0 = auto_anon_in_8_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_8_a_bits_source_0 = auto_anon_in_8_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_8_a_bits_address_0 = auto_anon_in_8_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_8_a_bits_mask_0 = auto_anon_in_8_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_8_a_bits_data_0 = auto_anon_in_8_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_8_a_bits_corrupt_0 = auto_anon_in_8_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_8_d_ready_0 = auto_anon_in_8_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_7_a_valid_0 = auto_anon_in_7_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_7_a_bits_opcode_0 = auto_anon_in_7_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_7_a_bits_param_0 = auto_anon_in_7_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_7_a_bits_size_0 = auto_anon_in_7_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_7_a_bits_source_0 = auto_anon_in_7_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_7_a_bits_address_0 = auto_anon_in_7_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_7_a_bits_mask_0 = auto_anon_in_7_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_7_a_bits_data_0 = auto_anon_in_7_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_7_a_bits_corrupt_0 = auto_anon_in_7_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_7_d_ready_0 = auto_anon_in_7_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_6_a_valid_0 = auto_anon_in_6_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_6_a_bits_opcode_0 = auto_anon_in_6_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_6_a_bits_param_0 = auto_anon_in_6_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_6_a_bits_size_0 = auto_anon_in_6_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_6_a_bits_source_0 = auto_anon_in_6_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_6_a_bits_address_0 = auto_anon_in_6_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_6_a_bits_mask_0 = auto_anon_in_6_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_6_a_bits_data_0 = auto_anon_in_6_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_6_a_bits_corrupt_0 = auto_anon_in_6_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_6_d_ready_0 = auto_anon_in_6_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_5_a_valid_0 = auto_anon_in_5_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_5_a_bits_opcode_0 = auto_anon_in_5_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_5_a_bits_param_0 = auto_anon_in_5_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_5_a_bits_size_0 = auto_anon_in_5_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_5_a_bits_source_0 = auto_anon_in_5_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_5_a_bits_address_0 = auto_anon_in_5_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_5_a_bits_mask_0 = auto_anon_in_5_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_5_a_bits_data_0 = auto_anon_in_5_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_5_a_bits_corrupt_0 = auto_anon_in_5_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_5_d_ready_0 = auto_anon_in_5_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_4_a_valid_0 = auto_anon_in_4_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_4_a_bits_opcode_0 = auto_anon_in_4_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_4_a_bits_param_0 = auto_anon_in_4_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_4_a_bits_size_0 = auto_anon_in_4_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_4_a_bits_source_0 = auto_anon_in_4_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_4_a_bits_address_0 = auto_anon_in_4_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_4_a_bits_mask_0 = auto_anon_in_4_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_4_a_bits_data_0 = auto_anon_in_4_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_4_a_bits_corrupt_0 = auto_anon_in_4_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_4_d_ready_0 = auto_anon_in_4_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_3_a_valid_0 = auto_anon_in_3_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_3_a_bits_opcode_0 = auto_anon_in_3_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_3_a_bits_param_0 = auto_anon_in_3_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_3_a_bits_size_0 = auto_anon_in_3_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_3_a_bits_source_0 = auto_anon_in_3_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_3_a_bits_address_0 = auto_anon_in_3_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_3_a_bits_mask_0 = auto_anon_in_3_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_3_a_bits_data_0 = auto_anon_in_3_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_3_a_bits_corrupt_0 = auto_anon_in_3_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_3_d_ready_0 = auto_anon_in_3_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_a_bits_opcode_0 = auto_anon_in_2_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_a_bits_param_0 = auto_anon_in_2_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_a_bits_size_0 = auto_anon_in_2_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_2_a_bits_source_0 = auto_anon_in_2_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_2_a_bits_mask_0 = auto_anon_in_2_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_2_a_bits_data_0 = auto_anon_in_2_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_bits_corrupt_0 = auto_anon_in_2_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_ready_0 = auto_anon_in_2_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9]
wire [8:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9]
wire [8:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_30 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_58 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_68 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_78 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_88 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_98 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_108 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_118 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_128 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_138 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_148 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_158 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_168 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_178 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_188 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_198 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_208 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_218 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_228 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_238 = reset; // @[Arbiter.scala:22:12]
wire _readys_T_248 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_19_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_b_bits_size = 3'h6; // @[Xbar.scala:74:9]
wire [2:0] anonIn_19_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] in_19_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_2_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_3_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_4_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_5_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_6_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_7_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_8_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_9_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_10_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_11_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_12_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_13_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_14_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_15_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_16_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_17_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_18_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_19_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [3:0] auto_anon_in_19_b_bits_size = 4'h6; // @[Xbar.scala:74:9]
wire [3:0] anonIn_19_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] in_19_b_bits_size = 4'h6; // @[Xbar.scala:159:18]
wire [3:0] out_1_b_bits_size = 4'h6; // @[Xbar.scala:216:19]
wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_2_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_3_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_4_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_5_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_6_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_7_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_8_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_9_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_10_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_11_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_12_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_13_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_14_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_15_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_16_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_17_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_18_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_19_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire [1:0] auto_anon_in_19_b_bits_source = 2'h0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_19_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_2_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_3_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_4_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_5_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_6_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_7_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_8_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_9_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_10_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_11_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_12_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_13_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_14_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_15_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_16_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_17_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_18_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] _anonIn_b_bits_source_T = 2'h0; // @[Xbar.scala:156:69]
wire [1:0] out_0_b_bits_param = 2'h0; // @[Xbar.scala:216:19]
wire [1:0] requestBOI_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_9 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_10 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_19 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_21 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_22 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_29 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_30 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] requestBOI_uncommonBits_39 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_2_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_3_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_4_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_5_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_6_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_7_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_8_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_9_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_10_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_11_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_12_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_13_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_14_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_15_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_16_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_17_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_18_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_19_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [7:0] auto_anon_in_19_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:74:9]
wire [7:0] anonIn_19_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] x1_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] in_19_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] out_1_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19]
wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_1_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_2_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_3_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_4_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_5_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_6_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_7_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_8_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_9_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_10_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_11_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_12_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_13_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_14_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_15_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_16_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_17_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_18_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_19_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_anon_in_19_b_bits_data = 64'h0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_b_bits_data = 64'h0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_19_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] x1_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_0_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_2_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_2_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_3_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_3_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_4_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_4_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_5_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_5_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_6_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_6_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_7_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_7_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_8_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_8_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_9_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_9_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_10_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_10_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_11_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_11_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_12_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_12_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_13_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_13_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_14_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_14_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_15_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_15_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_16_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_16_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_17_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_17_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_18_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_18_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_19_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] out_0_c_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] out_1_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_2_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_3_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_4_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_5_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_6_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_7_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_8_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_9_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_10_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_11_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_12_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_13_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_14_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_15_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_16_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_17_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_18_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_19_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_2_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_3_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_4_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_5_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_6_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_7_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_8_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_9_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_10_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_11_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_12_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_13_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_14_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_15_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_16_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_17_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_18_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_19_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_1_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_2_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_2_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_3_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_3_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_4_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_4_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_5_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_5_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_6_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_6_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_7_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_7_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_8_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_8_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_9_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_9_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_10_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_10_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_11_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_11_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_12_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_12_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_13_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_13_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_14_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_14_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_15_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_15_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_16_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_16_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_17_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_17_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_18_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsCOI_filtered_18_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire auto_anon_in_19_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_19_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_2_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_2_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_3_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_3_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_3_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_3_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_3_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_3_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_3_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_4_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_4_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_4_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_4_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_4_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_4_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_4_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_5_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_5_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_5_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_5_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_5_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_5_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_5_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_6_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_6_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_6_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_6_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_6_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_6_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_6_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_7_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_7_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_7_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_7_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_7_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_7_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_7_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_8_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_8_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_8_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_8_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_8_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_8_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_8_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_9_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_9_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_9_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_9_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_9_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_9_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_9_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_10_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_10_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_10_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_10_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_10_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_10_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_10_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_11_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_11_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_11_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_11_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_11_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_11_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_11_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_12_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_12_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_12_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_12_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_12_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_12_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_12_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_13_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_13_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_13_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_13_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_13_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_13_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_13_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_14_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_14_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_14_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_14_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_14_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_14_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_14_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_15_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_15_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_15_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_15_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_15_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_15_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_15_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_16_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_16_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_16_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_16_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_16_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_16_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_16_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_17_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_17_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_17_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_17_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_17_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_17_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_17_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_18_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_18_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_18_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_18_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_18_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_18_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_18_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_19_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire out_0_b_ready = 1'h0; // @[Xbar.scala:216:19]
wire out_0_b_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire out_0_e_valid = 1'h0; // @[Xbar.scala:216:19]
wire out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _requestBOI_T_1 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_3 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_11 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_13 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_2 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_16 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_18 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_3 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_21 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_23 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_4 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_26 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_28 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_5 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_31 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_33 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_6 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_36 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_38 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_7 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_41 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_43 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_8 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_46 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_48 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_9 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_51 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_53 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_10 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_56 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_58 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_11 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_61 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_63 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_12 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_66 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_68 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_13 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_71 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_73 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_14 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_76 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_78 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_15 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_81 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_83 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_16 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_86 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_88 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_17 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_96 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_98 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_19 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_101 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_103 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_0 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_106 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_108 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_1 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_111 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_113 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_2 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_116 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_118 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_3 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_121 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_123 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_4 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_126 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_128 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_5 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_131 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_133 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_6 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_136 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_138 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_7 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_141 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_143 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_8 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_146 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_148 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_9 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_151 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_153 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_10 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_156 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_158 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_11 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_161 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_163 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_12 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_166 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_168 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_13 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_171 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_173 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_14 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_176 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_178 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_15 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_181 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_183 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_16 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_186 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_188 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_17 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_T_191 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_193 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_1_18 = 1'h0; // @[Parameters.scala:56:48]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_10 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_15 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_20 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_25 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_30 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_35 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_40 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_45 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_50 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_55 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_60 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_65 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_70 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_75 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_80 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_85 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_90 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_95 = 1'h0; // @[Parameters.scala:54:10]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire beatsBO_opdata_1 = 1'h0; // @[Edges.scala:97:28]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_3 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_4 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_5 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_6 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_7 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_8 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_9 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_10 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_11 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_12 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_13 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_14 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_15 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_16 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_17 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_18 = 1'h0; // @[Edges.scala:102:36]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_5_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_5_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_5_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_6_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_6_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_6_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_7_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_7_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_7_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_8_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_8_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_8_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_9_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_9_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_9_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_10_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_10_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_10_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_11_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_11_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_11_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_12_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_12_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_12_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_13_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_13_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_13_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_14_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_14_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_14_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_15_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_15_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_15_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_16_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_16_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_16_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_17_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_17_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_17_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_18_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_18_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_18_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_19_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_19_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_19_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_3_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_4_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_5_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_5_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_6_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_6_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_7_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_7_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_8_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_8_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_9_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_9_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_10_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_10_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_11_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_11_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_12_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_12_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_13_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_13_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_14_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_14_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_15_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_15_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_16_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_16_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_17_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_17_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_18_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_19_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_19_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_5 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_12 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_13 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_14 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_15 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_16 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_17 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_18 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_19 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_20 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_21 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_24 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_25 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_26 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_27 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_29 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_31 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_37 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_38 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_2_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_3_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_3_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_4_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_4_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_5_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_5_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_5_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_6_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_6_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_6_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_7_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_7_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_7_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_8_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_8_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_8_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_9_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_9_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_9_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_10_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_10_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_10_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_11_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_11_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_11_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_12_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_12_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_12_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_13_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_13_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_13_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_14_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_14_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_14_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_15_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_15_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_15_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_16_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_16_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_16_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_17_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_17_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_17_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_18_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_18_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_18_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_19_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_2_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_2_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_3_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_3_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_4_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_4_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_5_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_5_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_6_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_6_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_7_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_7_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_8_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_8_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_9_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_9_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_10_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_10_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_11_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_11_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_12_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_12_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_13_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_13_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_14_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_14_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_15_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_15_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_16_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_16_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_17_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_17_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_18_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_18_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_out_1_b_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_5 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_6 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_7 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_12 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_13 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_14 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_15 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_16 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_17 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_18 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_20 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_21 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_24 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_25 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_26 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_27 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_29 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_31 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_37 = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_0_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_0_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_1_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_1_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_1_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_1_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_2_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_2_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_2_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_2_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_3_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_7 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_3_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_3_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_3_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_3_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_4_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_9 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_4_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_4_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_4_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_4_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_5_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_5_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_11 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_11 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_5_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_5_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_5_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_5_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_6_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_6_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_13 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_13 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_6_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_6_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_6_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_6_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_7_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_7_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_15 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_15 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_7_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_7_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_7_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_7_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_8_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_8_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_8_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_8_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_8_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_8_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_17 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_17 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_8_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_8_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_8_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_8_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_9_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_9_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_9_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_9_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_9_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_9_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_19 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_19 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_9_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_9_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_9_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_9_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_10_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_10_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_10_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_10_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_10_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_10_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_21 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_21 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_10_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_10_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_10_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_10_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_11_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_11_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_11_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_11_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_11_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_11_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_23 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_23 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_11_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_11_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_11_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_11_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_12_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_12_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_12_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_12_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_12_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_12_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_25 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_25 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_12_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_12_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_12_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_12_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_13_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_13_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_13_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_13_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_13_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_13_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_27 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_27 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_13_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_13_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_13_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_13_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_14_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_14_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_14_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_14_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_14_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_14_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_29 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_29 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_14_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_14_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_14_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_14_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_15_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_15_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_15_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_15_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_15_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_15_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_31 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_31 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_15_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_15_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_15_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_15_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_16_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_16_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_16_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_16_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_16_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_16_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_33 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_33 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_16_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_16_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_16_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_16_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_17_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_17_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_17_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_17_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_17_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_17_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_35 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_35 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_17_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_17_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_17_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_17_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_18_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_18_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_18_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_18_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_18_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_18_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_37 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_filtered_1_valid_T_37 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_in_18_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_18_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_18_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_in_18_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_19_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_in_19_c_ready_T = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_0_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_0_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_1_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_1_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_1_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_1_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_4 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_2_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_2_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_2_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_2_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_3_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_6 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_7 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_3_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_3_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_3_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_3_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_4_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_8 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_9 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_4_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_4_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_4_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_4_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_5_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_5_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_10 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_11 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_11 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_5_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_5_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_5_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_5_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_6_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_6_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_12 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_13 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_13 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_6_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_6_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_6_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_6_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_7_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_7_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_14 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_15 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_15 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_7_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_7_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_7_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_7_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_8_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_8_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_8_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_8_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_16 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_17 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_17 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_8_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_8_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_8_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_8_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_9_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_9_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_9_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_9_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_18 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_19 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_19 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_9_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_9_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_9_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_9_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_10_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_10_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_10_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_10_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_20 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_21 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_21 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_10_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_10_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_10_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_10_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_11_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_11_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_11_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_11_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_22 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_23 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_23 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_11_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_11_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_11_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_11_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_12_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_12_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_12_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_12_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_24 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_25 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_25 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_12_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_12_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_12_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_12_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_13_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_13_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_13_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_13_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_26 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_27 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_27 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_13_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_13_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_13_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_13_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_14_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_14_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_14_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_14_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_28 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_29 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_29 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_14_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_14_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_14_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_14_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_15_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_15_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_15_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_15_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_30 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_31 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_31 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_15_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_15_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_15_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_15_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_16_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_16_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_16_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_16_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_32 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_33 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_33 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_16_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_16_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_16_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_16_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_17_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_17_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_17_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_17_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_34 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_35 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_35 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_17_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_17_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_17_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_17_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_18_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_18_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_18_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_18_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_36 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_37 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_filtered_1_valid_T_37 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_18_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_18_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_18_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsEOI_in_18_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73]
wire portsEOI_filtered_19_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_19_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_38 = 1'h0; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_39 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_in_19_e_ready_T = 1'h0; // @[Mux.scala:30:73]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_6 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_8 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_9 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_10 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_11 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_12 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_13 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_14 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_15 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_16 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_17 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_18 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_19 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_3 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_4 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_5 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_6 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_7 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_8 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_9 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_10 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_11 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_12 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_13 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_14 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_15 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_16 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_17 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_18 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1_19 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_4_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_4_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_5_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_6_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_6_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_7_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_8_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_8_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_9_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_9_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_10_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_10_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_11_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_11_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_12_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_12_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_13_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_13_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_14_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_14_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_15_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_15_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_16_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_16_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_17_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_17_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_18_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_18_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_19_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_19_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_20_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_20_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_21_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_21_1 = 1'h0; // @[Arbiter.scala:88:34]
wire auto_anon_in_19_e_ready = 1'h1; // @[Xbar.scala:74:9]
wire auto_anon_out_1_e_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_19_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_2_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_3_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_4_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_5_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_6_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_7_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_8_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_9_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_10_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_11_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_12_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_13_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_14_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_15_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_16_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_17_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_18_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_19_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire out_0_c_ready = 1'h1; // @[Xbar.scala:216:19]
wire out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire out_1_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_2_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_34 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_3_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_39 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_3_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_44 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_4_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_49 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_4_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_54 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_5_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_59 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_5_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_64 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_6_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_69 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_6_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_74 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_7_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_79 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_7_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_84 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_8_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_89 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_8_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_94 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_9_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_99 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_9_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_104 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_10_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_109 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_10_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_114 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_11_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_119 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_11_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_124 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_12_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_129 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_12_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_134 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_13_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_139 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_13_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_144 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_14_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_149 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_14_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_154 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_15_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_159 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_15_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_164 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_16_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_169 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_16_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_174 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_17_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_179 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_17_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_184 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_18_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_189 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_18_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_194 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_19_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_199 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_19_1 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_34 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_42 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_44 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_91 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_93 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_94 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_18 = 1'h1; // @[Parameters.scala:56:48]
wire _requestBOI_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_99 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_102 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_104 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_107 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_109 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_112 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_114 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_122 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_124 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_127 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_129 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_132 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_134 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_137 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_139 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_142 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_144 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_147 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_149 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_152 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_154 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_157 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_159 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_162 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_164 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_167 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_169 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_172 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_174 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_177 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_179 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_182 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_184 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_187 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_189 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_192 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_194 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_196 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_197 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_198 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_199 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_1_19 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_34 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_42 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_44 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_94 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_99 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_102 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_104 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_107 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_109 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_112 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_114 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_117 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_119 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_122 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_124 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_127 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_129 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_132 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_134 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_137 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_139 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_142 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_144 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_147 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_149 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_152 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_154 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_157 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_159 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_162 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_164 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_167 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_169 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_172 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_174 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_177 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_179 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_182 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_184 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_187 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_189 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_192 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_194 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_197 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_199 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_11 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_13 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_2_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_16 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_17 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_18 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_19 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_3_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_21 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_23 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_4_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_26 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_28 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_5_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_31 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_33 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_34 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_6_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_36 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_38 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_7_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_41 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_42 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_43 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_44 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_8_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_46 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_48 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_9_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_51 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_52 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_53 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_54 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_10_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_56 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_58 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_11_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_61 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_63 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_12_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_66 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_68 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_13_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_71 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_73 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_14_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_76 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_78 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_15_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_81 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_83 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_16_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_86 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_88 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_17_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_91 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_93 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_94 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_18_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_96 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_98 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_99 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_19_1 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _beatsBO_opdata_T_1 = 1'h1; // @[Edges.scala:97:37]
wire _portsBIO_filtered_18_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_19_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_10 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_10 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_12 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_12 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_14 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_14 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_16 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_16 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_18 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_18 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_20 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_20 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_22 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_22 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_24 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_24 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_26 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_26 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_28 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_28 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_30 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_30 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_32 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_32 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_34 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_34 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_36 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_36 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_38 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_1_valid_T_38 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_10 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_12 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_14 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_16 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_18 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_20 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_22 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_24 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_26 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_28 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_30 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_32 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_34 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_1_valid_T_36 = 1'h1; // @[Xbar.scala:355:54]
wire portsEOI_filtered_19_1_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_1_valid_T_38 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_in_19_e_ready_T_1 = 1'h1; // @[Mux.scala:30:73]
wire _portsEOI_in_19_e_ready_T_2 = 1'h1; // @[Mux.scala:30:73]
wire _portsEOI_in_19_e_ready_WIRE = 1'h1; // @[Mux.scala:30:73]
wire [8:0] auto_anon_out_1_b_bits_source = 9'h1E0; // @[Xbar.scala:74:9]
wire [8:0] x1_anonOut_b_bits_source = 9'h1E0; // @[MixedNode.scala:542:17]
wire [8:0] in_19_b_bits_source = 9'h1E0; // @[Xbar.scala:159:18]
wire [8:0] out_1_b_bits_source = 9'h1E0; // @[Xbar.scala:216:19]
wire [8:0] _requestBOI_uncommonBits_T_20 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_21 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_22 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_23 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_24 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_25 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_26 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_27 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_28 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_29 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_30 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_31 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_32 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_33 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_34 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_35 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_36 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_37 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_38 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_39 = 9'h1E0; // @[Parameters.scala:52:29]
wire [8:0] portsBIO_filtered_1_0_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_1_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_2_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_3_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_4_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_5_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_6_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_7_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_8_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_9_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_10_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_11_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_12_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_13_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_14_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_15_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_16_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_17_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_18_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_19_bits_source = 9'h1E0; // @[Xbar.scala:352:24]
wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_3_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_3_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_3_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_3_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_4_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_4_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_4_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_4_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_5_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_5_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_5_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_5_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_6_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_6_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_6_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_6_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_7_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_7_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_7_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_7_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_8_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_8_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_8_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_8_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_9_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_9_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_9_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_9_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_10_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_10_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_10_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_10_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_11_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_11_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_11_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_11_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_12_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_12_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_12_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_12_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_13_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_13_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_13_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_13_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_14_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_14_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_14_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_14_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_15_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_15_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_15_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_15_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_16_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_16_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_16_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_16_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_17_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_17_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_17_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_17_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_18_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_18_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_18_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_18_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] out_0_b_bits_opcode = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_c_bits_opcode = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_c_bits_param = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] out_0_e_bits_sink = 3'h0; // @[Xbar.scala:216:19]
wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_2 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_2 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_3 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_3 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_4 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_5 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_5 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_6 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_6 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_7 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_7 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_8 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_8 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_9 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_9 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_10 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_10 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_11 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_11 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_12 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_12 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_13 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_13 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_14 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_14 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_15 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_15 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_16 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_16 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_17 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_17 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_uncommonBits_T_18 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_18 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_3_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_4_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_5_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_6_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_7_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_8_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_9_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_10_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_11_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_12_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_13_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_14_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_15_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_16_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_17_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_18_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_19_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_3_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_4_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_5_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_6_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_7_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_8_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_8_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_8_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_8_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_9_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_9_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_9_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_9_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_10_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_10_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_10_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_10_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_11_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_11_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_11_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_11_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_12_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_12_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_12_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_12_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_13_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_13_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_13_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_13_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_14_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_14_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_14_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_14_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_15_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_15_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_15_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_15_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_16_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_16_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_16_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_16_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_17_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_17_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_17_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_17_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_18_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_18_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_18_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_18_1_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_1_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_2_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_2_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_3_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_3_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_4_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_4_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_5_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_5_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_6_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_6_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_7_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_7_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_8_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_8_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_9_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_9_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_10_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_10_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_11_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_11_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_12_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_12_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_13_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_13_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_14_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_14_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_15_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_15_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_16_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_16_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_17_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_17_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_18_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_18_1_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_2_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_2_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_3_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_3_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_4_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_4_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_5_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_5_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_6_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_6_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_7_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_7_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_8_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_8_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_9_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_9_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_10_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_10_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_11_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_11_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_12_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_12_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_13_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_13_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_14_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_14_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_15_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_15_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_16_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_16_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_17_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_17_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_18_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_18_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] out_0_b_bits_address = 32'h0; // @[Xbar.scala:216:19]
wire [31:0] out_0_c_bits_address = 32'h0; // @[Xbar.scala:216:19]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_15 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_20 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_25 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_30 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_35 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_40 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_45 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_50 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_55 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_60 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_65 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_70 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_75 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_80 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_85 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_90 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_95 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_100 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_105 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_110 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_115 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_120 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_125 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_130 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_135 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_140 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_145 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_150 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_155 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_160 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_165 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_170 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_175 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_180 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_185 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_3_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_4_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_5_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_6_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_7_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_8_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_9_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_10_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_11_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_12_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_13_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_14_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_15_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_16_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_17_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_18_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_19_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_1_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_2_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_2_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_3_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_3_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_4_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_4_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_5_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_5_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_6_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_6_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_7_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_7_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_8_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_8_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_9_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_9_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_10_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_10_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_11_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_11_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_12_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_12_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_13_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_13_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_14_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_14_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_15_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_15_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_16_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_16_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_17_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_17_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_18_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_18_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [8:0] in_0_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_0_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_1_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_1_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_2_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_2_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_3_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_3_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_4_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_4_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_5_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_5_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_6_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_6_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_7_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_7_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_8_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_8_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_9_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_9_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_10_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_10_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_11_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_11_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_12_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_12_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_13_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_13_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_14_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_14_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_15_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_15_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_16_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_16_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_17_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_17_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_18_b_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] in_18_c_bits_source = 9'h0; // @[Xbar.scala:159:18]
wire [8:0] out_0_b_bits_source = 9'h0; // @[Xbar.scala:216:19]
wire [8:0] out_0_c_bits_source = 9'h0; // @[Xbar.scala:216:19]
wire [8:0] _requestBOI_uncommonBits_T = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_1 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_2 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_3 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_4 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_5 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_6 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_7 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_8 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_9 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_10 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_11 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_12 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_13 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_14 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_15 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_16 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_17 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_18 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] _requestBOI_uncommonBits_T_19 = 9'h0; // @[Parameters.scala:52:29]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_2 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_2 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_3 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_3 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_4 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_4 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_5 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_5 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_6 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_6 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_7 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_7 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_8 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_8 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_9 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_9 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_10 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_10 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_11 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_11 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_12 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_12 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_13 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_13 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_14 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_14 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_15 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_15 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_16 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_16 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_17 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_17 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_18 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_18 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] portsBIO_filtered_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_2_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_3_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_4_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_5_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_6_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_7_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_8_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_9_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_10_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_11_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_12_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_13_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_14_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_15_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_16_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_17_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_18_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsBIO_filtered_19_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_1_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_1_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_2_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_2_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_3_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_3_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_4_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_4_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_5_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_5_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_6_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_6_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_7_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_7_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_8_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_8_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_9_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_9_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_10_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_10_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_11_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_11_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_12_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_12_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_13_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_13_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_14_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_14_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_15_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_15_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_16_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_16_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_17_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_17_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_18_0_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [8:0] portsCOI_filtered_18_1_bits_source = 9'h0; // @[Xbar.scala:352:24]
wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_2_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_2_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_3_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_3_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_4_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_4_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_5_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_5_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_6_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_6_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_7_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_7_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_8_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_8_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_9_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_9_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_10_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_10_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_11_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_11_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_12_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_12_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_13_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_13_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_14_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_14_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_15_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_15_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_16_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_16_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_17_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_17_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_18_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_18_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] out_0_b_bits_size = 4'h0; // @[Xbar.scala:216:19]
wire [3:0] out_0_c_bits_size = 4'h0; // @[Xbar.scala:216:19]
wire [3:0] _requestBOI_T = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_15 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_20 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_25 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_30 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_35 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_40 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_55 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_60 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_65 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_70 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_75 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_80 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_85 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_90 = 4'h0; // @[Parameters.scala:54:10]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_3_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_4_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_5_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_6_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_7_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_8_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_9_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_10_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_11_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_12_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_13_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_14_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_15_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_16_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_17_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_18_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_19_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_1_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_2_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_2_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_3_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_3_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_4_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_4_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_5_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_5_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_6_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_6_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_7_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_7_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_8_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_8_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_9_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_9_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_10_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_10_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_11_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_11_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_12_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_12_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_13_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_13_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_14_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_14_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_15_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_15_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_16_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_16_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_17_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_17_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_18_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_18_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [7:0] in_0_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_2_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_3_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_4_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_5_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_6_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_7_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_8_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_9_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_10_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_11_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_12_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_13_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_14_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_15_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_16_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_17_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] in_18_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [7:0] out_0_b_bits_mask = 8'h0; // @[Xbar.scala:216:19]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_2_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_3_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_4_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_5_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_6_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_7_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_8_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_9_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_10_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_11_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_12_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_13_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_14_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_15_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_16_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_17_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_18_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_19_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_8 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_11 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_14 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_17 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_20 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_23 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_26 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_29 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_32 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_35 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_38 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_41 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_44 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_47 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_50 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_53 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_56 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_7 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_10 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_13 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_16 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_19 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_22 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_25 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_28 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_31 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_34 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_37 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_40 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_43 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_46 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_49 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_52 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_55 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_6 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_9 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_12 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_15 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_18 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_21 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_24 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_27 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_30 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_33 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_36 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_39 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_42 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_45 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_48 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_51 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_54 = 27'hFFF; // @[package.scala:243:71]
wire [2:0] beatsBO_decode_1 = 3'h7; // @[Edges.scala:220:59]
wire [5:0] _beatsBO_decode_T_5 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _beatsBO_decode_T_4 = 6'h0; // @[package.scala:243:76]
wire [20:0] _beatsBO_decode_T_3 = 21'hFC0; // @[package.scala:243:71]
wire [6:0] _requestBOI_T_105 = 7'h78; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_110 = 7'h78; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_145 = 7'h78; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_150 = 7'h78; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_195 = 7'h78; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_100 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_115 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_120 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_125 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_130 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_135 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_140 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_155 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_160 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_165 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_170 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_175 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_180 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_185 = 4'hF; // @[Parameters.scala:54:10]
wire [3:0] _requestBOI_T_190 = 4'hF; // @[Parameters.scala:54:10]
wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_3 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_4 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_5 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_6 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_7 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_8 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_11 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_12 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_13 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_14 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_15 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_16 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_17 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_18 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_20 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_23 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_24 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_25 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_26 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_27 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_28 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_31 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_32 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_33 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_34 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_35 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_36 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_37 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] requestBOI_uncommonBits_38 = 5'h0; // @[Parameters.scala:52:56]
wire [6:0] _requestBOI_T_5 = 7'h0; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_10 = 7'h0; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_45 = 7'h0; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_50 = 7'h0; // @[Parameters.scala:54:10]
wire [6:0] _requestBOI_T_95 = 7'h0; // @[Parameters.scala:54:10]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_16 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_21 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_22 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_23 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_26 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_27 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_28 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_31 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_32 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_33 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_36 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_37 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_38 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_41 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_42 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_43 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_46 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_47 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_48 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_51 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_52 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_53 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_56 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_57 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_58 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_61 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_62 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_63 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_66 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_67 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_68 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_71 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_72 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_73 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_76 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_77 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_78 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_81 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_82 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_83 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_86 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_87 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_88 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_91 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_92 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_93 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_96 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_97 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_98 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_101 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_102 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_103 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_106 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_107 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_108 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_111 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_112 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_113 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_116 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_117 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_118 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_121 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_122 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_123 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_126 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_127 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_128 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_131 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_132 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_133 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_136 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_137 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_138 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_141 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_142 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_143 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_146 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_147 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_148 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_151 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_152 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_153 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_156 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_157 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_158 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_161 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_162 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_163 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_166 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_167 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_168 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_171 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_172 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_173 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_176 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_177 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_178 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_181 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_182 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_183 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_186 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_187 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_188 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_192 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_193 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_197 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_198 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_19_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_19_a_valid = auto_anon_in_19_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_19_a_bits_opcode = auto_anon_in_19_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_19_a_bits_param = auto_anon_in_19_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_19_a_bits_size = auto_anon_in_19_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_19_a_bits_source = auto_anon_in_19_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_19_a_bits_address = auto_anon_in_19_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_19_a_bits_mask = auto_anon_in_19_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_19_a_bits_data = auto_anon_in_19_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_19_a_bits_corrupt = auto_anon_in_19_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_19_b_ready = auto_anon_in_19_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_19_b_valid; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_19_b_bits_param; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_19_b_bits_address; // @[MixedNode.scala:551:17]
wire anonIn_19_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_19_c_valid = auto_anon_in_19_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_19_c_bits_opcode = auto_anon_in_19_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_19_c_bits_param = auto_anon_in_19_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_19_c_bits_size = auto_anon_in_19_c_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_19_c_bits_source = auto_anon_in_19_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_19_c_bits_address = auto_anon_in_19_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_19_c_bits_data = auto_anon_in_19_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_19_c_bits_corrupt = auto_anon_in_19_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_19_d_ready = auto_anon_in_19_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_19_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_19_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_19_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_19_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_19_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_19_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_19_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_19_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_19_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_19_e_valid = auto_anon_in_19_e_valid_0; // @[Xbar.scala:74:9]
wire anonIn_18_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_19_e_bits_sink = auto_anon_in_19_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonIn_18_a_valid = auto_anon_in_18_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_18_a_bits_opcode = auto_anon_in_18_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_18_a_bits_param = auto_anon_in_18_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_18_a_bits_size = auto_anon_in_18_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_18_a_bits_source = auto_anon_in_18_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_18_a_bits_address = auto_anon_in_18_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_18_a_bits_mask = auto_anon_in_18_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_18_a_bits_data = auto_anon_in_18_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_18_a_bits_corrupt = auto_anon_in_18_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_18_d_ready = auto_anon_in_18_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_18_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_18_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_18_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_18_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_18_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_18_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_18_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_18_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_18_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_17_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_17_a_valid = auto_anon_in_17_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_17_a_bits_opcode = auto_anon_in_17_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_17_a_bits_param = auto_anon_in_17_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_17_a_bits_size = auto_anon_in_17_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_17_a_bits_source = auto_anon_in_17_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_17_a_bits_address = auto_anon_in_17_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_17_a_bits_mask = auto_anon_in_17_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_17_a_bits_data = auto_anon_in_17_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_17_a_bits_corrupt = auto_anon_in_17_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_17_d_ready = auto_anon_in_17_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_17_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_17_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_17_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_17_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_17_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_17_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_17_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_17_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_17_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_16_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_16_a_valid = auto_anon_in_16_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_16_a_bits_opcode = auto_anon_in_16_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_16_a_bits_param = auto_anon_in_16_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_16_a_bits_size = auto_anon_in_16_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_16_a_bits_source = auto_anon_in_16_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_16_a_bits_address = auto_anon_in_16_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_16_a_bits_mask = auto_anon_in_16_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_16_a_bits_data = auto_anon_in_16_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_16_a_bits_corrupt = auto_anon_in_16_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_16_d_ready = auto_anon_in_16_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_16_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_16_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_16_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_16_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_16_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_16_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_16_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_16_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_16_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_15_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_15_a_valid = auto_anon_in_15_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_15_a_bits_opcode = auto_anon_in_15_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_15_a_bits_param = auto_anon_in_15_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_15_a_bits_size = auto_anon_in_15_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_15_a_bits_source = auto_anon_in_15_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_15_a_bits_address = auto_anon_in_15_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_15_a_bits_mask = auto_anon_in_15_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_15_a_bits_data = auto_anon_in_15_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_15_a_bits_corrupt = auto_anon_in_15_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_15_d_ready = auto_anon_in_15_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_15_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_15_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_15_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_15_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_15_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_15_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_15_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_15_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_15_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_14_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_14_a_valid = auto_anon_in_14_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_14_a_bits_opcode = auto_anon_in_14_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_14_a_bits_param = auto_anon_in_14_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_14_a_bits_size = auto_anon_in_14_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_14_a_bits_source = auto_anon_in_14_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_14_a_bits_address = auto_anon_in_14_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_14_a_bits_mask = auto_anon_in_14_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_14_a_bits_data = auto_anon_in_14_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_14_a_bits_corrupt = auto_anon_in_14_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_14_d_ready = auto_anon_in_14_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_14_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_14_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_14_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_14_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_14_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_14_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_14_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_14_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_14_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_13_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_13_a_valid = auto_anon_in_13_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_13_a_bits_opcode = auto_anon_in_13_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_13_a_bits_param = auto_anon_in_13_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_13_a_bits_size = auto_anon_in_13_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_13_a_bits_source = auto_anon_in_13_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_13_a_bits_address = auto_anon_in_13_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_13_a_bits_mask = auto_anon_in_13_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_13_a_bits_data = auto_anon_in_13_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_13_a_bits_corrupt = auto_anon_in_13_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_13_d_ready = auto_anon_in_13_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_13_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_13_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_13_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_13_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_13_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_13_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_13_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_13_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_13_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_12_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_12_a_valid = auto_anon_in_12_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_12_a_bits_opcode = auto_anon_in_12_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_12_a_bits_param = auto_anon_in_12_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_12_a_bits_size = auto_anon_in_12_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_12_a_bits_source = auto_anon_in_12_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_12_a_bits_address = auto_anon_in_12_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_12_a_bits_mask = auto_anon_in_12_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_12_a_bits_data = auto_anon_in_12_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_12_a_bits_corrupt = auto_anon_in_12_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_12_d_ready = auto_anon_in_12_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_12_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_12_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_12_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_12_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_12_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_12_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_12_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_12_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_12_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_11_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_11_a_valid = auto_anon_in_11_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_11_a_bits_opcode = auto_anon_in_11_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_11_a_bits_param = auto_anon_in_11_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_11_a_bits_size = auto_anon_in_11_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_11_a_bits_source = auto_anon_in_11_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_11_a_bits_address = auto_anon_in_11_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_11_a_bits_mask = auto_anon_in_11_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_11_a_bits_data = auto_anon_in_11_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_11_a_bits_corrupt = auto_anon_in_11_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_11_d_ready = auto_anon_in_11_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_11_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_11_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_11_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_11_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_11_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_11_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_11_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_11_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_11_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_10_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_10_a_valid = auto_anon_in_10_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_10_a_bits_opcode = auto_anon_in_10_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_10_a_bits_param = auto_anon_in_10_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_10_a_bits_size = auto_anon_in_10_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_10_a_bits_source = auto_anon_in_10_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_10_a_bits_address = auto_anon_in_10_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_10_a_bits_mask = auto_anon_in_10_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_10_a_bits_data = auto_anon_in_10_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_10_a_bits_corrupt = auto_anon_in_10_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_10_d_ready = auto_anon_in_10_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_10_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_10_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_10_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_10_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_10_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_10_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_10_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_10_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_10_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_9_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_9_a_valid = auto_anon_in_9_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_9_a_bits_opcode = auto_anon_in_9_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_9_a_bits_param = auto_anon_in_9_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_9_a_bits_size = auto_anon_in_9_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_9_a_bits_source = auto_anon_in_9_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_9_a_bits_address = auto_anon_in_9_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_9_a_bits_mask = auto_anon_in_9_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_9_a_bits_data = auto_anon_in_9_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_9_a_bits_corrupt = auto_anon_in_9_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_9_d_ready = auto_anon_in_9_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_9_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_9_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_9_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_9_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_9_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_9_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_9_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_9_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_9_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_8_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_8_a_valid = auto_anon_in_8_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_8_a_bits_opcode = auto_anon_in_8_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_8_a_bits_param = auto_anon_in_8_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_8_a_bits_size = auto_anon_in_8_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_8_a_bits_source = auto_anon_in_8_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_8_a_bits_address = auto_anon_in_8_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_8_a_bits_mask = auto_anon_in_8_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_8_a_bits_data = auto_anon_in_8_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_8_a_bits_corrupt = auto_anon_in_8_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_8_d_ready = auto_anon_in_8_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_8_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_8_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_8_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_8_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_8_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_8_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_8_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_8_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_8_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_7_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_7_a_valid = auto_anon_in_7_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_7_a_bits_opcode = auto_anon_in_7_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_7_a_bits_param = auto_anon_in_7_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_7_a_bits_size = auto_anon_in_7_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_7_a_bits_source = auto_anon_in_7_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_7_a_bits_address = auto_anon_in_7_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_7_a_bits_mask = auto_anon_in_7_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_7_a_bits_data = auto_anon_in_7_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_7_a_bits_corrupt = auto_anon_in_7_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_7_d_ready = auto_anon_in_7_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_7_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_7_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_7_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_7_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_7_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_7_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_7_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_7_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_7_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_6_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_6_a_valid = auto_anon_in_6_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_6_a_bits_opcode = auto_anon_in_6_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_6_a_bits_param = auto_anon_in_6_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_6_a_bits_size = auto_anon_in_6_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_6_a_bits_source = auto_anon_in_6_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_6_a_bits_address = auto_anon_in_6_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_6_a_bits_mask = auto_anon_in_6_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_6_a_bits_data = auto_anon_in_6_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_6_a_bits_corrupt = auto_anon_in_6_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_6_d_ready = auto_anon_in_6_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_6_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_6_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_6_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_6_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_6_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_6_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_6_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_6_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_5_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_5_a_valid = auto_anon_in_5_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_5_a_bits_opcode = auto_anon_in_5_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_5_a_bits_param = auto_anon_in_5_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_5_a_bits_size = auto_anon_in_5_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_5_a_bits_source = auto_anon_in_5_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_5_a_bits_address = auto_anon_in_5_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_5_a_bits_mask = auto_anon_in_5_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_5_a_bits_data = auto_anon_in_5_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_5_a_bits_corrupt = auto_anon_in_5_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_5_d_ready = auto_anon_in_5_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_5_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_5_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_5_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_5_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_5_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_5_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_5_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_5_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_4_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_4_a_valid = auto_anon_in_4_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_4_a_bits_opcode = auto_anon_in_4_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_4_a_bits_param = auto_anon_in_4_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_4_a_bits_size = auto_anon_in_4_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_4_a_bits_source = auto_anon_in_4_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_4_a_bits_address = auto_anon_in_4_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_4_a_bits_mask = auto_anon_in_4_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_4_a_bits_data = auto_anon_in_4_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_4_a_bits_corrupt = auto_anon_in_4_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_4_d_ready = auto_anon_in_4_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_4_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_4_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_4_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_4_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_4_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_4_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_4_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_4_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_3_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_3_a_valid = auto_anon_in_3_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_3_a_bits_opcode = auto_anon_in_3_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_3_a_bits_param = auto_anon_in_3_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_3_a_bits_size = auto_anon_in_3_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_3_a_bits_source = auto_anon_in_3_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_3_a_bits_address = auto_anon_in_3_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_3_a_bits_mask = auto_anon_in_3_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_3_a_bits_data = auto_anon_in_3_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_3_a_bits_corrupt = auto_anon_in_3_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_3_d_ready = auto_anon_in_3_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_3_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_3_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_3_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_3_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_3_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_3_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_3_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_3_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_2_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_param = auto_anon_in_2_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_2_a_bits_size = auto_anon_in_2_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_2_a_bits_source = auto_anon_in_2_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_2_a_bits_mask = auto_anon_in_2_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_2_a_bits_data = auto_anon_in_2_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_2_d_ready = auto_anon_in_2_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_2_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[Xbar.scala:74:9]
wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[Xbar.scala:74:9]
wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[Xbar.scala:74:9]
wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [8:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [8:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [8:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_a_ready_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_19_b_bits_param_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_19_b_bits_address_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_19_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_19_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_19_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_19_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_19_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_19_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_18_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_18_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_18_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_18_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_18_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_18_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_18_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_18_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_18_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_18_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_17_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_17_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_17_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_17_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_17_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_17_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_17_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_17_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_17_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_17_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_16_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_16_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_16_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_16_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_16_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_16_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_16_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_16_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_16_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_16_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_15_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_15_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_15_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_15_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_15_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_15_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_15_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_15_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_15_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_15_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_14_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_14_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_14_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_14_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_14_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_14_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_14_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_14_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_14_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_14_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_13_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_13_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_13_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_13_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_13_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_13_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_13_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_13_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_13_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_13_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_12_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_12_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_12_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_12_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_12_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_12_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_12_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_12_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_12_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_12_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_11_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_11_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_11_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_11_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_11_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_11_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_11_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_11_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_11_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_11_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_10_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_10_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_10_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_10_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_10_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_10_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_10_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_10_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_10_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_10_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_9_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_9_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_9_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_9_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_9_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_9_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_9_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_9_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_9_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_9_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_8_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_8_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_8_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_8_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_8_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_8_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_8_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_8_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_8_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_8_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_7_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_7_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_7_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_7_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_7_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_7_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_7_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_7_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_7_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_7_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_6_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_6_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_6_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_6_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_6_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_6_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_6_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_6_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_6_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_6_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_5_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_5_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_5_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_5_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_5_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_5_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_5_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_5_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_5_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_5_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_4_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_4_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_4_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_4_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_4_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_4_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_4_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_4_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_4_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_4_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_3_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_3_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_3_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_3_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_3_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_3_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_3_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_3_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_3_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_3_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_2_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [8:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_c_bits_size_0; // @[Xbar.scala:74:9]
wire [8:0] auto_anon_out_1_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_1_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_1_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_1_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_1_e_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [8:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_2_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9]
wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_2_a_bits_opcode = anonIn_2_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_2_a_bits_param = anonIn_2_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_2_a_bits_size = anonIn_2_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_2_a_bits_mask = anonIn_2_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_2_a_bits_data = anonIn_2_a_bits_data; // @[Xbar.scala:159:18]
wire in_2_a_bits_corrupt = anonIn_2_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_2_d_ready = anonIn_2_d_ready; // @[Xbar.scala:159:18]
wire in_2_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69]
assign auto_anon_in_2_d_bits_source_0 = anonIn_2_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_2_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9]
wire in_2_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_2_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9]
wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_3_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_3_a_ready_0 = anonIn_3_a_ready; // @[Xbar.scala:74:9]
wire in_3_a_valid = anonIn_3_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_3_a_bits_opcode = anonIn_3_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_3_a_bits_param = anonIn_3_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_3_a_bits_size = anonIn_3_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_3_a_bits_address = anonIn_3_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_3_a_bits_mask = anonIn_3_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_3_a_bits_data = anonIn_3_a_bits_data; // @[Xbar.scala:159:18]
wire in_3_a_bits_corrupt = anonIn_3_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_3_d_ready = anonIn_3_d_ready; // @[Xbar.scala:159:18]
wire in_3_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_valid_0 = anonIn_3_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_3_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_opcode_0 = anonIn_3_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_3_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_param_0 = anonIn_3_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_3_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_size_0 = anonIn_3_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69]
assign auto_anon_in_3_d_bits_source_0 = anonIn_3_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_3_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_sink_0 = anonIn_3_d_bits_sink; // @[Xbar.scala:74:9]
wire in_3_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_denied_0 = anonIn_3_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_3_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_data_0 = anonIn_3_d_bits_data; // @[Xbar.scala:74:9]
wire in_3_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_3_d_bits_corrupt_0 = anonIn_3_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_4_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_4_a_ready_0 = anonIn_4_a_ready; // @[Xbar.scala:74:9]
wire in_4_a_valid = anonIn_4_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_4_a_bits_opcode = anonIn_4_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_4_a_bits_param = anonIn_4_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_4_a_bits_size = anonIn_4_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_4_a_bits_address = anonIn_4_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_4_a_bits_mask = anonIn_4_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_4_a_bits_data = anonIn_4_a_bits_data; // @[Xbar.scala:159:18]
wire in_4_a_bits_corrupt = anonIn_4_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_4_d_ready = anonIn_4_d_ready; // @[Xbar.scala:159:18]
wire in_4_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_valid_0 = anonIn_4_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_4_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_opcode_0 = anonIn_4_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_4_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_param_0 = anonIn_4_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_4_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_size_0 = anonIn_4_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69]
assign auto_anon_in_4_d_bits_source_0 = anonIn_4_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_4_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_sink_0 = anonIn_4_d_bits_sink; // @[Xbar.scala:74:9]
wire in_4_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_denied_0 = anonIn_4_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_4_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_data_0 = anonIn_4_d_bits_data; // @[Xbar.scala:74:9]
wire in_4_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_4_d_bits_corrupt_0 = anonIn_4_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_5_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_5_a_ready_0 = anonIn_5_a_ready; // @[Xbar.scala:74:9]
wire in_5_a_valid = anonIn_5_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_5_a_bits_opcode = anonIn_5_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_5_a_bits_param = anonIn_5_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_5_a_bits_size = anonIn_5_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_5_a_bits_address = anonIn_5_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_5_a_bits_mask = anonIn_5_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_5_a_bits_data = anonIn_5_a_bits_data; // @[Xbar.scala:159:18]
wire in_5_a_bits_corrupt = anonIn_5_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_5_d_ready = anonIn_5_d_ready; // @[Xbar.scala:159:18]
wire in_5_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_valid_0 = anonIn_5_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_5_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_opcode_0 = anonIn_5_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_5_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_param_0 = anonIn_5_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_5_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_size_0 = anonIn_5_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_5; // @[Xbar.scala:156:69]
assign auto_anon_in_5_d_bits_source_0 = anonIn_5_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_5_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_sink_0 = anonIn_5_d_bits_sink; // @[Xbar.scala:74:9]
wire in_5_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_denied_0 = anonIn_5_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_5_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_data_0 = anonIn_5_d_bits_data; // @[Xbar.scala:74:9]
wire in_5_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_5_d_bits_corrupt_0 = anonIn_5_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_6_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_6_a_ready_0 = anonIn_6_a_ready; // @[Xbar.scala:74:9]
wire in_6_a_valid = anonIn_6_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_6_a_bits_opcode = anonIn_6_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_6_a_bits_param = anonIn_6_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_6_a_bits_size = anonIn_6_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_6_a_bits_address = anonIn_6_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_6_a_bits_mask = anonIn_6_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_6_a_bits_data = anonIn_6_a_bits_data; // @[Xbar.scala:159:18]
wire in_6_a_bits_corrupt = anonIn_6_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_6_d_ready = anonIn_6_d_ready; // @[Xbar.scala:159:18]
wire in_6_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_valid_0 = anonIn_6_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_6_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_opcode_0 = anonIn_6_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_6_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_param_0 = anonIn_6_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_6_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_size_0 = anonIn_6_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_6; // @[Xbar.scala:156:69]
assign auto_anon_in_6_d_bits_source_0 = anonIn_6_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_6_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_sink_0 = anonIn_6_d_bits_sink; // @[Xbar.scala:74:9]
wire in_6_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_denied_0 = anonIn_6_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_6_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_data_0 = anonIn_6_d_bits_data; // @[Xbar.scala:74:9]
wire in_6_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_6_d_bits_corrupt_0 = anonIn_6_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_7_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_7_a_ready_0 = anonIn_7_a_ready; // @[Xbar.scala:74:9]
wire in_7_a_valid = anonIn_7_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_7_a_bits_opcode = anonIn_7_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_7_a_bits_param = anonIn_7_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_7_a_bits_size = anonIn_7_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_7_a_bits_address = anonIn_7_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_7_a_bits_mask = anonIn_7_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_7_a_bits_data = anonIn_7_a_bits_data; // @[Xbar.scala:159:18]
wire in_7_a_bits_corrupt = anonIn_7_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_7_d_ready = anonIn_7_d_ready; // @[Xbar.scala:159:18]
wire in_7_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_valid_0 = anonIn_7_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_7_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_opcode_0 = anonIn_7_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_7_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_param_0 = anonIn_7_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_7_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_size_0 = anonIn_7_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_7; // @[Xbar.scala:156:69]
assign auto_anon_in_7_d_bits_source_0 = anonIn_7_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_7_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_sink_0 = anonIn_7_d_bits_sink; // @[Xbar.scala:74:9]
wire in_7_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_denied_0 = anonIn_7_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_7_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_data_0 = anonIn_7_d_bits_data; // @[Xbar.scala:74:9]
wire in_7_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_7_d_bits_corrupt_0 = anonIn_7_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_8_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_8_a_ready_0 = anonIn_8_a_ready; // @[Xbar.scala:74:9]
wire in_8_a_valid = anonIn_8_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_8_a_bits_opcode = anonIn_8_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_8_a_bits_param = anonIn_8_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_8_a_bits_size = anonIn_8_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_8_a_bits_address = anonIn_8_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_8_a_bits_mask = anonIn_8_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_8_a_bits_data = anonIn_8_a_bits_data; // @[Xbar.scala:159:18]
wire in_8_a_bits_corrupt = anonIn_8_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_8_d_ready = anonIn_8_d_ready; // @[Xbar.scala:159:18]
wire in_8_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_valid_0 = anonIn_8_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_8_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_opcode_0 = anonIn_8_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_8_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_param_0 = anonIn_8_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_8_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_size_0 = anonIn_8_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_8; // @[Xbar.scala:156:69]
assign auto_anon_in_8_d_bits_source_0 = anonIn_8_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_8_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_sink_0 = anonIn_8_d_bits_sink; // @[Xbar.scala:74:9]
wire in_8_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_denied_0 = anonIn_8_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_8_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_data_0 = anonIn_8_d_bits_data; // @[Xbar.scala:74:9]
wire in_8_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_8_d_bits_corrupt_0 = anonIn_8_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_9_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_9_a_ready_0 = anonIn_9_a_ready; // @[Xbar.scala:74:9]
wire in_9_a_valid = anonIn_9_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_9_a_bits_opcode = anonIn_9_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_9_a_bits_param = anonIn_9_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_9_a_bits_size = anonIn_9_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_9_a_bits_address = anonIn_9_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_9_a_bits_mask = anonIn_9_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_9_a_bits_data = anonIn_9_a_bits_data; // @[Xbar.scala:159:18]
wire in_9_a_bits_corrupt = anonIn_9_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_9_d_ready = anonIn_9_d_ready; // @[Xbar.scala:159:18]
wire in_9_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_valid_0 = anonIn_9_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_9_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_opcode_0 = anonIn_9_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_9_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_param_0 = anonIn_9_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_9_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_size_0 = anonIn_9_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_9; // @[Xbar.scala:156:69]
assign auto_anon_in_9_d_bits_source_0 = anonIn_9_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_9_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_sink_0 = anonIn_9_d_bits_sink; // @[Xbar.scala:74:9]
wire in_9_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_denied_0 = anonIn_9_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_9_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_data_0 = anonIn_9_d_bits_data; // @[Xbar.scala:74:9]
wire in_9_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_9_d_bits_corrupt_0 = anonIn_9_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_10_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_10_a_ready_0 = anonIn_10_a_ready; // @[Xbar.scala:74:9]
wire in_10_a_valid = anonIn_10_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_10_a_bits_opcode = anonIn_10_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_10_a_bits_param = anonIn_10_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_10_a_bits_size = anonIn_10_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_10_a_bits_address = anonIn_10_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_10_a_bits_mask = anonIn_10_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_10_a_bits_data = anonIn_10_a_bits_data; // @[Xbar.scala:159:18]
wire in_10_a_bits_corrupt = anonIn_10_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_10_d_ready = anonIn_10_d_ready; // @[Xbar.scala:159:18]
wire in_10_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_valid_0 = anonIn_10_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_10_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_opcode_0 = anonIn_10_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_10_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_param_0 = anonIn_10_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_10_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_size_0 = anonIn_10_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_10; // @[Xbar.scala:156:69]
assign auto_anon_in_10_d_bits_source_0 = anonIn_10_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_10_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_sink_0 = anonIn_10_d_bits_sink; // @[Xbar.scala:74:9]
wire in_10_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_denied_0 = anonIn_10_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_10_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_data_0 = anonIn_10_d_bits_data; // @[Xbar.scala:74:9]
wire in_10_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_10_d_bits_corrupt_0 = anonIn_10_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_11_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_11_a_ready_0 = anonIn_11_a_ready; // @[Xbar.scala:74:9]
wire in_11_a_valid = anonIn_11_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_11_a_bits_opcode = anonIn_11_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_11_a_bits_param = anonIn_11_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_11_a_bits_size = anonIn_11_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_11_a_bits_address = anonIn_11_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_11_a_bits_mask = anonIn_11_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_11_a_bits_data = anonIn_11_a_bits_data; // @[Xbar.scala:159:18]
wire in_11_a_bits_corrupt = anonIn_11_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_11_d_ready = anonIn_11_d_ready; // @[Xbar.scala:159:18]
wire in_11_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_valid_0 = anonIn_11_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_11_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_opcode_0 = anonIn_11_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_11_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_param_0 = anonIn_11_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_11_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_size_0 = anonIn_11_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_11; // @[Xbar.scala:156:69]
assign auto_anon_in_11_d_bits_source_0 = anonIn_11_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_11_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_sink_0 = anonIn_11_d_bits_sink; // @[Xbar.scala:74:9]
wire in_11_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_denied_0 = anonIn_11_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_11_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_data_0 = anonIn_11_d_bits_data; // @[Xbar.scala:74:9]
wire in_11_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_11_d_bits_corrupt_0 = anonIn_11_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_12_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_12_a_ready_0 = anonIn_12_a_ready; // @[Xbar.scala:74:9]
wire in_12_a_valid = anonIn_12_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_12_a_bits_opcode = anonIn_12_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_12_a_bits_param = anonIn_12_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_12_a_bits_size = anonIn_12_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_12_a_bits_address = anonIn_12_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_12_a_bits_mask = anonIn_12_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_12_a_bits_data = anonIn_12_a_bits_data; // @[Xbar.scala:159:18]
wire in_12_a_bits_corrupt = anonIn_12_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_12_d_ready = anonIn_12_d_ready; // @[Xbar.scala:159:18]
wire in_12_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_valid_0 = anonIn_12_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_12_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_opcode_0 = anonIn_12_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_12_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_param_0 = anonIn_12_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_12_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_size_0 = anonIn_12_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_12; // @[Xbar.scala:156:69]
assign auto_anon_in_12_d_bits_source_0 = anonIn_12_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_12_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_sink_0 = anonIn_12_d_bits_sink; // @[Xbar.scala:74:9]
wire in_12_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_denied_0 = anonIn_12_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_12_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_data_0 = anonIn_12_d_bits_data; // @[Xbar.scala:74:9]
wire in_12_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_12_d_bits_corrupt_0 = anonIn_12_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_13_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_13_a_ready_0 = anonIn_13_a_ready; // @[Xbar.scala:74:9]
wire in_13_a_valid = anonIn_13_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_13_a_bits_opcode = anonIn_13_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_13_a_bits_param = anonIn_13_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_13_a_bits_size = anonIn_13_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_13_a_bits_address = anonIn_13_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_13_a_bits_mask = anonIn_13_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_13_a_bits_data = anonIn_13_a_bits_data; // @[Xbar.scala:159:18]
wire in_13_a_bits_corrupt = anonIn_13_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_13_d_ready = anonIn_13_d_ready; // @[Xbar.scala:159:18]
wire in_13_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_valid_0 = anonIn_13_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_13_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_opcode_0 = anonIn_13_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_13_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_param_0 = anonIn_13_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_13_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_size_0 = anonIn_13_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_13; // @[Xbar.scala:156:69]
assign auto_anon_in_13_d_bits_source_0 = anonIn_13_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_13_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_sink_0 = anonIn_13_d_bits_sink; // @[Xbar.scala:74:9]
wire in_13_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_denied_0 = anonIn_13_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_13_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_data_0 = anonIn_13_d_bits_data; // @[Xbar.scala:74:9]
wire in_13_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_13_d_bits_corrupt_0 = anonIn_13_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_14_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_14_a_ready_0 = anonIn_14_a_ready; // @[Xbar.scala:74:9]
wire in_14_a_valid = anonIn_14_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_14_a_bits_opcode = anonIn_14_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_14_a_bits_param = anonIn_14_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_14_a_bits_size = anonIn_14_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_14_a_bits_address = anonIn_14_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_14_a_bits_mask = anonIn_14_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_14_a_bits_data = anonIn_14_a_bits_data; // @[Xbar.scala:159:18]
wire in_14_a_bits_corrupt = anonIn_14_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_14_d_ready = anonIn_14_d_ready; // @[Xbar.scala:159:18]
wire in_14_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_valid_0 = anonIn_14_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_14_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_opcode_0 = anonIn_14_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_14_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_param_0 = anonIn_14_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_14_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_size_0 = anonIn_14_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_14; // @[Xbar.scala:156:69]
assign auto_anon_in_14_d_bits_source_0 = anonIn_14_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_14_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_sink_0 = anonIn_14_d_bits_sink; // @[Xbar.scala:74:9]
wire in_14_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_denied_0 = anonIn_14_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_14_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_data_0 = anonIn_14_d_bits_data; // @[Xbar.scala:74:9]
wire in_14_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_14_d_bits_corrupt_0 = anonIn_14_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_15_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_15_a_ready_0 = anonIn_15_a_ready; // @[Xbar.scala:74:9]
wire in_15_a_valid = anonIn_15_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_15_a_bits_opcode = anonIn_15_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_15_a_bits_param = anonIn_15_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_15_a_bits_size = anonIn_15_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_15_a_bits_address = anonIn_15_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_15_a_bits_mask = anonIn_15_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_15_a_bits_data = anonIn_15_a_bits_data; // @[Xbar.scala:159:18]
wire in_15_a_bits_corrupt = anonIn_15_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_15_d_ready = anonIn_15_d_ready; // @[Xbar.scala:159:18]
wire in_15_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_valid_0 = anonIn_15_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_15_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_opcode_0 = anonIn_15_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_15_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_param_0 = anonIn_15_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_15_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_size_0 = anonIn_15_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_15; // @[Xbar.scala:156:69]
assign auto_anon_in_15_d_bits_source_0 = anonIn_15_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_15_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_sink_0 = anonIn_15_d_bits_sink; // @[Xbar.scala:74:9]
wire in_15_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_denied_0 = anonIn_15_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_15_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_data_0 = anonIn_15_d_bits_data; // @[Xbar.scala:74:9]
wire in_15_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_15_d_bits_corrupt_0 = anonIn_15_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_16_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_16_a_ready_0 = anonIn_16_a_ready; // @[Xbar.scala:74:9]
wire in_16_a_valid = anonIn_16_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_16_a_bits_opcode = anonIn_16_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_16_a_bits_param = anonIn_16_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_16_a_bits_size = anonIn_16_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_16_a_bits_address = anonIn_16_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_16_a_bits_mask = anonIn_16_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_16_a_bits_data = anonIn_16_a_bits_data; // @[Xbar.scala:159:18]
wire in_16_a_bits_corrupt = anonIn_16_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_16_d_ready = anonIn_16_d_ready; // @[Xbar.scala:159:18]
wire in_16_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_valid_0 = anonIn_16_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_16_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_opcode_0 = anonIn_16_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_16_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_param_0 = anonIn_16_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_16_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_size_0 = anonIn_16_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_16; // @[Xbar.scala:156:69]
assign auto_anon_in_16_d_bits_source_0 = anonIn_16_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_16_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_sink_0 = anonIn_16_d_bits_sink; // @[Xbar.scala:74:9]
wire in_16_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_denied_0 = anonIn_16_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_16_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_data_0 = anonIn_16_d_bits_data; // @[Xbar.scala:74:9]
wire in_16_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_16_d_bits_corrupt_0 = anonIn_16_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_17_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_17_a_ready_0 = anonIn_17_a_ready; // @[Xbar.scala:74:9]
wire in_17_a_valid = anonIn_17_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_17_a_bits_opcode = anonIn_17_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_17_a_bits_param = anonIn_17_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_17_a_bits_size = anonIn_17_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_17_a_bits_address = anonIn_17_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_17_a_bits_mask = anonIn_17_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_17_a_bits_data = anonIn_17_a_bits_data; // @[Xbar.scala:159:18]
wire in_17_a_bits_corrupt = anonIn_17_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_17_d_ready = anonIn_17_d_ready; // @[Xbar.scala:159:18]
wire in_17_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_valid_0 = anonIn_17_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_17_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_opcode_0 = anonIn_17_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_17_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_param_0 = anonIn_17_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_17_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_size_0 = anonIn_17_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_17; // @[Xbar.scala:156:69]
assign auto_anon_in_17_d_bits_source_0 = anonIn_17_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_17_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_sink_0 = anonIn_17_d_bits_sink; // @[Xbar.scala:74:9]
wire in_17_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_denied_0 = anonIn_17_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_17_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_data_0 = anonIn_17_d_bits_data; // @[Xbar.scala:74:9]
wire in_17_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_17_d_bits_corrupt_0 = anonIn_17_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_18_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_18_a_ready_0 = anonIn_18_a_ready; // @[Xbar.scala:74:9]
wire in_18_a_valid = anonIn_18_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_18_a_bits_opcode = anonIn_18_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_18_a_bits_param = anonIn_18_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_18_a_bits_size = anonIn_18_a_bits_size; // @[Xbar.scala:159:18]
wire [4:0] _in_18_a_bits_source_T = anonIn_18_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_18_a_bits_address = anonIn_18_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_18_a_bits_mask = anonIn_18_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_18_a_bits_data = anonIn_18_a_bits_data; // @[Xbar.scala:159:18]
wire in_18_a_bits_corrupt = anonIn_18_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_18_d_ready = anonIn_18_d_ready; // @[Xbar.scala:159:18]
wire in_18_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_valid_0 = anonIn_18_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_18_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_opcode_0 = anonIn_18_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_18_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_param_0 = anonIn_18_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_18_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_size_0 = anonIn_18_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_18; // @[Xbar.scala:156:69]
assign auto_anon_in_18_d_bits_source_0 = anonIn_18_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_18_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_sink_0 = anonIn_18_d_bits_sink; // @[Xbar.scala:74:9]
wire in_18_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_denied_0 = anonIn_18_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_18_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_data_0 = anonIn_18_d_bits_data; // @[Xbar.scala:74:9]
wire in_18_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_18_d_bits_corrupt_0 = anonIn_18_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_19_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_19_a_ready_0 = anonIn_19_a_ready; // @[Xbar.scala:74:9]
wire in_19_a_valid = anonIn_19_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_19_a_bits_opcode = anonIn_19_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_19_a_bits_param = anonIn_19_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_19_a_bits_size = anonIn_19_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_19_a_bits_address = anonIn_19_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_19_a_bits_mask = anonIn_19_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_19_a_bits_data = anonIn_19_a_bits_data; // @[Xbar.scala:159:18]
wire in_19_a_bits_corrupt = anonIn_19_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_19_b_ready = anonIn_19_b_ready; // @[Xbar.scala:159:18]
wire in_19_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_19_b_valid_0 = anonIn_19_b_valid; // @[Xbar.scala:74:9]
wire [1:0] in_19_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_19_b_bits_param_0 = anonIn_19_b_bits_param; // @[Xbar.scala:74:9]
wire [31:0] in_19_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_19_b_bits_address_0 = anonIn_19_b_bits_address; // @[Xbar.scala:74:9]
wire in_19_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_19_c_ready_0 = anonIn_19_c_ready; // @[Xbar.scala:74:9]
wire in_19_c_valid = anonIn_19_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_19_c_bits_opcode = anonIn_19_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_19_c_bits_param = anonIn_19_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_19_c_bits_size = anonIn_19_c_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_19_c_bits_address = anonIn_19_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_19_c_bits_data = anonIn_19_c_bits_data; // @[Xbar.scala:159:18]
wire in_19_c_bits_corrupt = anonIn_19_c_bits_corrupt; // @[Xbar.scala:159:18]
wire in_19_d_ready = anonIn_19_d_ready; // @[Xbar.scala:159:18]
wire in_19_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_valid_0 = anonIn_19_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_19_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_opcode_0 = anonIn_19_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_19_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_param_0 = anonIn_19_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_19_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_size_0 = anonIn_19_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] _anonIn_d_bits_source_T_19; // @[Xbar.scala:156:69]
assign auto_anon_in_19_d_bits_source_0 = anonIn_19_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_19_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_sink_0 = anonIn_19_d_bits_sink; // @[Xbar.scala:74:9]
wire in_19_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_denied_0 = anonIn_19_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_19_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_data_0 = anonIn_19_d_bits_data; // @[Xbar.scala:74:9]
wire in_19_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_19_d_bits_corrupt_0 = anonIn_19_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_19_e_valid = anonIn_19_e_valid; // @[Xbar.scala:159:18]
wire [2:0] in_19_e_bits_sink = anonIn_19_e_bits_sink; // @[Xbar.scala:159:18]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [8:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [8:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_1_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [8:0] out_1_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_1_b_valid = x1_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] out_1_b_bits_param = x1_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] out_1_b_bits_address = x1_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire out_1_c_ready = x1_anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_1_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_1_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_1_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[Xbar.scala:74:9]
assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [8:0] out_1_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_1_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] out_1_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_1_c_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[Xbar.scala:74:9]
wire out_1_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [8:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_1_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[Xbar.scala:74:9]
wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_0_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_2_0_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_1_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_0_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_1_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_2_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_2_0_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_2_1_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_2_0_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_2_1_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_56 = in_2_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_2_1_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_2_0_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_2_1_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_2_0_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_2_1_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_0_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_1_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_2_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18]
wire _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_3_a_ready = in_3_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_3_0_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_3_1_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_3_0_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_3_1_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_3_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_3_0_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_3_1_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_3_0_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_3_1_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_84 = in_3_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_3_0_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_3_1_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_3_0_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_3_1_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_3_0_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_3_1_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_3_0_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_3_1_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_3_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_3_d_valid = in_3_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_opcode = in_3_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_param = in_3_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_size = in_3_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_sink = in_3_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_denied = in_3_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_data = in_3_d_bits_data; // @[Xbar.scala:159:18]
wire _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_3_d_bits_corrupt = in_3_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_4_a_ready = in_4_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_4_0_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_4_1_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_4_0_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_4_1_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_4_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_4_0_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_4_1_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_4_0_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_4_1_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_112 = in_4_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_4_0_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_4_1_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_4_0_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_4_1_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_4_0_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_4_1_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_4_0_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_4_1_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_4_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_4_d_valid = in_4_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_4_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_opcode = in_4_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_4_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_param = in_4_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_4_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_size = in_4_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_4_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_sink = in_4_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_4_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_denied = in_4_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_4_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_data = in_4_d_bits_data; // @[Xbar.scala:159:18]
wire _in_4_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_4_d_bits_corrupt = in_4_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_5_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_5_a_ready = in_5_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_5_0_bits_opcode = in_5_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_5_1_bits_opcode = in_5_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_5_0_bits_param = in_5_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_5_1_bits_param = in_5_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_5_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_5_0_bits_size = in_5_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_5_1_bits_size = in_5_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_5_0_bits_source = in_5_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_5_1_bits_source = in_5_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_140 = in_5_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_5_0_bits_address = in_5_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_5_1_bits_address = in_5_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_5_0_bits_mask = in_5_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_5_1_bits_mask = in_5_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_5_0_bits_data = in_5_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_5_1_bits_data = in_5_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_5_0_bits_corrupt = in_5_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_5_1_bits_corrupt = in_5_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_5_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_5_d_valid = in_5_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_5_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_opcode = in_5_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_5_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_param = in_5_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_5_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_size = in_5_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_5_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_sink = in_5_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_5_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_denied = in_5_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_5_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_data = in_5_d_bits_data; // @[Xbar.scala:159:18]
wire _in_5_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_5_d_bits_corrupt = in_5_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_6_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_6_a_ready = in_6_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_6_0_bits_opcode = in_6_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_6_1_bits_opcode = in_6_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_6_0_bits_param = in_6_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_6_1_bits_param = in_6_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_6_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_6_0_bits_size = in_6_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_6_1_bits_size = in_6_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_6_0_bits_source = in_6_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_6_1_bits_source = in_6_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_168 = in_6_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_6_0_bits_address = in_6_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_6_1_bits_address = in_6_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_6_0_bits_mask = in_6_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_6_1_bits_mask = in_6_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_6_0_bits_data = in_6_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_6_1_bits_data = in_6_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_6_0_bits_corrupt = in_6_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_6_1_bits_corrupt = in_6_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_6_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_6_d_valid = in_6_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_6_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_opcode = in_6_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_6_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_param = in_6_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_6_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_size = in_6_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_6_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_sink = in_6_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_6_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_denied = in_6_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_6_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_data = in_6_d_bits_data; // @[Xbar.scala:159:18]
wire _in_6_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_6_d_bits_corrupt = in_6_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_7_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_7_a_ready = in_7_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_7_0_bits_opcode = in_7_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_7_1_bits_opcode = in_7_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_7_0_bits_param = in_7_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_7_1_bits_param = in_7_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_7_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_7_0_bits_size = in_7_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_7_1_bits_size = in_7_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_7_0_bits_source = in_7_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_7_1_bits_source = in_7_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_196 = in_7_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_7_0_bits_address = in_7_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_7_1_bits_address = in_7_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_7_0_bits_mask = in_7_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_7_1_bits_mask = in_7_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_7_0_bits_data = in_7_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_7_1_bits_data = in_7_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_7_0_bits_corrupt = in_7_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_7_1_bits_corrupt = in_7_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_7_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_7_d_valid = in_7_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_7_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_opcode = in_7_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_7_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_param = in_7_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_7_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_size = in_7_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_7_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_sink = in_7_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_7_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_denied = in_7_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_7_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_data = in_7_d_bits_data; // @[Xbar.scala:159:18]
wire _in_7_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_7_d_bits_corrupt = in_7_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_8_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_8_a_ready = in_8_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_8_0_bits_opcode = in_8_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_8_1_bits_opcode = in_8_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_8_0_bits_param = in_8_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_8_1_bits_param = in_8_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_8_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_8_0_bits_size = in_8_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_8_1_bits_size = in_8_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_8_0_bits_source = in_8_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_8_1_bits_source = in_8_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_224 = in_8_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_8_0_bits_address = in_8_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_8_1_bits_address = in_8_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_8_0_bits_mask = in_8_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_8_1_bits_mask = in_8_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_8_0_bits_data = in_8_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_8_1_bits_data = in_8_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_8_0_bits_corrupt = in_8_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_8_1_bits_corrupt = in_8_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_8_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_8_d_valid = in_8_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_8_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_opcode = in_8_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_8_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_param = in_8_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_8_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_size = in_8_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_8_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_sink = in_8_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_8_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_denied = in_8_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_8_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_data = in_8_d_bits_data; // @[Xbar.scala:159:18]
wire _in_8_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_8_d_bits_corrupt = in_8_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_9_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_9_a_ready = in_9_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_9_0_bits_opcode = in_9_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_9_1_bits_opcode = in_9_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_9_0_bits_param = in_9_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_9_1_bits_param = in_9_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_9_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_9_0_bits_size = in_9_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_9_1_bits_size = in_9_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_9_0_bits_source = in_9_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_9_1_bits_source = in_9_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_252 = in_9_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_9_0_bits_address = in_9_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_9_1_bits_address = in_9_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_9_0_bits_mask = in_9_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_9_1_bits_mask = in_9_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_9_0_bits_data = in_9_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_9_1_bits_data = in_9_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_9_0_bits_corrupt = in_9_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_9_1_bits_corrupt = in_9_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_9_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_9_d_valid = in_9_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_9_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_opcode = in_9_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_9_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_param = in_9_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_9_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_size = in_9_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_9_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_sink = in_9_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_9_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_denied = in_9_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_9_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_data = in_9_d_bits_data; // @[Xbar.scala:159:18]
wire _in_9_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_9_d_bits_corrupt = in_9_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_10_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_10_a_ready = in_10_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_10_0_bits_opcode = in_10_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_10_1_bits_opcode = in_10_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_10_0_bits_param = in_10_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_10_1_bits_param = in_10_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_10_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_10_0_bits_size = in_10_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_10_1_bits_size = in_10_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_10_0_bits_source = in_10_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_10_1_bits_source = in_10_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_280 = in_10_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_10_0_bits_address = in_10_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_10_1_bits_address = in_10_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_10_0_bits_mask = in_10_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_10_1_bits_mask = in_10_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_10_0_bits_data = in_10_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_10_1_bits_data = in_10_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_10_0_bits_corrupt = in_10_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_10_1_bits_corrupt = in_10_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_10_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_10_d_valid = in_10_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_10_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_opcode = in_10_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_10_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_param = in_10_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_10_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_size = in_10_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_10_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_sink = in_10_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_10_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_denied = in_10_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_10_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_data = in_10_d_bits_data; // @[Xbar.scala:159:18]
wire _in_10_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_10_d_bits_corrupt = in_10_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_11_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_11_a_ready = in_11_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_11_0_bits_opcode = in_11_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_11_1_bits_opcode = in_11_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_11_0_bits_param = in_11_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_11_1_bits_param = in_11_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_11_0_bits_size = in_11_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_11_1_bits_size = in_11_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_11_0_bits_source = in_11_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_11_1_bits_source = in_11_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_308 = in_11_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_11_0_bits_address = in_11_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_11_1_bits_address = in_11_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_11_0_bits_mask = in_11_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_11_1_bits_mask = in_11_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_11_0_bits_data = in_11_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_11_1_bits_data = in_11_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_11_0_bits_corrupt = in_11_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_11_1_bits_corrupt = in_11_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_11_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_11_d_valid = in_11_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_11_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_opcode = in_11_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_11_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_param = in_11_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_11_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_size = in_11_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_11_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_sink = in_11_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_11_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_denied = in_11_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_11_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_data = in_11_d_bits_data; // @[Xbar.scala:159:18]
wire _in_11_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_11_d_bits_corrupt = in_11_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_12_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_12_a_ready = in_12_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_12_0_bits_opcode = in_12_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_12_1_bits_opcode = in_12_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_12_0_bits_param = in_12_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_12_1_bits_param = in_12_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_12_0_bits_size = in_12_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_12_1_bits_size = in_12_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_12_0_bits_source = in_12_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_12_1_bits_source = in_12_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_336 = in_12_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_12_0_bits_address = in_12_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_12_1_bits_address = in_12_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_12_0_bits_mask = in_12_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_12_1_bits_mask = in_12_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_12_0_bits_data = in_12_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_12_1_bits_data = in_12_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_12_0_bits_corrupt = in_12_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_12_1_bits_corrupt = in_12_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_12_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_12_d_valid = in_12_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_12_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_opcode = in_12_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_12_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_param = in_12_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_12_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_size = in_12_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_12_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_sink = in_12_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_12_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_denied = in_12_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_12_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_data = in_12_d_bits_data; // @[Xbar.scala:159:18]
wire _in_12_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_12_d_bits_corrupt = in_12_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_13_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_13_a_ready = in_13_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_13_0_bits_opcode = in_13_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_13_1_bits_opcode = in_13_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_13_0_bits_param = in_13_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_13_1_bits_param = in_13_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_13_0_bits_size = in_13_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_13_1_bits_size = in_13_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_13_0_bits_source = in_13_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_13_1_bits_source = in_13_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_364 = in_13_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_13_0_bits_address = in_13_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_13_1_bits_address = in_13_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_13_0_bits_mask = in_13_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_13_1_bits_mask = in_13_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_13_0_bits_data = in_13_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_13_1_bits_data = in_13_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_13_0_bits_corrupt = in_13_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_13_1_bits_corrupt = in_13_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_13_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_13_d_valid = in_13_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_13_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_opcode = in_13_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_13_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_param = in_13_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_13_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_size = in_13_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_13_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_sink = in_13_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_13_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_denied = in_13_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_13_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_data = in_13_d_bits_data; // @[Xbar.scala:159:18]
wire _in_13_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_13_d_bits_corrupt = in_13_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_14_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_14_a_ready = in_14_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_14_0_bits_opcode = in_14_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_14_1_bits_opcode = in_14_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_14_0_bits_param = in_14_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_14_1_bits_param = in_14_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_14_0_bits_size = in_14_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_14_1_bits_size = in_14_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_14_0_bits_source = in_14_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_14_1_bits_source = in_14_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_392 = in_14_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_14_0_bits_address = in_14_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_14_1_bits_address = in_14_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_14_0_bits_mask = in_14_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_14_1_bits_mask = in_14_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_14_0_bits_data = in_14_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_14_1_bits_data = in_14_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_14_0_bits_corrupt = in_14_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_14_1_bits_corrupt = in_14_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_14_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_14_d_valid = in_14_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_14_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_opcode = in_14_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_14_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_param = in_14_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_14_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_size = in_14_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_14_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_sink = in_14_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_14_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_denied = in_14_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_14_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_data = in_14_d_bits_data; // @[Xbar.scala:159:18]
wire _in_14_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_14_d_bits_corrupt = in_14_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_15_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_15_a_ready = in_15_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_15_0_bits_opcode = in_15_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_15_1_bits_opcode = in_15_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_15_0_bits_param = in_15_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_15_1_bits_param = in_15_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_15_0_bits_size = in_15_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_15_1_bits_size = in_15_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_15_0_bits_source = in_15_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_15_1_bits_source = in_15_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_420 = in_15_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_15_0_bits_address = in_15_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_15_1_bits_address = in_15_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_15_0_bits_mask = in_15_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_15_1_bits_mask = in_15_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_15_0_bits_data = in_15_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_15_1_bits_data = in_15_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_15_0_bits_corrupt = in_15_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_15_1_bits_corrupt = in_15_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_15_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_15_d_valid = in_15_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_15_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_opcode = in_15_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_15_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_param = in_15_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_15_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_size = in_15_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_15_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_sink = in_15_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_15_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_denied = in_15_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_15_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_data = in_15_d_bits_data; // @[Xbar.scala:159:18]
wire _in_15_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_15_d_bits_corrupt = in_15_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_16_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_16_a_ready = in_16_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_16_0_bits_opcode = in_16_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_16_1_bits_opcode = in_16_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_16_0_bits_param = in_16_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_16_1_bits_param = in_16_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_16_0_bits_size = in_16_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_16_1_bits_size = in_16_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_16_0_bits_source = in_16_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_16_1_bits_source = in_16_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_448 = in_16_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_16_0_bits_address = in_16_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_16_1_bits_address = in_16_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_16_0_bits_mask = in_16_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_16_1_bits_mask = in_16_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_16_0_bits_data = in_16_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_16_1_bits_data = in_16_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_16_0_bits_corrupt = in_16_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_16_1_bits_corrupt = in_16_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_16_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_16_d_valid = in_16_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_16_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_opcode = in_16_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_16_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_param = in_16_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_16_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_size = in_16_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_16_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_sink = in_16_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_16_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_denied = in_16_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_16_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_data = in_16_d_bits_data; // @[Xbar.scala:159:18]
wire _in_16_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_16_d_bits_corrupt = in_16_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_17_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_17_a_ready = in_17_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_17_0_bits_opcode = in_17_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_17_1_bits_opcode = in_17_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_17_0_bits_param = in_17_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_17_1_bits_param = in_17_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_17_0_bits_size = in_17_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_17_1_bits_size = in_17_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_17_0_bits_source = in_17_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_17_1_bits_source = in_17_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_476 = in_17_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_17_0_bits_address = in_17_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_17_1_bits_address = in_17_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_17_0_bits_mask = in_17_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_17_1_bits_mask = in_17_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_17_0_bits_data = in_17_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_17_1_bits_data = in_17_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_17_0_bits_corrupt = in_17_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_17_1_bits_corrupt = in_17_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_17_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_17_d_valid = in_17_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_17_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_opcode = in_17_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_17_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_param = in_17_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_17_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_size = in_17_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_17_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_sink = in_17_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_17_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_denied = in_17_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_17_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_data = in_17_d_bits_data; // @[Xbar.scala:159:18]
wire _in_17_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_17_d_bits_corrupt = in_17_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_18_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_18_a_ready = in_18_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_18_0_bits_opcode = in_18_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_18_1_bits_opcode = in_18_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_18_0_bits_param = in_18_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_18_1_bits_param = in_18_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_18_0_bits_size = in_18_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_18_1_bits_size = in_18_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_18_0_bits_source = in_18_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_18_1_bits_source = in_18_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_504 = in_18_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_18_0_bits_address = in_18_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_18_1_bits_address = in_18_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_18_0_bits_mask = in_18_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_18_1_bits_mask = in_18_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_18_0_bits_data = in_18_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_18_1_bits_data = in_18_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_18_0_bits_corrupt = in_18_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_18_1_bits_corrupt = in_18_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_18_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_18_d_valid = in_18_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_18_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_opcode = in_18_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_18_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_param = in_18_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_18_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_size = in_18_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_18_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_sink = in_18_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_18_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_denied = in_18_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_18_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_data = in_18_d_bits_data; // @[Xbar.scala:159:18]
wire _in_18_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_18_d_bits_corrupt = in_18_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsAOI_in_19_a_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_19_a_ready = in_19_a_ready; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_19_0_bits_opcode = in_19_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_19_1_bits_opcode = in_19_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_19_0_bits_param = in_19_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_19_1_bits_param = in_19_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_19_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_19_0_bits_size = in_19_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_19_1_bits_size = in_19_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_19_0_bits_source = in_19_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsAOI_filtered_19_1_bits_source = in_19_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_532 = in_19_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_19_0_bits_address = in_19_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_19_1_bits_address = in_19_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_19_0_bits_mask = in_19_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_19_1_bits_mask = in_19_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_19_0_bits_data = in_19_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_19_1_bits_data = in_19_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_19_0_bits_corrupt = in_19_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_19_1_bits_corrupt = in_19_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_19_ready = in_19_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_19_valid; // @[Xbar.scala:352:24]
assign anonIn_19_b_valid = in_19_b_valid; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_1_19_bits_param; // @[Xbar.scala:352:24]
assign anonIn_19_b_bits_param = in_19_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] portsBIO_filtered_1_19_bits_address; // @[Xbar.scala:352:24]
assign anonIn_19_b_bits_address = in_19_b_bits_address; // @[Xbar.scala:159:18]
wire _portsCOI_in_19_c_ready_WIRE; // @[Mux.scala:30:73]
assign anonIn_19_c_ready = in_19_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_39 = in_19_c_valid; // @[Xbar.scala:159:18, :355:40]
wire _portsCOI_filtered_1_valid_T_39 = in_19_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_19_0_bits_opcode = in_19_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_19_1_bits_opcode = in_19_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_19_0_bits_param = in_19_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_19_1_bits_param = in_19_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [8:0] _in_19_c_bits_source_T; // @[Xbar.scala:187:55]
wire [3:0] portsCOI_filtered_19_0_bits_size = in_19_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_19_1_bits_size = in_19_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsCOI_filtered_19_0_bits_source = in_19_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [8:0] portsCOI_filtered_19_1_bits_source = in_19_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T_190 = in_19_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T_195 = in_19_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_19_0_bits_address = in_19_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsCOI_filtered_19_1_bits_address = in_19_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_19_0_bits_data = in_19_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_19_1_bits_data = in_19_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsCOI_filtered_19_0_bits_corrupt = in_19_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsCOI_filtered_19_1_bits_corrupt = in_19_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _in_19_d_valid_T_4; // @[Arbiter.scala:96:24]
assign anonIn_19_d_valid = in_19_d_valid; // @[Xbar.scala:159:18]
wire [2:0] _in_19_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_opcode = in_19_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] _in_19_d_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_param = in_19_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] _in_19_d_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_size = in_19_d_bits_size; // @[Xbar.scala:159:18]
wire [8:0] _in_19_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_19_d_bits_WIRE_sink; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_sink = in_19_d_bits_sink; // @[Xbar.scala:159:18]
wire _in_19_d_bits_WIRE_denied; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_denied = in_19_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] _in_19_d_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_data = in_19_d_bits_data; // @[Xbar.scala:159:18]
wire _in_19_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonIn_19_d_bits_corrupt = in_19_d_bits_corrupt; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_1_valid_T_39 = in_19_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] _requestEIO_uncommonBits_T_19 = in_19_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] portsEOI_filtered_19_0_bits_sink = in_19_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsEOI_filtered_19_1_bits_sink = in_19_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
wire [8:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_2_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_3_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_4_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_5_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_6_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_7_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_8_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_9_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_10_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_11_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_12_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_13_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_14_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_15_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_16_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_17_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_18_d_bits_source; // @[Xbar.scala:159:18]
wire [8:0] in_19_d_bits_source; // @[Xbar.scala:159:18]
assign _in_0_a_bits_source_T = {4'hE, anonIn_a_bits_source}; // @[Xbar.scala:166:55]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign _in_1_a_bits_source_T = {7'h7C, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55]
assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign _in_2_a_bits_source_T = {7'h7B, anonIn_2_a_bits_source}; // @[Xbar.scala:166:55]
assign in_2_a_bits_source = _in_2_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_2 = in_2_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_2_d_bits_source = _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69]
assign _in_3_a_bits_source_T = {4'hD, anonIn_3_a_bits_source}; // @[Xbar.scala:166:55]
assign in_3_a_bits_source = _in_3_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_3 = in_3_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_3_d_bits_source = _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69]
assign _in_4_a_bits_source_T = {4'hC, anonIn_4_a_bits_source}; // @[Xbar.scala:166:55]
assign in_4_a_bits_source = _in_4_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_4 = in_4_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_4_d_bits_source = _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69]
assign _in_5_a_bits_source_T = {4'hB, anonIn_5_a_bits_source}; // @[Xbar.scala:166:55]
assign in_5_a_bits_source = _in_5_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_5 = in_5_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_5_d_bits_source = _anonIn_d_bits_source_T_5; // @[Xbar.scala:156:69]
assign _in_6_a_bits_source_T = {4'hA, anonIn_6_a_bits_source}; // @[Xbar.scala:166:55]
assign in_6_a_bits_source = _in_6_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_6 = in_6_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_6_d_bits_source = _anonIn_d_bits_source_T_6; // @[Xbar.scala:156:69]
assign _in_7_a_bits_source_T = {4'h9, anonIn_7_a_bits_source}; // @[Xbar.scala:166:55]
assign in_7_a_bits_source = _in_7_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_7 = in_7_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_7_d_bits_source = _anonIn_d_bits_source_T_7; // @[Xbar.scala:156:69]
assign _in_8_a_bits_source_T = {4'h8, anonIn_8_a_bits_source}; // @[Xbar.scala:166:55]
assign in_8_a_bits_source = _in_8_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_8 = in_8_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_8_d_bits_source = _anonIn_d_bits_source_T_8; // @[Xbar.scala:156:69]
assign _in_9_a_bits_source_T = {7'h7A, anonIn_9_a_bits_source}; // @[Xbar.scala:166:55]
assign in_9_a_bits_source = _in_9_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_9 = in_9_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_9_d_bits_source = _anonIn_d_bits_source_T_9; // @[Xbar.scala:156:69]
assign _in_10_a_bits_source_T = {7'h79, anonIn_10_a_bits_source}; // @[Xbar.scala:166:55]
assign in_10_a_bits_source = _in_10_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T_10 = in_10_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_10_d_bits_source = _anonIn_d_bits_source_T_10; // @[Xbar.scala:156:69]
wire [7:0] _in_11_a_bits_source_T = {3'h7, anonIn_11_a_bits_source}; // @[Xbar.scala:166:55]
assign in_11_a_bits_source = {1'h0, _in_11_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_11 = in_11_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_11_d_bits_source = _anonIn_d_bits_source_T_11; // @[Xbar.scala:156:69]
wire [7:0] _in_12_a_bits_source_T = {3'h6, anonIn_12_a_bits_source}; // @[Xbar.scala:166:55]
assign in_12_a_bits_source = {1'h0, _in_12_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_12 = in_12_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_12_d_bits_source = _anonIn_d_bits_source_T_12; // @[Xbar.scala:156:69]
wire [7:0] _in_13_a_bits_source_T = {3'h5, anonIn_13_a_bits_source}; // @[Xbar.scala:166:55]
assign in_13_a_bits_source = {1'h0, _in_13_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_13 = in_13_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_13_d_bits_source = _anonIn_d_bits_source_T_13; // @[Xbar.scala:156:69]
wire [7:0] _in_14_a_bits_source_T = {3'h4, anonIn_14_a_bits_source}; // @[Xbar.scala:166:55]
assign in_14_a_bits_source = {1'h0, _in_14_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_14 = in_14_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_14_d_bits_source = _anonIn_d_bits_source_T_14; // @[Xbar.scala:156:69]
wire [6:0] _in_15_a_bits_source_T = {2'h3, anonIn_15_a_bits_source}; // @[Xbar.scala:166:55]
assign in_15_a_bits_source = {2'h0, _in_15_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_15 = in_15_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_15_d_bits_source = _anonIn_d_bits_source_T_15; // @[Xbar.scala:156:69]
wire [6:0] _in_16_a_bits_source_T = {2'h2, anonIn_16_a_bits_source}; // @[Xbar.scala:166:55]
assign in_16_a_bits_source = {2'h0, _in_16_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_16 = in_16_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_16_d_bits_source = _anonIn_d_bits_source_T_16; // @[Xbar.scala:156:69]
wire [5:0] _in_17_a_bits_source_T = {1'h1, anonIn_17_a_bits_source}; // @[Xbar.scala:166:55]
assign in_17_a_bits_source = {3'h0, _in_17_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_17 = in_17_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_17_d_bits_source = _anonIn_d_bits_source_T_17; // @[Xbar.scala:156:69]
assign in_18_a_bits_source = {4'h0, _in_18_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_18 = in_18_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_18_d_bits_source = _anonIn_d_bits_source_T_18; // @[Xbar.scala:156:69]
assign _in_19_a_bits_source_T = {7'h78, anonIn_19_a_bits_source}; // @[Xbar.scala:166:55]
assign in_19_a_bits_source = _in_19_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _in_19_c_bits_source_T = {7'h78, anonIn_19_c_bits_source}; // @[Xbar.scala:187:55]
assign in_19_c_bits_source = _in_19_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign _anonIn_d_bits_source_T_19 = in_19_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_19_d_bits_source = _anonIn_d_bits_source_T_19; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_58; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [8:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_3_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_4_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_5_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_6_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_7_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_8_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_9_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_10_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_11_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_12_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_13_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_14_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_15_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_16_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_17_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_18_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_19_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_3_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_4_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_5_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_6_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_7_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_8_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_9_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_10_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_11_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_12_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_13_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_14_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_15_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_16_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_17_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_18_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_19_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_3_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_4_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_5_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_6_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_7_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_8_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_9_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_10_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_11_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_12_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_13_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_14_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_15_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_16_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_17_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_18_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_19_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [8:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_2 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_3 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_4 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_5 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_6 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_7 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_8 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_9 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_10 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_11 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_12 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_13 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_14 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_15 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_16 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_17 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_18 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_19 = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_3_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_4_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_5_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_6_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_7_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_8_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_9_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_10_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_11_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_12_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_13_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_14_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_15_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_16_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_17_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_18_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_19_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_3_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_4_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_5_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_6_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_7_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_8_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_9_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_10_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_11_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_12_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_13_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_14_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_15_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_16_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_17_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_18_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_19_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_3_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_4_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_5_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_6_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_7_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_8_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_9_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_10_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_11_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_12_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_13_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_14_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_15_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_16_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_17_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_18_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_19_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_3_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_4_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_5_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_6_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_7_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_8_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_9_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_10_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_11_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_12_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_13_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_14_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_15_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_16_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_17_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_18_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_19_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_3_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_4_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_5_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_6_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_7_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_8_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_9_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_10_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_11_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_12_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_13_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_14_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_15_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_16_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_17_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_18_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_19_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire _out_1_a_valid_T_58; // @[Arbiter.scala:96:24]
assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19]
wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73]
assign x1_anonOut_b_ready = out_1_b_ready; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_19_valid_T_3 = out_1_b_valid; // @[Xbar.scala:216:19, :355:40]
wire [1:0] portsBIO_filtered_1_0_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_1_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_2_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_3_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_4_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_5_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_6_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_7_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_8_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_9_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_10_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_11_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_12_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_13_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_14_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_15_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_16_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_17_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_18_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_19_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_0_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_1_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_2_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_3_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_4_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_5_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_6_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_7_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_8_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_9_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_10_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_11_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_12_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_13_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_14_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_15_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_16_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_17_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_18_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_19_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_19_1_ready = out_1_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_19_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_c_valid = out_1_c_valid; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_opcode = out_1_c_bits_opcode; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_param = out_1_c_bits_param; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_source = out_1_c_bits_source; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_address = out_1_c_bits_address; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_data = out_1_c_bits_data; // @[Xbar.scala:216:19]
assign x1_anonOut_c_bits_corrupt = out_1_c_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73]
assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19]
wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_2_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_3_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_4_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_5_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_6_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_7_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_8_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_9_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_10_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_11_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_12_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_13_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_14_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_15_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_16_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_17_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_18_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_19_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_2_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_3_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_4_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_5_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_6_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_7_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_8_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_9_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_10_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_11_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_12_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_13_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_14_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_15_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_16_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_17_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_18_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsDIO_filtered_1_19_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_2_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_3_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_4_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_5_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_6_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_7_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_8_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_9_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_10_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_11_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_12_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_13_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_14_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_15_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_16_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_17_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_18_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsDIO_filtered_1_19_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [8:0] _requestDOI_uncommonBits_T_20 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_21 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_22 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_23 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_24 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_25 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_26 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_27 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_28 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_29 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_30 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_31 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_32 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_33 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_34 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_35 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_36 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_37 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_38 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] _requestDOI_uncommonBits_T_39 = out_1_d_bits_source; // @[Xbar.scala:216:19]
wire [8:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_2_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_3_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_4_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_5_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_6_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_7_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_8_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_9_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_10_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_11_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_12_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_13_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_14_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_15_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_16_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_17_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_18_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [8:0] portsDIO_filtered_1_19_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_2_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_3_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_4_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_5_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_6_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_7_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_8_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_9_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_10_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_11_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_12_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_13_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_14_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_15_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_16_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_17_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_18_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsDIO_filtered_1_19_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_2_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_3_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_4_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_5_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_6_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_7_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_8_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_9_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_10_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_11_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_12_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_13_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_14_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_15_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_16_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_17_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_18_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_19_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_2_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_3_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_4_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_5_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_6_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_7_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_8_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_9_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_10_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_11_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_12_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_13_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_14_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_15_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_16_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_17_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_18_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsDIO_filtered_1_19_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_2_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_3_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_4_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_5_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_6_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_7_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_8_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_9_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_10_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_11_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_12_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_13_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_14_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_15_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_16_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_17_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_18_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsDIO_filtered_1_19_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_19_1_valid; // @[Xbar.scala:352:24]
assign x1_anonOut_e_valid = out_1_e_valid; // @[Xbar.scala:216:19]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_1_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_1_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41]
assign out_0_d_bits_sink = {2'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}]
assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41]
assign x1_anonOut_c_bits_size = out_1_c_bits_size[2:0]; // @[Xbar.scala:216:19, :241:41]
assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29]
assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign x1_anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46]
wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46]
wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46]
wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_15 = _requestAIO_T_4 | _requestAIO_T_9; // @[Xbar.scala:291:92]
wire _requestAIO_T_16 = _requestAIO_T_15 | _requestAIO_T_14; // @[Xbar.scala:291:92]
wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46]
wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46]
wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_27 = _requestAIO_T_21 | _requestAIO_T_26; // @[Xbar.scala:291:92]
wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46]
wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46]
wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46]
wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_43 = _requestAIO_T_32 | _requestAIO_T_37; // @[Xbar.scala:291:92]
wire _requestAIO_T_44 = _requestAIO_T_43 | _requestAIO_T_42; // @[Xbar.scala:291:92]
wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46]
wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46]
wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_55 = _requestAIO_T_49 | _requestAIO_T_54; // @[Xbar.scala:291:92]
wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_57 = {1'h0, _requestAIO_T_56}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_58 = _requestAIO_T_57 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_59 = _requestAIO_T_58; // @[Parameters.scala:137:46]
wire _requestAIO_T_60 = _requestAIO_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_61 = {in_2_a_bits_address[31:17], in_2_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_62 = {1'h0, _requestAIO_T_61}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_63 = _requestAIO_T_62 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_64 = _requestAIO_T_63; // @[Parameters.scala:137:46]
wire _requestAIO_T_65 = _requestAIO_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_66 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_67 = {1'h0, _requestAIO_T_66}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_68 = _requestAIO_T_67 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_69 = _requestAIO_T_68; // @[Parameters.scala:137:46]
wire _requestAIO_T_70 = _requestAIO_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_71 = _requestAIO_T_60 | _requestAIO_T_65; // @[Xbar.scala:291:92]
wire _requestAIO_T_72 = _requestAIO_T_71 | _requestAIO_T_70; // @[Xbar.scala:291:92]
wire requestAIO_2_0 = _requestAIO_T_72; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_4 = requestAIO_2_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_73 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_74 = {1'h0, _requestAIO_T_73}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_75 = _requestAIO_T_74 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_76 = _requestAIO_T_75; // @[Parameters.scala:137:46]
wire _requestAIO_T_77 = _requestAIO_T_76 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_78 = in_2_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_79 = {1'h0, _requestAIO_T_78}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_80 = _requestAIO_T_79 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_81 = _requestAIO_T_80; // @[Parameters.scala:137:46]
wire _requestAIO_T_82 = _requestAIO_T_81 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_83 = _requestAIO_T_77 | _requestAIO_T_82; // @[Xbar.scala:291:92]
wire requestAIO_2_1 = _requestAIO_T_83; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_4 = requestAIO_2_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_85 = {1'h0, _requestAIO_T_84}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_86 = _requestAIO_T_85 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_87 = _requestAIO_T_86; // @[Parameters.scala:137:46]
wire _requestAIO_T_88 = _requestAIO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_89 = {in_3_a_bits_address[31:17], in_3_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_90 = {1'h0, _requestAIO_T_89}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_91 = _requestAIO_T_90 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_92 = _requestAIO_T_91; // @[Parameters.scala:137:46]
wire _requestAIO_T_93 = _requestAIO_T_92 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_94 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_95 = {1'h0, _requestAIO_T_94}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_96 = _requestAIO_T_95 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_97 = _requestAIO_T_96; // @[Parameters.scala:137:46]
wire _requestAIO_T_98 = _requestAIO_T_97 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_99 = _requestAIO_T_88 | _requestAIO_T_93; // @[Xbar.scala:291:92]
wire _requestAIO_T_100 = _requestAIO_T_99 | _requestAIO_T_98; // @[Xbar.scala:291:92]
wire requestAIO_3_0 = _requestAIO_T_100; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_6 = requestAIO_3_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_101 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_102 = {1'h0, _requestAIO_T_101}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_103 = _requestAIO_T_102 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_104 = _requestAIO_T_103; // @[Parameters.scala:137:46]
wire _requestAIO_T_105 = _requestAIO_T_104 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_106 = in_3_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_107 = {1'h0, _requestAIO_T_106}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_108 = _requestAIO_T_107 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_109 = _requestAIO_T_108; // @[Parameters.scala:137:46]
wire _requestAIO_T_110 = _requestAIO_T_109 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_111 = _requestAIO_T_105 | _requestAIO_T_110; // @[Xbar.scala:291:92]
wire requestAIO_3_1 = _requestAIO_T_111; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_6 = requestAIO_3_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_113 = {1'h0, _requestAIO_T_112}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_114 = _requestAIO_T_113 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_115 = _requestAIO_T_114; // @[Parameters.scala:137:46]
wire _requestAIO_T_116 = _requestAIO_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_117 = {in_4_a_bits_address[31:17], in_4_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_118 = {1'h0, _requestAIO_T_117}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_119 = _requestAIO_T_118 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_120 = _requestAIO_T_119; // @[Parameters.scala:137:46]
wire _requestAIO_T_121 = _requestAIO_T_120 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_122 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_123 = {1'h0, _requestAIO_T_122}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_124 = _requestAIO_T_123 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_125 = _requestAIO_T_124; // @[Parameters.scala:137:46]
wire _requestAIO_T_126 = _requestAIO_T_125 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_127 = _requestAIO_T_116 | _requestAIO_T_121; // @[Xbar.scala:291:92]
wire _requestAIO_T_128 = _requestAIO_T_127 | _requestAIO_T_126; // @[Xbar.scala:291:92]
wire requestAIO_4_0 = _requestAIO_T_128; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_8 = requestAIO_4_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_129 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_130 = {1'h0, _requestAIO_T_129}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_131 = _requestAIO_T_130 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_132 = _requestAIO_T_131; // @[Parameters.scala:137:46]
wire _requestAIO_T_133 = _requestAIO_T_132 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_134 = in_4_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_135 = {1'h0, _requestAIO_T_134}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_136 = _requestAIO_T_135 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_137 = _requestAIO_T_136; // @[Parameters.scala:137:46]
wire _requestAIO_T_138 = _requestAIO_T_137 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_139 = _requestAIO_T_133 | _requestAIO_T_138; // @[Xbar.scala:291:92]
wire requestAIO_4_1 = _requestAIO_T_139; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_8 = requestAIO_4_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_141 = {1'h0, _requestAIO_T_140}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_142 = _requestAIO_T_141 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_143 = _requestAIO_T_142; // @[Parameters.scala:137:46]
wire _requestAIO_T_144 = _requestAIO_T_143 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_145 = {in_5_a_bits_address[31:17], in_5_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_146 = {1'h0, _requestAIO_T_145}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_147 = _requestAIO_T_146 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_148 = _requestAIO_T_147; // @[Parameters.scala:137:46]
wire _requestAIO_T_149 = _requestAIO_T_148 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_150 = {in_5_a_bits_address[31:28], in_5_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_151 = {1'h0, _requestAIO_T_150}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_152 = _requestAIO_T_151 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_153 = _requestAIO_T_152; // @[Parameters.scala:137:46]
wire _requestAIO_T_154 = _requestAIO_T_153 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_155 = _requestAIO_T_144 | _requestAIO_T_149; // @[Xbar.scala:291:92]
wire _requestAIO_T_156 = _requestAIO_T_155 | _requestAIO_T_154; // @[Xbar.scala:291:92]
wire requestAIO_5_0 = _requestAIO_T_156; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_10 = requestAIO_5_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_157 = {in_5_a_bits_address[31:28], in_5_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_158 = {1'h0, _requestAIO_T_157}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_159 = _requestAIO_T_158 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_160 = _requestAIO_T_159; // @[Parameters.scala:137:46]
wire _requestAIO_T_161 = _requestAIO_T_160 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_162 = in_5_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_163 = {1'h0, _requestAIO_T_162}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_164 = _requestAIO_T_163 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_165 = _requestAIO_T_164; // @[Parameters.scala:137:46]
wire _requestAIO_T_166 = _requestAIO_T_165 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_167 = _requestAIO_T_161 | _requestAIO_T_166; // @[Xbar.scala:291:92]
wire requestAIO_5_1 = _requestAIO_T_167; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_10 = requestAIO_5_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_169 = {1'h0, _requestAIO_T_168}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_170 = _requestAIO_T_169 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_171 = _requestAIO_T_170; // @[Parameters.scala:137:46]
wire _requestAIO_T_172 = _requestAIO_T_171 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_173 = {in_6_a_bits_address[31:17], in_6_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_174 = {1'h0, _requestAIO_T_173}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_175 = _requestAIO_T_174 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_176 = _requestAIO_T_175; // @[Parameters.scala:137:46]
wire _requestAIO_T_177 = _requestAIO_T_176 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_178 = {in_6_a_bits_address[31:28], in_6_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_179 = {1'h0, _requestAIO_T_178}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_180 = _requestAIO_T_179 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_181 = _requestAIO_T_180; // @[Parameters.scala:137:46]
wire _requestAIO_T_182 = _requestAIO_T_181 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_183 = _requestAIO_T_172 | _requestAIO_T_177; // @[Xbar.scala:291:92]
wire _requestAIO_T_184 = _requestAIO_T_183 | _requestAIO_T_182; // @[Xbar.scala:291:92]
wire requestAIO_6_0 = _requestAIO_T_184; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_12 = requestAIO_6_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_185 = {in_6_a_bits_address[31:28], in_6_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_186 = {1'h0, _requestAIO_T_185}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_187 = _requestAIO_T_186 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_188 = _requestAIO_T_187; // @[Parameters.scala:137:46]
wire _requestAIO_T_189 = _requestAIO_T_188 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_190 = in_6_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_191 = {1'h0, _requestAIO_T_190}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_192 = _requestAIO_T_191 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_193 = _requestAIO_T_192; // @[Parameters.scala:137:46]
wire _requestAIO_T_194 = _requestAIO_T_193 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_195 = _requestAIO_T_189 | _requestAIO_T_194; // @[Xbar.scala:291:92]
wire requestAIO_6_1 = _requestAIO_T_195; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_12 = requestAIO_6_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_197 = {1'h0, _requestAIO_T_196}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_198 = _requestAIO_T_197 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_199 = _requestAIO_T_198; // @[Parameters.scala:137:46]
wire _requestAIO_T_200 = _requestAIO_T_199 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_201 = {in_7_a_bits_address[31:17], in_7_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_202 = {1'h0, _requestAIO_T_201}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_203 = _requestAIO_T_202 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_204 = _requestAIO_T_203; // @[Parameters.scala:137:46]
wire _requestAIO_T_205 = _requestAIO_T_204 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_206 = {in_7_a_bits_address[31:28], in_7_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_207 = {1'h0, _requestAIO_T_206}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_208 = _requestAIO_T_207 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_209 = _requestAIO_T_208; // @[Parameters.scala:137:46]
wire _requestAIO_T_210 = _requestAIO_T_209 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_211 = _requestAIO_T_200 | _requestAIO_T_205; // @[Xbar.scala:291:92]
wire _requestAIO_T_212 = _requestAIO_T_211 | _requestAIO_T_210; // @[Xbar.scala:291:92]
wire requestAIO_7_0 = _requestAIO_T_212; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_14 = requestAIO_7_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_213 = {in_7_a_bits_address[31:28], in_7_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_214 = {1'h0, _requestAIO_T_213}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_215 = _requestAIO_T_214 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_216 = _requestAIO_T_215; // @[Parameters.scala:137:46]
wire _requestAIO_T_217 = _requestAIO_T_216 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_218 = in_7_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_219 = {1'h0, _requestAIO_T_218}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_220 = _requestAIO_T_219 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_221 = _requestAIO_T_220; // @[Parameters.scala:137:46]
wire _requestAIO_T_222 = _requestAIO_T_221 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_223 = _requestAIO_T_217 | _requestAIO_T_222; // @[Xbar.scala:291:92]
wire requestAIO_7_1 = _requestAIO_T_223; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_14 = requestAIO_7_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_225 = {1'h0, _requestAIO_T_224}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_226 = _requestAIO_T_225 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_227 = _requestAIO_T_226; // @[Parameters.scala:137:46]
wire _requestAIO_T_228 = _requestAIO_T_227 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_229 = {in_8_a_bits_address[31:17], in_8_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_230 = {1'h0, _requestAIO_T_229}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_231 = _requestAIO_T_230 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_232 = _requestAIO_T_231; // @[Parameters.scala:137:46]
wire _requestAIO_T_233 = _requestAIO_T_232 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_234 = {in_8_a_bits_address[31:28], in_8_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_235 = {1'h0, _requestAIO_T_234}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_236 = _requestAIO_T_235 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_237 = _requestAIO_T_236; // @[Parameters.scala:137:46]
wire _requestAIO_T_238 = _requestAIO_T_237 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_239 = _requestAIO_T_228 | _requestAIO_T_233; // @[Xbar.scala:291:92]
wire _requestAIO_T_240 = _requestAIO_T_239 | _requestAIO_T_238; // @[Xbar.scala:291:92]
wire requestAIO_8_0 = _requestAIO_T_240; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_16 = requestAIO_8_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_241 = {in_8_a_bits_address[31:28], in_8_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_242 = {1'h0, _requestAIO_T_241}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_243 = _requestAIO_T_242 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_244 = _requestAIO_T_243; // @[Parameters.scala:137:46]
wire _requestAIO_T_245 = _requestAIO_T_244 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_246 = in_8_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_247 = {1'h0, _requestAIO_T_246}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_248 = _requestAIO_T_247 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_249 = _requestAIO_T_248; // @[Parameters.scala:137:46]
wire _requestAIO_T_250 = _requestAIO_T_249 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_251 = _requestAIO_T_245 | _requestAIO_T_250; // @[Xbar.scala:291:92]
wire requestAIO_8_1 = _requestAIO_T_251; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_16 = requestAIO_8_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_253 = {1'h0, _requestAIO_T_252}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_254 = _requestAIO_T_253 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_255 = _requestAIO_T_254; // @[Parameters.scala:137:46]
wire _requestAIO_T_256 = _requestAIO_T_255 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_257 = {in_9_a_bits_address[31:17], in_9_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_258 = {1'h0, _requestAIO_T_257}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_259 = _requestAIO_T_258 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_260 = _requestAIO_T_259; // @[Parameters.scala:137:46]
wire _requestAIO_T_261 = _requestAIO_T_260 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_262 = {in_9_a_bits_address[31:28], in_9_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_263 = {1'h0, _requestAIO_T_262}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_264 = _requestAIO_T_263 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_265 = _requestAIO_T_264; // @[Parameters.scala:137:46]
wire _requestAIO_T_266 = _requestAIO_T_265 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_267 = _requestAIO_T_256 | _requestAIO_T_261; // @[Xbar.scala:291:92]
wire _requestAIO_T_268 = _requestAIO_T_267 | _requestAIO_T_266; // @[Xbar.scala:291:92]
wire requestAIO_9_0 = _requestAIO_T_268; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_18 = requestAIO_9_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_269 = {in_9_a_bits_address[31:28], in_9_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_270 = {1'h0, _requestAIO_T_269}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_271 = _requestAIO_T_270 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_272 = _requestAIO_T_271; // @[Parameters.scala:137:46]
wire _requestAIO_T_273 = _requestAIO_T_272 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_274 = in_9_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_275 = {1'h0, _requestAIO_T_274}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_276 = _requestAIO_T_275 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_277 = _requestAIO_T_276; // @[Parameters.scala:137:46]
wire _requestAIO_T_278 = _requestAIO_T_277 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_279 = _requestAIO_T_273 | _requestAIO_T_278; // @[Xbar.scala:291:92]
wire requestAIO_9_1 = _requestAIO_T_279; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_18 = requestAIO_9_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_281 = {1'h0, _requestAIO_T_280}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_282 = _requestAIO_T_281 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_283 = _requestAIO_T_282; // @[Parameters.scala:137:46]
wire _requestAIO_T_284 = _requestAIO_T_283 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_285 = {in_10_a_bits_address[31:17], in_10_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_286 = {1'h0, _requestAIO_T_285}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_287 = _requestAIO_T_286 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_288 = _requestAIO_T_287; // @[Parameters.scala:137:46]
wire _requestAIO_T_289 = _requestAIO_T_288 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_290 = {in_10_a_bits_address[31:28], in_10_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_291 = {1'h0, _requestAIO_T_290}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_292 = _requestAIO_T_291 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_293 = _requestAIO_T_292; // @[Parameters.scala:137:46]
wire _requestAIO_T_294 = _requestAIO_T_293 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_295 = _requestAIO_T_284 | _requestAIO_T_289; // @[Xbar.scala:291:92]
wire _requestAIO_T_296 = _requestAIO_T_295 | _requestAIO_T_294; // @[Xbar.scala:291:92]
wire requestAIO_10_0 = _requestAIO_T_296; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_20 = requestAIO_10_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_297 = {in_10_a_bits_address[31:28], in_10_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_298 = {1'h0, _requestAIO_T_297}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_299 = _requestAIO_T_298 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_300 = _requestAIO_T_299; // @[Parameters.scala:137:46]
wire _requestAIO_T_301 = _requestAIO_T_300 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_302 = in_10_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_303 = {1'h0, _requestAIO_T_302}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_304 = _requestAIO_T_303 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_305 = _requestAIO_T_304; // @[Parameters.scala:137:46]
wire _requestAIO_T_306 = _requestAIO_T_305 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_307 = _requestAIO_T_301 | _requestAIO_T_306; // @[Xbar.scala:291:92]
wire requestAIO_10_1 = _requestAIO_T_307; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_20 = requestAIO_10_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_309 = {1'h0, _requestAIO_T_308}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_310 = _requestAIO_T_309 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_311 = _requestAIO_T_310; // @[Parameters.scala:137:46]
wire _requestAIO_T_312 = _requestAIO_T_311 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_313 = {in_11_a_bits_address[31:17], in_11_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_314 = {1'h0, _requestAIO_T_313}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_315 = _requestAIO_T_314 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_316 = _requestAIO_T_315; // @[Parameters.scala:137:46]
wire _requestAIO_T_317 = _requestAIO_T_316 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_318 = {in_11_a_bits_address[31:28], in_11_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_319 = {1'h0, _requestAIO_T_318}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_320 = _requestAIO_T_319 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_321 = _requestAIO_T_320; // @[Parameters.scala:137:46]
wire _requestAIO_T_322 = _requestAIO_T_321 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_323 = _requestAIO_T_312 | _requestAIO_T_317; // @[Xbar.scala:291:92]
wire _requestAIO_T_324 = _requestAIO_T_323 | _requestAIO_T_322; // @[Xbar.scala:291:92]
wire requestAIO_11_0 = _requestAIO_T_324; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_22 = requestAIO_11_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_325 = {in_11_a_bits_address[31:28], in_11_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_326 = {1'h0, _requestAIO_T_325}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_327 = _requestAIO_T_326 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_328 = _requestAIO_T_327; // @[Parameters.scala:137:46]
wire _requestAIO_T_329 = _requestAIO_T_328 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_330 = in_11_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_331 = {1'h0, _requestAIO_T_330}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_332 = _requestAIO_T_331 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_333 = _requestAIO_T_332; // @[Parameters.scala:137:46]
wire _requestAIO_T_334 = _requestAIO_T_333 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_335 = _requestAIO_T_329 | _requestAIO_T_334; // @[Xbar.scala:291:92]
wire requestAIO_11_1 = _requestAIO_T_335; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_22 = requestAIO_11_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_337 = {1'h0, _requestAIO_T_336}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_338 = _requestAIO_T_337 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_339 = _requestAIO_T_338; // @[Parameters.scala:137:46]
wire _requestAIO_T_340 = _requestAIO_T_339 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_341 = {in_12_a_bits_address[31:17], in_12_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_342 = {1'h0, _requestAIO_T_341}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_343 = _requestAIO_T_342 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_344 = _requestAIO_T_343; // @[Parameters.scala:137:46]
wire _requestAIO_T_345 = _requestAIO_T_344 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_346 = {in_12_a_bits_address[31:28], in_12_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_347 = {1'h0, _requestAIO_T_346}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_348 = _requestAIO_T_347 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_349 = _requestAIO_T_348; // @[Parameters.scala:137:46]
wire _requestAIO_T_350 = _requestAIO_T_349 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_351 = _requestAIO_T_340 | _requestAIO_T_345; // @[Xbar.scala:291:92]
wire _requestAIO_T_352 = _requestAIO_T_351 | _requestAIO_T_350; // @[Xbar.scala:291:92]
wire requestAIO_12_0 = _requestAIO_T_352; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_24 = requestAIO_12_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_353 = {in_12_a_bits_address[31:28], in_12_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_354 = {1'h0, _requestAIO_T_353}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_355 = _requestAIO_T_354 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_356 = _requestAIO_T_355; // @[Parameters.scala:137:46]
wire _requestAIO_T_357 = _requestAIO_T_356 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_358 = in_12_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_359 = {1'h0, _requestAIO_T_358}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_360 = _requestAIO_T_359 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_361 = _requestAIO_T_360; // @[Parameters.scala:137:46]
wire _requestAIO_T_362 = _requestAIO_T_361 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_363 = _requestAIO_T_357 | _requestAIO_T_362; // @[Xbar.scala:291:92]
wire requestAIO_12_1 = _requestAIO_T_363; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_24 = requestAIO_12_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_365 = {1'h0, _requestAIO_T_364}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_366 = _requestAIO_T_365 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_367 = _requestAIO_T_366; // @[Parameters.scala:137:46]
wire _requestAIO_T_368 = _requestAIO_T_367 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_369 = {in_13_a_bits_address[31:17], in_13_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_370 = {1'h0, _requestAIO_T_369}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_371 = _requestAIO_T_370 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_372 = _requestAIO_T_371; // @[Parameters.scala:137:46]
wire _requestAIO_T_373 = _requestAIO_T_372 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_374 = {in_13_a_bits_address[31:28], in_13_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_375 = {1'h0, _requestAIO_T_374}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_376 = _requestAIO_T_375 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_377 = _requestAIO_T_376; // @[Parameters.scala:137:46]
wire _requestAIO_T_378 = _requestAIO_T_377 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_379 = _requestAIO_T_368 | _requestAIO_T_373; // @[Xbar.scala:291:92]
wire _requestAIO_T_380 = _requestAIO_T_379 | _requestAIO_T_378; // @[Xbar.scala:291:92]
wire requestAIO_13_0 = _requestAIO_T_380; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_26 = requestAIO_13_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_381 = {in_13_a_bits_address[31:28], in_13_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_382 = {1'h0, _requestAIO_T_381}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_383 = _requestAIO_T_382 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_384 = _requestAIO_T_383; // @[Parameters.scala:137:46]
wire _requestAIO_T_385 = _requestAIO_T_384 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_386 = in_13_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_387 = {1'h0, _requestAIO_T_386}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_388 = _requestAIO_T_387 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_389 = _requestAIO_T_388; // @[Parameters.scala:137:46]
wire _requestAIO_T_390 = _requestAIO_T_389 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_391 = _requestAIO_T_385 | _requestAIO_T_390; // @[Xbar.scala:291:92]
wire requestAIO_13_1 = _requestAIO_T_391; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_26 = requestAIO_13_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_393 = {1'h0, _requestAIO_T_392}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_394 = _requestAIO_T_393 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_395 = _requestAIO_T_394; // @[Parameters.scala:137:46]
wire _requestAIO_T_396 = _requestAIO_T_395 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_397 = {in_14_a_bits_address[31:17], in_14_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_398 = {1'h0, _requestAIO_T_397}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_399 = _requestAIO_T_398 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_400 = _requestAIO_T_399; // @[Parameters.scala:137:46]
wire _requestAIO_T_401 = _requestAIO_T_400 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_402 = {in_14_a_bits_address[31:28], in_14_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_403 = {1'h0, _requestAIO_T_402}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_404 = _requestAIO_T_403 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_405 = _requestAIO_T_404; // @[Parameters.scala:137:46]
wire _requestAIO_T_406 = _requestAIO_T_405 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_407 = _requestAIO_T_396 | _requestAIO_T_401; // @[Xbar.scala:291:92]
wire _requestAIO_T_408 = _requestAIO_T_407 | _requestAIO_T_406; // @[Xbar.scala:291:92]
wire requestAIO_14_0 = _requestAIO_T_408; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_28 = requestAIO_14_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_409 = {in_14_a_bits_address[31:28], in_14_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_410 = {1'h0, _requestAIO_T_409}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_411 = _requestAIO_T_410 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_412 = _requestAIO_T_411; // @[Parameters.scala:137:46]
wire _requestAIO_T_413 = _requestAIO_T_412 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_414 = in_14_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_415 = {1'h0, _requestAIO_T_414}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_416 = _requestAIO_T_415 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_417 = _requestAIO_T_416; // @[Parameters.scala:137:46]
wire _requestAIO_T_418 = _requestAIO_T_417 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_419 = _requestAIO_T_413 | _requestAIO_T_418; // @[Xbar.scala:291:92]
wire requestAIO_14_1 = _requestAIO_T_419; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_28 = requestAIO_14_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_421 = {1'h0, _requestAIO_T_420}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_422 = _requestAIO_T_421 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_423 = _requestAIO_T_422; // @[Parameters.scala:137:46]
wire _requestAIO_T_424 = _requestAIO_T_423 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_425 = {in_15_a_bits_address[31:17], in_15_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_426 = {1'h0, _requestAIO_T_425}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_427 = _requestAIO_T_426 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_428 = _requestAIO_T_427; // @[Parameters.scala:137:46]
wire _requestAIO_T_429 = _requestAIO_T_428 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_430 = {in_15_a_bits_address[31:28], in_15_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_431 = {1'h0, _requestAIO_T_430}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_432 = _requestAIO_T_431 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_433 = _requestAIO_T_432; // @[Parameters.scala:137:46]
wire _requestAIO_T_434 = _requestAIO_T_433 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_435 = _requestAIO_T_424 | _requestAIO_T_429; // @[Xbar.scala:291:92]
wire _requestAIO_T_436 = _requestAIO_T_435 | _requestAIO_T_434; // @[Xbar.scala:291:92]
wire requestAIO_15_0 = _requestAIO_T_436; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_30 = requestAIO_15_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_437 = {in_15_a_bits_address[31:28], in_15_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_438 = {1'h0, _requestAIO_T_437}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_439 = _requestAIO_T_438 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_440 = _requestAIO_T_439; // @[Parameters.scala:137:46]
wire _requestAIO_T_441 = _requestAIO_T_440 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_442 = in_15_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_443 = {1'h0, _requestAIO_T_442}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_444 = _requestAIO_T_443 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_445 = _requestAIO_T_444; // @[Parameters.scala:137:46]
wire _requestAIO_T_446 = _requestAIO_T_445 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_447 = _requestAIO_T_441 | _requestAIO_T_446; // @[Xbar.scala:291:92]
wire requestAIO_15_1 = _requestAIO_T_447; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_30 = requestAIO_15_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_449 = {1'h0, _requestAIO_T_448}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_450 = _requestAIO_T_449 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_451 = _requestAIO_T_450; // @[Parameters.scala:137:46]
wire _requestAIO_T_452 = _requestAIO_T_451 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_453 = {in_16_a_bits_address[31:17], in_16_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_454 = {1'h0, _requestAIO_T_453}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_455 = _requestAIO_T_454 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_456 = _requestAIO_T_455; // @[Parameters.scala:137:46]
wire _requestAIO_T_457 = _requestAIO_T_456 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_458 = {in_16_a_bits_address[31:28], in_16_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_459 = {1'h0, _requestAIO_T_458}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_460 = _requestAIO_T_459 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_461 = _requestAIO_T_460; // @[Parameters.scala:137:46]
wire _requestAIO_T_462 = _requestAIO_T_461 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_463 = _requestAIO_T_452 | _requestAIO_T_457; // @[Xbar.scala:291:92]
wire _requestAIO_T_464 = _requestAIO_T_463 | _requestAIO_T_462; // @[Xbar.scala:291:92]
wire requestAIO_16_0 = _requestAIO_T_464; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_32 = requestAIO_16_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_465 = {in_16_a_bits_address[31:28], in_16_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_466 = {1'h0, _requestAIO_T_465}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_467 = _requestAIO_T_466 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_468 = _requestAIO_T_467; // @[Parameters.scala:137:46]
wire _requestAIO_T_469 = _requestAIO_T_468 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_470 = in_16_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_471 = {1'h0, _requestAIO_T_470}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_472 = _requestAIO_T_471 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_473 = _requestAIO_T_472; // @[Parameters.scala:137:46]
wire _requestAIO_T_474 = _requestAIO_T_473 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_475 = _requestAIO_T_469 | _requestAIO_T_474; // @[Xbar.scala:291:92]
wire requestAIO_16_1 = _requestAIO_T_475; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_32 = requestAIO_16_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_477 = {1'h0, _requestAIO_T_476}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_478 = _requestAIO_T_477 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_479 = _requestAIO_T_478; // @[Parameters.scala:137:46]
wire _requestAIO_T_480 = _requestAIO_T_479 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_481 = {in_17_a_bits_address[31:17], in_17_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_482 = {1'h0, _requestAIO_T_481}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_483 = _requestAIO_T_482 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_484 = _requestAIO_T_483; // @[Parameters.scala:137:46]
wire _requestAIO_T_485 = _requestAIO_T_484 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_486 = {in_17_a_bits_address[31:28], in_17_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_487 = {1'h0, _requestAIO_T_486}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_488 = _requestAIO_T_487 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_489 = _requestAIO_T_488; // @[Parameters.scala:137:46]
wire _requestAIO_T_490 = _requestAIO_T_489 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_491 = _requestAIO_T_480 | _requestAIO_T_485; // @[Xbar.scala:291:92]
wire _requestAIO_T_492 = _requestAIO_T_491 | _requestAIO_T_490; // @[Xbar.scala:291:92]
wire requestAIO_17_0 = _requestAIO_T_492; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_34 = requestAIO_17_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_493 = {in_17_a_bits_address[31:28], in_17_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_494 = {1'h0, _requestAIO_T_493}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_495 = _requestAIO_T_494 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_496 = _requestAIO_T_495; // @[Parameters.scala:137:46]
wire _requestAIO_T_497 = _requestAIO_T_496 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_498 = in_17_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_499 = {1'h0, _requestAIO_T_498}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_500 = _requestAIO_T_499 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_501 = _requestAIO_T_500; // @[Parameters.scala:137:46]
wire _requestAIO_T_502 = _requestAIO_T_501 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_503 = _requestAIO_T_497 | _requestAIO_T_502; // @[Xbar.scala:291:92]
wire requestAIO_17_1 = _requestAIO_T_503; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_34 = requestAIO_17_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_505 = {1'h0, _requestAIO_T_504}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_506 = _requestAIO_T_505 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_507 = _requestAIO_T_506; // @[Parameters.scala:137:46]
wire _requestAIO_T_508 = _requestAIO_T_507 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_509 = {in_18_a_bits_address[31:17], in_18_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_510 = {1'h0, _requestAIO_T_509}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_511 = _requestAIO_T_510 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_512 = _requestAIO_T_511; // @[Parameters.scala:137:46]
wire _requestAIO_T_513 = _requestAIO_T_512 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_514 = {in_18_a_bits_address[31:28], in_18_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_515 = {1'h0, _requestAIO_T_514}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_516 = _requestAIO_T_515 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_517 = _requestAIO_T_516; // @[Parameters.scala:137:46]
wire _requestAIO_T_518 = _requestAIO_T_517 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_519 = _requestAIO_T_508 | _requestAIO_T_513; // @[Xbar.scala:291:92]
wire _requestAIO_T_520 = _requestAIO_T_519 | _requestAIO_T_518; // @[Xbar.scala:291:92]
wire requestAIO_18_0 = _requestAIO_T_520; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_36 = requestAIO_18_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_521 = {in_18_a_bits_address[31:28], in_18_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_522 = {1'h0, _requestAIO_T_521}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_523 = _requestAIO_T_522 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_524 = _requestAIO_T_523; // @[Parameters.scala:137:46]
wire _requestAIO_T_525 = _requestAIO_T_524 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_526 = in_18_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_527 = {1'h0, _requestAIO_T_526}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_528 = _requestAIO_T_527 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_529 = _requestAIO_T_528; // @[Parameters.scala:137:46]
wire _requestAIO_T_530 = _requestAIO_T_529 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_531 = _requestAIO_T_525 | _requestAIO_T_530; // @[Xbar.scala:291:92]
wire requestAIO_18_1 = _requestAIO_T_531; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_36 = requestAIO_18_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestAIO_T_533 = {1'h0, _requestAIO_T_532}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_534 = _requestAIO_T_533 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_535 = _requestAIO_T_534; // @[Parameters.scala:137:46]
wire _requestAIO_T_536 = _requestAIO_T_535 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_537 = {in_19_a_bits_address[31:17], in_19_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_538 = {1'h0, _requestAIO_T_537}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_539 = _requestAIO_T_538 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_540 = _requestAIO_T_539; // @[Parameters.scala:137:46]
wire _requestAIO_T_541 = _requestAIO_T_540 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_542 = {in_19_a_bits_address[31:28], in_19_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_543 = {1'h0, _requestAIO_T_542}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_544 = _requestAIO_T_543 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_545 = _requestAIO_T_544; // @[Parameters.scala:137:46]
wire _requestAIO_T_546 = _requestAIO_T_545 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_547 = _requestAIO_T_536 | _requestAIO_T_541; // @[Xbar.scala:291:92]
wire _requestAIO_T_548 = _requestAIO_T_547 | _requestAIO_T_546; // @[Xbar.scala:291:92]
wire requestAIO_19_0 = _requestAIO_T_548; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_0_valid_T_38 = requestAIO_19_0; // @[Xbar.scala:307:107, :355:54]
wire [31:0] _requestAIO_T_549 = {in_19_a_bits_address[31:28], in_19_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_550 = {1'h0, _requestAIO_T_549}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_551 = _requestAIO_T_550 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_552 = _requestAIO_T_551; // @[Parameters.scala:137:46]
wire _requestAIO_T_553 = _requestAIO_T_552 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _requestAIO_T_554 = in_19_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18]
wire [32:0] _requestAIO_T_555 = {1'h0, _requestAIO_T_554}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_556 = _requestAIO_T_555 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _requestAIO_T_557 = _requestAIO_T_556; // @[Parameters.scala:137:46]
wire _requestAIO_T_558 = _requestAIO_T_557 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _requestAIO_T_559 = _requestAIO_T_553 | _requestAIO_T_558; // @[Xbar.scala:291:92]
wire requestAIO_19_1 = _requestAIO_T_559; // @[Xbar.scala:291:92, :307:107]
wire _portsAOI_filtered_1_valid_T_38 = requestAIO_19_1; // @[Xbar.scala:307:107, :355:54]
wire [32:0] _requestCIO_T_191 = {1'h0, _requestCIO_T_190}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_196 = {1'h0, _requestCIO_T_195}; // @[Parameters.scala:137:{31,41}]
wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _requestDOI_T = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_15 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_20 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_25 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_30 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_35 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_40 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_55 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_60 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_65 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_70 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_75 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_80 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_85 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_90 = out_0_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = _requestDOI_T == 4'hE; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _requestDOI_T_5 = out_0_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_10 = out_0_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_45 = out_0_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_50 = out_0_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_95 = out_0_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire _requestDOI_T_6 = _requestDOI_T_5 == 7'h7C; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_11 = _requestDOI_T_10 == 7'h7B; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_2 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_16 = _requestDOI_T_15 == 4'hD; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_3 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_3_valid_T = requestDOI_0_3; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_21 = _requestDOI_T_20 == 4'hC; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_23 = _requestDOI_T_21; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_4 = _requestDOI_T_23; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_4_valid_T = requestDOI_0_4; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_26 = _requestDOI_T_25 == 4'hB; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_28 = _requestDOI_T_26; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_5 = _requestDOI_T_28; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_5_valid_T = requestDOI_0_5; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_6 = _requestDOI_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_31 = _requestDOI_T_30 == 4'hA; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_33 = _requestDOI_T_31; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_6 = _requestDOI_T_33; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_6_valid_T = requestDOI_0_6; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_7 = _requestDOI_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_36 = _requestDOI_T_35 == 4'h9; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_38 = _requestDOI_T_36; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_7 = _requestDOI_T_38; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_7_valid_T = requestDOI_0_7; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_8 = _requestDOI_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_41 = _requestDOI_T_40 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_43 = _requestDOI_T_41; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_8 = _requestDOI_T_43; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_8_valid_T = requestDOI_0_8; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_9 = _requestDOI_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_46 = _requestDOI_T_45 == 7'h7A; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_48 = _requestDOI_T_46; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_9 = _requestDOI_T_48; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_9_valid_T = requestDOI_0_9; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_10 = _requestDOI_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_51 = _requestDOI_T_50 == 7'h79; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_53 = _requestDOI_T_51; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_10 = _requestDOI_T_53; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_10_valid_T = requestDOI_0_10; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_11 = _requestDOI_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_56 = _requestDOI_T_55 == 4'h7; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_58 = _requestDOI_T_56; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_11 = _requestDOI_T_58; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_11_valid_T = requestDOI_0_11; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_12 = _requestDOI_uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_61 = _requestDOI_T_60 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_63 = _requestDOI_T_61; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_12 = _requestDOI_T_63; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_12_valid_T = requestDOI_0_12; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_13 = _requestDOI_uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_66 = _requestDOI_T_65 == 4'h5; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_68 = _requestDOI_T_66; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_13 = _requestDOI_T_68; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_13_valid_T = requestDOI_0_13; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_14 = _requestDOI_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_71 = _requestDOI_T_70 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_73 = _requestDOI_T_71; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_14 = _requestDOI_T_73; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_14_valid_T = requestDOI_0_14; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_15 = _requestDOI_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_76 = _requestDOI_T_75 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_78 = _requestDOI_T_76; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_15 = _requestDOI_T_78; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_15_valid_T = requestDOI_0_15; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_16 = _requestDOI_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_81 = _requestDOI_T_80 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_83 = _requestDOI_T_81; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_16 = _requestDOI_T_83; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_16_valid_T = requestDOI_0_16; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_17 = _requestDOI_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_86 = _requestDOI_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_88 = _requestDOI_T_86; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_17 = _requestDOI_T_88; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_17_valid_T = requestDOI_0_17; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_18 = _requestDOI_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_91 = _requestDOI_T_90 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_93 = _requestDOI_T_91; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_18 = _requestDOI_T_93; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_18_valid_T = requestDOI_0_18; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_19 = _requestDOI_uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_96 = _requestDOI_T_95 == 7'h78; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_98 = _requestDOI_T_96; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_19 = _requestDOI_T_98; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_19_valid_T = requestDOI_0_19; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_20 = _requestDOI_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _requestDOI_T_100 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_115 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_120 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_125 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_130 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_135 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_140 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_155 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_160 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_165 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_170 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_175 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_180 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_185 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire [3:0] _requestDOI_T_190 = out_1_d_bits_source[8:5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_101 = _requestDOI_T_100 == 4'hE; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_103 = _requestDOI_T_101; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_0 = _requestDOI_T_103; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_21 = _requestDOI_uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _requestDOI_T_105 = out_1_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_110 = out_1_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_145 = out_1_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_150 = out_1_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire [6:0] _requestDOI_T_195 = out_1_d_bits_source[8:2]; // @[Xbar.scala:216:19]
wire _requestDOI_T_106 = _requestDOI_T_105 == 7'h7C; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_108 = _requestDOI_T_106; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_1 = _requestDOI_T_108; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_22 = _requestDOI_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_111 = _requestDOI_T_110 == 7'h7B; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_113 = _requestDOI_T_111; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_2 = _requestDOI_T_113; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_2_valid_T_2 = requestDOI_1_2; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_23 = _requestDOI_uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_116 = _requestDOI_T_115 == 4'hD; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_118 = _requestDOI_T_116; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_3 = _requestDOI_T_118; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_3_valid_T_2 = requestDOI_1_3; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_24 = _requestDOI_uncommonBits_T_24[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_121 = _requestDOI_T_120 == 4'hC; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_123 = _requestDOI_T_121; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_4 = _requestDOI_T_123; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_4_valid_T_2 = requestDOI_1_4; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_25 = _requestDOI_uncommonBits_T_25[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_126 = _requestDOI_T_125 == 4'hB; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_128 = _requestDOI_T_126; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_5 = _requestDOI_T_128; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_5_valid_T_2 = requestDOI_1_5; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_26 = _requestDOI_uncommonBits_T_26[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_131 = _requestDOI_T_130 == 4'hA; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_133 = _requestDOI_T_131; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_6 = _requestDOI_T_133; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_6_valid_T_2 = requestDOI_1_6; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_27 = _requestDOI_uncommonBits_T_27[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_136 = _requestDOI_T_135 == 4'h9; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_138 = _requestDOI_T_136; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_7 = _requestDOI_T_138; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_7_valid_T_2 = requestDOI_1_7; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_28 = _requestDOI_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_141 = _requestDOI_T_140 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_143 = _requestDOI_T_141; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_8 = _requestDOI_T_143; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_8_valid_T_2 = requestDOI_1_8; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_29 = _requestDOI_uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_146 = _requestDOI_T_145 == 7'h7A; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_148 = _requestDOI_T_146; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_9 = _requestDOI_T_148; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_9_valid_T_2 = requestDOI_1_9; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_30 = _requestDOI_uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_151 = _requestDOI_T_150 == 7'h79; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_153 = _requestDOI_T_151; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_10 = _requestDOI_T_153; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_10_valid_T_2 = requestDOI_1_10; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_31 = _requestDOI_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_156 = _requestDOI_T_155 == 4'h7; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_158 = _requestDOI_T_156; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_11 = _requestDOI_T_158; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_11_valid_T_2 = requestDOI_1_11; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_32 = _requestDOI_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_161 = _requestDOI_T_160 == 4'h6; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_163 = _requestDOI_T_161; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_12 = _requestDOI_T_163; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_12_valid_T_2 = requestDOI_1_12; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_33 = _requestDOI_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_166 = _requestDOI_T_165 == 4'h5; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_168 = _requestDOI_T_166; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_13 = _requestDOI_T_168; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_13_valid_T_2 = requestDOI_1_13; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_34 = _requestDOI_uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_171 = _requestDOI_T_170 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_173 = _requestDOI_T_171; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_14 = _requestDOI_T_173; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_14_valid_T_2 = requestDOI_1_14; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_35 = _requestDOI_uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_176 = _requestDOI_T_175 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_178 = _requestDOI_T_176; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_15 = _requestDOI_T_178; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_15_valid_T_2 = requestDOI_1_15; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_36 = _requestDOI_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_181 = _requestDOI_T_180 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_183 = _requestDOI_T_181; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_16 = _requestDOI_T_183; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_16_valid_T_2 = requestDOI_1_16; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_37 = _requestDOI_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_186 = _requestDOI_T_185 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_188 = _requestDOI_T_186; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_17 = _requestDOI_T_188; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_17_valid_T_2 = requestDOI_1_17; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_38 = _requestDOI_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_191 = _requestDOI_T_190 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_193 = _requestDOI_T_191; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_18 = _requestDOI_T_193; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_18_valid_T_2 = requestDOI_1_18; // @[Xbar.scala:355:54]
wire [1:0] requestDOI_uncommonBits_39 = _requestDOI_uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_196 = _requestDOI_T_195 == 7'h78; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_198 = _requestDOI_T_196; // @[Parameters.scala:54:{32,67}]
wire requestDOI_1_19 = _requestDOI_T_198; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_19_valid_T_2 = requestDOI_1_19; // @[Xbar.scala:355:54]
wire [2:0] requestEIO_uncommonBits_19 = _requestEIO_uncommonBits_T_19; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_6 = 27'hFFF << in_2_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_7 = _beatsAI_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_8 = ~_beatsAI_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_2 = _beatsAI_decode_T_8[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_2 = in_2_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_2 = ~_beatsAI_opdata_T_2; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_2 = beatsAI_opdata_2 ? beatsAI_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_9 = 27'hFFF << in_3_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_10 = _beatsAI_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_11 = ~_beatsAI_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_3 = _beatsAI_decode_T_11[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_3 = in_3_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_3 = ~_beatsAI_opdata_T_3; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_3 = beatsAI_opdata_3 ? beatsAI_decode_3 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_12 = 27'hFFF << in_4_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_13 = _beatsAI_decode_T_12[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_14 = ~_beatsAI_decode_T_13; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_4 = _beatsAI_decode_T_14[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_4 = in_4_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_4 = ~_beatsAI_opdata_T_4; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_4 = beatsAI_opdata_4 ? beatsAI_decode_4 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_15 = 27'hFFF << in_5_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_16 = _beatsAI_decode_T_15[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_17 = ~_beatsAI_decode_T_16; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_5 = _beatsAI_decode_T_17[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_5 = in_5_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_5 = ~_beatsAI_opdata_T_5; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_5 = beatsAI_opdata_5 ? beatsAI_decode_5 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_18 = 27'hFFF << in_6_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_19 = _beatsAI_decode_T_18[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_20 = ~_beatsAI_decode_T_19; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_6 = _beatsAI_decode_T_20[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_6 = in_6_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_6 = ~_beatsAI_opdata_T_6; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_6 = beatsAI_opdata_6 ? beatsAI_decode_6 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_21 = 27'hFFF << in_7_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_22 = _beatsAI_decode_T_21[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_23 = ~_beatsAI_decode_T_22; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_7 = _beatsAI_decode_T_23[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_7 = in_7_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_7 = ~_beatsAI_opdata_T_7; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_7 = beatsAI_opdata_7 ? beatsAI_decode_7 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_24 = 27'hFFF << in_8_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_25 = _beatsAI_decode_T_24[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_26 = ~_beatsAI_decode_T_25; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_8 = _beatsAI_decode_T_26[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_8 = in_8_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_8 = ~_beatsAI_opdata_T_8; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_8 = beatsAI_opdata_8 ? beatsAI_decode_8 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_27 = 27'hFFF << in_9_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_28 = _beatsAI_decode_T_27[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_29 = ~_beatsAI_decode_T_28; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_9 = _beatsAI_decode_T_29[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_9 = in_9_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_9 = ~_beatsAI_opdata_T_9; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_9 = beatsAI_opdata_9 ? beatsAI_decode_9 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_30 = 27'hFFF << in_10_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_31 = _beatsAI_decode_T_30[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_32 = ~_beatsAI_decode_T_31; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_10 = _beatsAI_decode_T_32[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_10 = in_10_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_10 = ~_beatsAI_opdata_T_10; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_10 = beatsAI_opdata_10 ? beatsAI_decode_10 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_33 = 27'hFFF << in_11_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_34 = _beatsAI_decode_T_33[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_35 = ~_beatsAI_decode_T_34; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_11 = _beatsAI_decode_T_35[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_11 = in_11_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_11 = ~_beatsAI_opdata_T_11; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_11 = beatsAI_opdata_11 ? beatsAI_decode_11 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_36 = 27'hFFF << in_12_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_37 = _beatsAI_decode_T_36[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_38 = ~_beatsAI_decode_T_37; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_12 = _beatsAI_decode_T_38[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_12 = in_12_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_12 = ~_beatsAI_opdata_T_12; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_12 = beatsAI_opdata_12 ? beatsAI_decode_12 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_39 = 27'hFFF << in_13_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_40 = _beatsAI_decode_T_39[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_41 = ~_beatsAI_decode_T_40; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_13 = _beatsAI_decode_T_41[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_13 = in_13_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_13 = ~_beatsAI_opdata_T_13; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_13 = beatsAI_opdata_13 ? beatsAI_decode_13 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_42 = 27'hFFF << in_14_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_43 = _beatsAI_decode_T_42[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_44 = ~_beatsAI_decode_T_43; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_14 = _beatsAI_decode_T_44[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_14 = in_14_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_14 = ~_beatsAI_opdata_T_14; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_14 = beatsAI_opdata_14 ? beatsAI_decode_14 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_45 = 27'hFFF << in_15_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_46 = _beatsAI_decode_T_45[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_47 = ~_beatsAI_decode_T_46; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_15 = _beatsAI_decode_T_47[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_15 = in_15_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_15 = ~_beatsAI_opdata_T_15; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_15 = beatsAI_opdata_15 ? beatsAI_decode_15 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_48 = 27'hFFF << in_16_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_49 = _beatsAI_decode_T_48[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_50 = ~_beatsAI_decode_T_49; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_16 = _beatsAI_decode_T_50[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_16 = in_16_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_16 = ~_beatsAI_opdata_T_16; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_16 = beatsAI_opdata_16 ? beatsAI_decode_16 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_51 = 27'hFFF << in_17_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_52 = _beatsAI_decode_T_51[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_53 = ~_beatsAI_decode_T_52; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_17 = _beatsAI_decode_T_53[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_17 = in_17_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_17 = ~_beatsAI_opdata_T_17; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_17 = beatsAI_opdata_17 ? beatsAI_decode_17 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_54 = 27'hFFF << in_18_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_55 = _beatsAI_decode_T_54[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_56 = ~_beatsAI_decode_T_55; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_18 = _beatsAI_decode_T_56[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_18 = in_18_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_18 = ~_beatsAI_opdata_T_18; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_18 = beatsAI_opdata_18 ? beatsAI_decode_18 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_57 = 27'hFFF << in_19_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_58 = _beatsAI_decode_T_57[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_59 = ~_beatsAI_decode_T_58; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_19 = _beatsAI_decode_T_59[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_19 = in_19_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_19 = ~_beatsAI_opdata_T_19; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_19 = beatsAI_opdata_19 ? beatsAI_decode_19 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsCI_decode_T_57 = 27'hFFF << in_19_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_58 = _beatsCI_decode_T_57[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_59 = ~_beatsCI_decode_T_58; // @[package.scala:243:{46,76}]
wire [8:0] beatsCI_decode_19 = _beatsCI_decode_T_59[11:3]; // @[package.scala:243:46]
wire beatsCI_opdata_19 = in_19_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [8:0] beatsCI_19 = beatsCI_opdata_19 ? beatsCI_decode_19 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71]
wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46]
wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73]
assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T | _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73]
assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:355:40]
wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_5 = in_2_a_valid & _portsAOI_filtered_0_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_5 = in_2_a_valid & _portsAOI_filtered_1_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_2_1_valid = _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_2_a_ready_T = requestAIO_2_0 & portsAOI_filtered_2_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_2_a_ready_T_1 = requestAIO_2_1 & portsAOI_filtered_2_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_2_a_ready_T_2 = _portsAOI_in_2_a_ready_T | _portsAOI_in_2_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_2_a_ready_WIRE = _portsAOI_in_2_a_ready_T_2; // @[Mux.scala:30:73]
assign in_2_a_ready = _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:355:40]
wire portsAOI_filtered_3_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_3_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_7 = in_3_a_valid & _portsAOI_filtered_0_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_3_0_valid = _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_7 = in_3_a_valid & _portsAOI_filtered_1_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_3_1_valid = _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_3_a_ready_T = requestAIO_3_0 & portsAOI_filtered_3_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_3_a_ready_T_1 = requestAIO_3_1 & portsAOI_filtered_3_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_3_a_ready_T_2 = _portsAOI_in_3_a_ready_T | _portsAOI_in_3_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_3_a_ready_WIRE = _portsAOI_in_3_a_ready_T_2; // @[Mux.scala:30:73]
assign in_3_a_ready = _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_4; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:355:40]
wire portsAOI_filtered_4_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_4_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_9 = in_4_a_valid & _portsAOI_filtered_0_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_4_0_valid = _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_9 = in_4_a_valid & _portsAOI_filtered_1_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_4_1_valid = _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_4_a_ready_T = requestAIO_4_0 & portsAOI_filtered_4_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_4_a_ready_T_1 = requestAIO_4_1 & portsAOI_filtered_4_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_4_a_ready_T_2 = _portsAOI_in_4_a_ready_T | _portsAOI_in_4_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_4_a_ready_WIRE = _portsAOI_in_4_a_ready_T_2; // @[Mux.scala:30:73]
assign in_4_a_ready = _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_5; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_11; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_5; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_11; // @[Xbar.scala:355:40]
wire portsAOI_filtered_5_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_5_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_5_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_5_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_11 = in_5_a_valid & _portsAOI_filtered_0_valid_T_10; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_5_0_valid = _portsAOI_filtered_0_valid_T_11; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_11 = in_5_a_valid & _portsAOI_filtered_1_valid_T_10; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_5_1_valid = _portsAOI_filtered_1_valid_T_11; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_5_a_ready_T = requestAIO_5_0 & portsAOI_filtered_5_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_5_a_ready_T_1 = requestAIO_5_1 & portsAOI_filtered_5_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_5_a_ready_T_2 = _portsAOI_in_5_a_ready_T | _portsAOI_in_5_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_5_a_ready_WIRE = _portsAOI_in_5_a_ready_T_2; // @[Mux.scala:30:73]
assign in_5_a_ready = _portsAOI_in_5_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_6; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_13; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_6; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_13; // @[Xbar.scala:355:40]
wire portsAOI_filtered_6_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_6_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_6_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_6_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_13 = in_6_a_valid & _portsAOI_filtered_0_valid_T_12; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_6_0_valid = _portsAOI_filtered_0_valid_T_13; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_13 = in_6_a_valid & _portsAOI_filtered_1_valid_T_12; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_6_1_valid = _portsAOI_filtered_1_valid_T_13; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_6_a_ready_T = requestAIO_6_0 & portsAOI_filtered_6_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_6_a_ready_T_1 = requestAIO_6_1 & portsAOI_filtered_6_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_6_a_ready_T_2 = _portsAOI_in_6_a_ready_T | _portsAOI_in_6_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_6_a_ready_WIRE = _portsAOI_in_6_a_ready_T_2; // @[Mux.scala:30:73]
assign in_6_a_ready = _portsAOI_in_6_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_7; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_15; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_7; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_15; // @[Xbar.scala:355:40]
wire portsAOI_filtered_7_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_7_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_7_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_7_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_15 = in_7_a_valid & _portsAOI_filtered_0_valid_T_14; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_7_0_valid = _portsAOI_filtered_0_valid_T_15; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_15 = in_7_a_valid & _portsAOI_filtered_1_valid_T_14; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_7_1_valid = _portsAOI_filtered_1_valid_T_15; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_7_a_ready_T = requestAIO_7_0 & portsAOI_filtered_7_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_7_a_ready_T_1 = requestAIO_7_1 & portsAOI_filtered_7_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_7_a_ready_T_2 = _portsAOI_in_7_a_ready_T | _portsAOI_in_7_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_7_a_ready_WIRE = _portsAOI_in_7_a_ready_T_2; // @[Mux.scala:30:73]
assign in_7_a_ready = _portsAOI_in_7_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_8; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_17; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_8; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_17; // @[Xbar.scala:355:40]
wire portsAOI_filtered_8_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_8_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_8_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_8_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_17 = in_8_a_valid & _portsAOI_filtered_0_valid_T_16; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_8_0_valid = _portsAOI_filtered_0_valid_T_17; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_17 = in_8_a_valid & _portsAOI_filtered_1_valid_T_16; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_8_1_valid = _portsAOI_filtered_1_valid_T_17; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_8_a_ready_T = requestAIO_8_0 & portsAOI_filtered_8_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_8_a_ready_T_1 = requestAIO_8_1 & portsAOI_filtered_8_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_8_a_ready_T_2 = _portsAOI_in_8_a_ready_T | _portsAOI_in_8_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_8_a_ready_WIRE = _portsAOI_in_8_a_ready_T_2; // @[Mux.scala:30:73]
assign in_8_a_ready = _portsAOI_in_8_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_9; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_19; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_9; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_19; // @[Xbar.scala:355:40]
wire portsAOI_filtered_9_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_9_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_9_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_9_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_19 = in_9_a_valid & _portsAOI_filtered_0_valid_T_18; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_9_0_valid = _portsAOI_filtered_0_valid_T_19; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_19 = in_9_a_valid & _portsAOI_filtered_1_valid_T_18; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_9_1_valid = _portsAOI_filtered_1_valid_T_19; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_9_a_ready_T = requestAIO_9_0 & portsAOI_filtered_9_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_9_a_ready_T_1 = requestAIO_9_1 & portsAOI_filtered_9_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_9_a_ready_T_2 = _portsAOI_in_9_a_ready_T | _portsAOI_in_9_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_9_a_ready_WIRE = _portsAOI_in_9_a_ready_T_2; // @[Mux.scala:30:73]
assign in_9_a_ready = _portsAOI_in_9_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_10; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_21; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_10; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_21; // @[Xbar.scala:355:40]
wire portsAOI_filtered_10_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_10_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_10_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_10_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_21 = in_10_a_valid & _portsAOI_filtered_0_valid_T_20; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_10_0_valid = _portsAOI_filtered_0_valid_T_21; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_21 = in_10_a_valid & _portsAOI_filtered_1_valid_T_20; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_10_1_valid = _portsAOI_filtered_1_valid_T_21; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_10_a_ready_T = requestAIO_10_0 & portsAOI_filtered_10_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_10_a_ready_T_1 = requestAIO_10_1 & portsAOI_filtered_10_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_10_a_ready_T_2 = _portsAOI_in_10_a_ready_T | _portsAOI_in_10_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_10_a_ready_WIRE = _portsAOI_in_10_a_ready_T_2; // @[Mux.scala:30:73]
assign in_10_a_ready = _portsAOI_in_10_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_11; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_23; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_11; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_23; // @[Xbar.scala:355:40]
wire portsAOI_filtered_11_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_11_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_11_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_11_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_23 = in_11_a_valid & _portsAOI_filtered_0_valid_T_22; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_11_0_valid = _portsAOI_filtered_0_valid_T_23; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_23 = in_11_a_valid & _portsAOI_filtered_1_valid_T_22; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_11_1_valid = _portsAOI_filtered_1_valid_T_23; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_11_a_ready_T = requestAIO_11_0 & portsAOI_filtered_11_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_11_a_ready_T_1 = requestAIO_11_1 & portsAOI_filtered_11_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_11_a_ready_T_2 = _portsAOI_in_11_a_ready_T | _portsAOI_in_11_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_11_a_ready_WIRE = _portsAOI_in_11_a_ready_T_2; // @[Mux.scala:30:73]
assign in_11_a_ready = _portsAOI_in_11_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_12; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_25; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_12; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_25; // @[Xbar.scala:355:40]
wire portsAOI_filtered_12_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_12_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_12_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_12_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_25 = in_12_a_valid & _portsAOI_filtered_0_valid_T_24; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_12_0_valid = _portsAOI_filtered_0_valid_T_25; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_25 = in_12_a_valid & _portsAOI_filtered_1_valid_T_24; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_12_1_valid = _portsAOI_filtered_1_valid_T_25; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_12_a_ready_T = requestAIO_12_0 & portsAOI_filtered_12_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_12_a_ready_T_1 = requestAIO_12_1 & portsAOI_filtered_12_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_12_a_ready_T_2 = _portsAOI_in_12_a_ready_T | _portsAOI_in_12_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_12_a_ready_WIRE = _portsAOI_in_12_a_ready_T_2; // @[Mux.scala:30:73]
assign in_12_a_ready = _portsAOI_in_12_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_13; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_27; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_13; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_27; // @[Xbar.scala:355:40]
wire portsAOI_filtered_13_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_13_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_13_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_13_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_27 = in_13_a_valid & _portsAOI_filtered_0_valid_T_26; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_13_0_valid = _portsAOI_filtered_0_valid_T_27; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_27 = in_13_a_valid & _portsAOI_filtered_1_valid_T_26; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_13_1_valid = _portsAOI_filtered_1_valid_T_27; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_13_a_ready_T = requestAIO_13_0 & portsAOI_filtered_13_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_13_a_ready_T_1 = requestAIO_13_1 & portsAOI_filtered_13_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_13_a_ready_T_2 = _portsAOI_in_13_a_ready_T | _portsAOI_in_13_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_13_a_ready_WIRE = _portsAOI_in_13_a_ready_T_2; // @[Mux.scala:30:73]
assign in_13_a_ready = _portsAOI_in_13_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_14; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_29; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_14; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_29; // @[Xbar.scala:355:40]
wire portsAOI_filtered_14_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_14_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_14_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_14_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_29 = in_14_a_valid & _portsAOI_filtered_0_valid_T_28; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_14_0_valid = _portsAOI_filtered_0_valid_T_29; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_29 = in_14_a_valid & _portsAOI_filtered_1_valid_T_28; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_14_1_valid = _portsAOI_filtered_1_valid_T_29; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_14_a_ready_T = requestAIO_14_0 & portsAOI_filtered_14_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_14_a_ready_T_1 = requestAIO_14_1 & portsAOI_filtered_14_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_14_a_ready_T_2 = _portsAOI_in_14_a_ready_T | _portsAOI_in_14_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_14_a_ready_WIRE = _portsAOI_in_14_a_ready_T_2; // @[Mux.scala:30:73]
assign in_14_a_ready = _portsAOI_in_14_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_15; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_31; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_15; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_31; // @[Xbar.scala:355:40]
wire portsAOI_filtered_15_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_15_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_15_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_15_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_31 = in_15_a_valid & _portsAOI_filtered_0_valid_T_30; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_15_0_valid = _portsAOI_filtered_0_valid_T_31; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_31 = in_15_a_valid & _portsAOI_filtered_1_valid_T_30; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_15_1_valid = _portsAOI_filtered_1_valid_T_31; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_15_a_ready_T = requestAIO_15_0 & portsAOI_filtered_15_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_15_a_ready_T_1 = requestAIO_15_1 & portsAOI_filtered_15_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_15_a_ready_T_2 = _portsAOI_in_15_a_ready_T | _portsAOI_in_15_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_15_a_ready_WIRE = _portsAOI_in_15_a_ready_T_2; // @[Mux.scala:30:73]
assign in_15_a_ready = _portsAOI_in_15_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_16; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_33; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_16; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_33; // @[Xbar.scala:355:40]
wire portsAOI_filtered_16_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_16_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_16_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_16_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_33 = in_16_a_valid & _portsAOI_filtered_0_valid_T_32; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_16_0_valid = _portsAOI_filtered_0_valid_T_33; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_33 = in_16_a_valid & _portsAOI_filtered_1_valid_T_32; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_16_1_valid = _portsAOI_filtered_1_valid_T_33; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_16_a_ready_T = requestAIO_16_0 & portsAOI_filtered_16_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_16_a_ready_T_1 = requestAIO_16_1 & portsAOI_filtered_16_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_16_a_ready_T_2 = _portsAOI_in_16_a_ready_T | _portsAOI_in_16_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_16_a_ready_WIRE = _portsAOI_in_16_a_ready_T_2; // @[Mux.scala:30:73]
assign in_16_a_ready = _portsAOI_in_16_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_17; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_35; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_17; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_35; // @[Xbar.scala:355:40]
wire portsAOI_filtered_17_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_17_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_17_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_17_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_35 = in_17_a_valid & _portsAOI_filtered_0_valid_T_34; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_17_0_valid = _portsAOI_filtered_0_valid_T_35; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_35 = in_17_a_valid & _portsAOI_filtered_1_valid_T_34; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_17_1_valid = _portsAOI_filtered_1_valid_T_35; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_17_a_ready_T = requestAIO_17_0 & portsAOI_filtered_17_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_17_a_ready_T_1 = requestAIO_17_1 & portsAOI_filtered_17_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_17_a_ready_T_2 = _portsAOI_in_17_a_ready_T | _portsAOI_in_17_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_17_a_ready_WIRE = _portsAOI_in_17_a_ready_T_2; // @[Mux.scala:30:73]
assign in_17_a_ready = _portsAOI_in_17_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_18; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_37; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_18; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_37; // @[Xbar.scala:355:40]
wire portsAOI_filtered_18_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_18_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_18_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_18_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_37 = in_18_a_valid & _portsAOI_filtered_0_valid_T_36; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_18_0_valid = _portsAOI_filtered_0_valid_T_37; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_37 = in_18_a_valid & _portsAOI_filtered_1_valid_T_36; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_18_1_valid = _portsAOI_filtered_1_valid_T_37; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_18_a_ready_T = requestAIO_18_0 & portsAOI_filtered_18_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_18_a_ready_T_1 = requestAIO_18_1 & portsAOI_filtered_18_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_18_a_ready_T_2 = _portsAOI_in_18_a_ready_T | _portsAOI_in_18_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_18_a_ready_WIRE = _portsAOI_in_18_a_ready_T_2; // @[Mux.scala:30:73]
assign in_18_a_ready = _portsAOI_in_18_a_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_19; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_0_valid_T_39; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_19; // @[Arbiter.scala:94:31]
wire _portsAOI_filtered_1_valid_T_39; // @[Xbar.scala:355:40]
wire portsAOI_filtered_19_0_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_19_0_valid; // @[Xbar.scala:352:24]
wire portsAOI_filtered_19_1_ready; // @[Xbar.scala:352:24]
wire portsAOI_filtered_19_1_valid; // @[Xbar.scala:352:24]
assign _portsAOI_filtered_0_valid_T_39 = in_19_a_valid & _portsAOI_filtered_0_valid_T_38; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_19_0_valid = _portsAOI_filtered_0_valid_T_39; // @[Xbar.scala:352:24, :355:40]
assign _portsAOI_filtered_1_valid_T_39 = in_19_a_valid & _portsAOI_filtered_1_valid_T_38; // @[Xbar.scala:159:18, :355:{40,54}]
assign portsAOI_filtered_19_1_valid = _portsAOI_filtered_1_valid_T_39; // @[Xbar.scala:352:24, :355:40]
wire _portsAOI_in_19_a_ready_T = requestAIO_19_0 & portsAOI_filtered_19_0_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_19_a_ready_T_1 = requestAIO_19_1 & portsAOI_filtered_19_1_ready; // @[Mux.scala:30:73]
wire _portsAOI_in_19_a_ready_T_2 = _portsAOI_in_19_a_ready_T | _portsAOI_in_19_a_ready_T_1; // @[Mux.scala:30:73]
assign _portsAOI_in_19_a_ready_WIRE = _portsAOI_in_19_a_ready_T_2; // @[Mux.scala:30:73]
assign in_19_a_ready = _portsAOI_in_19_a_ready_WIRE; // @[Mux.scala:30:73]
wire _portsBIO_out_1_b_ready_T_19 = portsBIO_filtered_1_19_ready; // @[Mux.scala:30:73]
assign in_19_b_valid = portsBIO_filtered_1_19_valid; // @[Xbar.scala:159:18, :352:24]
assign in_19_b_bits_param = portsBIO_filtered_1_19_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_19_b_bits_address = portsBIO_filtered_1_19_bits_address; // @[Xbar.scala:159:18, :352:24]
assign portsBIO_filtered_1_19_valid = _portsBIO_filtered_19_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_1_b_ready_T_38 = _portsBIO_out_1_b_ready_T_19; // @[Mux.scala:30:73]
assign _portsBIO_out_1_b_ready_WIRE = _portsBIO_out_1_b_ready_T_38; // @[Mux.scala:30:73]
assign out_1_b_ready = _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73]
wire _portsCOI_in_19_c_ready_T_1 = portsCOI_filtered_19_1_ready; // @[Mux.scala:30:73]
assign out_1_c_valid = portsCOI_filtered_19_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_opcode = portsCOI_filtered_19_1_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_param = portsCOI_filtered_19_1_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_size = portsCOI_filtered_19_1_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_source = portsCOI_filtered_19_1_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_address = portsCOI_filtered_19_1_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_data = portsCOI_filtered_19_1_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_1_c_bits_corrupt = portsCOI_filtered_19_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_19_0_valid; // @[Xbar.scala:352:24]
assign portsCOI_filtered_19_0_valid = _portsCOI_filtered_0_valid_T_39; // @[Xbar.scala:352:24, :355:40]
assign portsCOI_filtered_19_1_valid = _portsCOI_filtered_1_valid_T_39; // @[Xbar.scala:352:24, :355:40]
wire _portsCOI_in_19_c_ready_T_2 = _portsCOI_in_19_c_ready_T_1; // @[Mux.scala:30:73]
assign _portsCOI_in_19_c_ready_WIRE = _portsCOI_in_19_c_ready_T_2; // @[Mux.scala:30:73]
assign in_19_c_ready = _portsCOI_in_19_c_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_20; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_20; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_2_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_3_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_4_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_5_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_5_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_6_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_6_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_7_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_7_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_8_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_8_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_9_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_9_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_10_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_10_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_11_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_11_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_12_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_12_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_13_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_13_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_14_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_14_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_15_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_15_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_16_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_16_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_17_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_17_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_18_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_18_valid_T_1; // @[Xbar.scala:355:40]
wire _filtered_19_ready_T; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_19_valid_T_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_2_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_3_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_3_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_4_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_4_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_5_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_5_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_6_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_6_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_7_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_7_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_8_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_8_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_9_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_9_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_10_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_10_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_11_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_11_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_12_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_12_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_13_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_13_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_14_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_14_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_15_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_15_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_16_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_16_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_17_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_17_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_18_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_18_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_19_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_19_valid; // @[Xbar.scala:352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_3_valid_T_1 = out_0_d_valid & _portsDIO_filtered_3_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_3_valid = _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_4_valid_T_1 = out_0_d_valid & _portsDIO_filtered_4_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_4_valid = _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_5_valid_T_1 = out_0_d_valid & _portsDIO_filtered_5_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_5_valid = _portsDIO_filtered_5_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_6_valid_T_1 = out_0_d_valid & _portsDIO_filtered_6_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_6_valid = _portsDIO_filtered_6_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_7_valid_T_1 = out_0_d_valid & _portsDIO_filtered_7_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_7_valid = _portsDIO_filtered_7_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_8_valid_T_1 = out_0_d_valid & _portsDIO_filtered_8_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_8_valid = _portsDIO_filtered_8_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_9_valid_T_1 = out_0_d_valid & _portsDIO_filtered_9_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_9_valid = _portsDIO_filtered_9_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_10_valid_T_1 = out_0_d_valid & _portsDIO_filtered_10_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_10_valid = _portsDIO_filtered_10_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_11_valid_T_1 = out_0_d_valid & _portsDIO_filtered_11_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_11_valid = _portsDIO_filtered_11_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_12_valid_T_1 = out_0_d_valid & _portsDIO_filtered_12_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_12_valid = _portsDIO_filtered_12_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_13_valid_T_1 = out_0_d_valid & _portsDIO_filtered_13_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_13_valid = _portsDIO_filtered_13_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_14_valid_T_1 = out_0_d_valid & _portsDIO_filtered_14_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_14_valid = _portsDIO_filtered_14_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_15_valid_T_1 = out_0_d_valid & _portsDIO_filtered_15_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_15_valid = _portsDIO_filtered_15_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_16_valid_T_1 = out_0_d_valid & _portsDIO_filtered_16_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_16_valid = _portsDIO_filtered_16_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_17_valid_T_1 = out_0_d_valid & _portsDIO_filtered_17_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_17_valid = _portsDIO_filtered_17_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_18_valid_T_1 = out_0_d_valid & _portsDIO_filtered_18_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_18_valid = _portsDIO_filtered_18_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_19_valid_T_1 = out_0_d_valid & _portsDIO_filtered_19_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_19_valid = _portsDIO_filtered_19_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2 & portsDIO_filtered_2_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_3 = requestDOI_0_3 & portsDIO_filtered_3_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_4 = requestDOI_0_4 & portsDIO_filtered_4_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_5 = requestDOI_0_5 & portsDIO_filtered_5_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_6 = requestDOI_0_6 & portsDIO_filtered_6_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_7 = requestDOI_0_7 & portsDIO_filtered_7_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_8 = requestDOI_0_8 & portsDIO_filtered_8_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_9 = requestDOI_0_9 & portsDIO_filtered_9_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_10 = requestDOI_0_10 & portsDIO_filtered_10_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_11 = requestDOI_0_11 & portsDIO_filtered_11_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_12 = requestDOI_0_12 & portsDIO_filtered_12_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_13 = requestDOI_0_13 & portsDIO_filtered_13_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_14 = requestDOI_0_14 & portsDIO_filtered_14_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_15 = requestDOI_0_15 & portsDIO_filtered_15_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_16 = requestDOI_0_16 & portsDIO_filtered_16_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_17 = requestDOI_0_17 & portsDIO_filtered_17_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_18 = requestDOI_0_18 & portsDIO_filtered_18_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_19 = requestDOI_0_19 & portsDIO_filtered_19_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_20 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_21 = _portsDIO_out_0_d_ready_T_20 | _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_22 = _portsDIO_out_0_d_ready_T_21 | _portsDIO_out_0_d_ready_T_3; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_23 = _portsDIO_out_0_d_ready_T_22 | _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_24 = _portsDIO_out_0_d_ready_T_23 | _portsDIO_out_0_d_ready_T_5; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_25 = _portsDIO_out_0_d_ready_T_24 | _portsDIO_out_0_d_ready_T_6; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_26 = _portsDIO_out_0_d_ready_T_25 | _portsDIO_out_0_d_ready_T_7; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_27 = _portsDIO_out_0_d_ready_T_26 | _portsDIO_out_0_d_ready_T_8; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_28 = _portsDIO_out_0_d_ready_T_27 | _portsDIO_out_0_d_ready_T_9; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_29 = _portsDIO_out_0_d_ready_T_28 | _portsDIO_out_0_d_ready_T_10; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_30 = _portsDIO_out_0_d_ready_T_29 | _portsDIO_out_0_d_ready_T_11; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_31 = _portsDIO_out_0_d_ready_T_30 | _portsDIO_out_0_d_ready_T_12; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_32 = _portsDIO_out_0_d_ready_T_31 | _portsDIO_out_0_d_ready_T_13; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_33 = _portsDIO_out_0_d_ready_T_32 | _portsDIO_out_0_d_ready_T_14; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_34 = _portsDIO_out_0_d_ready_T_33 | _portsDIO_out_0_d_ready_T_15; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_35 = _portsDIO_out_0_d_ready_T_34 | _portsDIO_out_0_d_ready_T_16; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_36 = _portsDIO_out_0_d_ready_T_35 | _portsDIO_out_0_d_ready_T_17; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_37 = _portsDIO_out_0_d_ready_T_36 | _portsDIO_out_0_d_ready_T_18; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_38 = _portsDIO_out_0_d_ready_T_37 | _portsDIO_out_0_d_ready_T_19; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_38; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
wire _filtered_0_ready_T_21; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_1_ready_T_21; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_2_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_3_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_4_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_5_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_5_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_6_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_6_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_7_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_7_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_8_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_8_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_9_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_9_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_10_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_10_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_11_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_11_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_12_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_12_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_13_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_13_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_14_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_14_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_15_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_15_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_16_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_16_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_17_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_17_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_18_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_18_valid_T_3; // @[Xbar.scala:355:40]
wire _filtered_19_ready_T_1; // @[Arbiter.scala:94:31]
wire _portsDIO_filtered_19_valid_T_3; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_2_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_3_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_4_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_5_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_5_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_6_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_6_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_7_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_7_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_8_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_8_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_9_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_9_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_10_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_10_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_11_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_11_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_12_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_12_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_13_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_13_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_14_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_14_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_15_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_15_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_16_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_16_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_17_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_17_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_18_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_18_valid; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_19_ready; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_19_valid; // @[Xbar.scala:352:24]
assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_2_valid_T_3 = out_1_d_valid & _portsDIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_2_valid = _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_3_valid_T_3 = out_1_d_valid & _portsDIO_filtered_3_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_3_valid = _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_4_valid_T_3 = out_1_d_valid & _portsDIO_filtered_4_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_4_valid = _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_5_valid_T_3 = out_1_d_valid & _portsDIO_filtered_5_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_5_valid = _portsDIO_filtered_5_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_6_valid_T_3 = out_1_d_valid & _portsDIO_filtered_6_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_6_valid = _portsDIO_filtered_6_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_7_valid_T_3 = out_1_d_valid & _portsDIO_filtered_7_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_7_valid = _portsDIO_filtered_7_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_8_valid_T_3 = out_1_d_valid & _portsDIO_filtered_8_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_8_valid = _portsDIO_filtered_8_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_9_valid_T_3 = out_1_d_valid & _portsDIO_filtered_9_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_9_valid = _portsDIO_filtered_9_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_10_valid_T_3 = out_1_d_valid & _portsDIO_filtered_10_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_10_valid = _portsDIO_filtered_10_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_11_valid_T_3 = out_1_d_valid & _portsDIO_filtered_11_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_11_valid = _portsDIO_filtered_11_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_12_valid_T_3 = out_1_d_valid & _portsDIO_filtered_12_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_12_valid = _portsDIO_filtered_12_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_13_valid_T_3 = out_1_d_valid & _portsDIO_filtered_13_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_13_valid = _portsDIO_filtered_13_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_14_valid_T_3 = out_1_d_valid & _portsDIO_filtered_14_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_14_valid = _portsDIO_filtered_14_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_15_valid_T_3 = out_1_d_valid & _portsDIO_filtered_15_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_15_valid = _portsDIO_filtered_15_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_16_valid_T_3 = out_1_d_valid & _portsDIO_filtered_16_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_16_valid = _portsDIO_filtered_16_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_17_valid_T_3 = out_1_d_valid & _portsDIO_filtered_17_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_17_valid = _portsDIO_filtered_17_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_18_valid_T_3 = out_1_d_valid & _portsDIO_filtered_18_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_18_valid = _portsDIO_filtered_18_valid_T_3; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_19_valid_T_3 = out_1_d_valid & _portsDIO_filtered_19_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_19_valid = _portsDIO_filtered_19_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_2 = requestDOI_1_2 & portsDIO_filtered_1_2_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_3 = requestDOI_1_3 & portsDIO_filtered_1_3_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_4 = requestDOI_1_4 & portsDIO_filtered_1_4_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_5 = requestDOI_1_5 & portsDIO_filtered_1_5_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_6 = requestDOI_1_6 & portsDIO_filtered_1_6_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_7 = requestDOI_1_7 & portsDIO_filtered_1_7_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_8 = requestDOI_1_8 & portsDIO_filtered_1_8_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_9 = requestDOI_1_9 & portsDIO_filtered_1_9_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_10 = requestDOI_1_10 & portsDIO_filtered_1_10_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_11 = requestDOI_1_11 & portsDIO_filtered_1_11_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_12 = requestDOI_1_12 & portsDIO_filtered_1_12_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_13 = requestDOI_1_13 & portsDIO_filtered_1_13_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_14 = requestDOI_1_14 & portsDIO_filtered_1_14_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_15 = requestDOI_1_15 & portsDIO_filtered_1_15_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_16 = requestDOI_1_16 & portsDIO_filtered_1_16_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_17 = requestDOI_1_17 & portsDIO_filtered_1_17_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_18 = requestDOI_1_18 & portsDIO_filtered_1_18_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_19 = requestDOI_1_19 & portsDIO_filtered_1_19_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_20 = _portsDIO_out_1_d_ready_T | _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_21 = _portsDIO_out_1_d_ready_T_20 | _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_22 = _portsDIO_out_1_d_ready_T_21 | _portsDIO_out_1_d_ready_T_3; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_23 = _portsDIO_out_1_d_ready_T_22 | _portsDIO_out_1_d_ready_T_4; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_24 = _portsDIO_out_1_d_ready_T_23 | _portsDIO_out_1_d_ready_T_5; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_25 = _portsDIO_out_1_d_ready_T_24 | _portsDIO_out_1_d_ready_T_6; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_26 = _portsDIO_out_1_d_ready_T_25 | _portsDIO_out_1_d_ready_T_7; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_27 = _portsDIO_out_1_d_ready_T_26 | _portsDIO_out_1_d_ready_T_8; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_28 = _portsDIO_out_1_d_ready_T_27 | _portsDIO_out_1_d_ready_T_9; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_29 = _portsDIO_out_1_d_ready_T_28 | _portsDIO_out_1_d_ready_T_10; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_30 = _portsDIO_out_1_d_ready_T_29 | _portsDIO_out_1_d_ready_T_11; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_31 = _portsDIO_out_1_d_ready_T_30 | _portsDIO_out_1_d_ready_T_12; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_32 = _portsDIO_out_1_d_ready_T_31 | _portsDIO_out_1_d_ready_T_13; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_33 = _portsDIO_out_1_d_ready_T_32 | _portsDIO_out_1_d_ready_T_14; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_34 = _portsDIO_out_1_d_ready_T_33 | _portsDIO_out_1_d_ready_T_15; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_35 = _portsDIO_out_1_d_ready_T_34 | _portsDIO_out_1_d_ready_T_16; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_36 = _portsDIO_out_1_d_ready_T_35 | _portsDIO_out_1_d_ready_T_17; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_37 = _portsDIO_out_1_d_ready_T_36 | _portsDIO_out_1_d_ready_T_18; // @[Mux.scala:30:73]
wire _portsDIO_out_1_d_ready_T_38 = _portsDIO_out_1_d_ready_T_37 | _portsDIO_out_1_d_ready_T_19; // @[Mux.scala:30:73]
assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_38; // @[Mux.scala:30:73]
assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73]
assign out_1_e_valid = portsEOI_filtered_19_1_valid; // @[Xbar.scala:216:19, :352:24]
assign out_1_e_bits_sink = portsEOI_filtered_19_1_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_19_1_valid = _portsEOI_filtered_1_valid_T_39; // @[Xbar.scala:352:24, :355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] readys_lo_lo_lo = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_lo_lo_hi_hi = {portsAOI_filtered_4_0_valid, portsAOI_filtered_3_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_lo_lo_hi = {readys_lo_lo_hi_hi, portsAOI_filtered_2_0_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_lo_lo = {readys_lo_lo_hi, readys_lo_lo_lo}; // @[Arbiter.scala:68:51]
wire [1:0] readys_lo_hi_lo = {portsAOI_filtered_6_0_valid, portsAOI_filtered_5_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_lo_hi_hi_hi = {portsAOI_filtered_9_0_valid, portsAOI_filtered_8_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_lo_hi_hi = {readys_lo_hi_hi_hi, portsAOI_filtered_7_0_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_lo_hi = {readys_lo_hi_hi, readys_lo_hi_lo}; // @[Arbiter.scala:68:51]
wire [9:0] readys_lo = {readys_lo_hi, readys_lo_lo}; // @[Arbiter.scala:68:51]
wire [1:0] readys_hi_lo_lo = {portsAOI_filtered_11_0_valid, portsAOI_filtered_10_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_hi_lo_hi_hi = {portsAOI_filtered_14_0_valid, portsAOI_filtered_13_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_hi_lo_hi = {readys_hi_lo_hi_hi, portsAOI_filtered_12_0_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_hi_lo = {readys_hi_lo_hi, readys_hi_lo_lo}; // @[Arbiter.scala:68:51]
wire [1:0] readys_hi_hi_lo = {portsAOI_filtered_16_0_valid, portsAOI_filtered_15_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_hi_hi_hi_hi = {portsAOI_filtered_19_0_valid, portsAOI_filtered_18_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_hi_hi_hi = {readys_hi_hi_hi_hi, portsAOI_filtered_17_0_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_hi_hi = {readys_hi_hi_hi, readys_hi_hi_lo}; // @[Arbiter.scala:68:51]
wire [9:0] readys_hi = {readys_hi_hi, readys_hi_lo}; // @[Arbiter.scala:68:51]
wire [19:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51]
wire [19:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [19:0] readys_mask; // @[Arbiter.scala:23:23]
wire [19:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [19:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [39:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [38:0] _readys_unready_T = readys_filter[39:1]; // @[package.scala:262:48]
wire [39:0] _readys_unready_T_1 = {readys_filter[39], readys_filter[38:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [37:0] _readys_unready_T_2 = _readys_unready_T_1[39:2]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_3 = {_readys_unready_T_1[39:38], _readys_unready_T_1[37:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}]
wire [35:0] _readys_unready_T_4 = _readys_unready_T_3[39:4]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_5 = {_readys_unready_T_3[39:36], _readys_unready_T_3[35:0] | _readys_unready_T_4}; // @[package.scala:262:{43,48}]
wire [31:0] _readys_unready_T_6 = _readys_unready_T_5[39:8]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_7 = {_readys_unready_T_5[39:32], _readys_unready_T_5[31:0] | _readys_unready_T_6}; // @[package.scala:262:{43,48}]
wire [23:0] _readys_unready_T_8 = _readys_unready_T_7[39:16]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_9 = {_readys_unready_T_7[39:24], _readys_unready_T_7[23:0] | _readys_unready_T_8}; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_10 = _readys_unready_T_9; // @[package.scala:262:43, :263:17]
wire [38:0] _readys_unready_T_11 = _readys_unready_T_10[39:1]; // @[package.scala:263:17]
wire [39:0] _readys_unready_T_12 = {readys_mask, 20'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [39:0] readys_unready = {1'h0, _readys_unready_T_11} | _readys_unready_T_12; // @[Arbiter.scala:25:{52,58,66}]
wire [19:0] _readys_readys_T = readys_unready[39:20]; // @[Arbiter.scala:25:58, :26:29]
wire [19:0] _readys_readys_T_1 = readys_unready[19:0]; // @[Arbiter.scala:25:58, :26:48]
wire [19:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [19:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [19:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [19:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [20:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [19:0] _readys_mask_T_2 = _readys_mask_T_1[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [21:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_5 = _readys_mask_T_4[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}]
wire [23:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_8 = _readys_mask_T_7[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_8; // @[package.scala:253:{43,53}]
wire [27:0] _readys_mask_T_10 = {_readys_mask_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_11 = _readys_mask_T_10[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_12 = _readys_mask_T_9 | _readys_mask_T_11; // @[package.scala:253:{43,53}]
wire [35:0] _readys_mask_T_13 = {_readys_mask_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_14 = _readys_mask_T_13[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_15 = _readys_mask_T_12 | _readys_mask_T_14; // @[package.scala:253:{43,53}]
wire [19:0] _readys_mask_T_16 = _readys_mask_T_15; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_11 = _readys_T_7[3]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3 = _readys_T_11; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_12 = _readys_T_7[4]; // @[Arbiter.scala:30:11, :68:76]
wire readys_4 = _readys_T_12; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_13 = _readys_T_7[5]; // @[Arbiter.scala:30:11, :68:76]
wire readys_5 = _readys_T_13; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_14 = _readys_T_7[6]; // @[Arbiter.scala:30:11, :68:76]
wire readys_6 = _readys_T_14; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_15 = _readys_T_7[7]; // @[Arbiter.scala:30:11, :68:76]
wire readys_7 = _readys_T_15; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_16 = _readys_T_7[8]; // @[Arbiter.scala:30:11, :68:76]
wire readys_8 = _readys_T_16; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_17 = _readys_T_7[9]; // @[Arbiter.scala:30:11, :68:76]
wire readys_9 = _readys_T_17; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_18 = _readys_T_7[10]; // @[Arbiter.scala:30:11, :68:76]
wire readys_10 = _readys_T_18; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_19 = _readys_T_7[11]; // @[Arbiter.scala:30:11, :68:76]
wire readys_11 = _readys_T_19; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_20 = _readys_T_7[12]; // @[Arbiter.scala:30:11, :68:76]
wire readys_12 = _readys_T_20; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_21 = _readys_T_7[13]; // @[Arbiter.scala:30:11, :68:76]
wire readys_13 = _readys_T_21; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_22 = _readys_T_7[14]; // @[Arbiter.scala:30:11, :68:76]
wire readys_14 = _readys_T_22; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_23 = _readys_T_7[15]; // @[Arbiter.scala:30:11, :68:76]
wire readys_15 = _readys_T_23; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_24 = _readys_T_7[16]; // @[Arbiter.scala:30:11, :68:76]
wire readys_16 = _readys_T_24; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_25 = _readys_T_7[17]; // @[Arbiter.scala:30:11, :68:76]
wire readys_17 = _readys_T_25; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_26 = _readys_T_7[18]; // @[Arbiter.scala:30:11, :68:76]
wire readys_18 = _readys_T_26; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_27 = _readys_T_7[19]; // @[Arbiter.scala:30:11, :68:76]
wire readys_19 = _readys_T_27; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_3 = readys_3 & portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24]
wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_4 = readys_4 & portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24]
wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_5 = readys_5 & portsAOI_filtered_5_0_valid; // @[Xbar.scala:352:24]
wire winner_5 = _winner_T_5; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_6 = readys_6 & portsAOI_filtered_6_0_valid; // @[Xbar.scala:352:24]
wire winner_6 = _winner_T_6; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_7 = readys_7 & portsAOI_filtered_7_0_valid; // @[Xbar.scala:352:24]
wire winner_7 = _winner_T_7; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_8 = readys_8 & portsAOI_filtered_8_0_valid; // @[Xbar.scala:352:24]
wire winner_8 = _winner_T_8; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_9 = readys_9 & portsAOI_filtered_9_0_valid; // @[Xbar.scala:352:24]
wire winner_9 = _winner_T_9; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_10 = readys_10 & portsAOI_filtered_10_0_valid; // @[Xbar.scala:352:24]
wire winner_10 = _winner_T_10; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_11 = readys_11 & portsAOI_filtered_11_0_valid; // @[Xbar.scala:352:24]
wire winner_11 = _winner_T_11; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_12 = readys_12 & portsAOI_filtered_12_0_valid; // @[Xbar.scala:352:24]
wire winner_12 = _winner_T_12; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_13 = readys_13 & portsAOI_filtered_13_0_valid; // @[Xbar.scala:352:24]
wire winner_13 = _winner_T_13; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_14 = readys_14 & portsAOI_filtered_14_0_valid; // @[Xbar.scala:352:24]
wire winner_14 = _winner_T_14; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_15 = readys_15 & portsAOI_filtered_15_0_valid; // @[Xbar.scala:352:24]
wire winner_15 = _winner_T_15; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_16 = readys_16 & portsAOI_filtered_16_0_valid; // @[Xbar.scala:352:24]
wire winner_16 = _winner_T_16; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_17 = readys_17 & portsAOI_filtered_17_0_valid; // @[Xbar.scala:352:24]
wire winner_17 = _winner_T_17; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_18 = readys_18 & portsAOI_filtered_18_0_valid; // @[Xbar.scala:352:24]
wire winner_18 = _winner_T_18; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_19 = readys_19 & portsAOI_filtered_19_0_valid; // @[Xbar.scala:352:24]
wire winner_19 = _winner_T_19; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_3 = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_4 = prefixOR_3 | winner_3; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_5 = prefixOR_4 | winner_4; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_6 = prefixOR_5 | winner_5; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_7 = prefixOR_6 | winner_6; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_8 = prefixOR_7 | winner_7; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_9 = prefixOR_8 | winner_8; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_10 = prefixOR_9 | winner_9; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_11 = prefixOR_10 | winner_10; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_12 = prefixOR_11 | winner_11; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_13 = prefixOR_12 | winner_12; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_14 = prefixOR_13 | winner_13; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_15 = prefixOR_14 | winner_14; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_16 = prefixOR_15 | winner_15; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_17 = prefixOR_16 | winner_16; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_18 = prefixOR_17 | winner_17; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_19 = prefixOR_18 | winner_18; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_19 | winner_19; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_2 = winner_2 ? beatsAI_2 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_3 = winner_3 ? beatsAI_3 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_4 = winner_4 ? beatsAI_4 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_5 = winner_5 ? beatsAI_5 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_6 = winner_6 ? beatsAI_6 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_7 = winner_7 ? beatsAI_7 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_8 = winner_8 ? beatsAI_8 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_9 = winner_9 ? beatsAI_9 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_10 = winner_10 ? beatsAI_10 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_11 = winner_11 ? beatsAI_11 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_12 = winner_12 ? beatsAI_12 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_13 = winner_13 ? beatsAI_13 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_14 = winner_14 ? beatsAI_14 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_15 = winner_15 ? beatsAI_15 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_16 = winner_16 ? beatsAI_16 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_17 = winner_17 ? beatsAI_17 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_18 = winner_18 ? beatsAI_18 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_19 = winner_19 ? beatsAI_19 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] _initBeats_T = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_1 = _initBeats_T | maskedBeats_2; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_2 = _initBeats_T_1 | maskedBeats_3; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_3 = _initBeats_T_2 | maskedBeats_4; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_4 = _initBeats_T_3 | maskedBeats_5; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_5 = _initBeats_T_4 | maskedBeats_6; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_6 = _initBeats_T_5 | maskedBeats_7; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_7 = _initBeats_T_6 | maskedBeats_8; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_8 = _initBeats_T_7 | maskedBeats_9; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_9 = _initBeats_T_8 | maskedBeats_10; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_10 = _initBeats_T_9 | maskedBeats_11; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_11 = _initBeats_T_10 | maskedBeats_12; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_12 = _initBeats_T_11 | maskedBeats_13; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_13 = _initBeats_T_12 | maskedBeats_14; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_14 = _initBeats_T_13 | maskedBeats_15; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_15 = _initBeats_T_14 | maskedBeats_16; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_16 = _initBeats_T_15 | maskedBeats_17; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_17 = _initBeats_T_16 | maskedBeats_18; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] initBeats = _initBeats_T_17 | maskedBeats_19; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {9'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_2 = _beatsLeft_T_1[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
reg state_2; // @[Arbiter.scala:88:26]
reg state_3; // @[Arbiter.scala:88:26]
reg state_4; // @[Arbiter.scala:88:26]
reg state_5; // @[Arbiter.scala:88:26]
reg state_6; // @[Arbiter.scala:88:26]
reg state_7; // @[Arbiter.scala:88:26]
reg state_8; // @[Arbiter.scala:88:26]
reg state_9; // @[Arbiter.scala:88:26]
reg state_10; // @[Arbiter.scala:88:26]
reg state_11; // @[Arbiter.scala:88:26]
reg state_12; // @[Arbiter.scala:88:26]
reg state_13; // @[Arbiter.scala:88:26]
reg state_14; // @[Arbiter.scala:88:26]
reg state_15; // @[Arbiter.scala:88:26]
reg state_16; // @[Arbiter.scala:88:26]
reg state_17; // @[Arbiter.scala:88:26]
reg state_18; // @[Arbiter.scala:88:26]
reg state_19; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_3 = idle ? winner_3 : state_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_4 = idle ? winner_4 : state_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_5 = idle ? winner_5 : state_5; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_6 = idle ? winner_6 : state_6; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_7 = idle ? winner_7 : state_7; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_8 = idle ? winner_8 : state_8; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_9 = idle ? winner_9 : state_9; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_10 = idle ? winner_10 : state_10; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_11 = idle ? winner_11 : state_11; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_12 = idle ? winner_12 : state_12; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_13 = idle ? winner_13 : state_13; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_14 = idle ? winner_14 : state_14; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_15 = idle ? winner_15 : state_15; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_16 = idle ? winner_16 : state_16; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_17 = idle ? winner_17 : state_17; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_18 = idle ? winner_18 : state_18; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_19 = idle ? winner_19 : state_19; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_5 = idle ? readys_5 : state_5; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_6 = idle ? readys_6 : state_6; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_7 = idle ? readys_7 : state_7; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_8 = idle ? readys_8 : state_8; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_9 = idle ? readys_9 : state_9; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_10 = idle ? readys_10 : state_10; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_11 = idle ? readys_11 : state_11; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_12 = idle ? readys_12 : state_12; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_13 = idle ? readys_13 : state_13; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_14 = idle ? readys_14 : state_14; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_15 = idle ? readys_15 : state_15; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_16 = idle ? readys_16 : state_16; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_17 = idle ? readys_17 : state_17; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_18 = idle ? readys_18 : state_18; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_19 = idle ? readys_19 : state_19; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19]
assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_2 = out_0_a_ready & allowed_2; // @[Xbar.scala:216:19]
assign portsAOI_filtered_2_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_3 = out_0_a_ready & allowed_3; // @[Xbar.scala:216:19]
assign portsAOI_filtered_3_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_4 = out_0_a_ready & allowed_4; // @[Xbar.scala:216:19]
assign portsAOI_filtered_4_0_ready = _filtered_0_ready_T_4; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_5 = out_0_a_ready & allowed_5; // @[Xbar.scala:216:19]
assign portsAOI_filtered_5_0_ready = _filtered_0_ready_T_5; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_6 = out_0_a_ready & allowed_6; // @[Xbar.scala:216:19]
assign portsAOI_filtered_6_0_ready = _filtered_0_ready_T_6; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_7 = out_0_a_ready & allowed_7; // @[Xbar.scala:216:19]
assign portsAOI_filtered_7_0_ready = _filtered_0_ready_T_7; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_8 = out_0_a_ready & allowed_8; // @[Xbar.scala:216:19]
assign portsAOI_filtered_8_0_ready = _filtered_0_ready_T_8; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_9 = out_0_a_ready & allowed_9; // @[Xbar.scala:216:19]
assign portsAOI_filtered_9_0_ready = _filtered_0_ready_T_9; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_10 = out_0_a_ready & allowed_10; // @[Xbar.scala:216:19]
assign portsAOI_filtered_10_0_ready = _filtered_0_ready_T_10; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_11 = out_0_a_ready & allowed_11; // @[Xbar.scala:216:19]
assign portsAOI_filtered_11_0_ready = _filtered_0_ready_T_11; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_12 = out_0_a_ready & allowed_12; // @[Xbar.scala:216:19]
assign portsAOI_filtered_12_0_ready = _filtered_0_ready_T_12; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_13 = out_0_a_ready & allowed_13; // @[Xbar.scala:216:19]
assign portsAOI_filtered_13_0_ready = _filtered_0_ready_T_13; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_14 = out_0_a_ready & allowed_14; // @[Xbar.scala:216:19]
assign portsAOI_filtered_14_0_ready = _filtered_0_ready_T_14; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_15 = out_0_a_ready & allowed_15; // @[Xbar.scala:216:19]
assign portsAOI_filtered_15_0_ready = _filtered_0_ready_T_15; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_16 = out_0_a_ready & allowed_16; // @[Xbar.scala:216:19]
assign portsAOI_filtered_16_0_ready = _filtered_0_ready_T_16; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_17 = out_0_a_ready & allowed_17; // @[Xbar.scala:216:19]
assign portsAOI_filtered_17_0_ready = _filtered_0_ready_T_17; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_18 = out_0_a_ready & allowed_18; // @[Xbar.scala:216:19]
assign portsAOI_filtered_18_0_ready = _filtered_0_ready_T_18; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_19 = out_0_a_ready & allowed_19; // @[Xbar.scala:216:19]
assign portsAOI_filtered_19_0_ready = _filtered_0_ready_T_19; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_1 = _out_0_a_valid_T | portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_2 = _out_0_a_valid_T_1 | portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_3 = _out_0_a_valid_T_2 | portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_4 = _out_0_a_valid_T_3 | portsAOI_filtered_5_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_5 = _out_0_a_valid_T_4 | portsAOI_filtered_6_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_6 = _out_0_a_valid_T_5 | portsAOI_filtered_7_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_7 = _out_0_a_valid_T_6 | portsAOI_filtered_8_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_8 = _out_0_a_valid_T_7 | portsAOI_filtered_9_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_9 = _out_0_a_valid_T_8 | portsAOI_filtered_10_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_10 = _out_0_a_valid_T_9 | portsAOI_filtered_11_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_11 = _out_0_a_valid_T_10 | portsAOI_filtered_12_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_12 = _out_0_a_valid_T_11 | portsAOI_filtered_13_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_13 = _out_0_a_valid_T_12 | portsAOI_filtered_14_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_14 = _out_0_a_valid_T_13 | portsAOI_filtered_15_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_15 = _out_0_a_valid_T_14 | portsAOI_filtered_16_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_16 = _out_0_a_valid_T_15 | portsAOI_filtered_17_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_17 = _out_0_a_valid_T_16 | portsAOI_filtered_18_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_18 = _out_0_a_valid_T_17 | portsAOI_filtered_19_0_valid; // @[Xbar.scala:352:24]
wire _out_0_a_valid_T_19 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_20 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_21 = state_2 & portsAOI_filtered_2_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_22 = state_3 & portsAOI_filtered_3_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_23 = state_4 & portsAOI_filtered_4_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_24 = state_5 & portsAOI_filtered_5_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_25 = state_6 & portsAOI_filtered_6_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_26 = state_7 & portsAOI_filtered_7_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_27 = state_8 & portsAOI_filtered_8_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_28 = state_9 & portsAOI_filtered_9_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_29 = state_10 & portsAOI_filtered_10_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_30 = state_11 & portsAOI_filtered_11_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_31 = state_12 & portsAOI_filtered_12_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_32 = state_13 & portsAOI_filtered_13_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_33 = state_14 & portsAOI_filtered_14_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_34 = state_15 & portsAOI_filtered_15_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_35 = state_16 & portsAOI_filtered_16_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_36 = state_17 & portsAOI_filtered_17_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_37 = state_18 & portsAOI_filtered_18_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_38 = state_19 & portsAOI_filtered_19_0_valid; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_39 = _out_0_a_valid_T_19 | _out_0_a_valid_T_20; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_40 = _out_0_a_valid_T_39 | _out_0_a_valid_T_21; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_41 = _out_0_a_valid_T_40 | _out_0_a_valid_T_22; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_42 = _out_0_a_valid_T_41 | _out_0_a_valid_T_23; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_43 = _out_0_a_valid_T_42 | _out_0_a_valid_T_24; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_44 = _out_0_a_valid_T_43 | _out_0_a_valid_T_25; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_45 = _out_0_a_valid_T_44 | _out_0_a_valid_T_26; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_46 = _out_0_a_valid_T_45 | _out_0_a_valid_T_27; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_47 = _out_0_a_valid_T_46 | _out_0_a_valid_T_28; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_48 = _out_0_a_valid_T_47 | _out_0_a_valid_T_29; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_49 = _out_0_a_valid_T_48 | _out_0_a_valid_T_30; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_50 = _out_0_a_valid_T_49 | _out_0_a_valid_T_31; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_51 = _out_0_a_valid_T_50 | _out_0_a_valid_T_32; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_52 = _out_0_a_valid_T_51 | _out_0_a_valid_T_33; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_53 = _out_0_a_valid_T_52 | _out_0_a_valid_T_34; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_54 = _out_0_a_valid_T_53 | _out_0_a_valid_T_35; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_55 = _out_0_a_valid_T_54 | _out_0_a_valid_T_36; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_56 = _out_0_a_valid_T_55 | _out_0_a_valid_T_37; // @[Mux.scala:30:73]
wire _out_0_a_valid_T_57 = _out_0_a_valid_T_56 | _out_0_a_valid_T_38; // @[Mux.scala:30:73]
wire _out_0_a_valid_WIRE = _out_0_a_valid_T_57; // @[Mux.scala:30:73]
assign _out_0_a_valid_T_58 = idle ? _out_0_a_valid_T_18 : _out_0_a_valid_WIRE; // @[Mux.scala:30:73]
assign out_0_a_valid = _out_0_a_valid_T_58; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73]
assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73]
assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73]
assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73]
assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73]
assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73]
assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73]
assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73]
assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_2 = muxState_2 & portsAOI_filtered_2_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_3 = muxState_3 & portsAOI_filtered_3_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_4 = muxState_4 & portsAOI_filtered_4_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_5 = muxState_5 & portsAOI_filtered_5_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_6 = muxState_6 & portsAOI_filtered_6_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_7 = muxState_7 & portsAOI_filtered_7_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_8 = muxState_8 & portsAOI_filtered_8_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_9 = muxState_9 & portsAOI_filtered_9_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_10 = muxState_10 & portsAOI_filtered_10_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_11 = muxState_11 & portsAOI_filtered_11_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_12 = muxState_12 & portsAOI_filtered_12_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_13 = muxState_13 & portsAOI_filtered_13_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_14 = muxState_14 & portsAOI_filtered_14_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_15 = muxState_15 & portsAOI_filtered_15_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_16 = muxState_16 & portsAOI_filtered_16_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_17 = muxState_17 & portsAOI_filtered_17_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_18 = muxState_18 & portsAOI_filtered_18_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_19 = muxState_19 & portsAOI_filtered_19_0_bits_corrupt; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_20 = _out_0_a_bits_T | _out_0_a_bits_T_1; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_21 = _out_0_a_bits_T_20 | _out_0_a_bits_T_2; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_22 = _out_0_a_bits_T_21 | _out_0_a_bits_T_3; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_23 = _out_0_a_bits_T_22 | _out_0_a_bits_T_4; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_24 = _out_0_a_bits_T_23 | _out_0_a_bits_T_5; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_25 = _out_0_a_bits_T_24 | _out_0_a_bits_T_6; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_26 = _out_0_a_bits_T_25 | _out_0_a_bits_T_7; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_27 = _out_0_a_bits_T_26 | _out_0_a_bits_T_8; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_28 = _out_0_a_bits_T_27 | _out_0_a_bits_T_9; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_29 = _out_0_a_bits_T_28 | _out_0_a_bits_T_10; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_30 = _out_0_a_bits_T_29 | _out_0_a_bits_T_11; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_31 = _out_0_a_bits_T_30 | _out_0_a_bits_T_12; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_32 = _out_0_a_bits_T_31 | _out_0_a_bits_T_13; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_33 = _out_0_a_bits_T_32 | _out_0_a_bits_T_14; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_34 = _out_0_a_bits_T_33 | _out_0_a_bits_T_15; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_35 = _out_0_a_bits_T_34 | _out_0_a_bits_T_16; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_36 = _out_0_a_bits_T_35 | _out_0_a_bits_T_17; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_37 = _out_0_a_bits_T_36 | _out_0_a_bits_T_18; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_38 = _out_0_a_bits_T_37 | _out_0_a_bits_T_19; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_38; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_39 = muxState_0 ? portsAOI_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_40 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_41 = muxState_2 ? portsAOI_filtered_2_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_42 = muxState_3 ? portsAOI_filtered_3_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_43 = muxState_4 ? portsAOI_filtered_4_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_44 = muxState_5 ? portsAOI_filtered_5_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_45 = muxState_6 ? portsAOI_filtered_6_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_46 = muxState_7 ? portsAOI_filtered_7_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_47 = muxState_8 ? portsAOI_filtered_8_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_48 = muxState_9 ? portsAOI_filtered_9_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_49 = muxState_10 ? portsAOI_filtered_10_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_50 = muxState_11 ? portsAOI_filtered_11_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_51 = muxState_12 ? portsAOI_filtered_12_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_52 = muxState_13 ? portsAOI_filtered_13_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_53 = muxState_14 ? portsAOI_filtered_14_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_54 = muxState_15 ? portsAOI_filtered_15_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_55 = muxState_16 ? portsAOI_filtered_16_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_56 = muxState_17 ? portsAOI_filtered_17_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_57 = muxState_18 ? portsAOI_filtered_18_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_58 = muxState_19 ? portsAOI_filtered_19_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_59 = _out_0_a_bits_T_39 | _out_0_a_bits_T_40; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_60 = _out_0_a_bits_T_59 | _out_0_a_bits_T_41; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_61 = _out_0_a_bits_T_60 | _out_0_a_bits_T_42; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_62 = _out_0_a_bits_T_61 | _out_0_a_bits_T_43; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_63 = _out_0_a_bits_T_62 | _out_0_a_bits_T_44; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_64 = _out_0_a_bits_T_63 | _out_0_a_bits_T_45; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_65 = _out_0_a_bits_T_64 | _out_0_a_bits_T_46; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_66 = _out_0_a_bits_T_65 | _out_0_a_bits_T_47; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_67 = _out_0_a_bits_T_66 | _out_0_a_bits_T_48; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_68 = _out_0_a_bits_T_67 | _out_0_a_bits_T_49; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_69 = _out_0_a_bits_T_68 | _out_0_a_bits_T_50; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_70 = _out_0_a_bits_T_69 | _out_0_a_bits_T_51; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_71 = _out_0_a_bits_T_70 | _out_0_a_bits_T_52; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_72 = _out_0_a_bits_T_71 | _out_0_a_bits_T_53; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_73 = _out_0_a_bits_T_72 | _out_0_a_bits_T_54; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_74 = _out_0_a_bits_T_73 | _out_0_a_bits_T_55; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_75 = _out_0_a_bits_T_74 | _out_0_a_bits_T_56; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_76 = _out_0_a_bits_T_75 | _out_0_a_bits_T_57; // @[Mux.scala:30:73]
wire [63:0] _out_0_a_bits_T_77 = _out_0_a_bits_T_76 | _out_0_a_bits_T_58; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_77; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_78 = muxState_0 ? portsAOI_filtered_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_79 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_80 = muxState_2 ? portsAOI_filtered_2_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_81 = muxState_3 ? portsAOI_filtered_3_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_82 = muxState_4 ? portsAOI_filtered_4_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_83 = muxState_5 ? portsAOI_filtered_5_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_84 = muxState_6 ? portsAOI_filtered_6_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_85 = muxState_7 ? portsAOI_filtered_7_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_86 = muxState_8 ? portsAOI_filtered_8_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_87 = muxState_9 ? portsAOI_filtered_9_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_88 = muxState_10 ? portsAOI_filtered_10_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_89 = muxState_11 ? portsAOI_filtered_11_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_90 = muxState_12 ? portsAOI_filtered_12_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_91 = muxState_13 ? portsAOI_filtered_13_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_92 = muxState_14 ? portsAOI_filtered_14_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_93 = muxState_15 ? portsAOI_filtered_15_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_94 = muxState_16 ? portsAOI_filtered_16_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_95 = muxState_17 ? portsAOI_filtered_17_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_96 = muxState_18 ? portsAOI_filtered_18_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_97 = muxState_19 ? portsAOI_filtered_19_0_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_98 = _out_0_a_bits_T_78 | _out_0_a_bits_T_79; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_99 = _out_0_a_bits_T_98 | _out_0_a_bits_T_80; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_100 = _out_0_a_bits_T_99 | _out_0_a_bits_T_81; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_101 = _out_0_a_bits_T_100 | _out_0_a_bits_T_82; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_102 = _out_0_a_bits_T_101 | _out_0_a_bits_T_83; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_103 = _out_0_a_bits_T_102 | _out_0_a_bits_T_84; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_104 = _out_0_a_bits_T_103 | _out_0_a_bits_T_85; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_105 = _out_0_a_bits_T_104 | _out_0_a_bits_T_86; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_106 = _out_0_a_bits_T_105 | _out_0_a_bits_T_87; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_107 = _out_0_a_bits_T_106 | _out_0_a_bits_T_88; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_108 = _out_0_a_bits_T_107 | _out_0_a_bits_T_89; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_109 = _out_0_a_bits_T_108 | _out_0_a_bits_T_90; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_110 = _out_0_a_bits_T_109 | _out_0_a_bits_T_91; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_111 = _out_0_a_bits_T_110 | _out_0_a_bits_T_92; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_112 = _out_0_a_bits_T_111 | _out_0_a_bits_T_93; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_113 = _out_0_a_bits_T_112 | _out_0_a_bits_T_94; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_114 = _out_0_a_bits_T_113 | _out_0_a_bits_T_95; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_115 = _out_0_a_bits_T_114 | _out_0_a_bits_T_96; // @[Mux.scala:30:73]
wire [7:0] _out_0_a_bits_T_116 = _out_0_a_bits_T_115 | _out_0_a_bits_T_97; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_116; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_117 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_118 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_119 = muxState_2 ? portsAOI_filtered_2_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_120 = muxState_3 ? portsAOI_filtered_3_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_121 = muxState_4 ? portsAOI_filtered_4_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_122 = muxState_5 ? portsAOI_filtered_5_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_123 = muxState_6 ? portsAOI_filtered_6_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_124 = muxState_7 ? portsAOI_filtered_7_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_125 = muxState_8 ? portsAOI_filtered_8_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_126 = muxState_9 ? portsAOI_filtered_9_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_127 = muxState_10 ? portsAOI_filtered_10_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_128 = muxState_11 ? portsAOI_filtered_11_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_129 = muxState_12 ? portsAOI_filtered_12_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_130 = muxState_13 ? portsAOI_filtered_13_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_131 = muxState_14 ? portsAOI_filtered_14_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_132 = muxState_15 ? portsAOI_filtered_15_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_133 = muxState_16 ? portsAOI_filtered_16_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_134 = muxState_17 ? portsAOI_filtered_17_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_135 = muxState_18 ? portsAOI_filtered_18_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_136 = muxState_19 ? portsAOI_filtered_19_0_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_137 = _out_0_a_bits_T_117 | _out_0_a_bits_T_118; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_138 = _out_0_a_bits_T_137 | _out_0_a_bits_T_119; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_139 = _out_0_a_bits_T_138 | _out_0_a_bits_T_120; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_140 = _out_0_a_bits_T_139 | _out_0_a_bits_T_121; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_141 = _out_0_a_bits_T_140 | _out_0_a_bits_T_122; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_142 = _out_0_a_bits_T_141 | _out_0_a_bits_T_123; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_143 = _out_0_a_bits_T_142 | _out_0_a_bits_T_124; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_144 = _out_0_a_bits_T_143 | _out_0_a_bits_T_125; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_145 = _out_0_a_bits_T_144 | _out_0_a_bits_T_126; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_146 = _out_0_a_bits_T_145 | _out_0_a_bits_T_127; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_147 = _out_0_a_bits_T_146 | _out_0_a_bits_T_128; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_148 = _out_0_a_bits_T_147 | _out_0_a_bits_T_129; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_149 = _out_0_a_bits_T_148 | _out_0_a_bits_T_130; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_150 = _out_0_a_bits_T_149 | _out_0_a_bits_T_131; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_151 = _out_0_a_bits_T_150 | _out_0_a_bits_T_132; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_152 = _out_0_a_bits_T_151 | _out_0_a_bits_T_133; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_153 = _out_0_a_bits_T_152 | _out_0_a_bits_T_134; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_154 = _out_0_a_bits_T_153 | _out_0_a_bits_T_135; // @[Mux.scala:30:73]
wire [31:0] _out_0_a_bits_T_155 = _out_0_a_bits_T_154 | _out_0_a_bits_T_136; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_155; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_156 = muxState_0 ? portsAOI_filtered_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_157 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_158 = muxState_2 ? portsAOI_filtered_2_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_159 = muxState_3 ? portsAOI_filtered_3_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_160 = muxState_4 ? portsAOI_filtered_4_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_161 = muxState_5 ? portsAOI_filtered_5_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_162 = muxState_6 ? portsAOI_filtered_6_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_163 = muxState_7 ? portsAOI_filtered_7_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_164 = muxState_8 ? portsAOI_filtered_8_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_165 = muxState_9 ? portsAOI_filtered_9_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_166 = muxState_10 ? portsAOI_filtered_10_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_167 = muxState_11 ? portsAOI_filtered_11_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_168 = muxState_12 ? portsAOI_filtered_12_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_169 = muxState_13 ? portsAOI_filtered_13_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_170 = muxState_14 ? portsAOI_filtered_14_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_171 = muxState_15 ? portsAOI_filtered_15_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_172 = muxState_16 ? portsAOI_filtered_16_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_173 = muxState_17 ? portsAOI_filtered_17_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_174 = muxState_18 ? portsAOI_filtered_18_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_175 = muxState_19 ? portsAOI_filtered_19_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_176 = _out_0_a_bits_T_156 | _out_0_a_bits_T_157; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_177 = _out_0_a_bits_T_176 | _out_0_a_bits_T_158; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_178 = _out_0_a_bits_T_177 | _out_0_a_bits_T_159; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_179 = _out_0_a_bits_T_178 | _out_0_a_bits_T_160; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_180 = _out_0_a_bits_T_179 | _out_0_a_bits_T_161; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_181 = _out_0_a_bits_T_180 | _out_0_a_bits_T_162; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_182 = _out_0_a_bits_T_181 | _out_0_a_bits_T_163; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_183 = _out_0_a_bits_T_182 | _out_0_a_bits_T_164; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_184 = _out_0_a_bits_T_183 | _out_0_a_bits_T_165; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_185 = _out_0_a_bits_T_184 | _out_0_a_bits_T_166; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_186 = _out_0_a_bits_T_185 | _out_0_a_bits_T_167; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_187 = _out_0_a_bits_T_186 | _out_0_a_bits_T_168; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_188 = _out_0_a_bits_T_187 | _out_0_a_bits_T_169; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_189 = _out_0_a_bits_T_188 | _out_0_a_bits_T_170; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_190 = _out_0_a_bits_T_189 | _out_0_a_bits_T_171; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_191 = _out_0_a_bits_T_190 | _out_0_a_bits_T_172; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_192 = _out_0_a_bits_T_191 | _out_0_a_bits_T_173; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_193 = _out_0_a_bits_T_192 | _out_0_a_bits_T_174; // @[Mux.scala:30:73]
wire [8:0] _out_0_a_bits_T_194 = _out_0_a_bits_T_193 | _out_0_a_bits_T_175; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_194; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_195 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_196 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_197 = muxState_2 ? portsAOI_filtered_2_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_198 = muxState_3 ? portsAOI_filtered_3_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_199 = muxState_4 ? portsAOI_filtered_4_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_200 = muxState_5 ? portsAOI_filtered_5_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_201 = muxState_6 ? portsAOI_filtered_6_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_202 = muxState_7 ? portsAOI_filtered_7_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_203 = muxState_8 ? portsAOI_filtered_8_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_204 = muxState_9 ? portsAOI_filtered_9_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_205 = muxState_10 ? portsAOI_filtered_10_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_206 = muxState_11 ? portsAOI_filtered_11_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_207 = muxState_12 ? portsAOI_filtered_12_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_208 = muxState_13 ? portsAOI_filtered_13_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_209 = muxState_14 ? portsAOI_filtered_14_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_210 = muxState_15 ? portsAOI_filtered_15_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_211 = muxState_16 ? portsAOI_filtered_16_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_212 = muxState_17 ? portsAOI_filtered_17_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_213 = muxState_18 ? portsAOI_filtered_18_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_214 = muxState_19 ? portsAOI_filtered_19_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_215 = _out_0_a_bits_T_195 | _out_0_a_bits_T_196; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_216 = _out_0_a_bits_T_215 | _out_0_a_bits_T_197; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_217 = _out_0_a_bits_T_216 | _out_0_a_bits_T_198; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_218 = _out_0_a_bits_T_217 | _out_0_a_bits_T_199; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_219 = _out_0_a_bits_T_218 | _out_0_a_bits_T_200; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_220 = _out_0_a_bits_T_219 | _out_0_a_bits_T_201; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_221 = _out_0_a_bits_T_220 | _out_0_a_bits_T_202; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_222 = _out_0_a_bits_T_221 | _out_0_a_bits_T_203; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_223 = _out_0_a_bits_T_222 | _out_0_a_bits_T_204; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_224 = _out_0_a_bits_T_223 | _out_0_a_bits_T_205; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_225 = _out_0_a_bits_T_224 | _out_0_a_bits_T_206; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_226 = _out_0_a_bits_T_225 | _out_0_a_bits_T_207; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_227 = _out_0_a_bits_T_226 | _out_0_a_bits_T_208; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_228 = _out_0_a_bits_T_227 | _out_0_a_bits_T_209; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_229 = _out_0_a_bits_T_228 | _out_0_a_bits_T_210; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_230 = _out_0_a_bits_T_229 | _out_0_a_bits_T_211; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_231 = _out_0_a_bits_T_230 | _out_0_a_bits_T_212; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_232 = _out_0_a_bits_T_231 | _out_0_a_bits_T_213; // @[Mux.scala:30:73]
wire [3:0] _out_0_a_bits_T_233 = _out_0_a_bits_T_232 | _out_0_a_bits_T_214; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_233; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_234 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_235 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_236 = muxState_2 ? portsAOI_filtered_2_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_237 = muxState_3 ? portsAOI_filtered_3_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_238 = muxState_4 ? portsAOI_filtered_4_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_239 = muxState_5 ? portsAOI_filtered_5_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_240 = muxState_6 ? portsAOI_filtered_6_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_241 = muxState_7 ? portsAOI_filtered_7_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_242 = muxState_8 ? portsAOI_filtered_8_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_243 = muxState_9 ? portsAOI_filtered_9_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_244 = muxState_10 ? portsAOI_filtered_10_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_245 = muxState_11 ? portsAOI_filtered_11_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_246 = muxState_12 ? portsAOI_filtered_12_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_247 = muxState_13 ? portsAOI_filtered_13_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_248 = muxState_14 ? portsAOI_filtered_14_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_249 = muxState_15 ? portsAOI_filtered_15_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_250 = muxState_16 ? portsAOI_filtered_16_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_251 = muxState_17 ? portsAOI_filtered_17_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_252 = muxState_18 ? portsAOI_filtered_18_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_253 = muxState_19 ? portsAOI_filtered_19_0_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_254 = _out_0_a_bits_T_234 | _out_0_a_bits_T_235; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_255 = _out_0_a_bits_T_254 | _out_0_a_bits_T_236; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_256 = _out_0_a_bits_T_255 | _out_0_a_bits_T_237; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_257 = _out_0_a_bits_T_256 | _out_0_a_bits_T_238; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_258 = _out_0_a_bits_T_257 | _out_0_a_bits_T_239; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_259 = _out_0_a_bits_T_258 | _out_0_a_bits_T_240; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_260 = _out_0_a_bits_T_259 | _out_0_a_bits_T_241; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_261 = _out_0_a_bits_T_260 | _out_0_a_bits_T_242; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_262 = _out_0_a_bits_T_261 | _out_0_a_bits_T_243; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_263 = _out_0_a_bits_T_262 | _out_0_a_bits_T_244; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_264 = _out_0_a_bits_T_263 | _out_0_a_bits_T_245; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_265 = _out_0_a_bits_T_264 | _out_0_a_bits_T_246; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_266 = _out_0_a_bits_T_265 | _out_0_a_bits_T_247; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_267 = _out_0_a_bits_T_266 | _out_0_a_bits_T_248; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_268 = _out_0_a_bits_T_267 | _out_0_a_bits_T_249; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_269 = _out_0_a_bits_T_268 | _out_0_a_bits_T_250; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_270 = _out_0_a_bits_T_269 | _out_0_a_bits_T_251; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_271 = _out_0_a_bits_T_270 | _out_0_a_bits_T_252; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_272 = _out_0_a_bits_T_271 | _out_0_a_bits_T_253; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_272; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_273 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_274 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_275 = muxState_2 ? portsAOI_filtered_2_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_276 = muxState_3 ? portsAOI_filtered_3_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_277 = muxState_4 ? portsAOI_filtered_4_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_278 = muxState_5 ? portsAOI_filtered_5_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_279 = muxState_6 ? portsAOI_filtered_6_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_280 = muxState_7 ? portsAOI_filtered_7_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_281 = muxState_8 ? portsAOI_filtered_8_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_282 = muxState_9 ? portsAOI_filtered_9_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_283 = muxState_10 ? portsAOI_filtered_10_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_284 = muxState_11 ? portsAOI_filtered_11_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_285 = muxState_12 ? portsAOI_filtered_12_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_286 = muxState_13 ? portsAOI_filtered_13_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_287 = muxState_14 ? portsAOI_filtered_14_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_288 = muxState_15 ? portsAOI_filtered_15_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_289 = muxState_16 ? portsAOI_filtered_16_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_290 = muxState_17 ? portsAOI_filtered_17_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_291 = muxState_18 ? portsAOI_filtered_18_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_292 = muxState_19 ? portsAOI_filtered_19_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_293 = _out_0_a_bits_T_273 | _out_0_a_bits_T_274; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_294 = _out_0_a_bits_T_293 | _out_0_a_bits_T_275; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_295 = _out_0_a_bits_T_294 | _out_0_a_bits_T_276; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_296 = _out_0_a_bits_T_295 | _out_0_a_bits_T_277; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_297 = _out_0_a_bits_T_296 | _out_0_a_bits_T_278; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_298 = _out_0_a_bits_T_297 | _out_0_a_bits_T_279; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_299 = _out_0_a_bits_T_298 | _out_0_a_bits_T_280; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_300 = _out_0_a_bits_T_299 | _out_0_a_bits_T_281; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_301 = _out_0_a_bits_T_300 | _out_0_a_bits_T_282; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_302 = _out_0_a_bits_T_301 | _out_0_a_bits_T_283; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_303 = _out_0_a_bits_T_302 | _out_0_a_bits_T_284; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_304 = _out_0_a_bits_T_303 | _out_0_a_bits_T_285; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_305 = _out_0_a_bits_T_304 | _out_0_a_bits_T_286; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_306 = _out_0_a_bits_T_305 | _out_0_a_bits_T_287; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_307 = _out_0_a_bits_T_306 | _out_0_a_bits_T_288; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_308 = _out_0_a_bits_T_307 | _out_0_a_bits_T_289; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_309 = _out_0_a_bits_T_308 | _out_0_a_bits_T_290; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_310 = _out_0_a_bits_T_309 | _out_0_a_bits_T_291; // @[Mux.scala:30:73]
wire [2:0] _out_0_a_bits_T_311 = _out_0_a_bits_T_310 | _out_0_a_bits_T_292; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_311; // @[Mux.scala:30:73]
assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19]
wire [1:0] readys_lo_lo_lo_1 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_lo_lo_hi_hi_1 = {portsAOI_filtered_4_1_valid, portsAOI_filtered_3_1_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_lo_lo_hi_1 = {readys_lo_lo_hi_hi_1, portsAOI_filtered_2_1_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_lo_lo_1 = {readys_lo_lo_hi_1, readys_lo_lo_lo_1}; // @[Arbiter.scala:68:51]
wire [1:0] readys_lo_hi_lo_1 = {portsAOI_filtered_6_1_valid, portsAOI_filtered_5_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_lo_hi_hi_hi_1 = {portsAOI_filtered_9_1_valid, portsAOI_filtered_8_1_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_lo_hi_hi_1 = {readys_lo_hi_hi_hi_1, portsAOI_filtered_7_1_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_lo_hi_1 = {readys_lo_hi_hi_1, readys_lo_hi_lo_1}; // @[Arbiter.scala:68:51]
wire [9:0] readys_lo_1 = {readys_lo_hi_1, readys_lo_lo_1}; // @[Arbiter.scala:68:51]
wire [1:0] readys_hi_lo_lo_1 = {portsAOI_filtered_11_1_valid, portsAOI_filtered_10_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_hi_lo_hi_hi_1 = {portsAOI_filtered_14_1_valid, portsAOI_filtered_13_1_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_hi_lo_hi_1 = {readys_hi_lo_hi_hi_1, portsAOI_filtered_12_1_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_hi_lo_1 = {readys_hi_lo_hi_1, readys_hi_lo_lo_1}; // @[Arbiter.scala:68:51]
wire [1:0] readys_hi_hi_lo_1 = {portsAOI_filtered_16_1_valid, portsAOI_filtered_15_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_hi_hi_hi_hi_1 = {portsAOI_filtered_19_1_valid, portsAOI_filtered_18_1_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_hi_hi_hi_1 = {readys_hi_hi_hi_hi_1, portsAOI_filtered_17_1_valid}; // @[Xbar.scala:352:24]
wire [4:0] readys_hi_hi_1 = {readys_hi_hi_hi_1, readys_hi_hi_lo_1}; // @[Arbiter.scala:68:51]
wire [9:0] readys_hi_1 = {readys_hi_hi_1, readys_hi_lo_1}; // @[Arbiter.scala:68:51]
wire [19:0] _readys_T_28 = {readys_hi_1, readys_lo_1}; // @[Arbiter.scala:68:51]
wire [19:0] readys_valid_1 = _readys_T_28; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_29 = readys_valid_1 == _readys_T_28; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_31 = ~_readys_T_30; // @[Arbiter.scala:22:12]
wire _readys_T_32 = ~_readys_T_29; // @[Arbiter.scala:22:{12,19}]
reg [19:0] readys_mask_1; // @[Arbiter.scala:23:23]
wire [19:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30]
wire [19:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [39:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [38:0] _readys_unready_T_13 = readys_filter_1[39:1]; // @[package.scala:262:48]
wire [39:0] _readys_unready_T_14 = {readys_filter_1[39], readys_filter_1[38:0] | _readys_unready_T_13}; // @[package.scala:262:{43,48}]
wire [37:0] _readys_unready_T_15 = _readys_unready_T_14[39:2]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_16 = {_readys_unready_T_14[39:38], _readys_unready_T_14[37:0] | _readys_unready_T_15}; // @[package.scala:262:{43,48}]
wire [35:0] _readys_unready_T_17 = _readys_unready_T_16[39:4]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_18 = {_readys_unready_T_16[39:36], _readys_unready_T_16[35:0] | _readys_unready_T_17}; // @[package.scala:262:{43,48}]
wire [31:0] _readys_unready_T_19 = _readys_unready_T_18[39:8]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_20 = {_readys_unready_T_18[39:32], _readys_unready_T_18[31:0] | _readys_unready_T_19}; // @[package.scala:262:{43,48}]
wire [23:0] _readys_unready_T_21 = _readys_unready_T_20[39:16]; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_22 = {_readys_unready_T_20[39:24], _readys_unready_T_20[23:0] | _readys_unready_T_21}; // @[package.scala:262:{43,48}]
wire [39:0] _readys_unready_T_23 = _readys_unready_T_22; // @[package.scala:262:43, :263:17]
wire [38:0] _readys_unready_T_24 = _readys_unready_T_23[39:1]; // @[package.scala:263:17]
wire [39:0] _readys_unready_T_25 = {readys_mask_1, 20'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [39:0] readys_unready_1 = {1'h0, _readys_unready_T_24} | _readys_unready_T_25; // @[Arbiter.scala:25:{52,58,66}]
wire [19:0] _readys_readys_T_3 = readys_unready_1[39:20]; // @[Arbiter.scala:25:58, :26:29]
wire [19:0] _readys_readys_T_4 = readys_unready_1[19:0]; // @[Arbiter.scala:25:58, :26:48]
wire [19:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}]
wire [19:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}]
wire [19:0] _readys_T_35 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_33 = |readys_valid_1; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_34 = latch_1 & _readys_T_33; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [19:0] _readys_mask_T_17 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [20:0] _readys_mask_T_18 = {_readys_mask_T_17, 1'h0}; // @[package.scala:253:48]
wire [19:0] _readys_mask_T_19 = _readys_mask_T_18[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_20 = _readys_mask_T_17 | _readys_mask_T_19; // @[package.scala:253:{43,53}]
wire [21:0] _readys_mask_T_21 = {_readys_mask_T_20, 2'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_22 = _readys_mask_T_21[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_23 = _readys_mask_T_20 | _readys_mask_T_22; // @[package.scala:253:{43,53}]
wire [23:0] _readys_mask_T_24 = {_readys_mask_T_23, 4'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_25 = _readys_mask_T_24[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_26 = _readys_mask_T_23 | _readys_mask_T_25; // @[package.scala:253:{43,53}]
wire [27:0] _readys_mask_T_27 = {_readys_mask_T_26, 8'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_28 = _readys_mask_T_27[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_29 = _readys_mask_T_26 | _readys_mask_T_28; // @[package.scala:253:{43,53}]
wire [35:0] _readys_mask_T_30 = {_readys_mask_T_29, 16'h0}; // @[package.scala:253:{43,48}]
wire [19:0] _readys_mask_T_31 = _readys_mask_T_30[19:0]; // @[package.scala:253:{48,53}]
wire [19:0] _readys_mask_T_32 = _readys_mask_T_29 | _readys_mask_T_31; // @[package.scala:253:{43,53}]
wire [19:0] _readys_mask_T_33 = _readys_mask_T_32; // @[package.scala:253:43, :254:17]
wire _readys_T_36 = _readys_T_35[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_0 = _readys_T_36; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_37 = _readys_T_35[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_1 = _readys_T_37; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_38 = _readys_T_35[2]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_2 = _readys_T_38; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_39 = _readys_T_35[3]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_3 = _readys_T_39; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_40 = _readys_T_35[4]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_4 = _readys_T_40; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_41 = _readys_T_35[5]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_5 = _readys_T_41; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_42 = _readys_T_35[6]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_6 = _readys_T_42; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_43 = _readys_T_35[7]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_7 = _readys_T_43; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_44 = _readys_T_35[8]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_8 = _readys_T_44; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_45 = _readys_T_35[9]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_9 = _readys_T_45; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_46 = _readys_T_35[10]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_10 = _readys_T_46; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_47 = _readys_T_35[11]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_11 = _readys_T_47; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_48 = _readys_T_35[12]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_12 = _readys_T_48; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_49 = _readys_T_35[13]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_13 = _readys_T_49; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_50 = _readys_T_35[14]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_14 = _readys_T_50; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_51 = _readys_T_35[15]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_15 = _readys_T_51; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_52 = _readys_T_35[16]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_16 = _readys_T_52; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_53 = _readys_T_35[17]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_17 = _readys_T_53; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_54 = _readys_T_35[18]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_18 = _readys_T_54; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_55 = _readys_T_35[19]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1_19 = _readys_T_55; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_20 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24]
wire winner_1_0 = _winner_T_20; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_21 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire winner_1_1 = _winner_T_21; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_22 = readys_1_2 & portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24]
wire winner_1_2 = _winner_T_22; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_23 = readys_1_3 & portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24]
wire winner_1_3 = _winner_T_23; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_24 = readys_1_4 & portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24]
wire winner_1_4 = _winner_T_24; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_25 = readys_1_5 & portsAOI_filtered_5_1_valid; // @[Xbar.scala:352:24]
wire winner_1_5 = _winner_T_25; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_26 = readys_1_6 & portsAOI_filtered_6_1_valid; // @[Xbar.scala:352:24]
wire winner_1_6 = _winner_T_26; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_27 = readys_1_7 & portsAOI_filtered_7_1_valid; // @[Xbar.scala:352:24]
wire winner_1_7 = _winner_T_27; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_28 = readys_1_8 & portsAOI_filtered_8_1_valid; // @[Xbar.scala:352:24]
wire winner_1_8 = _winner_T_28; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_29 = readys_1_9 & portsAOI_filtered_9_1_valid; // @[Xbar.scala:352:24]
wire winner_1_9 = _winner_T_29; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_30 = readys_1_10 & portsAOI_filtered_10_1_valid; // @[Xbar.scala:352:24]
wire winner_1_10 = _winner_T_30; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_31 = readys_1_11 & portsAOI_filtered_11_1_valid; // @[Xbar.scala:352:24]
wire winner_1_11 = _winner_T_31; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_32 = readys_1_12 & portsAOI_filtered_12_1_valid; // @[Xbar.scala:352:24]
wire winner_1_12 = _winner_T_32; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_33 = readys_1_13 & portsAOI_filtered_13_1_valid; // @[Xbar.scala:352:24]
wire winner_1_13 = _winner_T_33; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_34 = readys_1_14 & portsAOI_filtered_14_1_valid; // @[Xbar.scala:352:24]
wire winner_1_14 = _winner_T_34; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_35 = readys_1_15 & portsAOI_filtered_15_1_valid; // @[Xbar.scala:352:24]
wire winner_1_15 = _winner_T_35; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_36 = readys_1_16 & portsAOI_filtered_16_1_valid; // @[Xbar.scala:352:24]
wire winner_1_16 = _winner_T_36; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_37 = readys_1_17 & portsAOI_filtered_17_1_valid; // @[Xbar.scala:352:24]
wire winner_1_17 = _winner_T_37; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_38 = readys_1_18 & portsAOI_filtered_18_1_valid; // @[Xbar.scala:352:24]
wire winner_1_18 = _winner_T_38; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_39 = readys_1_19 & portsAOI_filtered_19_1_valid; // @[Xbar.scala:352:24]
wire winner_1_19 = _winner_T_39; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_3_1 = prefixOR_2_1 | winner_1_2; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_4_1 = prefixOR_3_1 | winner_1_3; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_5_1 = prefixOR_4_1 | winner_1_4; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_6_1 = prefixOR_5_1 | winner_1_5; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_7_1 = prefixOR_6_1 | winner_1_6; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_8_1 = prefixOR_7_1 | winner_1_7; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_9_1 = prefixOR_8_1 | winner_1_8; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_10_1 = prefixOR_9_1 | winner_1_9; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_11_1 = prefixOR_10_1 | winner_1_10; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_12_1 = prefixOR_11_1 | winner_1_11; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_13_1 = prefixOR_12_1 | winner_1_12; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_14_1 = prefixOR_13_1 | winner_1_13; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_15_1 = prefixOR_14_1 | winner_1_14; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_16_1 = prefixOR_15_1 | winner_1_15; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_17_1 = prefixOR_16_1 | winner_1_16; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_18_1 = prefixOR_17_1 | winner_1_17; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_19_1 = prefixOR_18_1 | winner_1_18; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_1 = prefixOR_19_1 | winner_1_19; // @[Arbiter.scala:71:27, :76:48]
wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_2_1 = winner_1_2 ? beatsAI_2 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_3_1 = winner_1_3 ? beatsAI_3 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_4_1 = winner_1_4 ? beatsAI_4 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_5_1 = winner_1_5 ? beatsAI_5 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_6_1 = winner_1_6 ? beatsAI_6 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_7_1 = winner_1_7 ? beatsAI_7 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_8_1 = winner_1_8 ? beatsAI_8 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_9_1 = winner_1_9 ? beatsAI_9 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_10_1 = winner_1_10 ? beatsAI_10 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_11_1 = winner_1_11 ? beatsAI_11 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_12_1 = winner_1_12 ? beatsAI_12 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_13_1 = winner_1_13 ? beatsAI_13 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_14_1 = winner_1_14 ? beatsAI_14 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_15_1 = winner_1_15 ? beatsAI_15 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_16_1 = winner_1_16 ? beatsAI_16 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_17_1 = winner_1_17 ? beatsAI_17 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_18_1 = winner_1_18 ? beatsAI_18 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] maskedBeats_19_1 = winner_1_19 ? beatsAI_19 : 9'h0; // @[Edges.scala:221:14]
wire [8:0] _initBeats_T_18 = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_19 = _initBeats_T_18 | maskedBeats_2_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_20 = _initBeats_T_19 | maskedBeats_3_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_21 = _initBeats_T_20 | maskedBeats_4_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_22 = _initBeats_T_21 | maskedBeats_5_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_23 = _initBeats_T_22 | maskedBeats_6_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_24 = _initBeats_T_23 | maskedBeats_7_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_25 = _initBeats_T_24 | maskedBeats_8_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_26 = _initBeats_T_25 | maskedBeats_9_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_27 = _initBeats_T_26 | maskedBeats_10_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_28 = _initBeats_T_27 | maskedBeats_11_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_29 = _initBeats_T_28 | maskedBeats_12_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_30 = _initBeats_T_29 | maskedBeats_13_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_31 = _initBeats_T_30 | maskedBeats_14_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_32 = _initBeats_T_31 | maskedBeats_15_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_33 = _initBeats_T_32 | maskedBeats_16_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_34 = _initBeats_T_33 | maskedBeats_17_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] _initBeats_T_35 = _initBeats_T_34 | maskedBeats_18_1; // @[Arbiter.scala:82:69, :84:44]
wire [8:0] initBeats_1 = _initBeats_T_35 | maskedBeats_19_1; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {9'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_6 = _beatsLeft_T_5[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
reg state_1_2; // @[Arbiter.scala:88:26]
reg state_1_3; // @[Arbiter.scala:88:26]
reg state_1_4; // @[Arbiter.scala:88:26]
reg state_1_5; // @[Arbiter.scala:88:26]
reg state_1_6; // @[Arbiter.scala:88:26]
reg state_1_7; // @[Arbiter.scala:88:26]
reg state_1_8; // @[Arbiter.scala:88:26]
reg state_1_9; // @[Arbiter.scala:88:26]
reg state_1_10; // @[Arbiter.scala:88:26]
reg state_1_11; // @[Arbiter.scala:88:26]
reg state_1_12; // @[Arbiter.scala:88:26]
reg state_1_13; // @[Arbiter.scala:88:26]
reg state_1_14; // @[Arbiter.scala:88:26]
reg state_1_15; // @[Arbiter.scala:88:26]
reg state_1_16; // @[Arbiter.scala:88:26]
reg state_1_17; // @[Arbiter.scala:88:26]
reg state_1_18; // @[Arbiter.scala:88:26]
reg state_1_19; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_3 = idle_1 ? winner_1_3 : state_1_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_4 = idle_1 ? winner_1_4 : state_1_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_5 = idle_1 ? winner_1_5 : state_1_5; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_6 = idle_1 ? winner_1_6 : state_1_6; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_7 = idle_1 ? winner_1_7 : state_1_7; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_8 = idle_1 ? winner_1_8 : state_1_8; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_9 = idle_1 ? winner_1_9 : state_1_9; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_10 = idle_1 ? winner_1_10 : state_1_10; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_11 = idle_1 ? winner_1_11 : state_1_11; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_12 = idle_1 ? winner_1_12 : state_1_12; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_13 = idle_1 ? winner_1_13 : state_1_13; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_14 = idle_1 ? winner_1_14 : state_1_14; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_15 = idle_1 ? winner_1_15 : state_1_15; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_16 = idle_1 ? winner_1_16 : state_1_16; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_17 = idle_1 ? winner_1_17 : state_1_17; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_18 = idle_1 ? winner_1_18 : state_1_18; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1_19 = idle_1 ? winner_1_19 : state_1_19; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_3 = idle_1 ? readys_1_3 : state_1_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_4 = idle_1 ? readys_1_4 : state_1_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_5 = idle_1 ? readys_1_5 : state_1_5; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_6 = idle_1 ? readys_1_6 : state_1_6; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_7 = idle_1 ? readys_1_7 : state_1_7; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_8 = idle_1 ? readys_1_8 : state_1_8; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_9 = idle_1 ? readys_1_9 : state_1_9; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_10 = idle_1 ? readys_1_10 : state_1_10; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_11 = idle_1 ? readys_1_11 : state_1_11; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_12 = idle_1 ? readys_1_12 : state_1_12; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_13 = idle_1 ? readys_1_13 : state_1_13; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_14 = idle_1 ? readys_1_14 : state_1_14; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_15 = idle_1 ? readys_1_15 : state_1_15; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_16 = idle_1 ? readys_1_16 : state_1_16; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_17 = idle_1 ? readys_1_17 : state_1_17; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_18 = idle_1 ? readys_1_18 : state_1_18; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1_19 = idle_1 ? readys_1_19 : state_1_19; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19]
assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_2 = out_1_a_ready & allowed_1_2; // @[Xbar.scala:216:19]
assign portsAOI_filtered_2_1_ready = _filtered_1_ready_T_2; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_3 = out_1_a_ready & allowed_1_3; // @[Xbar.scala:216:19]
assign portsAOI_filtered_3_1_ready = _filtered_1_ready_T_3; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_4 = out_1_a_ready & allowed_1_4; // @[Xbar.scala:216:19]
assign portsAOI_filtered_4_1_ready = _filtered_1_ready_T_4; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_5 = out_1_a_ready & allowed_1_5; // @[Xbar.scala:216:19]
assign portsAOI_filtered_5_1_ready = _filtered_1_ready_T_5; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_6 = out_1_a_ready & allowed_1_6; // @[Xbar.scala:216:19]
assign portsAOI_filtered_6_1_ready = _filtered_1_ready_T_6; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_7 = out_1_a_ready & allowed_1_7; // @[Xbar.scala:216:19]
assign portsAOI_filtered_7_1_ready = _filtered_1_ready_T_7; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_8 = out_1_a_ready & allowed_1_8; // @[Xbar.scala:216:19]
assign portsAOI_filtered_8_1_ready = _filtered_1_ready_T_8; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_9 = out_1_a_ready & allowed_1_9; // @[Xbar.scala:216:19]
assign portsAOI_filtered_9_1_ready = _filtered_1_ready_T_9; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_10 = out_1_a_ready & allowed_1_10; // @[Xbar.scala:216:19]
assign portsAOI_filtered_10_1_ready = _filtered_1_ready_T_10; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_11 = out_1_a_ready & allowed_1_11; // @[Xbar.scala:216:19]
assign portsAOI_filtered_11_1_ready = _filtered_1_ready_T_11; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_12 = out_1_a_ready & allowed_1_12; // @[Xbar.scala:216:19]
assign portsAOI_filtered_12_1_ready = _filtered_1_ready_T_12; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_13 = out_1_a_ready & allowed_1_13; // @[Xbar.scala:216:19]
assign portsAOI_filtered_13_1_ready = _filtered_1_ready_T_13; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_14 = out_1_a_ready & allowed_1_14; // @[Xbar.scala:216:19]
assign portsAOI_filtered_14_1_ready = _filtered_1_ready_T_14; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_15 = out_1_a_ready & allowed_1_15; // @[Xbar.scala:216:19]
assign portsAOI_filtered_15_1_ready = _filtered_1_ready_T_15; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_16 = out_1_a_ready & allowed_1_16; // @[Xbar.scala:216:19]
assign portsAOI_filtered_16_1_ready = _filtered_1_ready_T_16; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_17 = out_1_a_ready & allowed_1_17; // @[Xbar.scala:216:19]
assign portsAOI_filtered_17_1_ready = _filtered_1_ready_T_17; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_18 = out_1_a_ready & allowed_1_18; // @[Xbar.scala:216:19]
assign portsAOI_filtered_18_1_ready = _filtered_1_ready_T_18; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_19 = out_1_a_ready & allowed_1_19; // @[Xbar.scala:216:19]
assign portsAOI_filtered_19_1_ready = _filtered_1_ready_T_19; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_1 = _out_1_a_valid_T | portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_2 = _out_1_a_valid_T_1 | portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_3 = _out_1_a_valid_T_2 | portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_4 = _out_1_a_valid_T_3 | portsAOI_filtered_5_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_5 = _out_1_a_valid_T_4 | portsAOI_filtered_6_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_6 = _out_1_a_valid_T_5 | portsAOI_filtered_7_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_7 = _out_1_a_valid_T_6 | portsAOI_filtered_8_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_8 = _out_1_a_valid_T_7 | portsAOI_filtered_9_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_9 = _out_1_a_valid_T_8 | portsAOI_filtered_10_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_10 = _out_1_a_valid_T_9 | portsAOI_filtered_11_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_11 = _out_1_a_valid_T_10 | portsAOI_filtered_12_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_12 = _out_1_a_valid_T_11 | portsAOI_filtered_13_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_13 = _out_1_a_valid_T_12 | portsAOI_filtered_14_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_14 = _out_1_a_valid_T_13 | portsAOI_filtered_15_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_15 = _out_1_a_valid_T_14 | portsAOI_filtered_16_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_16 = _out_1_a_valid_T_15 | portsAOI_filtered_17_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_17 = _out_1_a_valid_T_16 | portsAOI_filtered_18_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_18 = _out_1_a_valid_T_17 | portsAOI_filtered_19_1_valid; // @[Xbar.scala:352:24]
wire _out_1_a_valid_T_19 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_20 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_21 = state_1_2 & portsAOI_filtered_2_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_22 = state_1_3 & portsAOI_filtered_3_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_23 = state_1_4 & portsAOI_filtered_4_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_24 = state_1_5 & portsAOI_filtered_5_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_25 = state_1_6 & portsAOI_filtered_6_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_26 = state_1_7 & portsAOI_filtered_7_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_27 = state_1_8 & portsAOI_filtered_8_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_28 = state_1_9 & portsAOI_filtered_9_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_29 = state_1_10 & portsAOI_filtered_10_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_30 = state_1_11 & portsAOI_filtered_11_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_31 = state_1_12 & portsAOI_filtered_12_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_32 = state_1_13 & portsAOI_filtered_13_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_33 = state_1_14 & portsAOI_filtered_14_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_34 = state_1_15 & portsAOI_filtered_15_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_35 = state_1_16 & portsAOI_filtered_16_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_36 = state_1_17 & portsAOI_filtered_17_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_37 = state_1_18 & portsAOI_filtered_18_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_38 = state_1_19 & portsAOI_filtered_19_1_valid; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_39 = _out_1_a_valid_T_19 | _out_1_a_valid_T_20; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_40 = _out_1_a_valid_T_39 | _out_1_a_valid_T_21; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_41 = _out_1_a_valid_T_40 | _out_1_a_valid_T_22; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_42 = _out_1_a_valid_T_41 | _out_1_a_valid_T_23; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_43 = _out_1_a_valid_T_42 | _out_1_a_valid_T_24; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_44 = _out_1_a_valid_T_43 | _out_1_a_valid_T_25; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_45 = _out_1_a_valid_T_44 | _out_1_a_valid_T_26; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_46 = _out_1_a_valid_T_45 | _out_1_a_valid_T_27; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_47 = _out_1_a_valid_T_46 | _out_1_a_valid_T_28; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_48 = _out_1_a_valid_T_47 | _out_1_a_valid_T_29; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_49 = _out_1_a_valid_T_48 | _out_1_a_valid_T_30; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_50 = _out_1_a_valid_T_49 | _out_1_a_valid_T_31; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_51 = _out_1_a_valid_T_50 | _out_1_a_valid_T_32; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_52 = _out_1_a_valid_T_51 | _out_1_a_valid_T_33; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_53 = _out_1_a_valid_T_52 | _out_1_a_valid_T_34; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_54 = _out_1_a_valid_T_53 | _out_1_a_valid_T_35; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_55 = _out_1_a_valid_T_54 | _out_1_a_valid_T_36; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_56 = _out_1_a_valid_T_55 | _out_1_a_valid_T_37; // @[Mux.scala:30:73]
wire _out_1_a_valid_T_57 = _out_1_a_valid_T_56 | _out_1_a_valid_T_38; // @[Mux.scala:30:73]
wire _out_1_a_valid_WIRE = _out_1_a_valid_T_57; // @[Mux.scala:30:73]
assign _out_1_a_valid_T_58 = idle_1 ? _out_1_a_valid_T_18 : _out_1_a_valid_WIRE; // @[Mux.scala:30:73]
assign out_1_a_valid = _out_1_a_valid_T_58; // @[Xbar.scala:216:19]
wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73]
assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73]
assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73]
assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73]
assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73]
assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73]
assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73]
assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73]
wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73]
assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_2 = muxState_1_2 & portsAOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_3 = muxState_1_3 & portsAOI_filtered_3_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_4 = muxState_1_4 & portsAOI_filtered_4_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_5 = muxState_1_5 & portsAOI_filtered_5_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_6 = muxState_1_6 & portsAOI_filtered_6_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_7 = muxState_1_7 & portsAOI_filtered_7_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_8 = muxState_1_8 & portsAOI_filtered_8_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_9 = muxState_1_9 & portsAOI_filtered_9_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_10 = muxState_1_10 & portsAOI_filtered_10_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_11 = muxState_1_11 & portsAOI_filtered_11_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_12 = muxState_1_12 & portsAOI_filtered_12_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_13 = muxState_1_13 & portsAOI_filtered_13_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_14 = muxState_1_14 & portsAOI_filtered_14_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_15 = muxState_1_15 & portsAOI_filtered_15_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_16 = muxState_1_16 & portsAOI_filtered_16_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_17 = muxState_1_17 & portsAOI_filtered_17_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_18 = muxState_1_18 & portsAOI_filtered_18_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_19 = muxState_1_19 & portsAOI_filtered_19_1_bits_corrupt; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_20 = _out_1_a_bits_T | _out_1_a_bits_T_1; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_21 = _out_1_a_bits_T_20 | _out_1_a_bits_T_2; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_22 = _out_1_a_bits_T_21 | _out_1_a_bits_T_3; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_23 = _out_1_a_bits_T_22 | _out_1_a_bits_T_4; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_24 = _out_1_a_bits_T_23 | _out_1_a_bits_T_5; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_25 = _out_1_a_bits_T_24 | _out_1_a_bits_T_6; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_26 = _out_1_a_bits_T_25 | _out_1_a_bits_T_7; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_27 = _out_1_a_bits_T_26 | _out_1_a_bits_T_8; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_28 = _out_1_a_bits_T_27 | _out_1_a_bits_T_9; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_29 = _out_1_a_bits_T_28 | _out_1_a_bits_T_10; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_30 = _out_1_a_bits_T_29 | _out_1_a_bits_T_11; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_31 = _out_1_a_bits_T_30 | _out_1_a_bits_T_12; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_32 = _out_1_a_bits_T_31 | _out_1_a_bits_T_13; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_33 = _out_1_a_bits_T_32 | _out_1_a_bits_T_14; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_34 = _out_1_a_bits_T_33 | _out_1_a_bits_T_15; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_35 = _out_1_a_bits_T_34 | _out_1_a_bits_T_16; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_36 = _out_1_a_bits_T_35 | _out_1_a_bits_T_17; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_37 = _out_1_a_bits_T_36 | _out_1_a_bits_T_18; // @[Mux.scala:30:73]
wire _out_1_a_bits_T_38 = _out_1_a_bits_T_37 | _out_1_a_bits_T_19; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_38; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_39 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_40 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_41 = muxState_1_2 ? portsAOI_filtered_2_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_42 = muxState_1_3 ? portsAOI_filtered_3_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_43 = muxState_1_4 ? portsAOI_filtered_4_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_44 = muxState_1_5 ? portsAOI_filtered_5_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_45 = muxState_1_6 ? portsAOI_filtered_6_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_46 = muxState_1_7 ? portsAOI_filtered_7_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_47 = muxState_1_8 ? portsAOI_filtered_8_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_48 = muxState_1_9 ? portsAOI_filtered_9_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_49 = muxState_1_10 ? portsAOI_filtered_10_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_50 = muxState_1_11 ? portsAOI_filtered_11_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_51 = muxState_1_12 ? portsAOI_filtered_12_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_52 = muxState_1_13 ? portsAOI_filtered_13_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_53 = muxState_1_14 ? portsAOI_filtered_14_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_54 = muxState_1_15 ? portsAOI_filtered_15_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_55 = muxState_1_16 ? portsAOI_filtered_16_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_56 = muxState_1_17 ? portsAOI_filtered_17_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_57 = muxState_1_18 ? portsAOI_filtered_18_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_58 = muxState_1_19 ? portsAOI_filtered_19_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_59 = _out_1_a_bits_T_39 | _out_1_a_bits_T_40; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_60 = _out_1_a_bits_T_59 | _out_1_a_bits_T_41; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_61 = _out_1_a_bits_T_60 | _out_1_a_bits_T_42; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_62 = _out_1_a_bits_T_61 | _out_1_a_bits_T_43; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_63 = _out_1_a_bits_T_62 | _out_1_a_bits_T_44; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_64 = _out_1_a_bits_T_63 | _out_1_a_bits_T_45; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_65 = _out_1_a_bits_T_64 | _out_1_a_bits_T_46; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_66 = _out_1_a_bits_T_65 | _out_1_a_bits_T_47; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_67 = _out_1_a_bits_T_66 | _out_1_a_bits_T_48; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_68 = _out_1_a_bits_T_67 | _out_1_a_bits_T_49; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_69 = _out_1_a_bits_T_68 | _out_1_a_bits_T_50; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_70 = _out_1_a_bits_T_69 | _out_1_a_bits_T_51; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_71 = _out_1_a_bits_T_70 | _out_1_a_bits_T_52; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_72 = _out_1_a_bits_T_71 | _out_1_a_bits_T_53; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_73 = _out_1_a_bits_T_72 | _out_1_a_bits_T_54; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_74 = _out_1_a_bits_T_73 | _out_1_a_bits_T_55; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_75 = _out_1_a_bits_T_74 | _out_1_a_bits_T_56; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_76 = _out_1_a_bits_T_75 | _out_1_a_bits_T_57; // @[Mux.scala:30:73]
wire [63:0] _out_1_a_bits_T_77 = _out_1_a_bits_T_76 | _out_1_a_bits_T_58; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_77; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_78 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_79 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_80 = muxState_1_2 ? portsAOI_filtered_2_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_81 = muxState_1_3 ? portsAOI_filtered_3_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_82 = muxState_1_4 ? portsAOI_filtered_4_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_83 = muxState_1_5 ? portsAOI_filtered_5_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_84 = muxState_1_6 ? portsAOI_filtered_6_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_85 = muxState_1_7 ? portsAOI_filtered_7_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_86 = muxState_1_8 ? portsAOI_filtered_8_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_87 = muxState_1_9 ? portsAOI_filtered_9_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_88 = muxState_1_10 ? portsAOI_filtered_10_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_89 = muxState_1_11 ? portsAOI_filtered_11_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_90 = muxState_1_12 ? portsAOI_filtered_12_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_91 = muxState_1_13 ? portsAOI_filtered_13_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_92 = muxState_1_14 ? portsAOI_filtered_14_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_93 = muxState_1_15 ? portsAOI_filtered_15_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_94 = muxState_1_16 ? portsAOI_filtered_16_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_95 = muxState_1_17 ? portsAOI_filtered_17_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_96 = muxState_1_18 ? portsAOI_filtered_18_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_97 = muxState_1_19 ? portsAOI_filtered_19_1_bits_mask : 8'h0; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_98 = _out_1_a_bits_T_78 | _out_1_a_bits_T_79; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_99 = _out_1_a_bits_T_98 | _out_1_a_bits_T_80; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_100 = _out_1_a_bits_T_99 | _out_1_a_bits_T_81; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_101 = _out_1_a_bits_T_100 | _out_1_a_bits_T_82; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_102 = _out_1_a_bits_T_101 | _out_1_a_bits_T_83; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_103 = _out_1_a_bits_T_102 | _out_1_a_bits_T_84; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_104 = _out_1_a_bits_T_103 | _out_1_a_bits_T_85; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_105 = _out_1_a_bits_T_104 | _out_1_a_bits_T_86; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_106 = _out_1_a_bits_T_105 | _out_1_a_bits_T_87; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_107 = _out_1_a_bits_T_106 | _out_1_a_bits_T_88; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_108 = _out_1_a_bits_T_107 | _out_1_a_bits_T_89; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_109 = _out_1_a_bits_T_108 | _out_1_a_bits_T_90; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_110 = _out_1_a_bits_T_109 | _out_1_a_bits_T_91; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_111 = _out_1_a_bits_T_110 | _out_1_a_bits_T_92; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_112 = _out_1_a_bits_T_111 | _out_1_a_bits_T_93; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_113 = _out_1_a_bits_T_112 | _out_1_a_bits_T_94; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_114 = _out_1_a_bits_T_113 | _out_1_a_bits_T_95; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_115 = _out_1_a_bits_T_114 | _out_1_a_bits_T_96; // @[Mux.scala:30:73]
wire [7:0] _out_1_a_bits_T_116 = _out_1_a_bits_T_115 | _out_1_a_bits_T_97; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_116; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_117 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_118 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_119 = muxState_1_2 ? portsAOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_120 = muxState_1_3 ? portsAOI_filtered_3_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_121 = muxState_1_4 ? portsAOI_filtered_4_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_122 = muxState_1_5 ? portsAOI_filtered_5_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_123 = muxState_1_6 ? portsAOI_filtered_6_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_124 = muxState_1_7 ? portsAOI_filtered_7_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_125 = muxState_1_8 ? portsAOI_filtered_8_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_126 = muxState_1_9 ? portsAOI_filtered_9_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_127 = muxState_1_10 ? portsAOI_filtered_10_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_128 = muxState_1_11 ? portsAOI_filtered_11_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_129 = muxState_1_12 ? portsAOI_filtered_12_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_130 = muxState_1_13 ? portsAOI_filtered_13_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_131 = muxState_1_14 ? portsAOI_filtered_14_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_132 = muxState_1_15 ? portsAOI_filtered_15_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_133 = muxState_1_16 ? portsAOI_filtered_16_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_134 = muxState_1_17 ? portsAOI_filtered_17_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_135 = muxState_1_18 ? portsAOI_filtered_18_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_136 = muxState_1_19 ? portsAOI_filtered_19_1_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_137 = _out_1_a_bits_T_117 | _out_1_a_bits_T_118; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_138 = _out_1_a_bits_T_137 | _out_1_a_bits_T_119; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_139 = _out_1_a_bits_T_138 | _out_1_a_bits_T_120; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_140 = _out_1_a_bits_T_139 | _out_1_a_bits_T_121; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_141 = _out_1_a_bits_T_140 | _out_1_a_bits_T_122; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_142 = _out_1_a_bits_T_141 | _out_1_a_bits_T_123; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_143 = _out_1_a_bits_T_142 | _out_1_a_bits_T_124; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_144 = _out_1_a_bits_T_143 | _out_1_a_bits_T_125; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_145 = _out_1_a_bits_T_144 | _out_1_a_bits_T_126; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_146 = _out_1_a_bits_T_145 | _out_1_a_bits_T_127; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_147 = _out_1_a_bits_T_146 | _out_1_a_bits_T_128; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_148 = _out_1_a_bits_T_147 | _out_1_a_bits_T_129; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_149 = _out_1_a_bits_T_148 | _out_1_a_bits_T_130; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_150 = _out_1_a_bits_T_149 | _out_1_a_bits_T_131; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_151 = _out_1_a_bits_T_150 | _out_1_a_bits_T_132; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_152 = _out_1_a_bits_T_151 | _out_1_a_bits_T_133; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_153 = _out_1_a_bits_T_152 | _out_1_a_bits_T_134; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_154 = _out_1_a_bits_T_153 | _out_1_a_bits_T_135; // @[Mux.scala:30:73]
wire [31:0] _out_1_a_bits_T_155 = _out_1_a_bits_T_154 | _out_1_a_bits_T_136; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_155; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_156 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_157 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_158 = muxState_1_2 ? portsAOI_filtered_2_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_159 = muxState_1_3 ? portsAOI_filtered_3_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_160 = muxState_1_4 ? portsAOI_filtered_4_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_161 = muxState_1_5 ? portsAOI_filtered_5_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_162 = muxState_1_6 ? portsAOI_filtered_6_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_163 = muxState_1_7 ? portsAOI_filtered_7_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_164 = muxState_1_8 ? portsAOI_filtered_8_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_165 = muxState_1_9 ? portsAOI_filtered_9_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_166 = muxState_1_10 ? portsAOI_filtered_10_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_167 = muxState_1_11 ? portsAOI_filtered_11_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_168 = muxState_1_12 ? portsAOI_filtered_12_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_169 = muxState_1_13 ? portsAOI_filtered_13_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_170 = muxState_1_14 ? portsAOI_filtered_14_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_171 = muxState_1_15 ? portsAOI_filtered_15_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_172 = muxState_1_16 ? portsAOI_filtered_16_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_173 = muxState_1_17 ? portsAOI_filtered_17_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_174 = muxState_1_18 ? portsAOI_filtered_18_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_175 = muxState_1_19 ? portsAOI_filtered_19_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_176 = _out_1_a_bits_T_156 | _out_1_a_bits_T_157; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_177 = _out_1_a_bits_T_176 | _out_1_a_bits_T_158; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_178 = _out_1_a_bits_T_177 | _out_1_a_bits_T_159; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_179 = _out_1_a_bits_T_178 | _out_1_a_bits_T_160; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_180 = _out_1_a_bits_T_179 | _out_1_a_bits_T_161; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_181 = _out_1_a_bits_T_180 | _out_1_a_bits_T_162; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_182 = _out_1_a_bits_T_181 | _out_1_a_bits_T_163; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_183 = _out_1_a_bits_T_182 | _out_1_a_bits_T_164; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_184 = _out_1_a_bits_T_183 | _out_1_a_bits_T_165; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_185 = _out_1_a_bits_T_184 | _out_1_a_bits_T_166; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_186 = _out_1_a_bits_T_185 | _out_1_a_bits_T_167; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_187 = _out_1_a_bits_T_186 | _out_1_a_bits_T_168; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_188 = _out_1_a_bits_T_187 | _out_1_a_bits_T_169; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_189 = _out_1_a_bits_T_188 | _out_1_a_bits_T_170; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_190 = _out_1_a_bits_T_189 | _out_1_a_bits_T_171; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_191 = _out_1_a_bits_T_190 | _out_1_a_bits_T_172; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_192 = _out_1_a_bits_T_191 | _out_1_a_bits_T_173; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_193 = _out_1_a_bits_T_192 | _out_1_a_bits_T_174; // @[Mux.scala:30:73]
wire [8:0] _out_1_a_bits_T_194 = _out_1_a_bits_T_193 | _out_1_a_bits_T_175; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_194; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_195 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_196 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_197 = muxState_1_2 ? portsAOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_198 = muxState_1_3 ? portsAOI_filtered_3_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_199 = muxState_1_4 ? portsAOI_filtered_4_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_200 = muxState_1_5 ? portsAOI_filtered_5_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_201 = muxState_1_6 ? portsAOI_filtered_6_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_202 = muxState_1_7 ? portsAOI_filtered_7_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_203 = muxState_1_8 ? portsAOI_filtered_8_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_204 = muxState_1_9 ? portsAOI_filtered_9_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_205 = muxState_1_10 ? portsAOI_filtered_10_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_206 = muxState_1_11 ? portsAOI_filtered_11_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_207 = muxState_1_12 ? portsAOI_filtered_12_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_208 = muxState_1_13 ? portsAOI_filtered_13_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_209 = muxState_1_14 ? portsAOI_filtered_14_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_210 = muxState_1_15 ? portsAOI_filtered_15_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_211 = muxState_1_16 ? portsAOI_filtered_16_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_212 = muxState_1_17 ? portsAOI_filtered_17_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_213 = muxState_1_18 ? portsAOI_filtered_18_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_214 = muxState_1_19 ? portsAOI_filtered_19_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_215 = _out_1_a_bits_T_195 | _out_1_a_bits_T_196; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_216 = _out_1_a_bits_T_215 | _out_1_a_bits_T_197; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_217 = _out_1_a_bits_T_216 | _out_1_a_bits_T_198; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_218 = _out_1_a_bits_T_217 | _out_1_a_bits_T_199; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_219 = _out_1_a_bits_T_218 | _out_1_a_bits_T_200; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_220 = _out_1_a_bits_T_219 | _out_1_a_bits_T_201; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_221 = _out_1_a_bits_T_220 | _out_1_a_bits_T_202; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_222 = _out_1_a_bits_T_221 | _out_1_a_bits_T_203; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_223 = _out_1_a_bits_T_222 | _out_1_a_bits_T_204; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_224 = _out_1_a_bits_T_223 | _out_1_a_bits_T_205; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_225 = _out_1_a_bits_T_224 | _out_1_a_bits_T_206; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_226 = _out_1_a_bits_T_225 | _out_1_a_bits_T_207; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_227 = _out_1_a_bits_T_226 | _out_1_a_bits_T_208; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_228 = _out_1_a_bits_T_227 | _out_1_a_bits_T_209; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_229 = _out_1_a_bits_T_228 | _out_1_a_bits_T_210; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_230 = _out_1_a_bits_T_229 | _out_1_a_bits_T_211; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_231 = _out_1_a_bits_T_230 | _out_1_a_bits_T_212; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_232 = _out_1_a_bits_T_231 | _out_1_a_bits_T_213; // @[Mux.scala:30:73]
wire [3:0] _out_1_a_bits_T_233 = _out_1_a_bits_T_232 | _out_1_a_bits_T_214; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_233; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_234 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_235 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_236 = muxState_1_2 ? portsAOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_237 = muxState_1_3 ? portsAOI_filtered_3_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_238 = muxState_1_4 ? portsAOI_filtered_4_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_239 = muxState_1_5 ? portsAOI_filtered_5_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_240 = muxState_1_6 ? portsAOI_filtered_6_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_241 = muxState_1_7 ? portsAOI_filtered_7_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_242 = muxState_1_8 ? portsAOI_filtered_8_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_243 = muxState_1_9 ? portsAOI_filtered_9_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_244 = muxState_1_10 ? portsAOI_filtered_10_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_245 = muxState_1_11 ? portsAOI_filtered_11_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_246 = muxState_1_12 ? portsAOI_filtered_12_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_247 = muxState_1_13 ? portsAOI_filtered_13_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_248 = muxState_1_14 ? portsAOI_filtered_14_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_249 = muxState_1_15 ? portsAOI_filtered_15_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_250 = muxState_1_16 ? portsAOI_filtered_16_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_251 = muxState_1_17 ? portsAOI_filtered_17_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_252 = muxState_1_18 ? portsAOI_filtered_18_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_253 = muxState_1_19 ? portsAOI_filtered_19_1_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_254 = _out_1_a_bits_T_234 | _out_1_a_bits_T_235; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_255 = _out_1_a_bits_T_254 | _out_1_a_bits_T_236; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_256 = _out_1_a_bits_T_255 | _out_1_a_bits_T_237; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_257 = _out_1_a_bits_T_256 | _out_1_a_bits_T_238; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_258 = _out_1_a_bits_T_257 | _out_1_a_bits_T_239; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_259 = _out_1_a_bits_T_258 | _out_1_a_bits_T_240; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_260 = _out_1_a_bits_T_259 | _out_1_a_bits_T_241; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_261 = _out_1_a_bits_T_260 | _out_1_a_bits_T_242; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_262 = _out_1_a_bits_T_261 | _out_1_a_bits_T_243; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_263 = _out_1_a_bits_T_262 | _out_1_a_bits_T_244; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_264 = _out_1_a_bits_T_263 | _out_1_a_bits_T_245; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_265 = _out_1_a_bits_T_264 | _out_1_a_bits_T_246; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_266 = _out_1_a_bits_T_265 | _out_1_a_bits_T_247; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_267 = _out_1_a_bits_T_266 | _out_1_a_bits_T_248; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_268 = _out_1_a_bits_T_267 | _out_1_a_bits_T_249; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_269 = _out_1_a_bits_T_268 | _out_1_a_bits_T_250; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_270 = _out_1_a_bits_T_269 | _out_1_a_bits_T_251; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_271 = _out_1_a_bits_T_270 | _out_1_a_bits_T_252; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_272 = _out_1_a_bits_T_271 | _out_1_a_bits_T_253; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_272; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_273 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_274 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_275 = muxState_1_2 ? portsAOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_276 = muxState_1_3 ? portsAOI_filtered_3_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_277 = muxState_1_4 ? portsAOI_filtered_4_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_278 = muxState_1_5 ? portsAOI_filtered_5_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_279 = muxState_1_6 ? portsAOI_filtered_6_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_280 = muxState_1_7 ? portsAOI_filtered_7_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_281 = muxState_1_8 ? portsAOI_filtered_8_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_282 = muxState_1_9 ? portsAOI_filtered_9_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_283 = muxState_1_10 ? portsAOI_filtered_10_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_284 = muxState_1_11 ? portsAOI_filtered_11_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_285 = muxState_1_12 ? portsAOI_filtered_12_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_286 = muxState_1_13 ? portsAOI_filtered_13_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_287 = muxState_1_14 ? portsAOI_filtered_14_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_288 = muxState_1_15 ? portsAOI_filtered_15_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_289 = muxState_1_16 ? portsAOI_filtered_16_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_290 = muxState_1_17 ? portsAOI_filtered_17_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_291 = muxState_1_18 ? portsAOI_filtered_18_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_292 = muxState_1_19 ? portsAOI_filtered_19_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_293 = _out_1_a_bits_T_273 | _out_1_a_bits_T_274; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_294 = _out_1_a_bits_T_293 | _out_1_a_bits_T_275; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_295 = _out_1_a_bits_T_294 | _out_1_a_bits_T_276; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_296 = _out_1_a_bits_T_295 | _out_1_a_bits_T_277; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_297 = _out_1_a_bits_T_296 | _out_1_a_bits_T_278; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_298 = _out_1_a_bits_T_297 | _out_1_a_bits_T_279; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_299 = _out_1_a_bits_T_298 | _out_1_a_bits_T_280; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_300 = _out_1_a_bits_T_299 | _out_1_a_bits_T_281; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_301 = _out_1_a_bits_T_300 | _out_1_a_bits_T_282; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_302 = _out_1_a_bits_T_301 | _out_1_a_bits_T_283; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_303 = _out_1_a_bits_T_302 | _out_1_a_bits_T_284; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_304 = _out_1_a_bits_T_303 | _out_1_a_bits_T_285; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_305 = _out_1_a_bits_T_304 | _out_1_a_bits_T_286; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_306 = _out_1_a_bits_T_305 | _out_1_a_bits_T_287; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_307 = _out_1_a_bits_T_306 | _out_1_a_bits_T_288; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_308 = _out_1_a_bits_T_307 | _out_1_a_bits_T_289; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_309 = _out_1_a_bits_T_308 | _out_1_a_bits_T_290; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_310 = _out_1_a_bits_T_309 | _out_1_a_bits_T_291; // @[Mux.scala:30:73]
wire [2:0] _out_1_a_bits_T_311 = _out_1_a_bits_T_310 | _out_1_a_bits_T_292; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_311; // @[Mux.scala:30:73]
assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_2 = idle_2 & in_0_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_56 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_2 = _readys_T_56; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_57 = readys_valid_2 == _readys_T_56; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_59 = ~_readys_T_58; // @[Arbiter.scala:22:12]
wire _readys_T_60 = ~_readys_T_57; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_26 = readys_filter_2[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_27 = {readys_filter_2[3], readys_filter_2[2:0] | _readys_unready_T_26}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_28 = _readys_unready_T_27; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_29 = _readys_unready_T_28[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_30 = {readys_mask_2, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_2 = {1'h0, _readys_unready_T_29} | _readys_unready_T_30; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_6 = readys_unready_2[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_7 = readys_unready_2[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_63 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_61 = |readys_valid_2; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_62 = latch_2 & _readys_T_61; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_34 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_35 = {_readys_mask_T_34, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_36 = _readys_mask_T_35[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_37 = _readys_mask_T_34 | _readys_mask_T_36; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_38 = _readys_mask_T_37; // @[package.scala:253:43, :254:17]
wire _readys_T_64 = _readys_T_63[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2_0 = _readys_T_64; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_65 = _readys_T_63[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2_1 = _readys_T_65; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_40 = readys_2_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_2_0 = _winner_T_40; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_41 = readys_2_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_2_1 = _winner_T_41; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_2 = winner_2_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_2 = winner_2_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_2 = {maskedBeats_0_2[8:3], maskedBeats_0_2[2:0] | maskedBeats_1_2}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_8 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {9'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_10 = _beatsLeft_T_9[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_0_ready_T_20 = in_0_d_ready & allowed_2_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_0_ready = _filtered_0_ready_T_20; // @[Xbar.scala:352:24]
assign _filtered_0_ready_T_21 = in_0_d_ready & allowed_2_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_21; // @[Xbar.scala:352:24]
wire _in_0_d_valid_T_1 = state_2_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_valid_T_2 = state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 | _in_0_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_0_d_valid_T_4 = idle_2 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T = muxState_2_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_1 = muxState_2_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = _in_0_d_bits_T | _in_0_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_3 = muxState_2_0 ? portsDIO_filtered_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_4 = muxState_2_1 ? portsDIO_filtered_1_0_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 | _in_0_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_6 = muxState_2_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_7 = muxState_2_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 | _in_0_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_9 = muxState_2_0 ? portsDIO_filtered_0_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_10 = muxState_2_1 ? portsDIO_filtered_1_0_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 | _in_0_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_0_d_bits_T_12 = muxState_2_0 ? portsDIO_filtered_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_0_d_bits_T_13 = muxState_2_1 ? portsDIO_filtered_1_0_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 | _in_0_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_15 = muxState_2_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_16 = muxState_2_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 | _in_0_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_18 = muxState_2_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_19 = muxState_2_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 | _in_0_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_21 = muxState_2_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_22 = muxState_2_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 | _in_0_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_3 = idle_3 & in_1_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_66 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_3 = _readys_T_66; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_67 = readys_valid_3 == _readys_T_66; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_69 = ~_readys_T_68; // @[Arbiter.scala:22:12]
wire _readys_T_70 = ~_readys_T_67; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_31 = readys_filter_3[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_32 = {readys_filter_3[3], readys_filter_3[2:0] | _readys_unready_T_31}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_33 = _readys_unready_T_32; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_34 = _readys_unready_T_33[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_35 = {readys_mask_3, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_3 = {1'h0, _readys_unready_T_34} | _readys_unready_T_35; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_9 = readys_unready_3[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_10 = readys_unready_3[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_73 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_71 = |readys_valid_3; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_72 = latch_3 & _readys_T_71; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_39 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_40 = {_readys_mask_T_39, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_41 = _readys_mask_T_40[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_42 = _readys_mask_T_39 | _readys_mask_T_41; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_43 = _readys_mask_T_42; // @[package.scala:253:43, :254:17]
wire _readys_T_74 = _readys_T_73[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3_0 = _readys_T_74; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_75 = _readys_T_73[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_3_1 = _readys_T_75; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_42 = readys_3_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
wire winner_3_0 = _winner_T_42; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_43 = readys_3_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire winner_3_1 = _winner_T_43; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_3 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_3 = winner_3_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_3 = winner_3_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_3 = {maskedBeats_0_3[8:3], maskedBeats_0_3[2:0] | maskedBeats_1_3}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_12 = in_1_d_ready & in_1_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_13 = {1'h0, beatsLeft_3} - {9'h0, _beatsLeft_T_12}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_14 = _beatsLeft_T_13[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_15 = latch_3 ? initBeats_3 : _beatsLeft_T_14; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_3_0; // @[Arbiter.scala:88:26]
reg state_3_1; // @[Arbiter.scala:88:26]
wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_3_0 = idle_3 ? readys_3_0 : state_3_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_3_1 = idle_3 ? readys_3_1 : state_3_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_1_ready_T_20 = in_1_d_ready & allowed_3_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_ready = _filtered_1_ready_T_20; // @[Xbar.scala:352:24]
assign _filtered_1_ready_T_21 = in_1_d_ready & allowed_3_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_1_ready = _filtered_1_ready_T_21; // @[Xbar.scala:352:24]
wire _in_1_d_valid_T_1 = state_3_0 & portsDIO_filtered_1_valid; // @[Mux.scala:30:73]
wire _in_1_d_valid_T_2 = state_3_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73]
wire _in_1_d_valid_T_3 = _in_1_d_valid_T_1 | _in_1_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_1_d_valid_WIRE = _in_1_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_1_d_valid_T_4 = idle_3 ? _in_1_d_valid_T : _in_1_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_1_d_valid = _in_1_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_1_d_bits_opcode = _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_1_d_bits_param = _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_1_d_bits_size = _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_1_d_bits_source = _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_1_d_bits_sink = _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_1_d_bits_denied = _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_1_d_bits_data = _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_1_d_bits_corrupt = _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_1_d_bits_T = muxState_3_0 & portsDIO_filtered_1_bits_corrupt; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_1 = muxState_3_1 & portsDIO_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_2 = _in_1_d_bits_T | _in_1_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_1 = _in_1_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_corrupt = _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_1_d_bits_T_3 = muxState_3_0 ? portsDIO_filtered_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_1_d_bits_T_4 = muxState_3_1 ? portsDIO_filtered_1_1_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_1_d_bits_T_5 = _in_1_d_bits_T_3 | _in_1_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_2 = _in_1_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_data = _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_6 = muxState_3_0 & portsDIO_filtered_1_bits_denied; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_7 = muxState_3_1 & portsDIO_filtered_1_1_bits_denied; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_8 = _in_1_d_bits_T_6 | _in_1_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_5 = _in_1_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_denied = _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_9 = muxState_3_0 ? portsDIO_filtered_1_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_10 = muxState_3_1 ? portsDIO_filtered_1_1_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_11 = _in_1_d_bits_T_9 | _in_1_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_6 = _in_1_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_sink = _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_1_d_bits_T_12 = muxState_3_0 ? portsDIO_filtered_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_1_d_bits_T_13 = muxState_3_1 ? portsDIO_filtered_1_1_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_1_d_bits_T_14 = _in_1_d_bits_T_12 | _in_1_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_7 = _in_1_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_source = _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_1_d_bits_T_15 = muxState_3_0 ? portsDIO_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_1_d_bits_T_16 = muxState_3_1 ? portsDIO_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_1_d_bits_T_17 = _in_1_d_bits_T_15 | _in_1_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_8 = _in_1_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_size = _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_1_d_bits_T_18 = muxState_3_0 ? portsDIO_filtered_1_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_1_d_bits_T_19 = muxState_3_1 ? portsDIO_filtered_1_1_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_1_d_bits_T_20 = _in_1_d_bits_T_18 | _in_1_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_9 = _in_1_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_param = _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_21 = muxState_3_0 ? portsDIO_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_22 = muxState_3_1 ? portsDIO_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_23 = _in_1_d_bits_T_21 | _in_1_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_10 = _in_1_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_1_d_bits_WIRE_opcode = _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_4; // @[Arbiter.scala:60:30]
wire idle_4 = beatsLeft_4 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_4 = idle_4 & in_2_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_76 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_4 = _readys_T_76; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_77 = readys_valid_4 == _readys_T_76; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_79 = ~_readys_T_78; // @[Arbiter.scala:22:12]
wire _readys_T_80 = ~_readys_T_77; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_8 = ~readys_mask_4; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_9 = readys_valid_4 & _readys_filter_T_8; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_4 = {_readys_filter_T_9, readys_valid_4}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_36 = readys_filter_4[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_37 = {readys_filter_4[3], readys_filter_4[2:0] | _readys_unready_T_36}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_38 = _readys_unready_T_37; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_39 = _readys_unready_T_38[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_40 = {readys_mask_4, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_4 = {1'h0, _readys_unready_T_39} | _readys_unready_T_40; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_12 = readys_unready_4[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_13 = readys_unready_4[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_14 = _readys_readys_T_12 & _readys_readys_T_13; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_4 = ~_readys_readys_T_14; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_83 = readys_readys_4; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_81 = |readys_valid_4; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_82 = latch_4 & _readys_T_81; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_44 = readys_readys_4 & readys_valid_4; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_45 = {_readys_mask_T_44, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_46 = _readys_mask_T_45[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_47 = _readys_mask_T_44 | _readys_mask_T_46; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_48 = _readys_mask_T_47; // @[package.scala:253:43, :254:17]
wire _readys_T_84 = _readys_T_83[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_4_0 = _readys_T_84; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_85 = _readys_T_83[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_4_1 = _readys_T_85; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_44 = readys_4_0 & portsDIO_filtered_2_valid; // @[Xbar.scala:352:24]
wire winner_4_0 = _winner_T_44; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_45 = readys_4_1 & portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24]
wire winner_4_1 = _winner_T_45; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_4 = winner_4_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_4 = prefixOR_1_4 | winner_4_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_2_d_valid_T = portsDIO_filtered_2_valid | portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_4 = winner_4_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_4 = winner_4_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_4 = {maskedBeats_0_4[8:3], maskedBeats_0_4[2:0] | maskedBeats_1_4}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_16 = in_2_d_ready & in_2_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_17 = {1'h0, beatsLeft_4} - {9'h0, _beatsLeft_T_16}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_18 = _beatsLeft_T_17[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_19 = latch_4 ? initBeats_4 : _beatsLeft_T_18; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_4_0; // @[Arbiter.scala:88:26]
reg state_4_1; // @[Arbiter.scala:88:26]
wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_4_0 = idle_4 ? readys_4_0 : state_4_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_4_1 = idle_4 ? readys_4_1 : state_4_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_2_ready_T = in_2_d_ready & allowed_4_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_2_ready = _filtered_2_ready_T; // @[Xbar.scala:352:24]
assign _filtered_2_ready_T_1 = in_2_d_ready & allowed_4_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_2_ready = _filtered_2_ready_T_1; // @[Xbar.scala:352:24]
wire _in_2_d_valid_T_1 = state_4_0 & portsDIO_filtered_2_valid; // @[Mux.scala:30:73]
wire _in_2_d_valid_T_2 = state_4_1 & portsDIO_filtered_1_2_valid; // @[Mux.scala:30:73]
wire _in_2_d_valid_T_3 = _in_2_d_valid_T_1 | _in_2_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_2_d_valid_WIRE = _in_2_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_2_d_valid_T_4 = idle_4 ? _in_2_d_valid_T : _in_2_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_2_d_valid = _in_2_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_2_d_bits_opcode = _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_2_d_bits_param = _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_2_d_bits_size = _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_2_d_bits_source = _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_2_d_bits_sink = _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_2_d_bits_denied = _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_2_d_bits_data = _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_2_d_bits_corrupt = _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_2_d_bits_T = muxState_4_0 & portsDIO_filtered_2_bits_corrupt; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_1 = muxState_4_1 & portsDIO_filtered_1_2_bits_corrupt; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_2 = _in_2_d_bits_T | _in_2_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_1 = _in_2_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_corrupt = _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_2_d_bits_T_3 = muxState_4_0 ? portsDIO_filtered_2_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_2_d_bits_T_4 = muxState_4_1 ? portsDIO_filtered_1_2_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_2_d_bits_T_5 = _in_2_d_bits_T_3 | _in_2_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_2 = _in_2_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_data = _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_6 = muxState_4_0 & portsDIO_filtered_2_bits_denied; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_7 = muxState_4_1 & portsDIO_filtered_1_2_bits_denied; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_8 = _in_2_d_bits_T_6 | _in_2_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_5 = _in_2_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_denied = _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_9 = muxState_4_0 ? portsDIO_filtered_2_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_10 = muxState_4_1 ? portsDIO_filtered_1_2_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_11 = _in_2_d_bits_T_9 | _in_2_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_6 = _in_2_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_sink = _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_2_d_bits_T_12 = muxState_4_0 ? portsDIO_filtered_2_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_2_d_bits_T_13 = muxState_4_1 ? portsDIO_filtered_1_2_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_2_d_bits_T_14 = _in_2_d_bits_T_12 | _in_2_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_7 = _in_2_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_source = _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_2_d_bits_T_15 = muxState_4_0 ? portsDIO_filtered_2_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_2_d_bits_T_16 = muxState_4_1 ? portsDIO_filtered_1_2_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_2_d_bits_T_17 = _in_2_d_bits_T_15 | _in_2_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_8 = _in_2_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_size = _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_2_d_bits_T_18 = muxState_4_0 ? portsDIO_filtered_2_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_2_d_bits_T_19 = muxState_4_1 ? portsDIO_filtered_1_2_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_2_d_bits_T_20 = _in_2_d_bits_T_18 | _in_2_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_9 = _in_2_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_param = _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_21 = muxState_4_0 ? portsDIO_filtered_2_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_22 = muxState_4_1 ? portsDIO_filtered_1_2_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_23 = _in_2_d_bits_T_21 | _in_2_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_10 = _in_2_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_2_d_bits_WIRE_opcode = _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_5; // @[Arbiter.scala:60:30]
wire idle_5 = beatsLeft_5 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_5 = idle_5 & in_3_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_86 = {portsDIO_filtered_1_3_valid, portsDIO_filtered_3_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_5 = _readys_T_86; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_87 = readys_valid_5 == _readys_T_86; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_89 = ~_readys_T_88; // @[Arbiter.scala:22:12]
wire _readys_T_90 = ~_readys_T_87; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_5; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_10 = ~readys_mask_5; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_11 = readys_valid_5 & _readys_filter_T_10; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_5 = {_readys_filter_T_11, readys_valid_5}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_41 = readys_filter_5[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_42 = {readys_filter_5[3], readys_filter_5[2:0] | _readys_unready_T_41}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_43 = _readys_unready_T_42; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_44 = _readys_unready_T_43[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_45 = {readys_mask_5, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_5 = {1'h0, _readys_unready_T_44} | _readys_unready_T_45; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_15 = readys_unready_5[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_16 = readys_unready_5[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_17 = _readys_readys_T_15 & _readys_readys_T_16; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_5 = ~_readys_readys_T_17; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_93 = readys_readys_5; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_91 = |readys_valid_5; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_92 = latch_5 & _readys_T_91; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_49 = readys_readys_5 & readys_valid_5; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_50 = {_readys_mask_T_49, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_51 = _readys_mask_T_50[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_52 = _readys_mask_T_49 | _readys_mask_T_51; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_53 = _readys_mask_T_52; // @[package.scala:253:43, :254:17]
wire _readys_T_94 = _readys_T_93[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_5_0 = _readys_T_94; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_95 = _readys_T_93[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_5_1 = _readys_T_95; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_46 = readys_5_0 & portsDIO_filtered_3_valid; // @[Xbar.scala:352:24]
wire winner_5_0 = _winner_T_46; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_47 = readys_5_1 & portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24]
wire winner_5_1 = _winner_T_47; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_5 = winner_5_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_5 = prefixOR_1_5 | winner_5_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_3_d_valid_T = portsDIO_filtered_3_valid | portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_5 = winner_5_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_5 = winner_5_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_5 = {maskedBeats_0_5[8:3], maskedBeats_0_5[2:0] | maskedBeats_1_5}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_20 = in_3_d_ready & in_3_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_21 = {1'h0, beatsLeft_5} - {9'h0, _beatsLeft_T_20}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_22 = _beatsLeft_T_21[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_23 = latch_5 ? initBeats_5 : _beatsLeft_T_22; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_5_0; // @[Arbiter.scala:88:26]
reg state_5_1; // @[Arbiter.scala:88:26]
wire muxState_5_0 = idle_5 ? winner_5_0 : state_5_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_5_0 = idle_5 ? readys_5_0 : state_5_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_5_1 = idle_5 ? readys_5_1 : state_5_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_3_ready_T = in_3_d_ready & allowed_5_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_3_ready = _filtered_3_ready_T; // @[Xbar.scala:352:24]
assign _filtered_3_ready_T_1 = in_3_d_ready & allowed_5_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_3_ready = _filtered_3_ready_T_1; // @[Xbar.scala:352:24]
wire _in_3_d_valid_T_1 = state_5_0 & portsDIO_filtered_3_valid; // @[Mux.scala:30:73]
wire _in_3_d_valid_T_2 = state_5_1 & portsDIO_filtered_1_3_valid; // @[Mux.scala:30:73]
wire _in_3_d_valid_T_3 = _in_3_d_valid_T_1 | _in_3_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_3_d_valid_WIRE = _in_3_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_3_d_valid_T_4 = idle_5 ? _in_3_d_valid_T : _in_3_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_3_d_valid = _in_3_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_3_d_bits_opcode = _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_3_d_bits_param = _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_3_d_bits_size = _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_3_d_bits_source = _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_3_d_bits_sink = _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_3_d_bits_denied = _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_3_d_bits_data = _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_3_d_bits_corrupt = _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_3_d_bits_T = muxState_5_0 & portsDIO_filtered_3_bits_corrupt; // @[Mux.scala:30:73]
wire _in_3_d_bits_T_1 = muxState_5_1 & portsDIO_filtered_1_3_bits_corrupt; // @[Mux.scala:30:73]
wire _in_3_d_bits_T_2 = _in_3_d_bits_T | _in_3_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_1 = _in_3_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_corrupt = _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_3_d_bits_T_3 = muxState_5_0 ? portsDIO_filtered_3_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_3_d_bits_T_4 = muxState_5_1 ? portsDIO_filtered_1_3_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_3_d_bits_T_5 = _in_3_d_bits_T_3 | _in_3_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_2 = _in_3_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_data = _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_3_d_bits_T_6 = muxState_5_0 & portsDIO_filtered_3_bits_denied; // @[Mux.scala:30:73]
wire _in_3_d_bits_T_7 = muxState_5_1 & portsDIO_filtered_1_3_bits_denied; // @[Mux.scala:30:73]
wire _in_3_d_bits_T_8 = _in_3_d_bits_T_6 | _in_3_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_5 = _in_3_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_denied = _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_9 = muxState_5_0 ? portsDIO_filtered_3_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_10 = muxState_5_1 ? portsDIO_filtered_1_3_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_11 = _in_3_d_bits_T_9 | _in_3_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_6 = _in_3_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_sink = _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_3_d_bits_T_12 = muxState_5_0 ? portsDIO_filtered_3_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_3_d_bits_T_13 = muxState_5_1 ? portsDIO_filtered_1_3_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_3_d_bits_T_14 = _in_3_d_bits_T_12 | _in_3_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_7 = _in_3_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_source = _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_3_d_bits_T_15 = muxState_5_0 ? portsDIO_filtered_3_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_3_d_bits_T_16 = muxState_5_1 ? portsDIO_filtered_1_3_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_3_d_bits_T_17 = _in_3_d_bits_T_15 | _in_3_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_8 = _in_3_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_size = _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_3_d_bits_T_18 = muxState_5_0 ? portsDIO_filtered_3_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_3_d_bits_T_19 = muxState_5_1 ? portsDIO_filtered_1_3_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_3_d_bits_T_20 = _in_3_d_bits_T_18 | _in_3_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_9 = _in_3_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_param = _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_21 = muxState_5_0 ? portsDIO_filtered_3_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_22 = muxState_5_1 ? portsDIO_filtered_1_3_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_3_d_bits_T_23 = _in_3_d_bits_T_21 | _in_3_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_10 = _in_3_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_3_d_bits_WIRE_opcode = _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_6; // @[Arbiter.scala:60:30]
wire idle_6 = beatsLeft_6 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_6 = idle_6 & in_4_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_96 = {portsDIO_filtered_1_4_valid, portsDIO_filtered_4_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_6 = _readys_T_96; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_97 = readys_valid_6 == _readys_T_96; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_99 = ~_readys_T_98; // @[Arbiter.scala:22:12]
wire _readys_T_100 = ~_readys_T_97; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_6; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_12 = ~readys_mask_6; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_13 = readys_valid_6 & _readys_filter_T_12; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_6 = {_readys_filter_T_13, readys_valid_6}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_46 = readys_filter_6[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_47 = {readys_filter_6[3], readys_filter_6[2:0] | _readys_unready_T_46}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_48 = _readys_unready_T_47; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_49 = _readys_unready_T_48[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_50 = {readys_mask_6, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_6 = {1'h0, _readys_unready_T_49} | _readys_unready_T_50; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_18 = readys_unready_6[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_19 = readys_unready_6[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_20 = _readys_readys_T_18 & _readys_readys_T_19; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_6 = ~_readys_readys_T_20; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_103 = readys_readys_6; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_101 = |readys_valid_6; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_102 = latch_6 & _readys_T_101; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_54 = readys_readys_6 & readys_valid_6; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_55 = {_readys_mask_T_54, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_56 = _readys_mask_T_55[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_57 = _readys_mask_T_54 | _readys_mask_T_56; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_58 = _readys_mask_T_57; // @[package.scala:253:43, :254:17]
wire _readys_T_104 = _readys_T_103[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_6_0 = _readys_T_104; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_105 = _readys_T_103[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_6_1 = _readys_T_105; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_48 = readys_6_0 & portsDIO_filtered_4_valid; // @[Xbar.scala:352:24]
wire winner_6_0 = _winner_T_48; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_49 = readys_6_1 & portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24]
wire winner_6_1 = _winner_T_49; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_6 = winner_6_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_6 = prefixOR_1_6 | winner_6_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_4_d_valid_T = portsDIO_filtered_4_valid | portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_6 = winner_6_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_6 = winner_6_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_6 = {maskedBeats_0_6[8:3], maskedBeats_0_6[2:0] | maskedBeats_1_6}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_24 = in_4_d_ready & in_4_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_25 = {1'h0, beatsLeft_6} - {9'h0, _beatsLeft_T_24}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_26 = _beatsLeft_T_25[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_27 = latch_6 ? initBeats_6 : _beatsLeft_T_26; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_6_0; // @[Arbiter.scala:88:26]
reg state_6_1; // @[Arbiter.scala:88:26]
wire muxState_6_0 = idle_6 ? winner_6_0 : state_6_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_6_1 = idle_6 ? winner_6_1 : state_6_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_6_0 = idle_6 ? readys_6_0 : state_6_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_6_1 = idle_6 ? readys_6_1 : state_6_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_4_ready_T = in_4_d_ready & allowed_6_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_4_ready = _filtered_4_ready_T; // @[Xbar.scala:352:24]
assign _filtered_4_ready_T_1 = in_4_d_ready & allowed_6_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_4_ready = _filtered_4_ready_T_1; // @[Xbar.scala:352:24]
wire _in_4_d_valid_T_1 = state_6_0 & portsDIO_filtered_4_valid; // @[Mux.scala:30:73]
wire _in_4_d_valid_T_2 = state_6_1 & portsDIO_filtered_1_4_valid; // @[Mux.scala:30:73]
wire _in_4_d_valid_T_3 = _in_4_d_valid_T_1 | _in_4_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_4_d_valid_WIRE = _in_4_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_4_d_valid_T_4 = idle_6 ? _in_4_d_valid_T : _in_4_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_4_d_valid = _in_4_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_4_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_4_d_bits_opcode = _in_4_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_4_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_4_d_bits_param = _in_4_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_4_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_4_d_bits_size = _in_4_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_4_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_4_d_bits_source = _in_4_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_4_d_bits_sink = _in_4_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_4_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_4_d_bits_denied = _in_4_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_4_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_4_d_bits_data = _in_4_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_4_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_4_d_bits_corrupt = _in_4_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_4_d_bits_T = muxState_6_0 & portsDIO_filtered_4_bits_corrupt; // @[Mux.scala:30:73]
wire _in_4_d_bits_T_1 = muxState_6_1 & portsDIO_filtered_1_4_bits_corrupt; // @[Mux.scala:30:73]
wire _in_4_d_bits_T_2 = _in_4_d_bits_T | _in_4_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_1 = _in_4_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_corrupt = _in_4_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_4_d_bits_T_3 = muxState_6_0 ? portsDIO_filtered_4_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_4_d_bits_T_4 = muxState_6_1 ? portsDIO_filtered_1_4_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_4_d_bits_T_5 = _in_4_d_bits_T_3 | _in_4_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_2 = _in_4_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_data = _in_4_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_4_d_bits_T_6 = muxState_6_0 & portsDIO_filtered_4_bits_denied; // @[Mux.scala:30:73]
wire _in_4_d_bits_T_7 = muxState_6_1 & portsDIO_filtered_1_4_bits_denied; // @[Mux.scala:30:73]
wire _in_4_d_bits_T_8 = _in_4_d_bits_T_6 | _in_4_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_5 = _in_4_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_denied = _in_4_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_9 = muxState_6_0 ? portsDIO_filtered_4_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_10 = muxState_6_1 ? portsDIO_filtered_1_4_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_11 = _in_4_d_bits_T_9 | _in_4_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_6 = _in_4_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_sink = _in_4_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_4_d_bits_T_12 = muxState_6_0 ? portsDIO_filtered_4_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_4_d_bits_T_13 = muxState_6_1 ? portsDIO_filtered_1_4_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_4_d_bits_T_14 = _in_4_d_bits_T_12 | _in_4_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_7 = _in_4_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_source = _in_4_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_4_d_bits_T_15 = muxState_6_0 ? portsDIO_filtered_4_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_4_d_bits_T_16 = muxState_6_1 ? portsDIO_filtered_1_4_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_4_d_bits_T_17 = _in_4_d_bits_T_15 | _in_4_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_8 = _in_4_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_size = _in_4_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_4_d_bits_T_18 = muxState_6_0 ? portsDIO_filtered_4_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_4_d_bits_T_19 = muxState_6_1 ? portsDIO_filtered_1_4_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_4_d_bits_T_20 = _in_4_d_bits_T_18 | _in_4_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_9 = _in_4_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_param = _in_4_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_21 = muxState_6_0 ? portsDIO_filtered_4_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_22 = muxState_6_1 ? portsDIO_filtered_1_4_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_4_d_bits_T_23 = _in_4_d_bits_T_21 | _in_4_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_10 = _in_4_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_4_d_bits_WIRE_opcode = _in_4_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_7; // @[Arbiter.scala:60:30]
wire idle_7 = beatsLeft_7 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_7 = idle_7 & in_5_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_106 = {portsDIO_filtered_1_5_valid, portsDIO_filtered_5_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_7 = _readys_T_106; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_107 = readys_valid_7 == _readys_T_106; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_109 = ~_readys_T_108; // @[Arbiter.scala:22:12]
wire _readys_T_110 = ~_readys_T_107; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_7; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_14 = ~readys_mask_7; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_15 = readys_valid_7 & _readys_filter_T_14; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_7 = {_readys_filter_T_15, readys_valid_7}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_51 = readys_filter_7[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_52 = {readys_filter_7[3], readys_filter_7[2:0] | _readys_unready_T_51}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_53 = _readys_unready_T_52; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_54 = _readys_unready_T_53[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_55 = {readys_mask_7, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_7 = {1'h0, _readys_unready_T_54} | _readys_unready_T_55; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_21 = readys_unready_7[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_22 = readys_unready_7[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_23 = _readys_readys_T_21 & _readys_readys_T_22; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_7 = ~_readys_readys_T_23; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_113 = readys_readys_7; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_111 = |readys_valid_7; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_112 = latch_7 & _readys_T_111; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_59 = readys_readys_7 & readys_valid_7; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_60 = {_readys_mask_T_59, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_61 = _readys_mask_T_60[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_62 = _readys_mask_T_59 | _readys_mask_T_61; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_63 = _readys_mask_T_62; // @[package.scala:253:43, :254:17]
wire _readys_T_114 = _readys_T_113[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_7_0 = _readys_T_114; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_115 = _readys_T_113[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_7_1 = _readys_T_115; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_50 = readys_7_0 & portsDIO_filtered_5_valid; // @[Xbar.scala:352:24]
wire winner_7_0 = _winner_T_50; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_51 = readys_7_1 & portsDIO_filtered_1_5_valid; // @[Xbar.scala:352:24]
wire winner_7_1 = _winner_T_51; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_7 = winner_7_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_7 = prefixOR_1_7 | winner_7_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_5_d_valid_T = portsDIO_filtered_5_valid | portsDIO_filtered_1_5_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_7 = winner_7_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_7 = winner_7_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_7 = {maskedBeats_0_7[8:3], maskedBeats_0_7[2:0] | maskedBeats_1_7}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_28 = in_5_d_ready & in_5_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_29 = {1'h0, beatsLeft_7} - {9'h0, _beatsLeft_T_28}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_30 = _beatsLeft_T_29[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_31 = latch_7 ? initBeats_7 : _beatsLeft_T_30; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_7_0; // @[Arbiter.scala:88:26]
reg state_7_1; // @[Arbiter.scala:88:26]
wire muxState_7_0 = idle_7 ? winner_7_0 : state_7_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_7_1 = idle_7 ? winner_7_1 : state_7_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_7_0 = idle_7 ? readys_7_0 : state_7_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_7_1 = idle_7 ? readys_7_1 : state_7_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_5_ready_T = in_5_d_ready & allowed_7_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_5_ready = _filtered_5_ready_T; // @[Xbar.scala:352:24]
assign _filtered_5_ready_T_1 = in_5_d_ready & allowed_7_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_5_ready = _filtered_5_ready_T_1; // @[Xbar.scala:352:24]
wire _in_5_d_valid_T_1 = state_7_0 & portsDIO_filtered_5_valid; // @[Mux.scala:30:73]
wire _in_5_d_valid_T_2 = state_7_1 & portsDIO_filtered_1_5_valid; // @[Mux.scala:30:73]
wire _in_5_d_valid_T_3 = _in_5_d_valid_T_1 | _in_5_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_5_d_valid_WIRE = _in_5_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_5_d_valid_T_4 = idle_7 ? _in_5_d_valid_T : _in_5_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_5_d_valid = _in_5_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_5_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_5_d_bits_opcode = _in_5_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_5_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_5_d_bits_param = _in_5_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_5_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_5_d_bits_size = _in_5_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_5_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_5_d_bits_source = _in_5_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_5_d_bits_sink = _in_5_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_5_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_5_d_bits_denied = _in_5_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_5_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_5_d_bits_data = _in_5_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_5_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_5_d_bits_corrupt = _in_5_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_5_d_bits_T = muxState_7_0 & portsDIO_filtered_5_bits_corrupt; // @[Mux.scala:30:73]
wire _in_5_d_bits_T_1 = muxState_7_1 & portsDIO_filtered_1_5_bits_corrupt; // @[Mux.scala:30:73]
wire _in_5_d_bits_T_2 = _in_5_d_bits_T | _in_5_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_1 = _in_5_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_corrupt = _in_5_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_5_d_bits_T_3 = muxState_7_0 ? portsDIO_filtered_5_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_5_d_bits_T_4 = muxState_7_1 ? portsDIO_filtered_1_5_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_5_d_bits_T_5 = _in_5_d_bits_T_3 | _in_5_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_2 = _in_5_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_data = _in_5_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_5_d_bits_T_6 = muxState_7_0 & portsDIO_filtered_5_bits_denied; // @[Mux.scala:30:73]
wire _in_5_d_bits_T_7 = muxState_7_1 & portsDIO_filtered_1_5_bits_denied; // @[Mux.scala:30:73]
wire _in_5_d_bits_T_8 = _in_5_d_bits_T_6 | _in_5_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_5 = _in_5_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_denied = _in_5_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_9 = muxState_7_0 ? portsDIO_filtered_5_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_10 = muxState_7_1 ? portsDIO_filtered_1_5_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_11 = _in_5_d_bits_T_9 | _in_5_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_6 = _in_5_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_sink = _in_5_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_5_d_bits_T_12 = muxState_7_0 ? portsDIO_filtered_5_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_5_d_bits_T_13 = muxState_7_1 ? portsDIO_filtered_1_5_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_5_d_bits_T_14 = _in_5_d_bits_T_12 | _in_5_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_7 = _in_5_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_source = _in_5_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_5_d_bits_T_15 = muxState_7_0 ? portsDIO_filtered_5_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_5_d_bits_T_16 = muxState_7_1 ? portsDIO_filtered_1_5_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_5_d_bits_T_17 = _in_5_d_bits_T_15 | _in_5_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_8 = _in_5_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_size = _in_5_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_5_d_bits_T_18 = muxState_7_0 ? portsDIO_filtered_5_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_5_d_bits_T_19 = muxState_7_1 ? portsDIO_filtered_1_5_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_5_d_bits_T_20 = _in_5_d_bits_T_18 | _in_5_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_9 = _in_5_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_param = _in_5_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_21 = muxState_7_0 ? portsDIO_filtered_5_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_22 = muxState_7_1 ? portsDIO_filtered_1_5_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_5_d_bits_T_23 = _in_5_d_bits_T_21 | _in_5_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_10 = _in_5_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_5_d_bits_WIRE_opcode = _in_5_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_8; // @[Arbiter.scala:60:30]
wire idle_8 = beatsLeft_8 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_8 = idle_8 & in_6_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_116 = {portsDIO_filtered_1_6_valid, portsDIO_filtered_6_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_8 = _readys_T_116; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_117 = readys_valid_8 == _readys_T_116; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_119 = ~_readys_T_118; // @[Arbiter.scala:22:12]
wire _readys_T_120 = ~_readys_T_117; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_8; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_16 = ~readys_mask_8; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_17 = readys_valid_8 & _readys_filter_T_16; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_8 = {_readys_filter_T_17, readys_valid_8}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_56 = readys_filter_8[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_57 = {readys_filter_8[3], readys_filter_8[2:0] | _readys_unready_T_56}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_58 = _readys_unready_T_57; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_59 = _readys_unready_T_58[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_60 = {readys_mask_8, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_8 = {1'h0, _readys_unready_T_59} | _readys_unready_T_60; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_24 = readys_unready_8[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_25 = readys_unready_8[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_26 = _readys_readys_T_24 & _readys_readys_T_25; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_8 = ~_readys_readys_T_26; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_123 = readys_readys_8; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_121 = |readys_valid_8; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_122 = latch_8 & _readys_T_121; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_64 = readys_readys_8 & readys_valid_8; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_65 = {_readys_mask_T_64, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_66 = _readys_mask_T_65[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_67 = _readys_mask_T_64 | _readys_mask_T_66; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_68 = _readys_mask_T_67; // @[package.scala:253:43, :254:17]
wire _readys_T_124 = _readys_T_123[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_8_0 = _readys_T_124; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_125 = _readys_T_123[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_8_1 = _readys_T_125; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_52 = readys_8_0 & portsDIO_filtered_6_valid; // @[Xbar.scala:352:24]
wire winner_8_0 = _winner_T_52; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_53 = readys_8_1 & portsDIO_filtered_1_6_valid; // @[Xbar.scala:352:24]
wire winner_8_1 = _winner_T_53; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_8 = winner_8_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_8 = prefixOR_1_8 | winner_8_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_6_d_valid_T = portsDIO_filtered_6_valid | portsDIO_filtered_1_6_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_8 = winner_8_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_8 = winner_8_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_8 = {maskedBeats_0_8[8:3], maskedBeats_0_8[2:0] | maskedBeats_1_8}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_32 = in_6_d_ready & in_6_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_33 = {1'h0, beatsLeft_8} - {9'h0, _beatsLeft_T_32}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_34 = _beatsLeft_T_33[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_35 = latch_8 ? initBeats_8 : _beatsLeft_T_34; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_8_0; // @[Arbiter.scala:88:26]
reg state_8_1; // @[Arbiter.scala:88:26]
wire muxState_8_0 = idle_8 ? winner_8_0 : state_8_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_8_1 = idle_8 ? winner_8_1 : state_8_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_8_0 = idle_8 ? readys_8_0 : state_8_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_8_1 = idle_8 ? readys_8_1 : state_8_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_6_ready_T = in_6_d_ready & allowed_8_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_6_ready = _filtered_6_ready_T; // @[Xbar.scala:352:24]
assign _filtered_6_ready_T_1 = in_6_d_ready & allowed_8_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_6_ready = _filtered_6_ready_T_1; // @[Xbar.scala:352:24]
wire _in_6_d_valid_T_1 = state_8_0 & portsDIO_filtered_6_valid; // @[Mux.scala:30:73]
wire _in_6_d_valid_T_2 = state_8_1 & portsDIO_filtered_1_6_valid; // @[Mux.scala:30:73]
wire _in_6_d_valid_T_3 = _in_6_d_valid_T_1 | _in_6_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_6_d_valid_WIRE = _in_6_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_6_d_valid_T_4 = idle_8 ? _in_6_d_valid_T : _in_6_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_6_d_valid = _in_6_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_6_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_6_d_bits_opcode = _in_6_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_6_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_6_d_bits_param = _in_6_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_6_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_6_d_bits_size = _in_6_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_6_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_6_d_bits_source = _in_6_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_6_d_bits_sink = _in_6_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_6_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_6_d_bits_denied = _in_6_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_6_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_6_d_bits_data = _in_6_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_6_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_6_d_bits_corrupt = _in_6_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_6_d_bits_T = muxState_8_0 & portsDIO_filtered_6_bits_corrupt; // @[Mux.scala:30:73]
wire _in_6_d_bits_T_1 = muxState_8_1 & portsDIO_filtered_1_6_bits_corrupt; // @[Mux.scala:30:73]
wire _in_6_d_bits_T_2 = _in_6_d_bits_T | _in_6_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_1 = _in_6_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_corrupt = _in_6_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_6_d_bits_T_3 = muxState_8_0 ? portsDIO_filtered_6_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_6_d_bits_T_4 = muxState_8_1 ? portsDIO_filtered_1_6_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_6_d_bits_T_5 = _in_6_d_bits_T_3 | _in_6_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_2 = _in_6_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_data = _in_6_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_6_d_bits_T_6 = muxState_8_0 & portsDIO_filtered_6_bits_denied; // @[Mux.scala:30:73]
wire _in_6_d_bits_T_7 = muxState_8_1 & portsDIO_filtered_1_6_bits_denied; // @[Mux.scala:30:73]
wire _in_6_d_bits_T_8 = _in_6_d_bits_T_6 | _in_6_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_5 = _in_6_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_denied = _in_6_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_9 = muxState_8_0 ? portsDIO_filtered_6_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_10 = muxState_8_1 ? portsDIO_filtered_1_6_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_11 = _in_6_d_bits_T_9 | _in_6_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_6 = _in_6_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_sink = _in_6_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_6_d_bits_T_12 = muxState_8_0 ? portsDIO_filtered_6_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_6_d_bits_T_13 = muxState_8_1 ? portsDIO_filtered_1_6_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_6_d_bits_T_14 = _in_6_d_bits_T_12 | _in_6_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_7 = _in_6_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_source = _in_6_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_6_d_bits_T_15 = muxState_8_0 ? portsDIO_filtered_6_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_6_d_bits_T_16 = muxState_8_1 ? portsDIO_filtered_1_6_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_6_d_bits_T_17 = _in_6_d_bits_T_15 | _in_6_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_8 = _in_6_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_size = _in_6_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_6_d_bits_T_18 = muxState_8_0 ? portsDIO_filtered_6_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_6_d_bits_T_19 = muxState_8_1 ? portsDIO_filtered_1_6_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_6_d_bits_T_20 = _in_6_d_bits_T_18 | _in_6_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_9 = _in_6_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_param = _in_6_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_21 = muxState_8_0 ? portsDIO_filtered_6_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_22 = muxState_8_1 ? portsDIO_filtered_1_6_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_6_d_bits_T_23 = _in_6_d_bits_T_21 | _in_6_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_10 = _in_6_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_6_d_bits_WIRE_opcode = _in_6_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_9; // @[Arbiter.scala:60:30]
wire idle_9 = beatsLeft_9 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_9 = idle_9 & in_7_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_126 = {portsDIO_filtered_1_7_valid, portsDIO_filtered_7_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_9 = _readys_T_126; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_127 = readys_valid_9 == _readys_T_126; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_129 = ~_readys_T_128; // @[Arbiter.scala:22:12]
wire _readys_T_130 = ~_readys_T_127; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_9; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_18 = ~readys_mask_9; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_19 = readys_valid_9 & _readys_filter_T_18; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_9 = {_readys_filter_T_19, readys_valid_9}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_61 = readys_filter_9[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_62 = {readys_filter_9[3], readys_filter_9[2:0] | _readys_unready_T_61}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_63 = _readys_unready_T_62; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_64 = _readys_unready_T_63[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_65 = {readys_mask_9, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_9 = {1'h0, _readys_unready_T_64} | _readys_unready_T_65; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_27 = readys_unready_9[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_28 = readys_unready_9[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_29 = _readys_readys_T_27 & _readys_readys_T_28; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_9 = ~_readys_readys_T_29; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_133 = readys_readys_9; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_131 = |readys_valid_9; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_132 = latch_9 & _readys_T_131; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_69 = readys_readys_9 & readys_valid_9; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_70 = {_readys_mask_T_69, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_71 = _readys_mask_T_70[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_72 = _readys_mask_T_69 | _readys_mask_T_71; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_73 = _readys_mask_T_72; // @[package.scala:253:43, :254:17]
wire _readys_T_134 = _readys_T_133[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_9_0 = _readys_T_134; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_135 = _readys_T_133[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_9_1 = _readys_T_135; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_54 = readys_9_0 & portsDIO_filtered_7_valid; // @[Xbar.scala:352:24]
wire winner_9_0 = _winner_T_54; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_55 = readys_9_1 & portsDIO_filtered_1_7_valid; // @[Xbar.scala:352:24]
wire winner_9_1 = _winner_T_55; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_9 = winner_9_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_9 = prefixOR_1_9 | winner_9_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_7_d_valid_T = portsDIO_filtered_7_valid | portsDIO_filtered_1_7_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_9 = winner_9_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_9 = winner_9_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_9 = {maskedBeats_0_9[8:3], maskedBeats_0_9[2:0] | maskedBeats_1_9}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_36 = in_7_d_ready & in_7_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_37 = {1'h0, beatsLeft_9} - {9'h0, _beatsLeft_T_36}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_38 = _beatsLeft_T_37[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_39 = latch_9 ? initBeats_9 : _beatsLeft_T_38; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_9_0; // @[Arbiter.scala:88:26]
reg state_9_1; // @[Arbiter.scala:88:26]
wire muxState_9_0 = idle_9 ? winner_9_0 : state_9_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_9_1 = idle_9 ? winner_9_1 : state_9_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_9_0 = idle_9 ? readys_9_0 : state_9_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_9_1 = idle_9 ? readys_9_1 : state_9_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_7_ready_T = in_7_d_ready & allowed_9_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_7_ready = _filtered_7_ready_T; // @[Xbar.scala:352:24]
assign _filtered_7_ready_T_1 = in_7_d_ready & allowed_9_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_7_ready = _filtered_7_ready_T_1; // @[Xbar.scala:352:24]
wire _in_7_d_valid_T_1 = state_9_0 & portsDIO_filtered_7_valid; // @[Mux.scala:30:73]
wire _in_7_d_valid_T_2 = state_9_1 & portsDIO_filtered_1_7_valid; // @[Mux.scala:30:73]
wire _in_7_d_valid_T_3 = _in_7_d_valid_T_1 | _in_7_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_7_d_valid_WIRE = _in_7_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_7_d_valid_T_4 = idle_9 ? _in_7_d_valid_T : _in_7_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_7_d_valid = _in_7_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_7_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_7_d_bits_opcode = _in_7_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_7_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_7_d_bits_param = _in_7_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_7_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_7_d_bits_size = _in_7_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_7_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_7_d_bits_source = _in_7_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_7_d_bits_sink = _in_7_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_7_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_7_d_bits_denied = _in_7_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_7_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_7_d_bits_data = _in_7_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_7_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_7_d_bits_corrupt = _in_7_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_7_d_bits_T = muxState_9_0 & portsDIO_filtered_7_bits_corrupt; // @[Mux.scala:30:73]
wire _in_7_d_bits_T_1 = muxState_9_1 & portsDIO_filtered_1_7_bits_corrupt; // @[Mux.scala:30:73]
wire _in_7_d_bits_T_2 = _in_7_d_bits_T | _in_7_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_1 = _in_7_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_corrupt = _in_7_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_7_d_bits_T_3 = muxState_9_0 ? portsDIO_filtered_7_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_7_d_bits_T_4 = muxState_9_1 ? portsDIO_filtered_1_7_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_7_d_bits_T_5 = _in_7_d_bits_T_3 | _in_7_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_2 = _in_7_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_data = _in_7_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_7_d_bits_T_6 = muxState_9_0 & portsDIO_filtered_7_bits_denied; // @[Mux.scala:30:73]
wire _in_7_d_bits_T_7 = muxState_9_1 & portsDIO_filtered_1_7_bits_denied; // @[Mux.scala:30:73]
wire _in_7_d_bits_T_8 = _in_7_d_bits_T_6 | _in_7_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_5 = _in_7_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_denied = _in_7_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_9 = muxState_9_0 ? portsDIO_filtered_7_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_10 = muxState_9_1 ? portsDIO_filtered_1_7_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_11 = _in_7_d_bits_T_9 | _in_7_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_6 = _in_7_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_sink = _in_7_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_7_d_bits_T_12 = muxState_9_0 ? portsDIO_filtered_7_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_7_d_bits_T_13 = muxState_9_1 ? portsDIO_filtered_1_7_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_7_d_bits_T_14 = _in_7_d_bits_T_12 | _in_7_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_7 = _in_7_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_source = _in_7_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_7_d_bits_T_15 = muxState_9_0 ? portsDIO_filtered_7_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_7_d_bits_T_16 = muxState_9_1 ? portsDIO_filtered_1_7_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_7_d_bits_T_17 = _in_7_d_bits_T_15 | _in_7_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_8 = _in_7_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_size = _in_7_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_7_d_bits_T_18 = muxState_9_0 ? portsDIO_filtered_7_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_7_d_bits_T_19 = muxState_9_1 ? portsDIO_filtered_1_7_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_7_d_bits_T_20 = _in_7_d_bits_T_18 | _in_7_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_9 = _in_7_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_param = _in_7_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_21 = muxState_9_0 ? portsDIO_filtered_7_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_22 = muxState_9_1 ? portsDIO_filtered_1_7_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_7_d_bits_T_23 = _in_7_d_bits_T_21 | _in_7_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_10 = _in_7_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_7_d_bits_WIRE_opcode = _in_7_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_10; // @[Arbiter.scala:60:30]
wire idle_10 = beatsLeft_10 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_10 = idle_10 & in_8_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_136 = {portsDIO_filtered_1_8_valid, portsDIO_filtered_8_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_10 = _readys_T_136; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_137 = readys_valid_10 == _readys_T_136; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_139 = ~_readys_T_138; // @[Arbiter.scala:22:12]
wire _readys_T_140 = ~_readys_T_137; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_10; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_20 = ~readys_mask_10; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_21 = readys_valid_10 & _readys_filter_T_20; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_10 = {_readys_filter_T_21, readys_valid_10}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_66 = readys_filter_10[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_67 = {readys_filter_10[3], readys_filter_10[2:0] | _readys_unready_T_66}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_68 = _readys_unready_T_67; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_69 = _readys_unready_T_68[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_70 = {readys_mask_10, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_10 = {1'h0, _readys_unready_T_69} | _readys_unready_T_70; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_30 = readys_unready_10[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_31 = readys_unready_10[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_32 = _readys_readys_T_30 & _readys_readys_T_31; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_10 = ~_readys_readys_T_32; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_143 = readys_readys_10; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_141 = |readys_valid_10; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_142 = latch_10 & _readys_T_141; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_74 = readys_readys_10 & readys_valid_10; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_75 = {_readys_mask_T_74, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_76 = _readys_mask_T_75[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_77 = _readys_mask_T_74 | _readys_mask_T_76; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_78 = _readys_mask_T_77; // @[package.scala:253:43, :254:17]
wire _readys_T_144 = _readys_T_143[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_10_0 = _readys_T_144; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_145 = _readys_T_143[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_10_1 = _readys_T_145; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_56 = readys_10_0 & portsDIO_filtered_8_valid; // @[Xbar.scala:352:24]
wire winner_10_0 = _winner_T_56; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_57 = readys_10_1 & portsDIO_filtered_1_8_valid; // @[Xbar.scala:352:24]
wire winner_10_1 = _winner_T_57; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_10 = winner_10_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_10 = prefixOR_1_10 | winner_10_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_8_d_valid_T = portsDIO_filtered_8_valid | portsDIO_filtered_1_8_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_10 = winner_10_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_10 = winner_10_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_10 = {maskedBeats_0_10[8:3], maskedBeats_0_10[2:0] | maskedBeats_1_10}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_40 = in_8_d_ready & in_8_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_41 = {1'h0, beatsLeft_10} - {9'h0, _beatsLeft_T_40}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_42 = _beatsLeft_T_41[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_43 = latch_10 ? initBeats_10 : _beatsLeft_T_42; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_10_0; // @[Arbiter.scala:88:26]
reg state_10_1; // @[Arbiter.scala:88:26]
wire muxState_10_0 = idle_10 ? winner_10_0 : state_10_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_10_1 = idle_10 ? winner_10_1 : state_10_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_10_0 = idle_10 ? readys_10_0 : state_10_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_10_1 = idle_10 ? readys_10_1 : state_10_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_8_ready_T = in_8_d_ready & allowed_10_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_8_ready = _filtered_8_ready_T; // @[Xbar.scala:352:24]
assign _filtered_8_ready_T_1 = in_8_d_ready & allowed_10_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_8_ready = _filtered_8_ready_T_1; // @[Xbar.scala:352:24]
wire _in_8_d_valid_T_1 = state_10_0 & portsDIO_filtered_8_valid; // @[Mux.scala:30:73]
wire _in_8_d_valid_T_2 = state_10_1 & portsDIO_filtered_1_8_valid; // @[Mux.scala:30:73]
wire _in_8_d_valid_T_3 = _in_8_d_valid_T_1 | _in_8_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_8_d_valid_WIRE = _in_8_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_8_d_valid_T_4 = idle_10 ? _in_8_d_valid_T : _in_8_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_8_d_valid = _in_8_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_8_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_8_d_bits_opcode = _in_8_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_8_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_8_d_bits_param = _in_8_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_8_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_8_d_bits_size = _in_8_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_8_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_8_d_bits_source = _in_8_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_8_d_bits_sink = _in_8_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_8_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_8_d_bits_denied = _in_8_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_8_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_8_d_bits_data = _in_8_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_8_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_8_d_bits_corrupt = _in_8_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_8_d_bits_T = muxState_10_0 & portsDIO_filtered_8_bits_corrupt; // @[Mux.scala:30:73]
wire _in_8_d_bits_T_1 = muxState_10_1 & portsDIO_filtered_1_8_bits_corrupt; // @[Mux.scala:30:73]
wire _in_8_d_bits_T_2 = _in_8_d_bits_T | _in_8_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_1 = _in_8_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_corrupt = _in_8_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_8_d_bits_T_3 = muxState_10_0 ? portsDIO_filtered_8_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_8_d_bits_T_4 = muxState_10_1 ? portsDIO_filtered_1_8_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_8_d_bits_T_5 = _in_8_d_bits_T_3 | _in_8_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_2 = _in_8_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_data = _in_8_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_8_d_bits_T_6 = muxState_10_0 & portsDIO_filtered_8_bits_denied; // @[Mux.scala:30:73]
wire _in_8_d_bits_T_7 = muxState_10_1 & portsDIO_filtered_1_8_bits_denied; // @[Mux.scala:30:73]
wire _in_8_d_bits_T_8 = _in_8_d_bits_T_6 | _in_8_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_5 = _in_8_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_denied = _in_8_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_9 = muxState_10_0 ? portsDIO_filtered_8_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_10 = muxState_10_1 ? portsDIO_filtered_1_8_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_11 = _in_8_d_bits_T_9 | _in_8_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_6 = _in_8_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_sink = _in_8_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_8_d_bits_T_12 = muxState_10_0 ? portsDIO_filtered_8_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_8_d_bits_T_13 = muxState_10_1 ? portsDIO_filtered_1_8_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_8_d_bits_T_14 = _in_8_d_bits_T_12 | _in_8_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_7 = _in_8_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_source = _in_8_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_8_d_bits_T_15 = muxState_10_0 ? portsDIO_filtered_8_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_8_d_bits_T_16 = muxState_10_1 ? portsDIO_filtered_1_8_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_8_d_bits_T_17 = _in_8_d_bits_T_15 | _in_8_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_8 = _in_8_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_size = _in_8_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_8_d_bits_T_18 = muxState_10_0 ? portsDIO_filtered_8_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_8_d_bits_T_19 = muxState_10_1 ? portsDIO_filtered_1_8_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_8_d_bits_T_20 = _in_8_d_bits_T_18 | _in_8_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_9 = _in_8_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_param = _in_8_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_21 = muxState_10_0 ? portsDIO_filtered_8_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_22 = muxState_10_1 ? portsDIO_filtered_1_8_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_8_d_bits_T_23 = _in_8_d_bits_T_21 | _in_8_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_10 = _in_8_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_8_d_bits_WIRE_opcode = _in_8_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_11; // @[Arbiter.scala:60:30]
wire idle_11 = beatsLeft_11 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_11 = idle_11 & in_9_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_146 = {portsDIO_filtered_1_9_valid, portsDIO_filtered_9_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_11 = _readys_T_146; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_147 = readys_valid_11 == _readys_T_146; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_149 = ~_readys_T_148; // @[Arbiter.scala:22:12]
wire _readys_T_150 = ~_readys_T_147; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_11; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_22 = ~readys_mask_11; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_23 = readys_valid_11 & _readys_filter_T_22; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_11 = {_readys_filter_T_23, readys_valid_11}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_71 = readys_filter_11[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_72 = {readys_filter_11[3], readys_filter_11[2:0] | _readys_unready_T_71}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_73 = _readys_unready_T_72; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_74 = _readys_unready_T_73[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_75 = {readys_mask_11, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_11 = {1'h0, _readys_unready_T_74} | _readys_unready_T_75; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_33 = readys_unready_11[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_34 = readys_unready_11[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_35 = _readys_readys_T_33 & _readys_readys_T_34; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_11 = ~_readys_readys_T_35; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_153 = readys_readys_11; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_151 = |readys_valid_11; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_152 = latch_11 & _readys_T_151; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_79 = readys_readys_11 & readys_valid_11; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_80 = {_readys_mask_T_79, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_81 = _readys_mask_T_80[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_82 = _readys_mask_T_79 | _readys_mask_T_81; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_83 = _readys_mask_T_82; // @[package.scala:253:43, :254:17]
wire _readys_T_154 = _readys_T_153[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_11_0 = _readys_T_154; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_155 = _readys_T_153[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_11_1 = _readys_T_155; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_58 = readys_11_0 & portsDIO_filtered_9_valid; // @[Xbar.scala:352:24]
wire winner_11_0 = _winner_T_58; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_59 = readys_11_1 & portsDIO_filtered_1_9_valid; // @[Xbar.scala:352:24]
wire winner_11_1 = _winner_T_59; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_11 = winner_11_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_11 = prefixOR_1_11 | winner_11_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_9_d_valid_T = portsDIO_filtered_9_valid | portsDIO_filtered_1_9_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_11 = winner_11_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_11 = winner_11_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_11 = {maskedBeats_0_11[8:3], maskedBeats_0_11[2:0] | maskedBeats_1_11}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_44 = in_9_d_ready & in_9_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_45 = {1'h0, beatsLeft_11} - {9'h0, _beatsLeft_T_44}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_46 = _beatsLeft_T_45[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_47 = latch_11 ? initBeats_11 : _beatsLeft_T_46; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_11_0; // @[Arbiter.scala:88:26]
reg state_11_1; // @[Arbiter.scala:88:26]
wire muxState_11_0 = idle_11 ? winner_11_0 : state_11_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_11_1 = idle_11 ? winner_11_1 : state_11_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_11_0 = idle_11 ? readys_11_0 : state_11_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_11_1 = idle_11 ? readys_11_1 : state_11_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_9_ready_T = in_9_d_ready & allowed_11_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_9_ready = _filtered_9_ready_T; // @[Xbar.scala:352:24]
assign _filtered_9_ready_T_1 = in_9_d_ready & allowed_11_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_9_ready = _filtered_9_ready_T_1; // @[Xbar.scala:352:24]
wire _in_9_d_valid_T_1 = state_11_0 & portsDIO_filtered_9_valid; // @[Mux.scala:30:73]
wire _in_9_d_valid_T_2 = state_11_1 & portsDIO_filtered_1_9_valid; // @[Mux.scala:30:73]
wire _in_9_d_valid_T_3 = _in_9_d_valid_T_1 | _in_9_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_9_d_valid_WIRE = _in_9_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_9_d_valid_T_4 = idle_11 ? _in_9_d_valid_T : _in_9_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_9_d_valid = _in_9_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_9_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_9_d_bits_opcode = _in_9_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_9_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_9_d_bits_param = _in_9_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_9_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_9_d_bits_size = _in_9_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_9_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_9_d_bits_source = _in_9_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_9_d_bits_sink = _in_9_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_9_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_9_d_bits_denied = _in_9_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_9_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_9_d_bits_data = _in_9_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_9_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_9_d_bits_corrupt = _in_9_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_9_d_bits_T = muxState_11_0 & portsDIO_filtered_9_bits_corrupt; // @[Mux.scala:30:73]
wire _in_9_d_bits_T_1 = muxState_11_1 & portsDIO_filtered_1_9_bits_corrupt; // @[Mux.scala:30:73]
wire _in_9_d_bits_T_2 = _in_9_d_bits_T | _in_9_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_1 = _in_9_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_corrupt = _in_9_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_9_d_bits_T_3 = muxState_11_0 ? portsDIO_filtered_9_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_9_d_bits_T_4 = muxState_11_1 ? portsDIO_filtered_1_9_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_9_d_bits_T_5 = _in_9_d_bits_T_3 | _in_9_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_2 = _in_9_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_data = _in_9_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_9_d_bits_T_6 = muxState_11_0 & portsDIO_filtered_9_bits_denied; // @[Mux.scala:30:73]
wire _in_9_d_bits_T_7 = muxState_11_1 & portsDIO_filtered_1_9_bits_denied; // @[Mux.scala:30:73]
wire _in_9_d_bits_T_8 = _in_9_d_bits_T_6 | _in_9_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_5 = _in_9_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_denied = _in_9_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_9 = muxState_11_0 ? portsDIO_filtered_9_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_10 = muxState_11_1 ? portsDIO_filtered_1_9_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_11 = _in_9_d_bits_T_9 | _in_9_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_6 = _in_9_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_sink = _in_9_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_9_d_bits_T_12 = muxState_11_0 ? portsDIO_filtered_9_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_9_d_bits_T_13 = muxState_11_1 ? portsDIO_filtered_1_9_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_9_d_bits_T_14 = _in_9_d_bits_T_12 | _in_9_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_7 = _in_9_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_source = _in_9_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_9_d_bits_T_15 = muxState_11_0 ? portsDIO_filtered_9_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_9_d_bits_T_16 = muxState_11_1 ? portsDIO_filtered_1_9_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_9_d_bits_T_17 = _in_9_d_bits_T_15 | _in_9_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_8 = _in_9_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_size = _in_9_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_9_d_bits_T_18 = muxState_11_0 ? portsDIO_filtered_9_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_9_d_bits_T_19 = muxState_11_1 ? portsDIO_filtered_1_9_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_9_d_bits_T_20 = _in_9_d_bits_T_18 | _in_9_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_9 = _in_9_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_param = _in_9_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_21 = muxState_11_0 ? portsDIO_filtered_9_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_22 = muxState_11_1 ? portsDIO_filtered_1_9_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_9_d_bits_T_23 = _in_9_d_bits_T_21 | _in_9_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_10 = _in_9_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_9_d_bits_WIRE_opcode = _in_9_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_12; // @[Arbiter.scala:60:30]
wire idle_12 = beatsLeft_12 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_12 = idle_12 & in_10_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_156 = {portsDIO_filtered_1_10_valid, portsDIO_filtered_10_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_12 = _readys_T_156; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_157 = readys_valid_12 == _readys_T_156; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_159 = ~_readys_T_158; // @[Arbiter.scala:22:12]
wire _readys_T_160 = ~_readys_T_157; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_12; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_24 = ~readys_mask_12; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_25 = readys_valid_12 & _readys_filter_T_24; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_12 = {_readys_filter_T_25, readys_valid_12}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_76 = readys_filter_12[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_77 = {readys_filter_12[3], readys_filter_12[2:0] | _readys_unready_T_76}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_78 = _readys_unready_T_77; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_79 = _readys_unready_T_78[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_80 = {readys_mask_12, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_12 = {1'h0, _readys_unready_T_79} | _readys_unready_T_80; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_36 = readys_unready_12[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_37 = readys_unready_12[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_38 = _readys_readys_T_36 & _readys_readys_T_37; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_12 = ~_readys_readys_T_38; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_163 = readys_readys_12; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_161 = |readys_valid_12; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_162 = latch_12 & _readys_T_161; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_84 = readys_readys_12 & readys_valid_12; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_85 = {_readys_mask_T_84, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_86 = _readys_mask_T_85[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_87 = _readys_mask_T_84 | _readys_mask_T_86; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_88 = _readys_mask_T_87; // @[package.scala:253:43, :254:17]
wire _readys_T_164 = _readys_T_163[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_12_0 = _readys_T_164; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_165 = _readys_T_163[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_12_1 = _readys_T_165; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_60 = readys_12_0 & portsDIO_filtered_10_valid; // @[Xbar.scala:352:24]
wire winner_12_0 = _winner_T_60; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_61 = readys_12_1 & portsDIO_filtered_1_10_valid; // @[Xbar.scala:352:24]
wire winner_12_1 = _winner_T_61; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_12 = winner_12_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_12 = prefixOR_1_12 | winner_12_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_10_d_valid_T = portsDIO_filtered_10_valid | portsDIO_filtered_1_10_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_12 = winner_12_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_12 = winner_12_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_12 = {maskedBeats_0_12[8:3], maskedBeats_0_12[2:0] | maskedBeats_1_12}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_48 = in_10_d_ready & in_10_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_49 = {1'h0, beatsLeft_12} - {9'h0, _beatsLeft_T_48}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_50 = _beatsLeft_T_49[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_51 = latch_12 ? initBeats_12 : _beatsLeft_T_50; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_12_0; // @[Arbiter.scala:88:26]
reg state_12_1; // @[Arbiter.scala:88:26]
wire muxState_12_0 = idle_12 ? winner_12_0 : state_12_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_12_1 = idle_12 ? winner_12_1 : state_12_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_12_0 = idle_12 ? readys_12_0 : state_12_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_12_1 = idle_12 ? readys_12_1 : state_12_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_10_ready_T = in_10_d_ready & allowed_12_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_10_ready = _filtered_10_ready_T; // @[Xbar.scala:352:24]
assign _filtered_10_ready_T_1 = in_10_d_ready & allowed_12_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_10_ready = _filtered_10_ready_T_1; // @[Xbar.scala:352:24]
wire _in_10_d_valid_T_1 = state_12_0 & portsDIO_filtered_10_valid; // @[Mux.scala:30:73]
wire _in_10_d_valid_T_2 = state_12_1 & portsDIO_filtered_1_10_valid; // @[Mux.scala:30:73]
wire _in_10_d_valid_T_3 = _in_10_d_valid_T_1 | _in_10_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_10_d_valid_WIRE = _in_10_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_10_d_valid_T_4 = idle_12 ? _in_10_d_valid_T : _in_10_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_10_d_valid = _in_10_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_10_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_10_d_bits_opcode = _in_10_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_10_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_10_d_bits_param = _in_10_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_10_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_10_d_bits_size = _in_10_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_10_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_10_d_bits_source = _in_10_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_10_d_bits_sink = _in_10_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_10_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_10_d_bits_denied = _in_10_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_10_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_10_d_bits_data = _in_10_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_10_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_10_d_bits_corrupt = _in_10_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_10_d_bits_T = muxState_12_0 & portsDIO_filtered_10_bits_corrupt; // @[Mux.scala:30:73]
wire _in_10_d_bits_T_1 = muxState_12_1 & portsDIO_filtered_1_10_bits_corrupt; // @[Mux.scala:30:73]
wire _in_10_d_bits_T_2 = _in_10_d_bits_T | _in_10_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_1 = _in_10_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_corrupt = _in_10_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_10_d_bits_T_3 = muxState_12_0 ? portsDIO_filtered_10_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_10_d_bits_T_4 = muxState_12_1 ? portsDIO_filtered_1_10_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_10_d_bits_T_5 = _in_10_d_bits_T_3 | _in_10_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_2 = _in_10_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_data = _in_10_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_10_d_bits_T_6 = muxState_12_0 & portsDIO_filtered_10_bits_denied; // @[Mux.scala:30:73]
wire _in_10_d_bits_T_7 = muxState_12_1 & portsDIO_filtered_1_10_bits_denied; // @[Mux.scala:30:73]
wire _in_10_d_bits_T_8 = _in_10_d_bits_T_6 | _in_10_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_5 = _in_10_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_denied = _in_10_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_9 = muxState_12_0 ? portsDIO_filtered_10_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_10 = muxState_12_1 ? portsDIO_filtered_1_10_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_11 = _in_10_d_bits_T_9 | _in_10_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_6 = _in_10_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_sink = _in_10_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_10_d_bits_T_12 = muxState_12_0 ? portsDIO_filtered_10_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_10_d_bits_T_13 = muxState_12_1 ? portsDIO_filtered_1_10_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_10_d_bits_T_14 = _in_10_d_bits_T_12 | _in_10_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_7 = _in_10_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_source = _in_10_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_10_d_bits_T_15 = muxState_12_0 ? portsDIO_filtered_10_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_10_d_bits_T_16 = muxState_12_1 ? portsDIO_filtered_1_10_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_10_d_bits_T_17 = _in_10_d_bits_T_15 | _in_10_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_8 = _in_10_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_size = _in_10_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_10_d_bits_T_18 = muxState_12_0 ? portsDIO_filtered_10_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_10_d_bits_T_19 = muxState_12_1 ? portsDIO_filtered_1_10_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_10_d_bits_T_20 = _in_10_d_bits_T_18 | _in_10_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_9 = _in_10_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_param = _in_10_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_21 = muxState_12_0 ? portsDIO_filtered_10_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_22 = muxState_12_1 ? portsDIO_filtered_1_10_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_10_d_bits_T_23 = _in_10_d_bits_T_21 | _in_10_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_10 = _in_10_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_10_d_bits_WIRE_opcode = _in_10_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_13; // @[Arbiter.scala:60:30]
wire idle_13 = beatsLeft_13 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_13 = idle_13 & in_11_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_166 = {portsDIO_filtered_1_11_valid, portsDIO_filtered_11_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_13 = _readys_T_166; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_167 = readys_valid_13 == _readys_T_166; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_169 = ~_readys_T_168; // @[Arbiter.scala:22:12]
wire _readys_T_170 = ~_readys_T_167; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_13; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_26 = ~readys_mask_13; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_27 = readys_valid_13 & _readys_filter_T_26; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_13 = {_readys_filter_T_27, readys_valid_13}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_81 = readys_filter_13[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_82 = {readys_filter_13[3], readys_filter_13[2:0] | _readys_unready_T_81}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_83 = _readys_unready_T_82; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_84 = _readys_unready_T_83[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_85 = {readys_mask_13, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_13 = {1'h0, _readys_unready_T_84} | _readys_unready_T_85; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_39 = readys_unready_13[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_40 = readys_unready_13[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_41 = _readys_readys_T_39 & _readys_readys_T_40; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_13 = ~_readys_readys_T_41; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_173 = readys_readys_13; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_171 = |readys_valid_13; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_172 = latch_13 & _readys_T_171; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_89 = readys_readys_13 & readys_valid_13; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_90 = {_readys_mask_T_89, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_91 = _readys_mask_T_90[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_92 = _readys_mask_T_89 | _readys_mask_T_91; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_93 = _readys_mask_T_92; // @[package.scala:253:43, :254:17]
wire _readys_T_174 = _readys_T_173[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_13_0 = _readys_T_174; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_175 = _readys_T_173[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_13_1 = _readys_T_175; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_62 = readys_13_0 & portsDIO_filtered_11_valid; // @[Xbar.scala:352:24]
wire winner_13_0 = _winner_T_62; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_63 = readys_13_1 & portsDIO_filtered_1_11_valid; // @[Xbar.scala:352:24]
wire winner_13_1 = _winner_T_63; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_13 = winner_13_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_13 = prefixOR_1_13 | winner_13_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_11_d_valid_T = portsDIO_filtered_11_valid | portsDIO_filtered_1_11_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_13 = winner_13_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_13 = winner_13_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_13 = {maskedBeats_0_13[8:3], maskedBeats_0_13[2:0] | maskedBeats_1_13}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_52 = in_11_d_ready & in_11_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_53 = {1'h0, beatsLeft_13} - {9'h0, _beatsLeft_T_52}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_54 = _beatsLeft_T_53[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_55 = latch_13 ? initBeats_13 : _beatsLeft_T_54; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_13_0; // @[Arbiter.scala:88:26]
reg state_13_1; // @[Arbiter.scala:88:26]
wire muxState_13_0 = idle_13 ? winner_13_0 : state_13_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_13_1 = idle_13 ? winner_13_1 : state_13_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_13_0 = idle_13 ? readys_13_0 : state_13_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_13_1 = idle_13 ? readys_13_1 : state_13_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_11_ready_T = in_11_d_ready & allowed_13_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_11_ready = _filtered_11_ready_T; // @[Xbar.scala:352:24]
assign _filtered_11_ready_T_1 = in_11_d_ready & allowed_13_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_11_ready = _filtered_11_ready_T_1; // @[Xbar.scala:352:24]
wire _in_11_d_valid_T_1 = state_13_0 & portsDIO_filtered_11_valid; // @[Mux.scala:30:73]
wire _in_11_d_valid_T_2 = state_13_1 & portsDIO_filtered_1_11_valid; // @[Mux.scala:30:73]
wire _in_11_d_valid_T_3 = _in_11_d_valid_T_1 | _in_11_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_11_d_valid_WIRE = _in_11_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_11_d_valid_T_4 = idle_13 ? _in_11_d_valid_T : _in_11_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_11_d_valid = _in_11_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_11_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_11_d_bits_opcode = _in_11_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_11_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_11_d_bits_param = _in_11_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_11_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_11_d_bits_size = _in_11_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_11_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_11_d_bits_source = _in_11_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_11_d_bits_sink = _in_11_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_11_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_11_d_bits_denied = _in_11_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_11_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_11_d_bits_data = _in_11_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_11_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_11_d_bits_corrupt = _in_11_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_11_d_bits_T = muxState_13_0 & portsDIO_filtered_11_bits_corrupt; // @[Mux.scala:30:73]
wire _in_11_d_bits_T_1 = muxState_13_1 & portsDIO_filtered_1_11_bits_corrupt; // @[Mux.scala:30:73]
wire _in_11_d_bits_T_2 = _in_11_d_bits_T | _in_11_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_1 = _in_11_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_corrupt = _in_11_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_11_d_bits_T_3 = muxState_13_0 ? portsDIO_filtered_11_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_11_d_bits_T_4 = muxState_13_1 ? portsDIO_filtered_1_11_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_11_d_bits_T_5 = _in_11_d_bits_T_3 | _in_11_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_2 = _in_11_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_data = _in_11_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_11_d_bits_T_6 = muxState_13_0 & portsDIO_filtered_11_bits_denied; // @[Mux.scala:30:73]
wire _in_11_d_bits_T_7 = muxState_13_1 & portsDIO_filtered_1_11_bits_denied; // @[Mux.scala:30:73]
wire _in_11_d_bits_T_8 = _in_11_d_bits_T_6 | _in_11_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_5 = _in_11_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_denied = _in_11_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_9 = muxState_13_0 ? portsDIO_filtered_11_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_10 = muxState_13_1 ? portsDIO_filtered_1_11_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_11 = _in_11_d_bits_T_9 | _in_11_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_6 = _in_11_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_sink = _in_11_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_11_d_bits_T_12 = muxState_13_0 ? portsDIO_filtered_11_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_11_d_bits_T_13 = muxState_13_1 ? portsDIO_filtered_1_11_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_11_d_bits_T_14 = _in_11_d_bits_T_12 | _in_11_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_7 = _in_11_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_source = _in_11_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_11_d_bits_T_15 = muxState_13_0 ? portsDIO_filtered_11_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_11_d_bits_T_16 = muxState_13_1 ? portsDIO_filtered_1_11_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_11_d_bits_T_17 = _in_11_d_bits_T_15 | _in_11_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_8 = _in_11_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_size = _in_11_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_11_d_bits_T_18 = muxState_13_0 ? portsDIO_filtered_11_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_11_d_bits_T_19 = muxState_13_1 ? portsDIO_filtered_1_11_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_11_d_bits_T_20 = _in_11_d_bits_T_18 | _in_11_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_9 = _in_11_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_param = _in_11_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_21 = muxState_13_0 ? portsDIO_filtered_11_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_22 = muxState_13_1 ? portsDIO_filtered_1_11_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_11_d_bits_T_23 = _in_11_d_bits_T_21 | _in_11_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_10 = _in_11_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_11_d_bits_WIRE_opcode = _in_11_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_14; // @[Arbiter.scala:60:30]
wire idle_14 = beatsLeft_14 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_14 = idle_14 & in_12_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_176 = {portsDIO_filtered_1_12_valid, portsDIO_filtered_12_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_14 = _readys_T_176; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_177 = readys_valid_14 == _readys_T_176; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_179 = ~_readys_T_178; // @[Arbiter.scala:22:12]
wire _readys_T_180 = ~_readys_T_177; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_14; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_28 = ~readys_mask_14; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_29 = readys_valid_14 & _readys_filter_T_28; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_14 = {_readys_filter_T_29, readys_valid_14}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_86 = readys_filter_14[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_87 = {readys_filter_14[3], readys_filter_14[2:0] | _readys_unready_T_86}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_88 = _readys_unready_T_87; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_89 = _readys_unready_T_88[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_90 = {readys_mask_14, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_14 = {1'h0, _readys_unready_T_89} | _readys_unready_T_90; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_42 = readys_unready_14[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_43 = readys_unready_14[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_44 = _readys_readys_T_42 & _readys_readys_T_43; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_14 = ~_readys_readys_T_44; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_183 = readys_readys_14; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_181 = |readys_valid_14; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_182 = latch_14 & _readys_T_181; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_94 = readys_readys_14 & readys_valid_14; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_95 = {_readys_mask_T_94, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_96 = _readys_mask_T_95[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_97 = _readys_mask_T_94 | _readys_mask_T_96; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_98 = _readys_mask_T_97; // @[package.scala:253:43, :254:17]
wire _readys_T_184 = _readys_T_183[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_14_0 = _readys_T_184; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_185 = _readys_T_183[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_14_1 = _readys_T_185; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_64 = readys_14_0 & portsDIO_filtered_12_valid; // @[Xbar.scala:352:24]
wire winner_14_0 = _winner_T_64; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_65 = readys_14_1 & portsDIO_filtered_1_12_valid; // @[Xbar.scala:352:24]
wire winner_14_1 = _winner_T_65; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_14 = winner_14_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_14 = prefixOR_1_14 | winner_14_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_12_d_valid_T = portsDIO_filtered_12_valid | portsDIO_filtered_1_12_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_14 = winner_14_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_14 = winner_14_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_14 = {maskedBeats_0_14[8:3], maskedBeats_0_14[2:0] | maskedBeats_1_14}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_56 = in_12_d_ready & in_12_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_57 = {1'h0, beatsLeft_14} - {9'h0, _beatsLeft_T_56}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_58 = _beatsLeft_T_57[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_59 = latch_14 ? initBeats_14 : _beatsLeft_T_58; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_14_0; // @[Arbiter.scala:88:26]
reg state_14_1; // @[Arbiter.scala:88:26]
wire muxState_14_0 = idle_14 ? winner_14_0 : state_14_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_14_1 = idle_14 ? winner_14_1 : state_14_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_14_0 = idle_14 ? readys_14_0 : state_14_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_14_1 = idle_14 ? readys_14_1 : state_14_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_12_ready_T = in_12_d_ready & allowed_14_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_12_ready = _filtered_12_ready_T; // @[Xbar.scala:352:24]
assign _filtered_12_ready_T_1 = in_12_d_ready & allowed_14_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_12_ready = _filtered_12_ready_T_1; // @[Xbar.scala:352:24]
wire _in_12_d_valid_T_1 = state_14_0 & portsDIO_filtered_12_valid; // @[Mux.scala:30:73]
wire _in_12_d_valid_T_2 = state_14_1 & portsDIO_filtered_1_12_valid; // @[Mux.scala:30:73]
wire _in_12_d_valid_T_3 = _in_12_d_valid_T_1 | _in_12_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_12_d_valid_WIRE = _in_12_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_12_d_valid_T_4 = idle_14 ? _in_12_d_valid_T : _in_12_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_12_d_valid = _in_12_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_12_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_12_d_bits_opcode = _in_12_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_12_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_12_d_bits_param = _in_12_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_12_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_12_d_bits_size = _in_12_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_12_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_12_d_bits_source = _in_12_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_12_d_bits_sink = _in_12_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_12_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_12_d_bits_denied = _in_12_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_12_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_12_d_bits_data = _in_12_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_12_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_12_d_bits_corrupt = _in_12_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_12_d_bits_T = muxState_14_0 & portsDIO_filtered_12_bits_corrupt; // @[Mux.scala:30:73]
wire _in_12_d_bits_T_1 = muxState_14_1 & portsDIO_filtered_1_12_bits_corrupt; // @[Mux.scala:30:73]
wire _in_12_d_bits_T_2 = _in_12_d_bits_T | _in_12_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_1 = _in_12_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_corrupt = _in_12_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_12_d_bits_T_3 = muxState_14_0 ? portsDIO_filtered_12_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_12_d_bits_T_4 = muxState_14_1 ? portsDIO_filtered_1_12_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_12_d_bits_T_5 = _in_12_d_bits_T_3 | _in_12_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_2 = _in_12_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_data = _in_12_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_12_d_bits_T_6 = muxState_14_0 & portsDIO_filtered_12_bits_denied; // @[Mux.scala:30:73]
wire _in_12_d_bits_T_7 = muxState_14_1 & portsDIO_filtered_1_12_bits_denied; // @[Mux.scala:30:73]
wire _in_12_d_bits_T_8 = _in_12_d_bits_T_6 | _in_12_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_5 = _in_12_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_denied = _in_12_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_9 = muxState_14_0 ? portsDIO_filtered_12_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_10 = muxState_14_1 ? portsDIO_filtered_1_12_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_11 = _in_12_d_bits_T_9 | _in_12_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_6 = _in_12_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_sink = _in_12_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_12_d_bits_T_12 = muxState_14_0 ? portsDIO_filtered_12_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_12_d_bits_T_13 = muxState_14_1 ? portsDIO_filtered_1_12_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_12_d_bits_T_14 = _in_12_d_bits_T_12 | _in_12_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_7 = _in_12_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_source = _in_12_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_12_d_bits_T_15 = muxState_14_0 ? portsDIO_filtered_12_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_12_d_bits_T_16 = muxState_14_1 ? portsDIO_filtered_1_12_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_12_d_bits_T_17 = _in_12_d_bits_T_15 | _in_12_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_8 = _in_12_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_size = _in_12_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_12_d_bits_T_18 = muxState_14_0 ? portsDIO_filtered_12_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_12_d_bits_T_19 = muxState_14_1 ? portsDIO_filtered_1_12_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_12_d_bits_T_20 = _in_12_d_bits_T_18 | _in_12_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_9 = _in_12_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_param = _in_12_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_21 = muxState_14_0 ? portsDIO_filtered_12_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_22 = muxState_14_1 ? portsDIO_filtered_1_12_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_12_d_bits_T_23 = _in_12_d_bits_T_21 | _in_12_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_10 = _in_12_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_12_d_bits_WIRE_opcode = _in_12_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_15; // @[Arbiter.scala:60:30]
wire idle_15 = beatsLeft_15 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_15 = idle_15 & in_13_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_186 = {portsDIO_filtered_1_13_valid, portsDIO_filtered_13_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_15 = _readys_T_186; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_187 = readys_valid_15 == _readys_T_186; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_189 = ~_readys_T_188; // @[Arbiter.scala:22:12]
wire _readys_T_190 = ~_readys_T_187; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_15; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_30 = ~readys_mask_15; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_31 = readys_valid_15 & _readys_filter_T_30; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_15 = {_readys_filter_T_31, readys_valid_15}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_91 = readys_filter_15[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_92 = {readys_filter_15[3], readys_filter_15[2:0] | _readys_unready_T_91}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_93 = _readys_unready_T_92; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_94 = _readys_unready_T_93[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_95 = {readys_mask_15, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_15 = {1'h0, _readys_unready_T_94} | _readys_unready_T_95; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_45 = readys_unready_15[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_46 = readys_unready_15[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_47 = _readys_readys_T_45 & _readys_readys_T_46; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_15 = ~_readys_readys_T_47; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_193 = readys_readys_15; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_191 = |readys_valid_15; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_192 = latch_15 & _readys_T_191; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_99 = readys_readys_15 & readys_valid_15; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_100 = {_readys_mask_T_99, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_101 = _readys_mask_T_100[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_102 = _readys_mask_T_99 | _readys_mask_T_101; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_103 = _readys_mask_T_102; // @[package.scala:253:43, :254:17]
wire _readys_T_194 = _readys_T_193[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_15_0 = _readys_T_194; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_195 = _readys_T_193[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_15_1 = _readys_T_195; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_66 = readys_15_0 & portsDIO_filtered_13_valid; // @[Xbar.scala:352:24]
wire winner_15_0 = _winner_T_66; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_67 = readys_15_1 & portsDIO_filtered_1_13_valid; // @[Xbar.scala:352:24]
wire winner_15_1 = _winner_T_67; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_15 = winner_15_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_15 = prefixOR_1_15 | winner_15_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_13_d_valid_T = portsDIO_filtered_13_valid | portsDIO_filtered_1_13_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_15 = winner_15_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_15 = winner_15_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_15 = {maskedBeats_0_15[8:3], maskedBeats_0_15[2:0] | maskedBeats_1_15}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_60 = in_13_d_ready & in_13_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_61 = {1'h0, beatsLeft_15} - {9'h0, _beatsLeft_T_60}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_62 = _beatsLeft_T_61[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_63 = latch_15 ? initBeats_15 : _beatsLeft_T_62; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_15_0; // @[Arbiter.scala:88:26]
reg state_15_1; // @[Arbiter.scala:88:26]
wire muxState_15_0 = idle_15 ? winner_15_0 : state_15_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_15_1 = idle_15 ? winner_15_1 : state_15_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_15_0 = idle_15 ? readys_15_0 : state_15_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_15_1 = idle_15 ? readys_15_1 : state_15_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_13_ready_T = in_13_d_ready & allowed_15_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_13_ready = _filtered_13_ready_T; // @[Xbar.scala:352:24]
assign _filtered_13_ready_T_1 = in_13_d_ready & allowed_15_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_13_ready = _filtered_13_ready_T_1; // @[Xbar.scala:352:24]
wire _in_13_d_valid_T_1 = state_15_0 & portsDIO_filtered_13_valid; // @[Mux.scala:30:73]
wire _in_13_d_valid_T_2 = state_15_1 & portsDIO_filtered_1_13_valid; // @[Mux.scala:30:73]
wire _in_13_d_valid_T_3 = _in_13_d_valid_T_1 | _in_13_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_13_d_valid_WIRE = _in_13_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_13_d_valid_T_4 = idle_15 ? _in_13_d_valid_T : _in_13_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_13_d_valid = _in_13_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_13_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_13_d_bits_opcode = _in_13_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_13_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_13_d_bits_param = _in_13_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_13_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_13_d_bits_size = _in_13_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_13_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_13_d_bits_source = _in_13_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_13_d_bits_sink = _in_13_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_13_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_13_d_bits_denied = _in_13_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_13_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_13_d_bits_data = _in_13_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_13_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_13_d_bits_corrupt = _in_13_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_13_d_bits_T = muxState_15_0 & portsDIO_filtered_13_bits_corrupt; // @[Mux.scala:30:73]
wire _in_13_d_bits_T_1 = muxState_15_1 & portsDIO_filtered_1_13_bits_corrupt; // @[Mux.scala:30:73]
wire _in_13_d_bits_T_2 = _in_13_d_bits_T | _in_13_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_1 = _in_13_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_corrupt = _in_13_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_13_d_bits_T_3 = muxState_15_0 ? portsDIO_filtered_13_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_13_d_bits_T_4 = muxState_15_1 ? portsDIO_filtered_1_13_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_13_d_bits_T_5 = _in_13_d_bits_T_3 | _in_13_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_2 = _in_13_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_data = _in_13_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_13_d_bits_T_6 = muxState_15_0 & portsDIO_filtered_13_bits_denied; // @[Mux.scala:30:73]
wire _in_13_d_bits_T_7 = muxState_15_1 & portsDIO_filtered_1_13_bits_denied; // @[Mux.scala:30:73]
wire _in_13_d_bits_T_8 = _in_13_d_bits_T_6 | _in_13_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_5 = _in_13_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_denied = _in_13_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_9 = muxState_15_0 ? portsDIO_filtered_13_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_10 = muxState_15_1 ? portsDIO_filtered_1_13_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_11 = _in_13_d_bits_T_9 | _in_13_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_6 = _in_13_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_sink = _in_13_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_13_d_bits_T_12 = muxState_15_0 ? portsDIO_filtered_13_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_13_d_bits_T_13 = muxState_15_1 ? portsDIO_filtered_1_13_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_13_d_bits_T_14 = _in_13_d_bits_T_12 | _in_13_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_7 = _in_13_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_source = _in_13_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_13_d_bits_T_15 = muxState_15_0 ? portsDIO_filtered_13_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_13_d_bits_T_16 = muxState_15_1 ? portsDIO_filtered_1_13_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_13_d_bits_T_17 = _in_13_d_bits_T_15 | _in_13_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_8 = _in_13_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_size = _in_13_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_13_d_bits_T_18 = muxState_15_0 ? portsDIO_filtered_13_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_13_d_bits_T_19 = muxState_15_1 ? portsDIO_filtered_1_13_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_13_d_bits_T_20 = _in_13_d_bits_T_18 | _in_13_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_9 = _in_13_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_param = _in_13_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_21 = muxState_15_0 ? portsDIO_filtered_13_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_22 = muxState_15_1 ? portsDIO_filtered_1_13_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_13_d_bits_T_23 = _in_13_d_bits_T_21 | _in_13_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_10 = _in_13_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_13_d_bits_WIRE_opcode = _in_13_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_16; // @[Arbiter.scala:60:30]
wire idle_16 = beatsLeft_16 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_16 = idle_16 & in_14_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_196 = {portsDIO_filtered_1_14_valid, portsDIO_filtered_14_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_16 = _readys_T_196; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_197 = readys_valid_16 == _readys_T_196; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_199 = ~_readys_T_198; // @[Arbiter.scala:22:12]
wire _readys_T_200 = ~_readys_T_197; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_16; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_32 = ~readys_mask_16; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_33 = readys_valid_16 & _readys_filter_T_32; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_16 = {_readys_filter_T_33, readys_valid_16}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_96 = readys_filter_16[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_97 = {readys_filter_16[3], readys_filter_16[2:0] | _readys_unready_T_96}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_98 = _readys_unready_T_97; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_99 = _readys_unready_T_98[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_100 = {readys_mask_16, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_16 = {1'h0, _readys_unready_T_99} | _readys_unready_T_100; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_48 = readys_unready_16[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_49 = readys_unready_16[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_50 = _readys_readys_T_48 & _readys_readys_T_49; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_16 = ~_readys_readys_T_50; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_203 = readys_readys_16; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_201 = |readys_valid_16; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_202 = latch_16 & _readys_T_201; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_104 = readys_readys_16 & readys_valid_16; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_105 = {_readys_mask_T_104, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_106 = _readys_mask_T_105[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_107 = _readys_mask_T_104 | _readys_mask_T_106; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_108 = _readys_mask_T_107; // @[package.scala:253:43, :254:17]
wire _readys_T_204 = _readys_T_203[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_16_0 = _readys_T_204; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_205 = _readys_T_203[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_16_1 = _readys_T_205; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_68 = readys_16_0 & portsDIO_filtered_14_valid; // @[Xbar.scala:352:24]
wire winner_16_0 = _winner_T_68; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_69 = readys_16_1 & portsDIO_filtered_1_14_valid; // @[Xbar.scala:352:24]
wire winner_16_1 = _winner_T_69; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_16 = winner_16_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_16 = prefixOR_1_16 | winner_16_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_14_d_valid_T = portsDIO_filtered_14_valid | portsDIO_filtered_1_14_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_16 = winner_16_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_16 = winner_16_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_16 = {maskedBeats_0_16[8:3], maskedBeats_0_16[2:0] | maskedBeats_1_16}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_64 = in_14_d_ready & in_14_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_65 = {1'h0, beatsLeft_16} - {9'h0, _beatsLeft_T_64}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_66 = _beatsLeft_T_65[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_67 = latch_16 ? initBeats_16 : _beatsLeft_T_66; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_16_0; // @[Arbiter.scala:88:26]
reg state_16_1; // @[Arbiter.scala:88:26]
wire muxState_16_0 = idle_16 ? winner_16_0 : state_16_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_16_1 = idle_16 ? winner_16_1 : state_16_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_16_0 = idle_16 ? readys_16_0 : state_16_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_16_1 = idle_16 ? readys_16_1 : state_16_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_14_ready_T = in_14_d_ready & allowed_16_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_14_ready = _filtered_14_ready_T; // @[Xbar.scala:352:24]
assign _filtered_14_ready_T_1 = in_14_d_ready & allowed_16_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_14_ready = _filtered_14_ready_T_1; // @[Xbar.scala:352:24]
wire _in_14_d_valid_T_1 = state_16_0 & portsDIO_filtered_14_valid; // @[Mux.scala:30:73]
wire _in_14_d_valid_T_2 = state_16_1 & portsDIO_filtered_1_14_valid; // @[Mux.scala:30:73]
wire _in_14_d_valid_T_3 = _in_14_d_valid_T_1 | _in_14_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_14_d_valid_WIRE = _in_14_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_14_d_valid_T_4 = idle_16 ? _in_14_d_valid_T : _in_14_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_14_d_valid = _in_14_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_14_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_14_d_bits_opcode = _in_14_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_14_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_14_d_bits_param = _in_14_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_14_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_14_d_bits_size = _in_14_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_14_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_14_d_bits_source = _in_14_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_14_d_bits_sink = _in_14_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_14_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_14_d_bits_denied = _in_14_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_14_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_14_d_bits_data = _in_14_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_14_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_14_d_bits_corrupt = _in_14_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_14_d_bits_T = muxState_16_0 & portsDIO_filtered_14_bits_corrupt; // @[Mux.scala:30:73]
wire _in_14_d_bits_T_1 = muxState_16_1 & portsDIO_filtered_1_14_bits_corrupt; // @[Mux.scala:30:73]
wire _in_14_d_bits_T_2 = _in_14_d_bits_T | _in_14_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_1 = _in_14_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_corrupt = _in_14_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_14_d_bits_T_3 = muxState_16_0 ? portsDIO_filtered_14_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_14_d_bits_T_4 = muxState_16_1 ? portsDIO_filtered_1_14_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_14_d_bits_T_5 = _in_14_d_bits_T_3 | _in_14_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_2 = _in_14_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_data = _in_14_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_14_d_bits_T_6 = muxState_16_0 & portsDIO_filtered_14_bits_denied; // @[Mux.scala:30:73]
wire _in_14_d_bits_T_7 = muxState_16_1 & portsDIO_filtered_1_14_bits_denied; // @[Mux.scala:30:73]
wire _in_14_d_bits_T_8 = _in_14_d_bits_T_6 | _in_14_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_5 = _in_14_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_denied = _in_14_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_9 = muxState_16_0 ? portsDIO_filtered_14_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_10 = muxState_16_1 ? portsDIO_filtered_1_14_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_11 = _in_14_d_bits_T_9 | _in_14_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_6 = _in_14_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_sink = _in_14_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_14_d_bits_T_12 = muxState_16_0 ? portsDIO_filtered_14_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_14_d_bits_T_13 = muxState_16_1 ? portsDIO_filtered_1_14_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_14_d_bits_T_14 = _in_14_d_bits_T_12 | _in_14_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_7 = _in_14_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_source = _in_14_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_14_d_bits_T_15 = muxState_16_0 ? portsDIO_filtered_14_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_14_d_bits_T_16 = muxState_16_1 ? portsDIO_filtered_1_14_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_14_d_bits_T_17 = _in_14_d_bits_T_15 | _in_14_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_8 = _in_14_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_size = _in_14_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_14_d_bits_T_18 = muxState_16_0 ? portsDIO_filtered_14_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_14_d_bits_T_19 = muxState_16_1 ? portsDIO_filtered_1_14_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_14_d_bits_T_20 = _in_14_d_bits_T_18 | _in_14_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_9 = _in_14_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_param = _in_14_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_21 = muxState_16_0 ? portsDIO_filtered_14_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_22 = muxState_16_1 ? portsDIO_filtered_1_14_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_14_d_bits_T_23 = _in_14_d_bits_T_21 | _in_14_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_10 = _in_14_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_14_d_bits_WIRE_opcode = _in_14_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_17; // @[Arbiter.scala:60:30]
wire idle_17 = beatsLeft_17 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_17 = idle_17 & in_15_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_206 = {portsDIO_filtered_1_15_valid, portsDIO_filtered_15_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_17 = _readys_T_206; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_207 = readys_valid_17 == _readys_T_206; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_209 = ~_readys_T_208; // @[Arbiter.scala:22:12]
wire _readys_T_210 = ~_readys_T_207; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_17; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_34 = ~readys_mask_17; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_35 = readys_valid_17 & _readys_filter_T_34; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_17 = {_readys_filter_T_35, readys_valid_17}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_101 = readys_filter_17[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_102 = {readys_filter_17[3], readys_filter_17[2:0] | _readys_unready_T_101}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_103 = _readys_unready_T_102; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_104 = _readys_unready_T_103[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_105 = {readys_mask_17, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_17 = {1'h0, _readys_unready_T_104} | _readys_unready_T_105; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_51 = readys_unready_17[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_52 = readys_unready_17[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_53 = _readys_readys_T_51 & _readys_readys_T_52; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_17 = ~_readys_readys_T_53; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_213 = readys_readys_17; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_211 = |readys_valid_17; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_212 = latch_17 & _readys_T_211; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_109 = readys_readys_17 & readys_valid_17; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_110 = {_readys_mask_T_109, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_111 = _readys_mask_T_110[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_112 = _readys_mask_T_109 | _readys_mask_T_111; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_113 = _readys_mask_T_112; // @[package.scala:253:43, :254:17]
wire _readys_T_214 = _readys_T_213[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_17_0 = _readys_T_214; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_215 = _readys_T_213[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_17_1 = _readys_T_215; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_70 = readys_17_0 & portsDIO_filtered_15_valid; // @[Xbar.scala:352:24]
wire winner_17_0 = _winner_T_70; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_71 = readys_17_1 & portsDIO_filtered_1_15_valid; // @[Xbar.scala:352:24]
wire winner_17_1 = _winner_T_71; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_17 = winner_17_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_17 = prefixOR_1_17 | winner_17_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_15_d_valid_T = portsDIO_filtered_15_valid | portsDIO_filtered_1_15_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_17 = winner_17_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_17 = winner_17_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_17 = {maskedBeats_0_17[8:3], maskedBeats_0_17[2:0] | maskedBeats_1_17}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_68 = in_15_d_ready & in_15_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_69 = {1'h0, beatsLeft_17} - {9'h0, _beatsLeft_T_68}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_70 = _beatsLeft_T_69[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_71 = latch_17 ? initBeats_17 : _beatsLeft_T_70; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_17_0; // @[Arbiter.scala:88:26]
reg state_17_1; // @[Arbiter.scala:88:26]
wire muxState_17_0 = idle_17 ? winner_17_0 : state_17_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_17_1 = idle_17 ? winner_17_1 : state_17_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_17_0 = idle_17 ? readys_17_0 : state_17_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_17_1 = idle_17 ? readys_17_1 : state_17_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_15_ready_T = in_15_d_ready & allowed_17_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_15_ready = _filtered_15_ready_T; // @[Xbar.scala:352:24]
assign _filtered_15_ready_T_1 = in_15_d_ready & allowed_17_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_15_ready = _filtered_15_ready_T_1; // @[Xbar.scala:352:24]
wire _in_15_d_valid_T_1 = state_17_0 & portsDIO_filtered_15_valid; // @[Mux.scala:30:73]
wire _in_15_d_valid_T_2 = state_17_1 & portsDIO_filtered_1_15_valid; // @[Mux.scala:30:73]
wire _in_15_d_valid_T_3 = _in_15_d_valid_T_1 | _in_15_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_15_d_valid_WIRE = _in_15_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_15_d_valid_T_4 = idle_17 ? _in_15_d_valid_T : _in_15_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_15_d_valid = _in_15_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_15_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_15_d_bits_opcode = _in_15_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_15_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_15_d_bits_param = _in_15_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_15_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_15_d_bits_size = _in_15_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_15_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_15_d_bits_source = _in_15_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_15_d_bits_sink = _in_15_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_15_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_15_d_bits_denied = _in_15_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_15_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_15_d_bits_data = _in_15_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_15_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_15_d_bits_corrupt = _in_15_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_15_d_bits_T = muxState_17_0 & portsDIO_filtered_15_bits_corrupt; // @[Mux.scala:30:73]
wire _in_15_d_bits_T_1 = muxState_17_1 & portsDIO_filtered_1_15_bits_corrupt; // @[Mux.scala:30:73]
wire _in_15_d_bits_T_2 = _in_15_d_bits_T | _in_15_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_1 = _in_15_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_corrupt = _in_15_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_15_d_bits_T_3 = muxState_17_0 ? portsDIO_filtered_15_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_15_d_bits_T_4 = muxState_17_1 ? portsDIO_filtered_1_15_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_15_d_bits_T_5 = _in_15_d_bits_T_3 | _in_15_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_2 = _in_15_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_data = _in_15_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_15_d_bits_T_6 = muxState_17_0 & portsDIO_filtered_15_bits_denied; // @[Mux.scala:30:73]
wire _in_15_d_bits_T_7 = muxState_17_1 & portsDIO_filtered_1_15_bits_denied; // @[Mux.scala:30:73]
wire _in_15_d_bits_T_8 = _in_15_d_bits_T_6 | _in_15_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_5 = _in_15_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_denied = _in_15_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_9 = muxState_17_0 ? portsDIO_filtered_15_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_10 = muxState_17_1 ? portsDIO_filtered_1_15_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_11 = _in_15_d_bits_T_9 | _in_15_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_6 = _in_15_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_sink = _in_15_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_15_d_bits_T_12 = muxState_17_0 ? portsDIO_filtered_15_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_15_d_bits_T_13 = muxState_17_1 ? portsDIO_filtered_1_15_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_15_d_bits_T_14 = _in_15_d_bits_T_12 | _in_15_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_7 = _in_15_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_source = _in_15_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_15_d_bits_T_15 = muxState_17_0 ? portsDIO_filtered_15_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_15_d_bits_T_16 = muxState_17_1 ? portsDIO_filtered_1_15_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_15_d_bits_T_17 = _in_15_d_bits_T_15 | _in_15_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_8 = _in_15_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_size = _in_15_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_15_d_bits_T_18 = muxState_17_0 ? portsDIO_filtered_15_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_15_d_bits_T_19 = muxState_17_1 ? portsDIO_filtered_1_15_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_15_d_bits_T_20 = _in_15_d_bits_T_18 | _in_15_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_9 = _in_15_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_param = _in_15_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_21 = muxState_17_0 ? portsDIO_filtered_15_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_22 = muxState_17_1 ? portsDIO_filtered_1_15_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_15_d_bits_T_23 = _in_15_d_bits_T_21 | _in_15_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_10 = _in_15_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_15_d_bits_WIRE_opcode = _in_15_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_18; // @[Arbiter.scala:60:30]
wire idle_18 = beatsLeft_18 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_18 = idle_18 & in_16_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_216 = {portsDIO_filtered_1_16_valid, portsDIO_filtered_16_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_18 = _readys_T_216; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_217 = readys_valid_18 == _readys_T_216; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_219 = ~_readys_T_218; // @[Arbiter.scala:22:12]
wire _readys_T_220 = ~_readys_T_217; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_18; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_36 = ~readys_mask_18; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_37 = readys_valid_18 & _readys_filter_T_36; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_18 = {_readys_filter_T_37, readys_valid_18}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_106 = readys_filter_18[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_107 = {readys_filter_18[3], readys_filter_18[2:0] | _readys_unready_T_106}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_108 = _readys_unready_T_107; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_109 = _readys_unready_T_108[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_110 = {readys_mask_18, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_18 = {1'h0, _readys_unready_T_109} | _readys_unready_T_110; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_54 = readys_unready_18[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_55 = readys_unready_18[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_56 = _readys_readys_T_54 & _readys_readys_T_55; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_18 = ~_readys_readys_T_56; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_223 = readys_readys_18; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_221 = |readys_valid_18; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_222 = latch_18 & _readys_T_221; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_114 = readys_readys_18 & readys_valid_18; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_115 = {_readys_mask_T_114, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_116 = _readys_mask_T_115[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_117 = _readys_mask_T_114 | _readys_mask_T_116; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_118 = _readys_mask_T_117; // @[package.scala:253:43, :254:17]
wire _readys_T_224 = _readys_T_223[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_18_0 = _readys_T_224; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_225 = _readys_T_223[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_18_1 = _readys_T_225; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_72 = readys_18_0 & portsDIO_filtered_16_valid; // @[Xbar.scala:352:24]
wire winner_18_0 = _winner_T_72; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_73 = readys_18_1 & portsDIO_filtered_1_16_valid; // @[Xbar.scala:352:24]
wire winner_18_1 = _winner_T_73; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_18 = winner_18_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_18 = prefixOR_1_18 | winner_18_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_16_d_valid_T = portsDIO_filtered_16_valid | portsDIO_filtered_1_16_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_18 = winner_18_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_18 = winner_18_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_18 = {maskedBeats_0_18[8:3], maskedBeats_0_18[2:0] | maskedBeats_1_18}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_72 = in_16_d_ready & in_16_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_73 = {1'h0, beatsLeft_18} - {9'h0, _beatsLeft_T_72}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_74 = _beatsLeft_T_73[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_75 = latch_18 ? initBeats_18 : _beatsLeft_T_74; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_18_0; // @[Arbiter.scala:88:26]
reg state_18_1; // @[Arbiter.scala:88:26]
wire muxState_18_0 = idle_18 ? winner_18_0 : state_18_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_18_1 = idle_18 ? winner_18_1 : state_18_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_18_0 = idle_18 ? readys_18_0 : state_18_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_18_1 = idle_18 ? readys_18_1 : state_18_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_16_ready_T = in_16_d_ready & allowed_18_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_16_ready = _filtered_16_ready_T; // @[Xbar.scala:352:24]
assign _filtered_16_ready_T_1 = in_16_d_ready & allowed_18_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_16_ready = _filtered_16_ready_T_1; // @[Xbar.scala:352:24]
wire _in_16_d_valid_T_1 = state_18_0 & portsDIO_filtered_16_valid; // @[Mux.scala:30:73]
wire _in_16_d_valid_T_2 = state_18_1 & portsDIO_filtered_1_16_valid; // @[Mux.scala:30:73]
wire _in_16_d_valid_T_3 = _in_16_d_valid_T_1 | _in_16_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_16_d_valid_WIRE = _in_16_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_16_d_valid_T_4 = idle_18 ? _in_16_d_valid_T : _in_16_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_16_d_valid = _in_16_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_16_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_16_d_bits_opcode = _in_16_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_16_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_16_d_bits_param = _in_16_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_16_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_16_d_bits_size = _in_16_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_16_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_16_d_bits_source = _in_16_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_16_d_bits_sink = _in_16_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_16_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_16_d_bits_denied = _in_16_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_16_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_16_d_bits_data = _in_16_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_16_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_16_d_bits_corrupt = _in_16_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_16_d_bits_T = muxState_18_0 & portsDIO_filtered_16_bits_corrupt; // @[Mux.scala:30:73]
wire _in_16_d_bits_T_1 = muxState_18_1 & portsDIO_filtered_1_16_bits_corrupt; // @[Mux.scala:30:73]
wire _in_16_d_bits_T_2 = _in_16_d_bits_T | _in_16_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_1 = _in_16_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_corrupt = _in_16_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_16_d_bits_T_3 = muxState_18_0 ? portsDIO_filtered_16_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_16_d_bits_T_4 = muxState_18_1 ? portsDIO_filtered_1_16_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_16_d_bits_T_5 = _in_16_d_bits_T_3 | _in_16_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_2 = _in_16_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_data = _in_16_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_16_d_bits_T_6 = muxState_18_0 & portsDIO_filtered_16_bits_denied; // @[Mux.scala:30:73]
wire _in_16_d_bits_T_7 = muxState_18_1 & portsDIO_filtered_1_16_bits_denied; // @[Mux.scala:30:73]
wire _in_16_d_bits_T_8 = _in_16_d_bits_T_6 | _in_16_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_5 = _in_16_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_denied = _in_16_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_9 = muxState_18_0 ? portsDIO_filtered_16_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_10 = muxState_18_1 ? portsDIO_filtered_1_16_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_11 = _in_16_d_bits_T_9 | _in_16_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_6 = _in_16_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_sink = _in_16_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_16_d_bits_T_12 = muxState_18_0 ? portsDIO_filtered_16_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_16_d_bits_T_13 = muxState_18_1 ? portsDIO_filtered_1_16_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_16_d_bits_T_14 = _in_16_d_bits_T_12 | _in_16_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_7 = _in_16_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_source = _in_16_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_16_d_bits_T_15 = muxState_18_0 ? portsDIO_filtered_16_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_16_d_bits_T_16 = muxState_18_1 ? portsDIO_filtered_1_16_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_16_d_bits_T_17 = _in_16_d_bits_T_15 | _in_16_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_8 = _in_16_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_size = _in_16_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_16_d_bits_T_18 = muxState_18_0 ? portsDIO_filtered_16_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_16_d_bits_T_19 = muxState_18_1 ? portsDIO_filtered_1_16_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_16_d_bits_T_20 = _in_16_d_bits_T_18 | _in_16_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_9 = _in_16_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_param = _in_16_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_21 = muxState_18_0 ? portsDIO_filtered_16_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_22 = muxState_18_1 ? portsDIO_filtered_1_16_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_16_d_bits_T_23 = _in_16_d_bits_T_21 | _in_16_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_10 = _in_16_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_16_d_bits_WIRE_opcode = _in_16_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_19; // @[Arbiter.scala:60:30]
wire idle_19 = beatsLeft_19 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_19 = idle_19 & in_17_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_226 = {portsDIO_filtered_1_17_valid, portsDIO_filtered_17_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_19 = _readys_T_226; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_227 = readys_valid_19 == _readys_T_226; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_229 = ~_readys_T_228; // @[Arbiter.scala:22:12]
wire _readys_T_230 = ~_readys_T_227; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_19; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_38 = ~readys_mask_19; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_39 = readys_valid_19 & _readys_filter_T_38; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_19 = {_readys_filter_T_39, readys_valid_19}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_111 = readys_filter_19[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_112 = {readys_filter_19[3], readys_filter_19[2:0] | _readys_unready_T_111}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_113 = _readys_unready_T_112; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_114 = _readys_unready_T_113[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_115 = {readys_mask_19, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_19 = {1'h0, _readys_unready_T_114} | _readys_unready_T_115; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_57 = readys_unready_19[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_58 = readys_unready_19[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_59 = _readys_readys_T_57 & _readys_readys_T_58; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_19 = ~_readys_readys_T_59; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_233 = readys_readys_19; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_231 = |readys_valid_19; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_232 = latch_19 & _readys_T_231; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_119 = readys_readys_19 & readys_valid_19; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_120 = {_readys_mask_T_119, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_121 = _readys_mask_T_120[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_122 = _readys_mask_T_119 | _readys_mask_T_121; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_123 = _readys_mask_T_122; // @[package.scala:253:43, :254:17]
wire _readys_T_234 = _readys_T_233[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_19_0 = _readys_T_234; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_235 = _readys_T_233[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_19_1 = _readys_T_235; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_74 = readys_19_0 & portsDIO_filtered_17_valid; // @[Xbar.scala:352:24]
wire winner_19_0 = _winner_T_74; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_75 = readys_19_1 & portsDIO_filtered_1_17_valid; // @[Xbar.scala:352:24]
wire winner_19_1 = _winner_T_75; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_19 = winner_19_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_19 = prefixOR_1_19 | winner_19_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_17_d_valid_T = portsDIO_filtered_17_valid | portsDIO_filtered_1_17_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_19 = winner_19_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_19 = winner_19_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_19 = {maskedBeats_0_19[8:3], maskedBeats_0_19[2:0] | maskedBeats_1_19}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_76 = in_17_d_ready & in_17_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_77 = {1'h0, beatsLeft_19} - {9'h0, _beatsLeft_T_76}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_78 = _beatsLeft_T_77[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_79 = latch_19 ? initBeats_19 : _beatsLeft_T_78; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_19_0; // @[Arbiter.scala:88:26]
reg state_19_1; // @[Arbiter.scala:88:26]
wire muxState_19_0 = idle_19 ? winner_19_0 : state_19_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_19_1 = idle_19 ? winner_19_1 : state_19_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_19_0 = idle_19 ? readys_19_0 : state_19_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_19_1 = idle_19 ? readys_19_1 : state_19_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_17_ready_T = in_17_d_ready & allowed_19_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_17_ready = _filtered_17_ready_T; // @[Xbar.scala:352:24]
assign _filtered_17_ready_T_1 = in_17_d_ready & allowed_19_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_17_ready = _filtered_17_ready_T_1; // @[Xbar.scala:352:24]
wire _in_17_d_valid_T_1 = state_19_0 & portsDIO_filtered_17_valid; // @[Mux.scala:30:73]
wire _in_17_d_valid_T_2 = state_19_1 & portsDIO_filtered_1_17_valid; // @[Mux.scala:30:73]
wire _in_17_d_valid_T_3 = _in_17_d_valid_T_1 | _in_17_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_17_d_valid_WIRE = _in_17_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_17_d_valid_T_4 = idle_19 ? _in_17_d_valid_T : _in_17_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_17_d_valid = _in_17_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_17_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_17_d_bits_opcode = _in_17_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_17_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_17_d_bits_param = _in_17_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_17_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_17_d_bits_size = _in_17_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_17_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_17_d_bits_source = _in_17_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_17_d_bits_sink = _in_17_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_17_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_17_d_bits_denied = _in_17_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_17_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_17_d_bits_data = _in_17_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_17_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_17_d_bits_corrupt = _in_17_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_17_d_bits_T = muxState_19_0 & portsDIO_filtered_17_bits_corrupt; // @[Mux.scala:30:73]
wire _in_17_d_bits_T_1 = muxState_19_1 & portsDIO_filtered_1_17_bits_corrupt; // @[Mux.scala:30:73]
wire _in_17_d_bits_T_2 = _in_17_d_bits_T | _in_17_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_1 = _in_17_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_corrupt = _in_17_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_17_d_bits_T_3 = muxState_19_0 ? portsDIO_filtered_17_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_17_d_bits_T_4 = muxState_19_1 ? portsDIO_filtered_1_17_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_17_d_bits_T_5 = _in_17_d_bits_T_3 | _in_17_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_2 = _in_17_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_data = _in_17_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_17_d_bits_T_6 = muxState_19_0 & portsDIO_filtered_17_bits_denied; // @[Mux.scala:30:73]
wire _in_17_d_bits_T_7 = muxState_19_1 & portsDIO_filtered_1_17_bits_denied; // @[Mux.scala:30:73]
wire _in_17_d_bits_T_8 = _in_17_d_bits_T_6 | _in_17_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_5 = _in_17_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_denied = _in_17_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_9 = muxState_19_0 ? portsDIO_filtered_17_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_10 = muxState_19_1 ? portsDIO_filtered_1_17_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_11 = _in_17_d_bits_T_9 | _in_17_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_6 = _in_17_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_sink = _in_17_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_17_d_bits_T_12 = muxState_19_0 ? portsDIO_filtered_17_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_17_d_bits_T_13 = muxState_19_1 ? portsDIO_filtered_1_17_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_17_d_bits_T_14 = _in_17_d_bits_T_12 | _in_17_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_7 = _in_17_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_source = _in_17_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_17_d_bits_T_15 = muxState_19_0 ? portsDIO_filtered_17_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_17_d_bits_T_16 = muxState_19_1 ? portsDIO_filtered_1_17_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_17_d_bits_T_17 = _in_17_d_bits_T_15 | _in_17_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_8 = _in_17_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_size = _in_17_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_17_d_bits_T_18 = muxState_19_0 ? portsDIO_filtered_17_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_17_d_bits_T_19 = muxState_19_1 ? portsDIO_filtered_1_17_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_17_d_bits_T_20 = _in_17_d_bits_T_18 | _in_17_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_9 = _in_17_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_param = _in_17_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_21 = muxState_19_0 ? portsDIO_filtered_17_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_22 = muxState_19_1 ? portsDIO_filtered_1_17_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_17_d_bits_T_23 = _in_17_d_bits_T_21 | _in_17_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_10 = _in_17_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_17_d_bits_WIRE_opcode = _in_17_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_20; // @[Arbiter.scala:60:30]
wire idle_20 = beatsLeft_20 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_20 = idle_20 & in_18_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_236 = {portsDIO_filtered_1_18_valid, portsDIO_filtered_18_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_20 = _readys_T_236; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_237 = readys_valid_20 == _readys_T_236; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_239 = ~_readys_T_238; // @[Arbiter.scala:22:12]
wire _readys_T_240 = ~_readys_T_237; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_20; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_40 = ~readys_mask_20; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_41 = readys_valid_20 & _readys_filter_T_40; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_20 = {_readys_filter_T_41, readys_valid_20}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_116 = readys_filter_20[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_117 = {readys_filter_20[3], readys_filter_20[2:0] | _readys_unready_T_116}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_118 = _readys_unready_T_117; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_119 = _readys_unready_T_118[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_120 = {readys_mask_20, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_20 = {1'h0, _readys_unready_T_119} | _readys_unready_T_120; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_60 = readys_unready_20[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_61 = readys_unready_20[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_62 = _readys_readys_T_60 & _readys_readys_T_61; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_20 = ~_readys_readys_T_62; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_243 = readys_readys_20; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_241 = |readys_valid_20; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_242 = latch_20 & _readys_T_241; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_124 = readys_readys_20 & readys_valid_20; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_125 = {_readys_mask_T_124, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_126 = _readys_mask_T_125[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_127 = _readys_mask_T_124 | _readys_mask_T_126; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_128 = _readys_mask_T_127; // @[package.scala:253:43, :254:17]
wire _readys_T_244 = _readys_T_243[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_20_0 = _readys_T_244; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_245 = _readys_T_243[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_20_1 = _readys_T_245; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_76 = readys_20_0 & portsDIO_filtered_18_valid; // @[Xbar.scala:352:24]
wire winner_20_0 = _winner_T_76; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_77 = readys_20_1 & portsDIO_filtered_1_18_valid; // @[Xbar.scala:352:24]
wire winner_20_1 = _winner_T_77; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_20 = winner_20_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_20 = prefixOR_1_20 | winner_20_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_18_d_valid_T = portsDIO_filtered_18_valid | portsDIO_filtered_1_18_valid; // @[Xbar.scala:352:24]
wire [8:0] maskedBeats_0_20 = winner_20_0 ? beatsDO_0 : 9'h0; // @[Edges.scala:221:14]
wire [2:0] maskedBeats_1_20 = winner_20_1 ? beatsDO_1 : 3'h0; // @[Edges.scala:221:14]
wire [8:0] initBeats_20 = {maskedBeats_0_20[8:3], maskedBeats_0_20[2:0] | maskedBeats_1_20}; // @[Arbiter.scala:82:69, :84:44]
wire _beatsLeft_T_80 = in_18_d_ready & in_18_d_valid; // @[Decoupled.scala:51:35]
wire [9:0] _beatsLeft_T_81 = {1'h0, beatsLeft_20} - {9'h0, _beatsLeft_T_80}; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_82 = _beatsLeft_T_81[8:0]; // @[Arbiter.scala:85:52]
wire [8:0] _beatsLeft_T_83 = latch_20 ? initBeats_20 : _beatsLeft_T_82; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_20_0; // @[Arbiter.scala:88:26]
reg state_20_1; // @[Arbiter.scala:88:26]
wire muxState_20_0 = idle_20 ? winner_20_0 : state_20_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_20_1 = idle_20 ? winner_20_1 : state_20_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_20_0 = idle_20 ? readys_20_0 : state_20_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_20_1 = idle_20 ? readys_20_1 : state_20_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
assign _filtered_18_ready_T = in_18_d_ready & allowed_20_0; // @[Xbar.scala:159:18]
assign portsDIO_filtered_18_ready = _filtered_18_ready_T; // @[Xbar.scala:352:24]
assign _filtered_18_ready_T_1 = in_18_d_ready & allowed_20_1; // @[Xbar.scala:159:18]
assign portsDIO_filtered_1_18_ready = _filtered_18_ready_T_1; // @[Xbar.scala:352:24]
wire _in_18_d_valid_T_1 = state_20_0 & portsDIO_filtered_18_valid; // @[Mux.scala:30:73]
wire _in_18_d_valid_T_2 = state_20_1 & portsDIO_filtered_1_18_valid; // @[Mux.scala:30:73]
wire _in_18_d_valid_T_3 = _in_18_d_valid_T_1 | _in_18_d_valid_T_2; // @[Mux.scala:30:73]
wire _in_18_d_valid_WIRE = _in_18_d_valid_T_3; // @[Mux.scala:30:73]
assign _in_18_d_valid_T_4 = idle_20 ? _in_18_d_valid_T : _in_18_d_valid_WIRE; // @[Mux.scala:30:73]
assign in_18_d_valid = _in_18_d_valid_T_4; // @[Xbar.scala:159:18]
wire [2:0] _in_18_d_bits_WIRE_10; // @[Mux.scala:30:73]
assign in_18_d_bits_opcode = _in_18_d_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [1:0] _in_18_d_bits_WIRE_9; // @[Mux.scala:30:73]
assign in_18_d_bits_param = _in_18_d_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _in_18_d_bits_WIRE_8; // @[Mux.scala:30:73]
assign in_18_d_bits_size = _in_18_d_bits_WIRE_size; // @[Mux.scala:30:73]
wire [8:0] _in_18_d_bits_WIRE_7; // @[Mux.scala:30:73]
assign in_18_d_bits_source = _in_18_d_bits_WIRE_source; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_WIRE_6; // @[Mux.scala:30:73]
assign in_18_d_bits_sink = _in_18_d_bits_WIRE_sink; // @[Mux.scala:30:73]
wire _in_18_d_bits_WIRE_5; // @[Mux.scala:30:73]
assign in_18_d_bits_denied = _in_18_d_bits_WIRE_denied; // @[Mux.scala:30:73]
wire [63:0] _in_18_d_bits_WIRE_2; // @[Mux.scala:30:73]
assign in_18_d_bits_data = _in_18_d_bits_WIRE_data; // @[Mux.scala:30:73]
wire _in_18_d_bits_WIRE_1; // @[Mux.scala:30:73]
assign in_18_d_bits_corrupt = _in_18_d_bits_WIRE_corrupt; // @[Mux.scala:30:73]
wire _in_18_d_bits_T = muxState_20_0 & portsDIO_filtered_18_bits_corrupt; // @[Mux.scala:30:73]
wire _in_18_d_bits_T_1 = muxState_20_1 & portsDIO_filtered_1_18_bits_corrupt; // @[Mux.scala:30:73]
wire _in_18_d_bits_T_2 = _in_18_d_bits_T | _in_18_d_bits_T_1; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_1 = _in_18_d_bits_T_2; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_corrupt = _in_18_d_bits_WIRE_1; // @[Mux.scala:30:73]
wire [63:0] _in_18_d_bits_T_3 = muxState_20_0 ? portsDIO_filtered_18_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_18_d_bits_T_4 = muxState_20_1 ? portsDIO_filtered_1_18_bits_data : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _in_18_d_bits_T_5 = _in_18_d_bits_T_3 | _in_18_d_bits_T_4; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_2 = _in_18_d_bits_T_5; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_data = _in_18_d_bits_WIRE_2; // @[Mux.scala:30:73]
wire _in_18_d_bits_T_6 = muxState_20_0 & portsDIO_filtered_18_bits_denied; // @[Mux.scala:30:73]
wire _in_18_d_bits_T_7 = muxState_20_1 & portsDIO_filtered_1_18_bits_denied; // @[Mux.scala:30:73]
wire _in_18_d_bits_T_8 = _in_18_d_bits_T_6 | _in_18_d_bits_T_7; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_5 = _in_18_d_bits_T_8; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_denied = _in_18_d_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_9 = muxState_20_0 ? portsDIO_filtered_18_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_10 = muxState_20_1 ? portsDIO_filtered_1_18_bits_sink : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_11 = _in_18_d_bits_T_9 | _in_18_d_bits_T_10; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_6 = _in_18_d_bits_T_11; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_sink = _in_18_d_bits_WIRE_6; // @[Mux.scala:30:73]
wire [8:0] _in_18_d_bits_T_12 = muxState_20_0 ? portsDIO_filtered_18_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_18_d_bits_T_13 = muxState_20_1 ? portsDIO_filtered_1_18_bits_source : 9'h0; // @[Mux.scala:30:73]
wire [8:0] _in_18_d_bits_T_14 = _in_18_d_bits_T_12 | _in_18_d_bits_T_13; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_7 = _in_18_d_bits_T_14; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_source = _in_18_d_bits_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _in_18_d_bits_T_15 = muxState_20_0 ? portsDIO_filtered_18_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_18_d_bits_T_16 = muxState_20_1 ? portsDIO_filtered_1_18_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _in_18_d_bits_T_17 = _in_18_d_bits_T_15 | _in_18_d_bits_T_16; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_8 = _in_18_d_bits_T_17; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_size = _in_18_d_bits_WIRE_8; // @[Mux.scala:30:73]
wire [1:0] _in_18_d_bits_T_18 = muxState_20_0 ? portsDIO_filtered_18_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_18_d_bits_T_19 = muxState_20_1 ? portsDIO_filtered_1_18_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _in_18_d_bits_T_20 = _in_18_d_bits_T_18 | _in_18_d_bits_T_19; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_9 = _in_18_d_bits_T_20; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_param = _in_18_d_bits_WIRE_9; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_21 = muxState_20_0 ? portsDIO_filtered_18_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_22 = muxState_20_1 ? portsDIO_filtered_1_18_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _in_18_d_bits_T_23 = _in_18_d_bits_T_21 | _in_18_d_bits_T_22; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_10 = _in_18_d_bits_T_23; // @[Mux.scala:30:73]
assign _in_18_d_bits_WIRE_opcode = _in_18_d_bits_WIRE_10; // @[Mux.scala:30:73]
reg [8:0] beatsLeft_21; // @[Arbiter.scala:60:30]
wire idle_21 = beatsLeft_21 == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch_21 = idle_21 & in_19_d_ready; // @[Xbar.scala:159:18]
wire [1:0] _readys_T_246 = {portsDIO_filtered_1_19_valid, portsDIO_filtered_19_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid_21 = _readys_T_246; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_247 = readys_valid_21 == _readys_T_246; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_249 = ~_readys_T_248; // @[Arbiter.scala:22:12]
wire _readys_T_250 = ~_readys_T_247; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask_21; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_42 = ~readys_mask_21; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_43 = readys_valid_21 & _readys_filter_T_42; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter_21 = {_readys_filter_T_43, readys_valid_21}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T_121 = readys_filter_21[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_122 = {readys_filter_21[3], readys_filter_21[2:0] | _readys_unready_T_121}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_123 = _readys_unready_T_122; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_124 = _readys_unready_T_123[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_125 = {readys_mask_21, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready_21 = {1'h0, _readys_unready_T_124} | _readys_unready_T_125; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T_63 = readys_unready_21[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_64 = readys_unready_21[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_65 = _readys_readys_T_63 & _readys_readys_T_64; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys_21 = ~_readys_readys_T_65; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_253 = readys_readys_21; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_251 = |readys_valid_21; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_252 = latch_21 & _readys_T_251; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T_129 = readys_readys_21 & readys_valid_21; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_130 = {_readys_mask_T_129, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_131 = _readys_mask_T_130[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_132 = _readys_mask_T_129 | _readys_mask_T_131; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_133 = _readys_mask_T_132; // @[package.scala:253:43, :254:17]
wire _readys_T_254 = _readys_T_253[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_21_0 = _readys_T_254; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_255 = _readys_T_253[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_21_1 = _readys_T_255; // @[Arbiter.scala:68:{27,76}]
wire _winner_T_78 = readys_21_0 & portsDIO_filtered_19_valid; // @[Xbar.scala:352:24]
wire winner_21_0 = _winner_T_78; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_79 = readys_21_1 & portsDIO_filtered_1_19_valid; // @[Xbar.scala:352:24]
wire winner_21_1 = _winner_T_79; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1_21 = winner_21_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T_21 = prefixOR_1_21 | winner_21_1; // @[Arbiter.scala:71:27, :76:48]
wire _in_19_d_valid_T = portsDIO_filtered_19_valid | portsDIO_filtered_1_19_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module PE_405 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_149
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_405( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_149 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_267 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_284
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_267( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_284 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_3 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst q of Queue1_TLBundleA_a32d64s6k5z4c_3
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000))
node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7)
node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000))
node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10)
node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9)
node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000))
node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25)
node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27)
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040))
node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30)
node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32)
node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040))
node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35)
node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37)
node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39)
node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41)
node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080))
node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42)
node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44)
node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080))
node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47)
node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49)
node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51)
node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53)
node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0))
node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54)
node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56)
node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0))
node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59)
node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61)
node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63)
node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0ha), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hd), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h10), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h13), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(has_body_opdata, _has_body_T_1)
connect has_body, _has_body_T_2
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h24))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLAToNoC_3( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC :
input clock : Clock
input reset : Reset
output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}}
invalidate io.tilelink.e.bits.sink
invalidate io.tilelink.e.valid
invalidate io.tilelink.e.ready
invalidate io.tilelink.d.bits.corrupt
invalidate io.tilelink.d.bits.data
invalidate io.tilelink.d.bits.denied
invalidate io.tilelink.d.bits.sink
invalidate io.tilelink.d.bits.source
invalidate io.tilelink.d.bits.size
invalidate io.tilelink.d.bits.param
invalidate io.tilelink.d.bits.opcode
invalidate io.tilelink.d.valid
invalidate io.tilelink.d.ready
invalidate io.tilelink.c.bits.corrupt
invalidate io.tilelink.c.bits.data
invalidate io.tilelink.c.bits.address
invalidate io.tilelink.c.bits.source
invalidate io.tilelink.c.bits.size
invalidate io.tilelink.c.bits.param
invalidate io.tilelink.c.bits.opcode
invalidate io.tilelink.c.valid
invalidate io.tilelink.c.ready
invalidate io.tilelink.b.bits.corrupt
invalidate io.tilelink.b.bits.data
invalidate io.tilelink.b.bits.mask
invalidate io.tilelink.b.bits.address
invalidate io.tilelink.b.bits.source
invalidate io.tilelink.b.bits.size
invalidate io.tilelink.b.bits.param
invalidate io.tilelink.b.bits.opcode
invalidate io.tilelink.b.valid
invalidate io.tilelink.b.ready
invalidate io.tilelink.a.bits.corrupt
invalidate io.tilelink.a.bits.data
invalidate io.tilelink.a.bits.mask
invalidate io.tilelink.a.bits.address
invalidate io.tilelink.a.bits.source
invalidate io.tilelink.a.bits.size
invalidate io.tilelink.a.bits.param
invalidate io.tilelink.a.bits.opcode
invalidate io.tilelink.a.valid
invalidate io.tilelink.a.ready
inst a of TLAToNoC
connect a.clock, clock
connect a.reset, reset
inst c of TLCToNoC
connect c.clock, clock
connect c.reset, reset
inst d of TLDFromNoC
connect d.clock, clock
connect d.reset, reset
connect a.io.protocol, io.tilelink.a
connect c.io.protocol, io.tilelink.c
connect io.tilelink.d.bits, d.io.protocol.bits
connect io.tilelink.d.valid, d.io.protocol.valid
connect d.io.protocol.ready, io.tilelink.d.ready
connect io.flits.a.bits, a.io.flit.bits
connect io.flits.a.valid, a.io.flit.valid
connect a.io.flit.ready, io.flits.a.ready
connect io.flits.c.bits, c.io.flit.bits
connect io.flits.c.valid, c.io.flit.valid
connect c.io.flit.ready, io.flits.c.ready
connect d.io.flit, io.flits.d | module TLMasterACDToNoC( // @[Tilelink.scala:72:7]
input clock, // @[Tilelink.scala:72:7]
input reset, // @[Tilelink.scala:72:7]
output io_tilelink_a_ready, // @[Tilelink.scala:79:14]
input io_tilelink_a_valid, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14]
input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14]
input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14]
input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14]
input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14]
input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14]
input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14]
input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14]
input io_tilelink_d_ready, // @[Tilelink.scala:79:14]
output io_tilelink_d_valid, // @[Tilelink.scala:79:14]
output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14]
output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14]
output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14]
output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14]
output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14]
output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14]
output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14]
input io_flits_a_ready, // @[Tilelink.scala:79:14]
output io_flits_a_valid, // @[Tilelink.scala:79:14]
output io_flits_a_bits_head, // @[Tilelink.scala:79:14]
output io_flits_a_bits_tail, // @[Tilelink.scala:79:14]
output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14]
output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14]
output io_flits_c_valid, // @[Tilelink.scala:79:14]
output io_flits_d_ready, // @[Tilelink.scala:79:14]
input io_flits_d_valid, // @[Tilelink.scala:79:14]
input io_flits_d_bits_head, // @[Tilelink.scala:79:14]
input io_flits_d_bits_tail, // @[Tilelink.scala:79:14]
input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14]
);
TLAToNoC a ( // @[Tilelink.scala:88:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload),
.io_flit_bits_egress_id (io_flits_a_bits_egress_id)
); // @[Tilelink.scala:88:17]
TLCToNoC c ( // @[Tilelink.scala:89:17]
.clock (clock),
.reset (reset),
.io_flit_valid (io_flits_c_valid)
); // @[Tilelink.scala:89:17]
TLDFromNoC d ( // @[Tilelink.scala:90:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14]
); // @[Tilelink.scala:90:17]
endmodule |
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