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-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
DECODE : string := "010";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
DECODE : string := "001";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
DECODE : string := "100";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
DECODE : string := "011";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNBHXAVAPH_1: if ((DECODE = "010") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNBHXAVAPH_1: alt_dspbuilder_decoder_GNBHXAVAPH
generic map(DECODE => "010", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNQPHUITBS_2: if ((DECODE = "001") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNQPHUITBS_2: alt_dspbuilder_decoder_GNQPHUITBS
generic map(DECODE => "001", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GN7W55JURN_3: if ((DECODE = "100") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GN7W55JURN_3: alt_dspbuilder_decoder_GN7W55JURN
generic map(DECODE => "100", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNBT6YIKS3_4: if ((DECODE = "011") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNBT6YIKS3_4: alt_dspbuilder_decoder_GNBT6YIKS3
generic map(DECODE => "011", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "010") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "001") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "100") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "011") and (PIPELINE = 1) and (WIDTH = 3)))
report "Please run generate again" severity error;
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: decryption_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY decryption_mem_tb IS
END ENTITY;
ARCHITECTURE decryption_mem_tb_ARCH OF decryption_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
decryption_mem_synth_inst:ENTITY work.decryption_mem_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Sync is
Port(
clk: in std_logic;
R_in, G_in, B_in : in std_logic_vector(3 downto 0);
x, y : out std_logic_vector(11 downto 0);
HSync, VSync: out std_logic;
R, G, B : out std_logic_vector(3 downto 0)
);
end Sync;
Architecture behavioral of Sync is
signal x_pos : unsigned(11 downto 0) := (others => '0');
signal y_pos : unsigned(11 downto 0) := (others => '0');
begin
--Output the correct x and y signals when their values are going to be rendered.
x <= std_logic_vector(x_pos - 160) when (x_pos > 159) else
(others => '1');
y <= std_logic_vector(y_pos-45) when (y_pos > 44) else
(others => '1');
process(clk)
begin
--On the rising edge of the clock increment the x and y values.
if(clk'event and clk='1') then
if(x_pos < 800) then
x_pos <= x_pos + 1;
else
x_pos <= (others => '0');
if(y_pos < 525) then
y_pos <= y_pos + 1;
else
y_pos <= (others => '0');
end if;
end if;
--for x <160 and y <45 we must follow the vga protocol.
if(x_pos > 15 and x_pos < 112) then
Hsync <= '0';
else
HSync <='1';
end if;
if(y_pos > 9 and y_pos < 12) then
Vsync <='0';
else
Vsync <='1';
end if;
if((x_pos >= 0 and x_pos < 160) or (y_pos >= 0 and y_pos < 45)) then
R <= (others => '0');
G <= (others => '0');
B <= (others => '0');
else --If we are in range, forward the red green and blue values coming in.
R <= R_in;
G <= G_in;
B <= B_in;
end if;
end if;
end process;
end behavioral; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
entity offset_correction is
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
rd_fifo_count : in std_logic;
parameters : in param;
wr_en_flag : in std_logic;
wr_fifo : out std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end offset_correction;
architecture RTL of offset_correction is
signal count : unsigned(1 downto 0);
signal raw_data : std_logic_vector(15 downto 0);
signal data_cor : std_logic_vector(15 downto 0);
signal count_value : unsigned(3 downto 0);
signal offset, offset_default : std_logic_vector(15 downto 0);
signal sign : std_logic;
type state_off is (idle,correction);
signal state : state_off;
begin
--------This process correct data values by subtracting the corresponding offset to the raw value.
process(clk,reset)
begin
if reset='0' then
count <= "00";
wr_fifo <= '0';
count_value <= x"0";
elsif clk'event and clk='1' then
if enable ='1' then
case(state) is
when idle =>
if wr_en_flag='1' then
count <= count +1;
raw_data <= raw_data(7 downto 0) & data_i;
elsif count="10" then
count <= "00";
state <= correction;
if rd_fifo_count='0' then
if count_value=x"9" then
count_value <= x"0";
else
count_value <= count_value+1;
end if;
if count_value<x"7" then
data_cor <= raw_data-offset;
else
data_cor <= raw_data;
end if;
else
data_cor <= raw_data;
end if;
end if;
when correction =>
if count="10" then
count <= "00";
state <= idle;
wr_fifo <= '0';
else
count <= count+1;
wr_fifo <= '1';
data_o <= data_cor(15 downto 8);
data_cor <= data_cor(7 downto 0) & data_cor(15 downto 8);
end if;
end case;
else
count <= "00";
wr_fifo <= '0';
count_value <= x"0";
state <= idle;
end if;
end if;
end process;
--------This process determine each offset to subtract depending on the actual configuration and its value (whether it is negative or positive)
process(clk,reset)
begin
if reset='0' then
offset <= x"0000";
elsif clk'event and clk='1' then
if enable = '1' then
if count_value<3 then
if parameters(0)(20 downto 19)="01" then
offset <= sign & offset_default(15 downto 1);
elsif parameters(0)(20 downto 19)="10" then
offset <= sign&sign& offset_default(15 downto 2);
elsif parameters(0)(20 downto 19)="11" then
offset <= sign&sign&sign& offset_default(15 downto 3);
else
offset <= offset_default;
end if;
else
if parameters(0)(22 downto 21)="01" then
offset <= sign & offset_default(15 downto 1);
elsif parameters(0)(22 downto 21)="10" then
offset <= sign&sign& offset_default(15 downto 2);
elsif parameters(0)(22 downto 21)="11" then
offset <= sign&sign&sign& offset_default(15 downto 3);
else
offset <= offset_default;
end if;
end if;
end if;
end if;
end process;
sign <= offset_default(15);
offset_default <= parameters(1)(15 downto 0) when count_value = x"0" else --offset accel X
parameters(2)(15 downto 0) when count_value = x"1" else --offset accel Y
parameters(3)(15 downto 0) when count_value = x"2" else --offset accel Z
parameters(1)(31 downto 16) when count_value = x"4" else --offset gyro X
parameters(2)(31 downto 16) when count_value = x"5" else --offset gyro Y
parameters(3)(31 downto 16) when count_value = x"6" else --offset gyro Z
x"0000";
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2C_TB is
end entity I2C_TB;
architecture RTL of I2C_TB is
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end component I2C;
type STATE_TYPE is(GET_COMMAND, EXECUTE_COMMAND, WRITE, READ);
signal STATE : STATE_TYPE;
type OPERATION_TYPE is(WRITE, READ);
type COMMAND_TYPE is
record
OPERATION : OPERATION_TYPE;
DATA : std_logic_vector(31 downto 0);
end record;
signal COMMAND : COMMAND_TYPE;
type COMMANDS_TYPE is array (integer range 0 to 5) of COMMAND_TYPE;
signal COMMANDS : COMMANDS_TYPE := (
0 => (OPERATION => WRITE, DATA => X"000000AA"),
1 => (OPERATION => READ, DATA => X"00000001"),
2 => (OPERATION => WRITE, DATA => X"000001AA"),
3 => (OPERATION => READ, DATA => X"000000FF"),
4 => (OPERATION => WRITE, DATA => X"00000DAA"),
5 => (OPERATION => READ, DATA => X"000000FF")
);
signal PROGRAM_COUNTER : integer := 0;
signal CLK : std_logic;
signal RST : std_logic;
signal SDA : std_logic;
signal SCL : std_logic;
signal I2C_IN : std_logic_vector(31 downto 0);
signal I2C_IN_STB : std_logic;
signal I2C_IN_ACK : std_logic;
signal I2C_OUT : std_logic_vector(31 downto 0);
signal I2C_OUT_STB : std_logic;
signal I2C_OUT_ACK : std_logic;
begin
UUT : I2C generic map(
CLOCKS_PER_SECOND => 50000000,
SPEED => 5000000
)
port map(
CLK => CLK,
RST => RST,
SDA => SDA,
SCL => SCL,
I2C_IN => I2C_IN,
I2C_IN_STB => I2C_IN_STB,
I2C_IN_ACK => I2C_IN_ACK,
I2C_OUT => I2C_OUT,
I2C_OUT_STB => I2C_OUT_STB,
I2C_OUT_ACK => I2C_OUT_ACK
);
process
begin
while True loop
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end loop;
wait;
end process;
process
begin
RST <= '1';
wait for 100 ns;
RST <= '0';
wait;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_COMMAND =>
report integer'image(PROGRAM_COUNTER);
COMMAND <= COMMANDS(PROGRAM_COUNTER);
if PROGRAM_COUNTER < 5 then
PROGRAM_COUNTER <= PROGRAM_COUNTER + 1;
end if;
STATE <= EXECUTE_COMMAND;
when EXECUTE_COMMAND =>
if COMMAND.OPERATION = WRITE then
STATE <= WRITE;
elsif COMMAND.OPERATION = READ then
STATE <= READ;
end if;
when WRITE =>
I2C_IN <= COMMAND.DATA;
I2C_IN_STB <= '1';
if I2C_IN_STB = '1' and I2C_IN_ACK = '1' then
I2C_IN_STB <= '0';
STATE <= GET_COMMAND;
end if;
when READ =>
I2C_OUT_ACK <= '1';
if I2C_OUT_STB = '1' and I2C_OUT_ACK = '1' then
I2C_OUT_ACK <= '0';
STATE <= GET_COMMAND;
report integer'image(to_integer(unsigned(I2C_OUT)));
assert I2C_OUT = COMMAND.DATA;
end if;
end case;
if RST = '1' then
STATE <= GET_COMMAND;
PROGRAM_COUNTER <= 0;
I2C_IN_STB <= '0';
I2C_OUT_ACK <= '0';
end if;
end process;
end RTL;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_sim_netlist.vhdl
-- Design : system_vga_hessian_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_bindec : entity is "bindec";
end system_vga_hessian_0_0_bindec;
architecture STRUCTURE of system_vga_hessian_0_0_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => ena,
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => addra(1),
O => ena_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_bindec_0 is
port (
enb_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_bindec_0 : entity is "bindec";
end system_vga_hessian_0_0_bindec_0;
architecture STRUCTURE of system_vga_hessian_0_0_bindec_0 is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => enb,
I1 => addrb(0),
I2 => addrb(1),
O => enb_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(1),
I1 => addrb(0),
I2 => enb,
O => enb_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(0),
I1 => enb,
I2 => addrb(1),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end system_vga_hessian_0_0_blk_mem_gen_mux;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\douta[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 8 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
clkb : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
begin
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(3)
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(4)
);
\doutb[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(5)
);
\doutb[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(6)
);
\doutb[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(7)
);
\doutb[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(8)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(0)
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(1)
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_vga_hessian_0_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 1) => B"000000000000000",
DIBDI(0) => dinb(0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => doutb(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => ena,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
I2 => enb,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_vga_hessian_0_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.system_vga_hessian_0_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(0) => DOPBDOP(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_vga_hessian_0_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal enb_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_9\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.system_vga_hessian_0_0_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena => ena,
ena_array(2 downto 0) => ena_array(2 downto 0)
);
\bindec_b.bindec_inst_b\: entity work.system_vga_hessian_0_0_bindec_0
port map (
addrb(1 downto 0) => addrb(13 downto 12),
enb => enb,
enb_array(2 downto 0) => enb_array(2 downto 0)
);
\has_mux_a.A\: entity work.system_vga_hessian_0_0_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_16\,
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(15 downto 7),
ena => ena
);
\has_mux_b.B\: entity work.\system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_17\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addrb(1 downto 0) => addrb(13 downto 12),
clkb => clkb,
doutb(8 downto 0) => doutb(15 downto 7),
enb => enb
);
\ramloop[0].ram.r\: entity work.system_vga_hessian_0_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
dinb(1 downto 0) => dinb(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
doutb(1 downto 0) => doutb(2 downto 1),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(4 downto 3),
dinb(1 downto 0) => dinb(4 downto 3),
douta(1 downto 0) => douta(4 downto 3),
doutb(1 downto 0) => doutb(4 downto 3),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(6 downto 5),
dinb(1 downto 0) => dinb(6 downto 5),
douta(1 downto 0) => douta(6 downto 5),
doutb(1 downto 0) => doutb(6 downto 5),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[4].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[4].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[4].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[4].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[4].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[4].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[4].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[4].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[4].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7) => \ramloop[4].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[4].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[4].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[4].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[4].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[4].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[4].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[4].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[4].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[5].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[5].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[5].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[5].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[5].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[5].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[5].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[5].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[5].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[5].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(1),
enb => enb,
enb_array(0) => enb_array(1),
\top_right_1_reg[14]\(7) => \ramloop[5].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[5].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[5].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[5].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[5].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[5].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[5].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[5].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[5].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[6].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[6].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[6].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[6].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[6].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[6].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[6].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[6].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[6].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[6].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(2),
enb => enb,
enb_array(0) => enb_array(2),
\top_right_1_reg[14]\(7) => \ramloop[6].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[6].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[6].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[6].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[6].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[6].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[6].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[6].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[6].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[7].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\
port map (
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_vga_hessian_0_0_blk_mem_gen_top;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.system_vga_hessian_0_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.system_vga_hessian_0_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "yes";
end system_vga_hessian_0_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_0";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end system_vga_hessian_0_0_blk_mem_gen_0;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_vga_hessian_0_0_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15 downto 0) => B"0000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_vga_hessian is
port (
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
clk_x16 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_vga_hessian : entity is "vga_hessian";
end system_vga_hessian_0_0_vga_hessian;
architecture STRUCTURE of system_vga_hessian_0_0_vga_hessian is
signal A : STD_LOGIC_VECTOR ( 15 downto 0 );
signal B : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx : STD_LOGIC;
signal \Lxx0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_1\ : STD_LOGIC;
signal \Lxx0_carry__0_n_2\ : STD_LOGIC;
signal \Lxx0_carry__0_n_3\ : STD_LOGIC;
signal \Lxx0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_1\ : STD_LOGIC;
signal \Lxx0_carry__1_n_2\ : STD_LOGIC;
signal \Lxx0_carry__1_n_3\ : STD_LOGIC;
signal \Lxx0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_n_1\ : STD_LOGIC;
signal \Lxx0_carry__2_n_2\ : STD_LOGIC;
signal \Lxx0_carry__2_n_3\ : STD_LOGIC;
signal Lxx0_carry_i_1_n_0 : STD_LOGIC;
signal Lxx0_carry_i_2_n_0 : STD_LOGIC;
signal Lxx0_carry_i_3_n_0 : STD_LOGIC;
signal Lxx0_carry_i_4_n_0 : STD_LOGIC;
signal Lxx0_carry_i_5_n_0 : STD_LOGIC;
signal Lxx0_carry_i_6_n_0 : STD_LOGIC;
signal Lxx0_carry_n_0 : STD_LOGIC;
signal Lxx0_carry_n_1 : STD_LOGIC;
signal Lxx0_carry_n_2 : STD_LOGIC;
signal Lxx0_carry_n_3 : STD_LOGIC;
signal Lxx_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx_00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_00__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_3\ : STD_LOGIC;
signal Lxx_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lxx_11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_11__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_3\ : STD_LOGIC;
signal \Lxx_2[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[9]\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry_n_7\ : STD_LOGIC;
signal \Lxy_0[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_1 : STD_LOGIC;
signal \Lxy_1_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_2 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxy_3 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy0_carry__2_n_3\ : STD_LOGIC;
signal Lyy0_carry_i_1_n_0 : STD_LOGIC;
signal Lyy0_carry_i_2_n_0 : STD_LOGIC;
signal Lyy0_carry_i_3_n_0 : STD_LOGIC;
signal Lyy0_carry_i_4_n_0 : STD_LOGIC;
signal Lyy0_carry_i_5_n_0 : STD_LOGIC;
signal Lyy0_carry_i_6_n_0 : STD_LOGIC;
signal Lyy0_carry_n_0 : STD_LOGIC;
signal Lyy0_carry_n_1 : STD_LOGIC;
signal Lyy0_carry_n_2 : STD_LOGIC;
signal Lyy0_carry_n_3 : STD_LOGIC;
signal Lyy_0 : STD_LOGIC;
signal \Lyy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lyy_20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_20__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_3\ : STD_LOGIC;
signal \Lyy_2[15]_i_1_n_0\ : STD_LOGIC;
signal Lyy_2_bottom_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right01_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_3\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_2_top_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_top_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal addr_0 : STD_LOGIC;
signal \addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal bottom_left_0 : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \bottom_right_0[0]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[10]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[11]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[12]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[13]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[14]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_3_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_4_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_5_n_0\ : STD_LOGIC;
signal \bottom_right_0[1]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[2]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[3]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[4]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[5]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[6]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[7]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[8]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[9]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_right_1 : STD_LOGIC;
signal \bottom_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \cache[10]_5\ : STD_LOGIC;
signal \cache[9][15]_i_1_n_0\ : STD_LOGIC;
signal \cache_reg[0]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[10]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[3][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[4]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[7][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[8]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[9]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg_gate__0_n_0\ : STD_LOGIC;
signal \cache_reg_gate__10_n_0\ : STD_LOGIC;
signal \cache_reg_gate__11_n_0\ : STD_LOGIC;
signal \cache_reg_gate__12_n_0\ : STD_LOGIC;
signal \cache_reg_gate__13_n_0\ : STD_LOGIC;
signal \cache_reg_gate__14_n_0\ : STD_LOGIC;
signal \cache_reg_gate__15_n_0\ : STD_LOGIC;
signal \cache_reg_gate__16_n_0\ : STD_LOGIC;
signal \cache_reg_gate__17_n_0\ : STD_LOGIC;
signal \cache_reg_gate__18_n_0\ : STD_LOGIC;
signal \cache_reg_gate__19_n_0\ : STD_LOGIC;
signal \cache_reg_gate__1_n_0\ : STD_LOGIC;
signal \cache_reg_gate__20_n_0\ : STD_LOGIC;
signal \cache_reg_gate__21_n_0\ : STD_LOGIC;
signal \cache_reg_gate__22_n_0\ : STD_LOGIC;
signal \cache_reg_gate__23_n_0\ : STD_LOGIC;
signal \cache_reg_gate__24_n_0\ : STD_LOGIC;
signal \cache_reg_gate__25_n_0\ : STD_LOGIC;
signal \cache_reg_gate__26_n_0\ : STD_LOGIC;
signal \cache_reg_gate__27_n_0\ : STD_LOGIC;
signal \cache_reg_gate__28_n_0\ : STD_LOGIC;
signal \cache_reg_gate__29_n_0\ : STD_LOGIC;
signal \cache_reg_gate__2_n_0\ : STD_LOGIC;
signal \cache_reg_gate__30_n_0\ : STD_LOGIC;
signal \cache_reg_gate__3_n_0\ : STD_LOGIC;
signal \cache_reg_gate__4_n_0\ : STD_LOGIC;
signal \cache_reg_gate__5_n_0\ : STD_LOGIC;
signal \cache_reg_gate__6_n_0\ : STD_LOGIC;
signal \cache_reg_gate__7_n_0\ : STD_LOGIC;
signal \cache_reg_gate__8_n_0\ : STD_LOGIC;
signal \cache_reg_gate__9_n_0\ : STD_LOGIC;
signal cache_reg_gate_n_0 : STD_LOGIC;
signal cache_reg_r_0_n_0 : STD_LOGIC;
signal cache_reg_r_1_n_0 : STD_LOGIC;
signal cache_reg_r_n_0 : STD_LOGIC;
signal compute_addr_0 : STD_LOGIC;
signal \compute_addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal compute_addr_2 : STD_LOGIC;
signal \compute_addr_2[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_4_n_0\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_3 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_3[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[9]_i_1_n_0\ : STD_LOGIC;
signal corner : STD_LOGIC;
signal \corner_reg_n_0_[0]\ : STD_LOGIC;
signal \corner_reg_n_0_[10]\ : STD_LOGIC;
signal \corner_reg_n_0_[11]\ : STD_LOGIC;
signal \corner_reg_n_0_[12]\ : STD_LOGIC;
signal \corner_reg_n_0_[13]\ : STD_LOGIC;
signal \corner_reg_n_0_[14]\ : STD_LOGIC;
signal \corner_reg_n_0_[15]\ : STD_LOGIC;
signal \corner_reg_n_0_[1]\ : STD_LOGIC;
signal \corner_reg_n_0_[2]\ : STD_LOGIC;
signal \corner_reg_n_0_[3]\ : STD_LOGIC;
signal \corner_reg_n_0_[4]\ : STD_LOGIC;
signal \corner_reg_n_0_[5]\ : STD_LOGIC;
signal \corner_reg_n_0_[6]\ : STD_LOGIC;
signal \corner_reg_n_0_[7]\ : STD_LOGIC;
signal \corner_reg_n_0_[8]\ : STD_LOGIC;
signal \corner_reg_n_0_[9]\ : STD_LOGIC;
signal cycle : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cycle[0]_i_1_n_0\ : STD_LOGIC;
signal \cycle[0]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1__0_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_2_n_0\ : STD_LOGIC;
signal \cycle_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[2]_rep_n_0\ : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data2 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data5 : STD_LOGIC_VECTOR ( 13 downto 10 );
signal det_0 : STD_LOGIC;
signal det_0_reg_i_2_n_0 : STD_LOGIC;
signal det_0_reg_n_106 : STD_LOGIC;
signal det_0_reg_n_107 : STD_LOGIC;
signal det_0_reg_n_108 : STD_LOGIC;
signal det_0_reg_n_109 : STD_LOGIC;
signal det_0_reg_n_110 : STD_LOGIC;
signal det_0_reg_n_111 : STD_LOGIC;
signal det_0_reg_n_112 : STD_LOGIC;
signal det_0_reg_n_113 : STD_LOGIC;
signal det_0_reg_n_114 : STD_LOGIC;
signal det_0_reg_n_115 : STD_LOGIC;
signal det_0_reg_n_116 : STD_LOGIC;
signal det_0_reg_n_117 : STD_LOGIC;
signal det_0_reg_n_118 : STD_LOGIC;
signal det_0_reg_n_119 : STD_LOGIC;
signal det_0_reg_n_120 : STD_LOGIC;
signal det_0_reg_n_121 : STD_LOGIC;
signal det_0_reg_n_122 : STD_LOGIC;
signal det_0_reg_n_123 : STD_LOGIC;
signal det_0_reg_n_124 : STD_LOGIC;
signal det_0_reg_n_125 : STD_LOGIC;
signal det_0_reg_n_126 : STD_LOGIC;
signal det_0_reg_n_127 : STD_LOGIC;
signal det_0_reg_n_128 : STD_LOGIC;
signal det_0_reg_n_129 : STD_LOGIC;
signal det_0_reg_n_130 : STD_LOGIC;
signal det_0_reg_n_131 : STD_LOGIC;
signal det_0_reg_n_132 : STD_LOGIC;
signal det_0_reg_n_133 : STD_LOGIC;
signal det_0_reg_n_134 : STD_LOGIC;
signal det_0_reg_n_135 : STD_LOGIC;
signal det_0_reg_n_136 : STD_LOGIC;
signal det_0_reg_n_137 : STD_LOGIC;
signal det_0_reg_n_138 : STD_LOGIC;
signal det_0_reg_n_139 : STD_LOGIC;
signal det_0_reg_n_140 : STD_LOGIC;
signal det_0_reg_n_141 : STD_LOGIC;
signal det_0_reg_n_142 : STD_LOGIC;
signal det_0_reg_n_143 : STD_LOGIC;
signal det_0_reg_n_144 : STD_LOGIC;
signal det_0_reg_n_145 : STD_LOGIC;
signal det_0_reg_n_146 : STD_LOGIC;
signal det_0_reg_n_147 : STD_LOGIC;
signal det_0_reg_n_148 : STD_LOGIC;
signal det_0_reg_n_149 : STD_LOGIC;
signal det_0_reg_n_150 : STD_LOGIC;
signal det_0_reg_n_151 : STD_LOGIC;
signal det_0_reg_n_152 : STD_LOGIC;
signal det_0_reg_n_153 : STD_LOGIC;
signal det_abs : STD_LOGIC_VECTOR ( 31 downto 0 );
signal det_abs0 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \det_abs[10]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[11]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[13]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[14]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[15]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[17]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[18]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[19]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[1]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[21]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[22]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[23]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[25]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[26]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[27]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[29]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[2]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[30]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[3]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_7_n_0\ : STD_LOGIC;
signal \det_abs[5]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[6]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[7]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[9]_i_1_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_3\ : STD_LOGIC;
signal det_reg_n_100 : STD_LOGIC;
signal det_reg_n_101 : STD_LOGIC;
signal det_reg_n_102 : STD_LOGIC;
signal det_reg_n_103 : STD_LOGIC;
signal det_reg_n_104 : STD_LOGIC;
signal det_reg_n_105 : STD_LOGIC;
signal det_reg_n_74 : STD_LOGIC;
signal det_reg_n_75 : STD_LOGIC;
signal det_reg_n_76 : STD_LOGIC;
signal det_reg_n_77 : STD_LOGIC;
signal det_reg_n_78 : STD_LOGIC;
signal det_reg_n_79 : STD_LOGIC;
signal det_reg_n_80 : STD_LOGIC;
signal det_reg_n_81 : STD_LOGIC;
signal det_reg_n_82 : STD_LOGIC;
signal det_reg_n_83 : STD_LOGIC;
signal det_reg_n_84 : STD_LOGIC;
signal det_reg_n_85 : STD_LOGIC;
signal det_reg_n_86 : STD_LOGIC;
signal det_reg_n_87 : STD_LOGIC;
signal det_reg_n_88 : STD_LOGIC;
signal det_reg_n_89 : STD_LOGIC;
signal det_reg_n_90 : STD_LOGIC;
signal det_reg_n_91 : STD_LOGIC;
signal det_reg_n_92 : STD_LOGIC;
signal det_reg_n_93 : STD_LOGIC;
signal det_reg_n_94 : STD_LOGIC;
signal det_reg_n_95 : STD_LOGIC;
signal det_reg_n_96 : STD_LOGIC;
signal det_reg_n_97 : STD_LOGIC;
signal det_reg_n_98 : STD_LOGIC;
signal det_reg_n_99 : STD_LOGIC;
signal \din_reg_n_0_[0]\ : STD_LOGIC;
signal \din_reg_n_0_[10]\ : STD_LOGIC;
signal \din_reg_n_0_[11]\ : STD_LOGIC;
signal \din_reg_n_0_[12]\ : STD_LOGIC;
signal \din_reg_n_0_[13]\ : STD_LOGIC;
signal \din_reg_n_0_[14]\ : STD_LOGIC;
signal \din_reg_n_0_[15]\ : STD_LOGIC;
signal \din_reg_n_0_[1]\ : STD_LOGIC;
signal \din_reg_n_0_[2]\ : STD_LOGIC;
signal \din_reg_n_0_[3]\ : STD_LOGIC;
signal \din_reg_n_0_[4]\ : STD_LOGIC;
signal \din_reg_n_0_[5]\ : STD_LOGIC;
signal \din_reg_n_0_[6]\ : STD_LOGIC;
signal \din_reg_n_0_[7]\ : STD_LOGIC;
signal \din_reg_n_0_[8]\ : STD_LOGIC;
signal \din_reg_n_0_[9]\ : STD_LOGIC;
signal dout_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal dout_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal last_value : STD_LOGIC_VECTOR ( 7 downto 0 );
signal left : STD_LOGIC;
signal \left[15]_i_2_n_0\ : STD_LOGIC;
signal \left[15]_i_3_n_0\ : STD_LOGIC;
signal \left_reg_n_0_[0]\ : STD_LOGIC;
signal \left_reg_n_0_[10]\ : STD_LOGIC;
signal \left_reg_n_0_[11]\ : STD_LOGIC;
signal \left_reg_n_0_[12]\ : STD_LOGIC;
signal \left_reg_n_0_[13]\ : STD_LOGIC;
signal \left_reg_n_0_[14]\ : STD_LOGIC;
signal \left_reg_n_0_[15]\ : STD_LOGIC;
signal \left_reg_n_0_[1]\ : STD_LOGIC;
signal \left_reg_n_0_[2]\ : STD_LOGIC;
signal \left_reg_n_0_[3]\ : STD_LOGIC;
signal \left_reg_n_0_[4]\ : STD_LOGIC;
signal \left_reg_n_0_[5]\ : STD_LOGIC;
signal \left_reg_n_0_[6]\ : STD_LOGIC;
signal \left_reg_n_0_[7]\ : STD_LOGIC;
signal \left_reg_n_0_[8]\ : STD_LOGIC;
signal \left_reg_n_0_[9]\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \plusOp_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_7\ : STD_LOGIC;
signal top : STD_LOGIC;
signal \top[15]_i_2_n_0\ : STD_LOGIC;
signal top_left_0 : STD_LOGIC;
signal \top_left_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \top_left_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_reg_n_0_[0]\ : STD_LOGIC;
signal \top_reg_n_0_[10]\ : STD_LOGIC;
signal \top_reg_n_0_[11]\ : STD_LOGIC;
signal \top_reg_n_0_[12]\ : STD_LOGIC;
signal \top_reg_n_0_[13]\ : STD_LOGIC;
signal \top_reg_n_0_[14]\ : STD_LOGIC;
signal \top_reg_n_0_[15]\ : STD_LOGIC;
signal \top_reg_n_0_[1]\ : STD_LOGIC;
signal \top_reg_n_0_[2]\ : STD_LOGIC;
signal \top_reg_n_0_[3]\ : STD_LOGIC;
signal \top_reg_n_0_[4]\ : STD_LOGIC;
signal \top_reg_n_0_[5]\ : STD_LOGIC;
signal \top_reg_n_0_[6]\ : STD_LOGIC;
signal \top_reg_n_0_[7]\ : STD_LOGIC;
signal \top_reg_n_0_[8]\ : STD_LOGIC;
signal \top_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_0 : STD_LOGIC;
signal \top_right_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_1 : STD_LOGIC;
signal \top_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \value_reg_n_0_[0]\ : STD_LOGIC;
signal \value_reg_n_0_[1]\ : STD_LOGIC;
signal \value_reg_n_0_[2]\ : STD_LOGIC;
signal \value_reg_n_0_[3]\ : STD_LOGIC;
signal \value_reg_n_0_[4]\ : STD_LOGIC;
signal \value_reg_n_0_[5]\ : STD_LOGIC;
signal \value_reg_n_0_[6]\ : STD_LOGIC;
signal \value_reg_n_0_[7]\ : STD_LOGIC;
signal wen_i_1_n_0 : STD_LOGIC;
signal wen_i_2_n_0 : STD_LOGIC;
signal wen_reg_n_0 : STD_LOGIC;
signal x : STD_LOGIC;
signal \x0[0]_i_2_n_0\ : STD_LOGIC;
signal \x0[0]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_2_n_0\ : STD_LOGIC;
signal \x0[1]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_1_n_0\ : STD_LOGIC;
signal \x0[2]_i_2_n_0\ : STD_LOGIC;
signal \x0[2]_i_3_n_0\ : STD_LOGIC;
signal \x0[2]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_1_n_0\ : STD_LOGIC;
signal \x0[3]_i_2_n_0\ : STD_LOGIC;
signal \x0[3]_i_3_n_0\ : STD_LOGIC;
signal \x0[3]_i_4_n_0\ : STD_LOGIC;
signal \x0[3]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_6_n_0\ : STD_LOGIC;
signal \x0[4]_i_1_n_0\ : STD_LOGIC;
signal \x0[4]_i_2_n_0\ : STD_LOGIC;
signal \x0[4]_i_3_n_0\ : STD_LOGIC;
signal \x0[4]_i_4_n_0\ : STD_LOGIC;
signal \x0[4]_i_5_n_0\ : STD_LOGIC;
signal \x0[5]_i_1_n_0\ : STD_LOGIC;
signal \x0[5]_i_2_n_0\ : STD_LOGIC;
signal \x0[5]_i_3_n_0\ : STD_LOGIC;
signal \x0[5]_i_4_n_0\ : STD_LOGIC;
signal \x0[5]_i_5_n_0\ : STD_LOGIC;
signal \x0[6]_i_1_n_0\ : STD_LOGIC;
signal \x0[6]_i_2_n_0\ : STD_LOGIC;
signal \x0[6]_i_3_n_0\ : STD_LOGIC;
signal \x0[6]_i_4_n_0\ : STD_LOGIC;
signal \x0[6]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_1_n_0\ : STD_LOGIC;
signal \x0[7]_i_2_n_0\ : STD_LOGIC;
signal \x0[7]_i_3_n_0\ : STD_LOGIC;
signal \x0[7]_i_4_n_0\ : STD_LOGIC;
signal \x0[7]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_6_n_0\ : STD_LOGIC;
signal \x0[7]_i_7_n_0\ : STD_LOGIC;
signal \x0[8]_i_1_n_0\ : STD_LOGIC;
signal \x0[8]_i_2_n_0\ : STD_LOGIC;
signal \x0[8]_i_3_n_0\ : STD_LOGIC;
signal \x0[8]_i_4_n_0\ : STD_LOGIC;
signal \x0[8]_i_5_n_0\ : STD_LOGIC;
signal \x0[8]_i_6_n_0\ : STD_LOGIC;
signal \x0[8]_i_7_n_0\ : STD_LOGIC;
signal \x0[9]_i_1_n_0\ : STD_LOGIC;
signal \x0[9]_i_2_n_0\ : STD_LOGIC;
signal \x0[9]_i_3_n_0\ : STD_LOGIC;
signal \x0[9]_i_4_n_0\ : STD_LOGIC;
signal \x0[9]_i_5_n_0\ : STD_LOGIC;
signal \x0[9]_i_6_n_0\ : STD_LOGIC;
signal \x0[9]_i_7_n_0\ : STD_LOGIC;
signal \x0_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \x0_reg[1]_i_1_n_0\ : STD_LOGIC;
signal x1 : STD_LOGIC;
signal \x1[0]_i_1_n_0\ : STD_LOGIC;
signal \x1[1]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_2_n_0\ : STD_LOGIC;
signal \x1[2]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_1_n_0\ : STD_LOGIC;
signal \x1[3]_i_2_n_0\ : STD_LOGIC;
signal \x1[3]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_1_n_0\ : STD_LOGIC;
signal \x1[4]_i_2_n_0\ : STD_LOGIC;
signal \x1[4]_i_3_n_0\ : STD_LOGIC;
signal \x1[4]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_5_n_0\ : STD_LOGIC;
signal \x1[5]_i_1_n_0\ : STD_LOGIC;
signal \x1[5]_i_2_n_0\ : STD_LOGIC;
signal \x1[5]_i_3_n_0\ : STD_LOGIC;
signal \x1[5]_i_4_n_0\ : STD_LOGIC;
signal \x1[5]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_1_n_0\ : STD_LOGIC;
signal \x1[6]_i_2_n_0\ : STD_LOGIC;
signal \x1[6]_i_3_n_0\ : STD_LOGIC;
signal \x1[6]_i_4_n_0\ : STD_LOGIC;
signal \x1[6]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_6_n_0\ : STD_LOGIC;
signal \x1[6]_i_7_n_0\ : STD_LOGIC;
signal \x1[6]_i_8_n_0\ : STD_LOGIC;
signal \x1[7]_i_1_n_0\ : STD_LOGIC;
signal \x1[7]_i_2_n_0\ : STD_LOGIC;
signal \x1[7]_i_3_n_0\ : STD_LOGIC;
signal \x1[7]_i_4_n_0\ : STD_LOGIC;
signal \x1[7]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_1_n_0\ : STD_LOGIC;
signal \x1[8]_i_2_n_0\ : STD_LOGIC;
signal \x1[8]_i_3_n_0\ : STD_LOGIC;
signal \x1[8]_i_4_n_0\ : STD_LOGIC;
signal \x1[8]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_2_n_0\ : STD_LOGIC;
signal \x1[9]_i_3_n_0\ : STD_LOGIC;
signal \x1[9]_i_4_n_0\ : STD_LOGIC;
signal \x1[9]_i_5_n_0\ : STD_LOGIC;
signal \x1[9]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_7_n_0\ : STD_LOGIC;
signal \x1[9]_i_8_n_0\ : STD_LOGIC;
signal \x_reg_n_0_[0]\ : STD_LOGIC;
signal \x_reg_n_0_[1]\ : STD_LOGIC;
signal \x_reg_n_0_[2]\ : STD_LOGIC;
signal \x_reg_n_0_[3]\ : STD_LOGIC;
signal \x_reg_n_0_[4]\ : STD_LOGIC;
signal \x_reg_n_0_[5]\ : STD_LOGIC;
signal \x_reg_n_0_[6]\ : STD_LOGIC;
signal \x_reg_n_0_[7]\ : STD_LOGIC;
signal \x_reg_n_0_[8]\ : STD_LOGIC;
signal \x_reg_n_0_[9]\ : STD_LOGIC;
signal y1 : STD_LOGIC;
signal \y1[2]_i_1_n_0\ : STD_LOGIC;
signal \y1[3]_i_1_n_0\ : STD_LOGIC;
signal \y1_reg_n_0_[0]\ : STD_LOGIC;
signal \y1_reg_n_0_[1]\ : STD_LOGIC;
signal \y1_reg_n_0_[2]\ : STD_LOGIC;
signal \y1_reg_n_0_[3]\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2[1]_i_1_n_0\ : STD_LOGIC;
signal \y2[2]_i_1_n_0\ : STD_LOGIC;
signal \y2[3]_i_1_n_0\ : STD_LOGIC;
signal \y2_reg_n_0_[0]\ : STD_LOGIC;
signal \y2_reg_n_0_[1]\ : STD_LOGIC;
signal \y2_reg_n_0_[2]\ : STD_LOGIC;
signal \y2_reg_n_0_[3]\ : STD_LOGIC;
signal y3 : STD_LOGIC;
signal \y3[1]_i_1_n_0\ : STD_LOGIC;
signal \y3[2]_i_1_n_0\ : STD_LOGIC;
signal \y3[3]_i_1_n_0\ : STD_LOGIC;
signal \y3_reg_n_0_[0]\ : STD_LOGIC;
signal \y3_reg_n_0_[1]\ : STD_LOGIC;
signal \y3_reg_n_0_[2]\ : STD_LOGIC;
signal \y3_reg_n_0_[3]\ : STD_LOGIC;
signal \y4[2]_i_1_n_0\ : STD_LOGIC;
signal \y4[3]_i_1_n_0\ : STD_LOGIC;
signal y5 : STD_LOGIC;
signal \y5[0]_i_1_n_0\ : STD_LOGIC;
signal \y5[1]_i_1_n_0\ : STD_LOGIC;
signal \y5[2]_i_1_n_0\ : STD_LOGIC;
signal \y5[3]_i_1_n_0\ : STD_LOGIC;
signal y6 : STD_LOGIC;
signal \y6[2]_i_1_n_0\ : STD_LOGIC;
signal \y6[3]_i_1_n_0\ : STD_LOGIC;
signal \y6_reg_n_0_[0]\ : STD_LOGIC;
signal \y6_reg_n_0_[1]\ : STD_LOGIC;
signal \y6_reg_n_0_[2]\ : STD_LOGIC;
signal \y6_reg_n_0_[3]\ : STD_LOGIC;
signal y7 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y7[2]_i_1_n_0\ : STD_LOGIC;
signal \y7[3]_i_1_n_0\ : STD_LOGIC;
signal y8 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y8[3]_i_1_n_0\ : STD_LOGIC;
signal y9 : STD_LOGIC;
signal \y9[3]_i_1_n_0\ : STD_LOGIC;
signal \y_actual_reg_n_0_[0]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[1]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[2]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[3]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[4]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[5]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[6]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[7]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[8]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[9]\ : STD_LOGIC;
signal \NLW_Lxx0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_0_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_0_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_0_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_det_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute HLUTNM : string;
attribute HLUTNM of \Lxx0_carry__0_i_1\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_2\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_3\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__0_i_4\ : label is "lutpair1";
attribute HLUTNM of \Lxx0_carry__0_i_5\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__0_i_6\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_7\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_8\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__1_i_1\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_2\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_3\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__1_i_4\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__1_i_5\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__1_i_6\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_7\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_8\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__2_i_1\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_2\ : label is "lutpair10";
attribute HLUTNM of \Lxx0_carry__2_i_3\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__2_i_6\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_7\ : label is "lutpair10";
attribute HLUTNM of Lxx0_carry_i_1 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_2 : label is "lutpair24";
attribute HLUTNM of Lxx0_carry_i_3 : label is "lutpair1";
attribute HLUTNM of Lxx0_carry_i_4 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_5 : label is "lutpair24";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_10\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_8\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_8\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_10\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_8\ : label is "soft_lutpair32";
attribute HLUTNM of \Lyy0_carry__0_i_1\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_2\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_3\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__0_i_4\ : label is "lutpair13";
attribute HLUTNM of \Lyy0_carry__0_i_5\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__0_i_6\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_7\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_8\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__1_i_1\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_2\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_3\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__1_i_4\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__1_i_5\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__1_i_6\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_7\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_8\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__2_i_1\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_2\ : label is "lutpair22";
attribute HLUTNM of \Lyy0_carry__2_i_3\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__2_i_6\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_7\ : label is "lutpair22";
attribute HLUTNM of Lyy0_carry_i_1 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_2 : label is "lutpair25";
attribute HLUTNM of Lyy0_carry_i_3 : label is "lutpair13";
attribute HLUTNM of Lyy0_carry_i_4 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_5 : label is "lutpair25";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_10\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_11\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_9\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_10\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_9\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_8\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry_i_8\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_11\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \addr_0[0]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[11]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[12]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[13]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_0[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[5]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[6]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[8]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[9]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_1[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \addr_1[10]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[12]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[13]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[3]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[5]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[6]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[7]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[8]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[9]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \bottom_right_0[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bottom_right_0[14]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_5\ : label is "soft_lutpair12";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_0 : label is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_0 : label is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_0 : label is "blk_mem_gen_v8_3_5,Vivado 2016.4";
attribute srl_bus_name : string;
attribute srl_bus_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name : string;
attribute srl_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 ";
attribute SOFT_HLUTNM of cache_reg_gate : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__10\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \cache_reg_gate__11\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__12\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__13\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__14\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__15\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__16\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__17\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__18\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__19\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__20\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__21\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__22\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__23\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__24\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__25\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__26\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__27\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__28\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__29\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__3\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__30\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__4\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__6\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__7\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__8\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__9\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \compute_addr_0[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \compute_addr_2[10]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[11]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[12]_i_2\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_3[10]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[11]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[12]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \compute_addr_3[13]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \cycle[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cycle[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[3]_i_2\ : label is "soft_lutpair15";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cycle_reg[0]\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[0]_rep\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[1]\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep__0\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[2]\ : label is "cycle_reg[2]";
attribute ORIG_CELL_NAME of \cycle_reg[2]_rep\ : label is "cycle_reg[2]";
attribute SOFT_HLUTNM of \det_abs[10]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[11]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[12]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[13]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[14]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[15]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[16]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[17]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[18]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[19]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \det_abs[1]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[21]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[22]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[24]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[25]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[26]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[27]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[28]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[30]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[6]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[8]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[9]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \left[15]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \left[15]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x0[1]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x0[2]_i_4\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[2]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x0[3]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \x0[3]_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[4]_i_4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[4]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[5]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x0[5]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[7]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x0[7]_i_6\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \x0[8]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[8]_i_5\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x0[8]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x0[8]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[9]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x1[3]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_5\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[5]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[5]_i_5\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x1[6]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x1[6]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[6]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[6]_i_8\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x1[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x1[7]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x1[8]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x1[9]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x1[9]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y1[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \y1[3]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y2[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y3[1]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y3[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y3[3]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y4[2]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y4[3]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y5[0]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y5[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y5[2]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y5[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y6[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y6[3]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y7[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y7[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y9[3]_i_1\ : label is "soft_lutpair20";
begin
Lxx0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lxx0_carry_n_0,
CO(2) => Lxx0_carry_n_1,
CO(1) => Lxx0_carry_n_2,
CO(0) => Lxx0_carry_n_3,
CYINIT => '0',
DI(3) => Lxx0_carry_i_1_n_0,
DI(2) => Lxx0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lxx_2_reg_n_0_[0]\,
O(3 downto 0) => A(3 downto 0),
S(3) => Lxx0_carry_i_3_n_0,
S(2) => Lxx0_carry_i_4_n_0,
S(1) => Lxx0_carry_i_5_n_0,
S(0) => Lxx0_carry_i_6_n_0
);
\Lxx0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lxx0_carry_n_0,
CO(3) => \Lxx0_carry__0_n_0\,
CO(2) => \Lxx0_carry__0_n_1\,
CO(1) => \Lxx0_carry__0_n_2\,
CO(0) => \Lxx0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__0_i_1_n_0\,
DI(2) => \Lxx0_carry__0_i_2_n_0\,
DI(1) => \Lxx0_carry__0_i_3_n_0\,
DI(0) => \Lxx0_carry__0_i_4_n_0\,
O(3 downto 0) => A(7 downto 4),
S(3) => \Lxx0_carry__0_i_5_n_0\,
S(2) => \Lxx0_carry__0_i_6_n_0\,
S(1) => \Lxx0_carry__0_i_7_n_0\,
S(0) => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
O => \Lxx0_carry__0_i_1_n_0\
);
\Lxx0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
O => \Lxx0_carry__0_i_2_n_0\
);
\Lxx0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
O => \Lxx0_carry__0_i_3_n_0\
);
\Lxx0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
O => \Lxx0_carry__0_i_4_n_0\
);
\Lxx0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
I3 => \Lxx0_carry__0_i_1_n_0\,
O => \Lxx0_carry__0_i_5_n_0\
);
\Lxx0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
I3 => \Lxx0_carry__0_i_2_n_0\,
O => \Lxx0_carry__0_i_6_n_0\
);
\Lxx0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
I3 => \Lxx0_carry__0_i_3_n_0\,
O => \Lxx0_carry__0_i_7_n_0\
);
\Lxx0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
I3 => \Lxx0_carry__0_i_4_n_0\,
O => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__0_n_0\,
CO(3) => \Lxx0_carry__1_n_0\,
CO(2) => \Lxx0_carry__1_n_1\,
CO(1) => \Lxx0_carry__1_n_2\,
CO(0) => \Lxx0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__1_i_1_n_0\,
DI(2) => \Lxx0_carry__1_i_2_n_0\,
DI(1) => \Lxx0_carry__1_i_3_n_0\,
DI(0) => \Lxx0_carry__1_i_4_n_0\,
O(3 downto 0) => A(11 downto 8),
S(3) => \Lxx0_carry__1_i_5_n_0\,
S(2) => \Lxx0_carry__1_i_6_n_0\,
S(1) => \Lxx0_carry__1_i_7_n_0\,
S(0) => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
O => \Lxx0_carry__1_i_1_n_0\
);
\Lxx0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
O => \Lxx0_carry__1_i_2_n_0\
);
\Lxx0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
O => \Lxx0_carry__1_i_3_n_0\
);
\Lxx0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
O => \Lxx0_carry__1_i_4_n_0\
);
\Lxx0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
I3 => \Lxx0_carry__1_i_1_n_0\,
O => \Lxx0_carry__1_i_5_n_0\
);
\Lxx0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
I3 => \Lxx0_carry__1_i_2_n_0\,
O => \Lxx0_carry__1_i_6_n_0\
);
\Lxx0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
I3 => \Lxx0_carry__1_i_3_n_0\,
O => \Lxx0_carry__1_i_7_n_0\
);
\Lxx0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
I3 => \Lxx0_carry__1_i_4_n_0\,
O => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__1_n_0\,
CO(3) => \NLW_Lxx0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx0_carry__2_n_1\,
CO(1) => \Lxx0_carry__2_n_2\,
CO(0) => \Lxx0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx0_carry__2_i_1_n_0\,
DI(1) => \Lxx0_carry__2_i_2_n_0\,
DI(0) => \Lxx0_carry__2_i_3_n_0\,
O(3 downto 0) => A(15 downto 12),
S(3) => \Lxx0_carry__2_i_4_n_0\,
S(2) => \Lxx0_carry__2_i_5_n_0\,
S(1) => \Lxx0_carry__2_i_6_n_0\,
S(0) => \Lxx0_carry__2_i_7_n_0\
);
\Lxx0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
O => \Lxx0_carry__2_i_1_n_0\
);
\Lxx0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
O => \Lxx0_carry__2_i_2_n_0\
);
\Lxx0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
O => \Lxx0_carry__2_i_3_n_0\
);
\Lxx0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => Lxx_0(14),
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => \Lxx_2_reg_n_0_[15]\,
I4 => Lxx_1(15),
I5 => Lxx_0(15),
O => \Lxx0_carry__2_i_4_n_0\
);
\Lxx0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxx0_carry__2_i_1_n_0\,
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => Lxx_0(14),
O => \Lxx0_carry__2_i_5_n_0\
);
\Lxx0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
I3 => \Lxx0_carry__2_i_2_n_0\,
O => \Lxx0_carry__2_i_6_n_0\
);
\Lxx0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
I3 => \Lxx0_carry__2_i_3_n_0\,
O => \Lxx0_carry__2_i_7_n_0\
);
Lxx0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
O => Lxx0_carry_i_1_n_0
);
Lxx0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_2_n_0
);
Lxx0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
I3 => Lxx0_carry_i_1_n_0,
O => Lxx0_carry_i_3_n_0
);
Lxx0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
I3 => Lxx0_carry_i_2_n_0,
O => Lxx0_carry_i_4_n_0
);
Lxx0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_5_n_0
);
Lxx0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lxx_2_reg_n_0_[0]\,
I1 => Lxx_0(0),
O => Lxx0_carry_i_6_n_0
);
\Lxx_00__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_00__1_carry_n_0\,
CO(2) => \Lxx_00__1_carry_n_1\,
CO(1) => \Lxx_00__1_carry_n_2\,
CO(0) => \Lxx_00__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry_i_1_n_0\,
DI(2) => \Lxx_00__1_carry_i_2_n_0\,
DI(1) => \Lxx_00__1_carry_i_3_n_0\,
DI(0) => \bottom_right_0_reg_n_0_[0]\,
O(3 downto 0) => Lxx_00(3 downto 0),
S(3) => \Lxx_00__1_carry_i_4_n_0\,
S(2) => \Lxx_00__1_carry_i_5_n_0\,
S(1) => \Lxx_00__1_carry_i_6_n_0\,
S(0) => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry_n_0\,
CO(3) => \Lxx_00__1_carry__0_n_0\,
CO(2) => \Lxx_00__1_carry__0_n_1\,
CO(1) => \Lxx_00__1_carry__0_n_2\,
CO(0) => \Lxx_00__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_00(7 downto 4),
S(3) => \Lxx_00__1_carry__0_i_5_n_0\,
S(2) => \Lxx_00__1_carry__0_i_6_n_0\,
S(1) => \Lxx_00__1_carry__0_i_7_n_0\,
S(0) => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[6]\,
I1 => \Lxx_00__1_carry__0_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[5]\,
I3 => \top_right_0_reg_n_0_[5]\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_1_n_0\
);
\Lxx_00__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[5]\,
I1 => \top_right_0_reg_n_0_[5]\,
I2 => \top_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_10_n_0\
);
\Lxx_00__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[4]\,
I1 => \top_right_0_reg_n_0_[4]\,
I2 => \top_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_11_n_0\
);
\Lxx_00__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[7]\,
I1 => \top_right_0_reg_n_0_[7]\,
I2 => \top_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__0_i_12_n_0\
);
\Lxx_00__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[5]\,
I1 => \Lxx_00__1_carry__0_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[4]\,
I3 => \top_right_0_reg_n_0_[4]\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_2_n_0\
);
\Lxx_00__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[4]\,
I1 => \Lxx_00__1_carry__0_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[3]\,
I3 => \top_right_0_reg_n_0_[3]\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry__0_i_3_n_0\
);
\Lxx_00__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[3]\,
I1 => \Lxx_00__1_carry_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[2]\,
I3 => \top_right_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry__0_i_4_n_0\
);
\Lxx_00__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[6]\,
I2 => \top_right_0_reg_n_0_[6]\,
I3 => \bottom_left_0_reg_n_0_[6]\,
I4 => \bottom_right_0_reg_n_0_[7]\,
I5 => \Lxx_00__1_carry__0_i_12_n_0\,
O => \Lxx_00__1_carry__0_i_5_n_0\
);
\Lxx_00__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[5]\,
I2 => \top_right_0_reg_n_0_[5]\,
I3 => \bottom_left_0_reg_n_0_[5]\,
I4 => \bottom_right_0_reg_n_0_[6]\,
I5 => \Lxx_00__1_carry__0_i_9_n_0\,
O => \Lxx_00__1_carry__0_i_6_n_0\
);
\Lxx_00__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[4]\,
I2 => \top_right_0_reg_n_0_[4]\,
I3 => \bottom_left_0_reg_n_0_[4]\,
I4 => \bottom_right_0_reg_n_0_[5]\,
I5 => \Lxx_00__1_carry__0_i_10_n_0\,
O => \Lxx_00__1_carry__0_i_7_n_0\
);
\Lxx_00__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[3]\,
I2 => \top_right_0_reg_n_0_[3]\,
I3 => \bottom_left_0_reg_n_0_[3]\,
I4 => \bottom_right_0_reg_n_0_[4]\,
I5 => \Lxx_00__1_carry__0_i_11_n_0\,
O => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[6]\,
I1 => \top_right_0_reg_n_0_[6]\,
I2 => \top_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__0_i_9_n_0\
);
\Lxx_00__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__0_n_0\,
CO(3) => \Lxx_00__1_carry__1_n_0\,
CO(2) => \Lxx_00__1_carry__1_n_1\,
CO(1) => \Lxx_00__1_carry__1_n_2\,
CO(0) => \Lxx_00__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_00(11 downto 8),
S(3) => \Lxx_00__1_carry__1_i_5_n_0\,
S(2) => \Lxx_00__1_carry__1_i_6_n_0\,
S(1) => \Lxx_00__1_carry__1_i_7_n_0\,
S(0) => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[10]\,
I1 => \Lxx_00__1_carry__1_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[9]\,
I3 => \top_right_0_reg_n_0_[9]\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_1_n_0\
);
\Lxx_00__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[9]\,
I1 => \top_right_0_reg_n_0_[9]\,
I2 => \top_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_10_n_0\
);
\Lxx_00__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[8]\,
I1 => \top_right_0_reg_n_0_[8]\,
I2 => \top_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_11_n_0\
);
\Lxx_00__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[11]\,
I1 => \top_right_0_reg_n_0_[11]\,
I2 => \top_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__1_i_12_n_0\
);
\Lxx_00__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[9]\,
I1 => \Lxx_00__1_carry__1_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[8]\,
I3 => \top_right_0_reg_n_0_[8]\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_2_n_0\
);
\Lxx_00__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[8]\,
I1 => \Lxx_00__1_carry__1_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[7]\,
I3 => \top_right_0_reg_n_0_[7]\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__1_i_3_n_0\
);
\Lxx_00__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[7]\,
I1 => \Lxx_00__1_carry__0_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[6]\,
I3 => \top_right_0_reg_n_0_[6]\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__1_i_4_n_0\
);
\Lxx_00__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[10]\,
I2 => \top_right_0_reg_n_0_[10]\,
I3 => \bottom_left_0_reg_n_0_[10]\,
I4 => \bottom_right_0_reg_n_0_[11]\,
I5 => \Lxx_00__1_carry__1_i_12_n_0\,
O => \Lxx_00__1_carry__1_i_5_n_0\
);
\Lxx_00__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[9]\,
I2 => \top_right_0_reg_n_0_[9]\,
I3 => \bottom_left_0_reg_n_0_[9]\,
I4 => \bottom_right_0_reg_n_0_[10]\,
I5 => \Lxx_00__1_carry__1_i_9_n_0\,
O => \Lxx_00__1_carry__1_i_6_n_0\
);
\Lxx_00__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[8]\,
I2 => \top_right_0_reg_n_0_[8]\,
I3 => \bottom_left_0_reg_n_0_[8]\,
I4 => \bottom_right_0_reg_n_0_[9]\,
I5 => \Lxx_00__1_carry__1_i_10_n_0\,
O => \Lxx_00__1_carry__1_i_7_n_0\
);
\Lxx_00__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[7]\,
I2 => \top_right_0_reg_n_0_[7]\,
I3 => \bottom_left_0_reg_n_0_[7]\,
I4 => \bottom_right_0_reg_n_0_[8]\,
I5 => \Lxx_00__1_carry__1_i_11_n_0\,
O => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[10]\,
I1 => \top_right_0_reg_n_0_[10]\,
I2 => \top_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__1_i_9_n_0\
);
\Lxx_00__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_00__1_carry__2_n_1\,
CO(1) => \Lxx_00__1_carry__2_n_2\,
CO(0) => \Lxx_00__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_00__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_00__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_00__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_00(15 downto 12),
S(3) => \Lxx_00__1_carry__2_i_4_n_0\,
S(2) => \Lxx_00__1_carry__2_i_5_n_0\,
S(1) => \Lxx_00__1_carry__2_i_6_n_0\,
S(0) => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[13]\,
I1 => \Lxx_00__1_carry__2_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[12]\,
I3 => \top_right_0_reg_n_0_[12]\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_1_n_0\
);
\Lxx_00__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => \top_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \bottom_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_10_n_0\
);
\Lxx_00__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_0_reg_n_0_[15]\,
I1 => \bottom_left_0_reg_n_0_[15]\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \top_left_0_reg_n_0_[15]\,
O => \Lxx_00__1_carry__2_i_11_n_0\
);
\Lxx_00__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[14]\,
I1 => \top_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
O => \Lxx_00__1_carry__2_i_12_n_0\
);
\Lxx_00__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[12]\,
I1 => \Lxx_00__1_carry__2_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[11]\,
I3 => \top_right_0_reg_n_0_[11]\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__2_i_2_n_0\
);
\Lxx_00__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[11]\,
I1 => \Lxx_00__1_carry__1_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[10]\,
I3 => \top_right_0_reg_n_0_[10]\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__2_i_3_n_0\
);
\Lxx_00__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_00__1_carry__2_i_10_n_0\,
I1 => \bottom_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
I3 => \top_right_0_reg_n_0_[14]\,
I4 => \bottom_left_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_11_n_0\,
O => \Lxx_00__1_carry__2_i_4_n_0\
);
\Lxx_00__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[13]\,
I2 => \top_right_0_reg_n_0_[13]\,
I3 => \bottom_left_0_reg_n_0_[13]\,
I4 => \bottom_right_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_12_n_0\,
O => \Lxx_00__1_carry__2_i_5_n_0\
);
\Lxx_00__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[12]\,
I2 => \top_right_0_reg_n_0_[12]\,
I3 => \bottom_left_0_reg_n_0_[12]\,
I4 => \bottom_right_0_reg_n_0_[13]\,
I5 => \Lxx_00__1_carry__2_i_8_n_0\,
O => \Lxx_00__1_carry__2_i_6_n_0\
);
\Lxx_00__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[11]\,
I2 => \top_right_0_reg_n_0_[11]\,
I3 => \bottom_left_0_reg_n_0_[11]\,
I4 => \bottom_right_0_reg_n_0_[12]\,
I5 => \Lxx_00__1_carry__2_i_9_n_0\,
O => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \top_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_8_n_0\
);
\Lxx_00__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[12]\,
I1 => \top_right_0_reg_n_0_[12]\,
I2 => \top_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_9_n_0\
);
\Lxx_00__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[2]\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[1]\,
I5 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_1_n_0\
);
\Lxx_00__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => \bottom_left_0_reg_n_0_[1]\,
I1 => \top_right_0_reg_n_0_[1]\,
I2 => \top_left_0_reg_n_0_[1]\,
I3 => \bottom_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_2_n_0\
);
\Lxx_00__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_0_reg_n_0_[1]\,
I1 => \bottom_left_0_reg_n_0_[1]\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \top_left_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_3_n_0\
);
\Lxx_00__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_right_0_reg_n_0_[3]\,
I5 => \Lxx_00__1_carry_i_8_n_0\,
O => \Lxx_00__1_carry_i_4_n_0\
);
\Lxx_00__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_00__1_carry_i_2_n_0\,
I1 => \bottom_right_0_reg_n_0_[2]\,
I2 => \Lxx_00__1_carry_i_9_n_0\,
I3 => \bottom_left_0_reg_n_0_[1]\,
I4 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_5_n_0\
);
\Lxx_00__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_00__1_carry_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[0]\,
I2 => \top_right_0_reg_n_0_[0]\,
I3 => \bottom_left_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_6_n_0\
);
\Lxx_00__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \bottom_left_0_reg_n_0_[0]\,
I1 => \top_right_0_reg_n_0_[0]\,
I2 => \top_left_0_reg_n_0_[0]\,
I3 => \bottom_right_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[3]\,
I1 => \top_right_0_reg_n_0_[3]\,
I2 => \top_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry_i_8_n_0\
);
\Lxx_00__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[2]\,
I1 => \top_right_0_reg_n_0_[2]\,
I2 => \top_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry_i_9_n_0\
);
\Lxx_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(0),
Q => Lxx_0(0),
R => '0'
);
\Lxx_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(10),
Q => Lxx_0(10),
R => '0'
);
\Lxx_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(11),
Q => Lxx_0(11),
R => '0'
);
\Lxx_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(12),
Q => Lxx_0(12),
R => '0'
);
\Lxx_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(13),
Q => Lxx_0(13),
R => '0'
);
\Lxx_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(14),
Q => Lxx_0(14),
R => '0'
);
\Lxx_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(15),
Q => Lxx_0(15),
R => '0'
);
\Lxx_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(1),
Q => Lxx_0(1),
R => '0'
);
\Lxx_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(2),
Q => Lxx_0(2),
R => '0'
);
\Lxx_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(3),
Q => Lxx_0(3),
R => '0'
);
\Lxx_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(4),
Q => Lxx_0(4),
R => '0'
);
\Lxx_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(5),
Q => Lxx_0(5),
R => '0'
);
\Lxx_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(6),
Q => Lxx_0(6),
R => '0'
);
\Lxx_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(7),
Q => Lxx_0(7),
R => '0'
);
\Lxx_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(8),
Q => Lxx_0(8),
R => '0'
);
\Lxx_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(9),
Q => Lxx_0(9),
R => '0'
);
\Lxx_11__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_11__1_carry_n_0\,
CO(2) => \Lxx_11__1_carry_n_1\,
CO(1) => \Lxx_11__1_carry_n_2\,
CO(0) => \Lxx_11__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry_i_1_n_0\,
DI(2) => \Lxx_11__1_carry_i_2_n_0\,
DI(1) => \Lxx_11__1_carry_i_3_n_0\,
DI(0) => \bottom_right_1_reg_n_0_[0]\,
O(3 downto 0) => Lxx_11(3 downto 0),
S(3) => \Lxx_11__1_carry_i_4_n_0\,
S(2) => \Lxx_11__1_carry_i_5_n_0\,
S(1) => \Lxx_11__1_carry_i_6_n_0\,
S(0) => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry_n_0\,
CO(3) => \Lxx_11__1_carry__0_n_0\,
CO(2) => \Lxx_11__1_carry__0_n_1\,
CO(1) => \Lxx_11__1_carry__0_n_2\,
CO(0) => \Lxx_11__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_11(7 downto 4),
S(3) => \Lxx_11__1_carry__0_i_5_n_0\,
S(2) => \Lxx_11__1_carry__0_i_6_n_0\,
S(1) => \Lxx_11__1_carry__0_i_7_n_0\,
S(0) => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[6]\,
I1 => \Lxx_11__1_carry__0_i_9_n_0\,
I2 => top_left_1(5),
I3 => \top_right_1_reg_n_0_[5]\,
I4 => bottom_left_1(5),
O => \Lxx_11__1_carry__0_i_1_n_0\
);
\Lxx_11__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(5),
I1 => \top_right_1_reg_n_0_[5]\,
I2 => top_left_1(5),
O => \Lxx_11__1_carry__0_i_10_n_0\
);
\Lxx_11__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(4),
I1 => \top_right_1_reg_n_0_[4]\,
I2 => top_left_1(4),
O => \Lxx_11__1_carry__0_i_11_n_0\
);
\Lxx_11__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(7),
I1 => \top_right_1_reg_n_0_[7]\,
I2 => top_left_1(7),
O => \Lxx_11__1_carry__0_i_12_n_0\
);
\Lxx_11__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[5]\,
I1 => \Lxx_11__1_carry__0_i_10_n_0\,
I2 => top_left_1(4),
I3 => \top_right_1_reg_n_0_[4]\,
I4 => bottom_left_1(4),
O => \Lxx_11__1_carry__0_i_2_n_0\
);
\Lxx_11__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[4]\,
I1 => \Lxx_11__1_carry__0_i_11_n_0\,
I2 => top_left_1(3),
I3 => \top_right_1_reg_n_0_[3]\,
I4 => bottom_left_1(3),
O => \Lxx_11__1_carry__0_i_3_n_0\
);
\Lxx_11__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[3]\,
I1 => \Lxx_11__1_carry_i_8_n_0\,
I2 => top_left_1(2),
I3 => \top_right_1_reg_n_0_[2]\,
I4 => bottom_left_1(2),
O => \Lxx_11__1_carry__0_i_4_n_0\
);
\Lxx_11__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_1_n_0\,
I1 => top_left_1(6),
I2 => \top_right_1_reg_n_0_[6]\,
I3 => bottom_left_1(6),
I4 => \bottom_right_1_reg_n_0_[7]\,
I5 => \Lxx_11__1_carry__0_i_12_n_0\,
O => \Lxx_11__1_carry__0_i_5_n_0\
);
\Lxx_11__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_2_n_0\,
I1 => top_left_1(5),
I2 => \top_right_1_reg_n_0_[5]\,
I3 => bottom_left_1(5),
I4 => \bottom_right_1_reg_n_0_[6]\,
I5 => \Lxx_11__1_carry__0_i_9_n_0\,
O => \Lxx_11__1_carry__0_i_6_n_0\
);
\Lxx_11__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_3_n_0\,
I1 => top_left_1(4),
I2 => \top_right_1_reg_n_0_[4]\,
I3 => bottom_left_1(4),
I4 => \bottom_right_1_reg_n_0_[5]\,
I5 => \Lxx_11__1_carry__0_i_10_n_0\,
O => \Lxx_11__1_carry__0_i_7_n_0\
);
\Lxx_11__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_4_n_0\,
I1 => top_left_1(3),
I2 => \top_right_1_reg_n_0_[3]\,
I3 => bottom_left_1(3),
I4 => \bottom_right_1_reg_n_0_[4]\,
I5 => \Lxx_11__1_carry__0_i_11_n_0\,
O => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(6),
I1 => \top_right_1_reg_n_0_[6]\,
I2 => top_left_1(6),
O => \Lxx_11__1_carry__0_i_9_n_0\
);
\Lxx_11__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__0_n_0\,
CO(3) => \Lxx_11__1_carry__1_n_0\,
CO(2) => \Lxx_11__1_carry__1_n_1\,
CO(1) => \Lxx_11__1_carry__1_n_2\,
CO(0) => \Lxx_11__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_11(11 downto 8),
S(3) => \Lxx_11__1_carry__1_i_5_n_0\,
S(2) => \Lxx_11__1_carry__1_i_6_n_0\,
S(1) => \Lxx_11__1_carry__1_i_7_n_0\,
S(0) => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[10]\,
I1 => \Lxx_11__1_carry__1_i_9_n_0\,
I2 => top_left_1(9),
I3 => \top_right_1_reg_n_0_[9]\,
I4 => bottom_left_1(9),
O => \Lxx_11__1_carry__1_i_1_n_0\
);
\Lxx_11__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(9),
I1 => \top_right_1_reg_n_0_[9]\,
I2 => top_left_1(9),
O => \Lxx_11__1_carry__1_i_10_n_0\
);
\Lxx_11__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(8),
I1 => \top_right_1_reg_n_0_[8]\,
I2 => top_left_1(8),
O => \Lxx_11__1_carry__1_i_11_n_0\
);
\Lxx_11__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(11),
I1 => \top_right_1_reg_n_0_[11]\,
I2 => top_left_1(11),
O => \Lxx_11__1_carry__1_i_12_n_0\
);
\Lxx_11__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[9]\,
I1 => \Lxx_11__1_carry__1_i_10_n_0\,
I2 => top_left_1(8),
I3 => \top_right_1_reg_n_0_[8]\,
I4 => bottom_left_1(8),
O => \Lxx_11__1_carry__1_i_2_n_0\
);
\Lxx_11__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[8]\,
I1 => \Lxx_11__1_carry__1_i_11_n_0\,
I2 => top_left_1(7),
I3 => \top_right_1_reg_n_0_[7]\,
I4 => bottom_left_1(7),
O => \Lxx_11__1_carry__1_i_3_n_0\
);
\Lxx_11__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[7]\,
I1 => \Lxx_11__1_carry__0_i_12_n_0\,
I2 => top_left_1(6),
I3 => \top_right_1_reg_n_0_[6]\,
I4 => bottom_left_1(6),
O => \Lxx_11__1_carry__1_i_4_n_0\
);
\Lxx_11__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_1_n_0\,
I1 => top_left_1(10),
I2 => \top_right_1_reg_n_0_[10]\,
I3 => bottom_left_1(10),
I4 => \bottom_right_1_reg_n_0_[11]\,
I5 => \Lxx_11__1_carry__1_i_12_n_0\,
O => \Lxx_11__1_carry__1_i_5_n_0\
);
\Lxx_11__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_2_n_0\,
I1 => top_left_1(9),
I2 => \top_right_1_reg_n_0_[9]\,
I3 => bottom_left_1(9),
I4 => \bottom_right_1_reg_n_0_[10]\,
I5 => \Lxx_11__1_carry__1_i_9_n_0\,
O => \Lxx_11__1_carry__1_i_6_n_0\
);
\Lxx_11__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_3_n_0\,
I1 => top_left_1(8),
I2 => \top_right_1_reg_n_0_[8]\,
I3 => bottom_left_1(8),
I4 => \bottom_right_1_reg_n_0_[9]\,
I5 => \Lxx_11__1_carry__1_i_10_n_0\,
O => \Lxx_11__1_carry__1_i_7_n_0\
);
\Lxx_11__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_4_n_0\,
I1 => top_left_1(7),
I2 => \top_right_1_reg_n_0_[7]\,
I3 => bottom_left_1(7),
I4 => \bottom_right_1_reg_n_0_[8]\,
I5 => \Lxx_11__1_carry__1_i_11_n_0\,
O => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(10),
I1 => \top_right_1_reg_n_0_[10]\,
I2 => top_left_1(10),
O => \Lxx_11__1_carry__1_i_9_n_0\
);
\Lxx_11__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_11__1_carry__2_n_1\,
CO(1) => \Lxx_11__1_carry__2_n_2\,
CO(0) => \Lxx_11__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_11__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_11__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_11__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_11(15 downto 12),
S(3) => \Lxx_11__1_carry__2_i_4_n_0\,
S(2) => \Lxx_11__1_carry__2_i_5_n_0\,
S(1) => \Lxx_11__1_carry__2_i_6_n_0\,
S(0) => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[13]\,
I1 => \Lxx_11__1_carry__2_i_8_n_0\,
I2 => top_left_1(12),
I3 => \top_right_1_reg_n_0_[12]\,
I4 => bottom_left_1(12),
O => \Lxx_11__1_carry__2_i_1_n_0\
);
\Lxx_11__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => top_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => bottom_left_1(13),
O => \Lxx_11__1_carry__2_i_10_n_0\
);
\Lxx_11__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_1_reg_n_0_[15]\,
I1 => bottom_left_1(15),
I2 => \bottom_right_1_reg_n_0_[15]\,
I3 => top_left_1(15),
O => \Lxx_11__1_carry__2_i_11_n_0\
);
\Lxx_11__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(14),
I1 => \top_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
O => \Lxx_11__1_carry__2_i_12_n_0\
);
\Lxx_11__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[12]\,
I1 => \Lxx_11__1_carry__2_i_9_n_0\,
I2 => top_left_1(11),
I3 => \top_right_1_reg_n_0_[11]\,
I4 => bottom_left_1(11),
O => \Lxx_11__1_carry__2_i_2_n_0\
);
\Lxx_11__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[11]\,
I1 => \Lxx_11__1_carry__1_i_12_n_0\,
I2 => top_left_1(10),
I3 => \top_right_1_reg_n_0_[10]\,
I4 => bottom_left_1(10),
O => \Lxx_11__1_carry__2_i_3_n_0\
);
\Lxx_11__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_11__1_carry__2_i_10_n_0\,
I1 => \bottom_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
I3 => \top_right_1_reg_n_0_[14]\,
I4 => bottom_left_1(14),
I5 => \Lxx_11__1_carry__2_i_11_n_0\,
O => \Lxx_11__1_carry__2_i_4_n_0\
);
\Lxx_11__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_1_n_0\,
I1 => top_left_1(13),
I2 => \top_right_1_reg_n_0_[13]\,
I3 => bottom_left_1(13),
I4 => \bottom_right_1_reg_n_0_[14]\,
I5 => \Lxx_11__1_carry__2_i_12_n_0\,
O => \Lxx_11__1_carry__2_i_5_n_0\
);
\Lxx_11__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_2_n_0\,
I1 => top_left_1(12),
I2 => \top_right_1_reg_n_0_[12]\,
I3 => bottom_left_1(12),
I4 => \bottom_right_1_reg_n_0_[13]\,
I5 => \Lxx_11__1_carry__2_i_8_n_0\,
O => \Lxx_11__1_carry__2_i_6_n_0\
);
\Lxx_11__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_3_n_0\,
I1 => top_left_1(11),
I2 => \top_right_1_reg_n_0_[11]\,
I3 => bottom_left_1(11),
I4 => \bottom_right_1_reg_n_0_[12]\,
I5 => \Lxx_11__1_carry__2_i_9_n_0\,
O => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => top_left_1(13),
O => \Lxx_11__1_carry__2_i_8_n_0\
);
\Lxx_11__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(12),
I1 => \top_right_1_reg_n_0_[12]\,
I2 => top_left_1(12),
O => \Lxx_11__1_carry__2_i_9_n_0\
);
\Lxx_11__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[2]\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => bottom_left_1(1),
I5 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_1_n_0\
);
\Lxx_11__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => bottom_left_1(1),
I1 => \top_right_1_reg_n_0_[1]\,
I2 => top_left_1(1),
I3 => \bottom_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_2_n_0\
);
\Lxx_11__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_1_reg_n_0_[1]\,
I1 => bottom_left_1(1),
I2 => \bottom_right_1_reg_n_0_[1]\,
I3 => top_left_1(1),
O => \Lxx_11__1_carry_i_3_n_0\
);
\Lxx_11__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry_i_1_n_0\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => \bottom_right_1_reg_n_0_[3]\,
I5 => \Lxx_11__1_carry_i_8_n_0\,
O => \Lxx_11__1_carry_i_4_n_0\
);
\Lxx_11__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_11__1_carry_i_2_n_0\,
I1 => \bottom_right_1_reg_n_0_[2]\,
I2 => \Lxx_11__1_carry_i_9_n_0\,
I3 => bottom_left_1(1),
I4 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_5_n_0\
);
\Lxx_11__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_11__1_carry_i_3_n_0\,
I1 => top_left_1(0),
I2 => \top_right_1_reg_n_0_[0]\,
I3 => bottom_left_1(0),
O => \Lxx_11__1_carry_i_6_n_0\
);
\Lxx_11__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => bottom_left_1(0),
I1 => \top_right_1_reg_n_0_[0]\,
I2 => top_left_1(0),
I3 => \bottom_right_1_reg_n_0_[0]\,
O => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(3),
I1 => \top_right_1_reg_n_0_[3]\,
I2 => top_left_1(3),
O => \Lxx_11__1_carry_i_8_n_0\
);
\Lxx_11__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(2),
I1 => \top_right_1_reg_n_0_[2]\,
I2 => top_left_1(2),
O => \Lxx_11__1_carry_i_9_n_0\
);
\Lxx_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(9),
Q => Lxx_1(10),
R => '0'
);
\Lxx_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(10),
Q => Lxx_1(11),
R => '0'
);
\Lxx_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(11),
Q => Lxx_1(12),
R => '0'
);
\Lxx_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(12),
Q => Lxx_1(13),
R => '0'
);
\Lxx_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(13),
Q => Lxx_1(14),
R => '0'
);
\Lxx_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(14),
Q => Lxx_1(15),
R => '0'
);
\Lxx_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(0),
Q => Lxx_1(1),
R => '0'
);
\Lxx_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(1),
Q => Lxx_1(2),
R => '0'
);
\Lxx_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(2),
Q => Lxx_1(3),
R => '0'
);
\Lxx_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(3),
Q => Lxx_1(4),
R => '0'
);
\Lxx_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(4),
Q => Lxx_1(5),
R => '0'
);
\Lxx_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(5),
Q => Lxx_1(6),
R => '0'
);
\Lxx_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(6),
Q => Lxx_1(7),
R => '0'
);
\Lxx_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(7),
Q => Lxx_1(8),
R => '0'
);
\Lxx_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(8),
Q => Lxx_1(9),
R => '0'
);
\Lxx_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => cycle(2),
I4 => rst,
I5 => active,
O => \Lxx_2[15]_i_1_n_0\
);
\Lxx_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxx_2_reg_n_0_[0]\,
R => '0'
);
\Lxx_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxx_2_reg_n_0_[10]\,
R => '0'
);
\Lxx_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxx_2_reg_n_0_[11]\,
R => '0'
);
\Lxx_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxx_2_reg_n_0_[12]\,
R => '0'
);
\Lxx_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxx_2_reg_n_0_[13]\,
R => '0'
);
\Lxx_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxx_2_reg_n_0_[14]\,
R => '0'
);
\Lxx_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxx_2_reg_n_0_[15]\,
R => '0'
);
\Lxx_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxx_2_reg_n_0_[1]\,
R => '0'
);
\Lxx_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxx_2_reg_n_0_[2]\,
R => '0'
);
\Lxx_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxx_2_reg_n_0_[3]\,
R => '0'
);
\Lxx_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxx_2_reg_n_0_[4]\,
R => '0'
);
\Lxx_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxx_2_reg_n_0_[5]\,
R => '0'
);
\Lxx_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxx_2_reg_n_0_[6]\,
R => '0'
);
\Lxx_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxx_2_reg_n_0_[7]\,
R => '0'
);
\Lxx_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxx_2_reg_n_0_[8]\,
R => '0'
);
\Lxx_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxx_2_reg_n_0_[9]\,
R => '0'
);
\Lxy0__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxy0__1_carry_n_0\,
CO(2) => \Lxy0__1_carry_n_1\,
CO(1) => \Lxy0__1_carry_n_2\,
CO(0) => \Lxy0__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry_i_1_n_0\,
DI(2) => \Lxy0__1_carry_i_2_n_0\,
DI(1) => \Lxy0__1_carry_i_3_n_0\,
DI(0) => \Lxy_0_reg_n_0_[0]\,
O(3) => \Lxy0__1_carry_n_4\,
O(2) => \Lxy0__1_carry_n_5\,
O(1) => \Lxy0__1_carry_n_6\,
O(0) => \Lxy0__1_carry_n_7\,
S(3) => \Lxy0__1_carry_i_4_n_0\,
S(2) => \Lxy0__1_carry_i_5_n_0\,
S(1) => \Lxy0__1_carry_i_6_n_0\,
S(0) => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry_n_0\,
CO(3) => \Lxy0__1_carry__0_n_0\,
CO(2) => \Lxy0__1_carry__0_n_1\,
CO(1) => \Lxy0__1_carry__0_n_2\,
CO(0) => \Lxy0__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__0_i_1_n_0\,
DI(2) => \Lxy0__1_carry__0_i_2_n_0\,
DI(1) => \Lxy0__1_carry__0_i_3_n_0\,
DI(0) => \Lxy0__1_carry__0_i_4_n_0\,
O(3) => \Lxy0__1_carry__0_n_4\,
O(2) => \Lxy0__1_carry__0_n_5\,
O(1) => \Lxy0__1_carry__0_n_6\,
O(0) => \Lxy0__1_carry__0_n_7\,
S(3) => \Lxy0__1_carry__0_i_5_n_0\,
S(2) => \Lxy0__1_carry__0_i_6_n_0\,
S(1) => \Lxy0__1_carry__0_i_7_n_0\,
S(0) => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[6]\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => Lxy_3(5),
I3 => Lxy_2(5),
I4 => \Lxy_1_reg_n_0_[5]\,
O => \Lxy0__1_carry__0_i_1_n_0\
);
\Lxy0__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(5),
I1 => \Lxy_1_reg_n_0_[5]\,
I2 => Lxy_2(5),
O => \Lxy0__1_carry__0_i_10_n_0\
);
\Lxy0__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(4),
I1 => \Lxy_1_reg_n_0_[4]\,
I2 => Lxy_2(4),
O => \Lxy0__1_carry__0_i_11_n_0\
);
\Lxy0__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(7),
I1 => \Lxy_1_reg_n_0_[7]\,
I2 => Lxy_2(7),
O => \Lxy0__1_carry__0_i_12_n_0\
);
\Lxy0__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[5]\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => Lxy_3(4),
I3 => Lxy_2(4),
I4 => \Lxy_1_reg_n_0_[4]\,
O => \Lxy0__1_carry__0_i_2_n_0\
);
\Lxy0__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[4]\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => Lxy_3(3),
I3 => Lxy_2(3),
I4 => \Lxy_1_reg_n_0_[3]\,
O => \Lxy0__1_carry__0_i_3_n_0\
);
\Lxy0__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[3]\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => Lxy_3(2),
I3 => Lxy_2(2),
I4 => \Lxy_1_reg_n_0_[2]\,
O => \Lxy0__1_carry__0_i_4_n_0\
);
\Lxy0__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_1_n_0\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[7]\,
I3 => \Lxy_1_reg_n_0_[6]\,
I4 => Lxy_2(6),
I5 => Lxy_3(6),
O => \Lxy0__1_carry__0_i_5_n_0\
);
\Lxy0__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_2_n_0\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[6]\,
I3 => \Lxy_1_reg_n_0_[5]\,
I4 => Lxy_2(5),
I5 => Lxy_3(5),
O => \Lxy0__1_carry__0_i_6_n_0\
);
\Lxy0__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_3_n_0\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[5]\,
I3 => \Lxy_1_reg_n_0_[4]\,
I4 => Lxy_2(4),
I5 => Lxy_3(4),
O => \Lxy0__1_carry__0_i_7_n_0\
);
\Lxy0__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_4_n_0\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[4]\,
I3 => \Lxy_1_reg_n_0_[3]\,
I4 => Lxy_2(3),
I5 => Lxy_3(3),
O => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(6),
I1 => \Lxy_1_reg_n_0_[6]\,
I2 => Lxy_2(6),
O => \Lxy0__1_carry__0_i_9_n_0\
);
\Lxy0__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__0_n_0\,
CO(3) => \Lxy0__1_carry__1_n_0\,
CO(2) => \Lxy0__1_carry__1_n_1\,
CO(1) => \Lxy0__1_carry__1_n_2\,
CO(0) => \Lxy0__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__1_i_1_n_0\,
DI(2) => \Lxy0__1_carry__1_i_2_n_0\,
DI(1) => \Lxy0__1_carry__1_i_3_n_0\,
DI(0) => \Lxy0__1_carry__1_i_4_n_0\,
O(3) => \Lxy0__1_carry__1_n_4\,
O(2) => \Lxy0__1_carry__1_n_5\,
O(1) => \Lxy0__1_carry__1_n_6\,
O(0) => \Lxy0__1_carry__1_n_7\,
S(3) => \Lxy0__1_carry__1_i_5_n_0\,
S(2) => \Lxy0__1_carry__1_i_6_n_0\,
S(1) => \Lxy0__1_carry__1_i_7_n_0\,
S(0) => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[10]\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => Lxy_3(9),
I3 => Lxy_2(9),
I4 => \Lxy_1_reg_n_0_[9]\,
O => \Lxy0__1_carry__1_i_1_n_0\
);
\Lxy0__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(9),
I1 => \Lxy_1_reg_n_0_[9]\,
I2 => Lxy_2(9),
O => \Lxy0__1_carry__1_i_10_n_0\
);
\Lxy0__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(8),
I1 => \Lxy_1_reg_n_0_[8]\,
I2 => Lxy_2(8),
O => \Lxy0__1_carry__1_i_11_n_0\
);
\Lxy0__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(11),
I1 => \Lxy_1_reg_n_0_[11]\,
I2 => Lxy_2(11),
O => \Lxy0__1_carry__1_i_12_n_0\
);
\Lxy0__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[9]\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => Lxy_3(8),
I3 => Lxy_2(8),
I4 => \Lxy_1_reg_n_0_[8]\,
O => \Lxy0__1_carry__1_i_2_n_0\
);
\Lxy0__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[8]\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => Lxy_3(7),
I3 => Lxy_2(7),
I4 => \Lxy_1_reg_n_0_[7]\,
O => \Lxy0__1_carry__1_i_3_n_0\
);
\Lxy0__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[7]\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => Lxy_3(6),
I3 => Lxy_2(6),
I4 => \Lxy_1_reg_n_0_[6]\,
O => \Lxy0__1_carry__1_i_4_n_0\
);
\Lxy0__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_1_n_0\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[11]\,
I3 => \Lxy_1_reg_n_0_[10]\,
I4 => Lxy_2(10),
I5 => Lxy_3(10),
O => \Lxy0__1_carry__1_i_5_n_0\
);
\Lxy0__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_2_n_0\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[10]\,
I3 => \Lxy_1_reg_n_0_[9]\,
I4 => Lxy_2(9),
I5 => Lxy_3(9),
O => \Lxy0__1_carry__1_i_6_n_0\
);
\Lxy0__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_3_n_0\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[9]\,
I3 => \Lxy_1_reg_n_0_[8]\,
I4 => Lxy_2(8),
I5 => Lxy_3(8),
O => \Lxy0__1_carry__1_i_7_n_0\
);
\Lxy0__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_4_n_0\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[8]\,
I3 => \Lxy_1_reg_n_0_[7]\,
I4 => Lxy_2(7),
I5 => Lxy_3(7),
O => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(10),
I1 => \Lxy_1_reg_n_0_[10]\,
I2 => Lxy_2(10),
O => \Lxy0__1_carry__1_i_9_n_0\
);
\Lxy0__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__1_n_0\,
CO(3) => \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxy0__1_carry__2_n_1\,
CO(1) => \Lxy0__1_carry__2_n_2\,
CO(0) => \Lxy0__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxy0__1_carry__2_i_1_n_0\,
DI(1) => \Lxy0__1_carry__2_i_2_n_0\,
DI(0) => \Lxy0__1_carry__2_i_3_n_0\,
O(3) => \Lxy0__1_carry__2_n_4\,
O(2) => \Lxy0__1_carry__2_n_5\,
O(1) => \Lxy0__1_carry__2_n_6\,
O(0) => \Lxy0__1_carry__2_n_7\,
S(3) => \Lxy0__1_carry__2_i_4_n_0\,
S(2) => \Lxy0__1_carry__2_i_5_n_0\,
S(1) => \Lxy0__1_carry__2_i_6_n_0\,
S(0) => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[13]\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => Lxy_3(12),
I3 => Lxy_2(12),
I4 => \Lxy_1_reg_n_0_[12]\,
O => \Lxy0__1_carry__2_i_1_n_0\
);
\Lxy0__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => \Lxy_1_reg_n_0_[13]\,
I1 => Lxy_2(13),
I2 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_10_n_0\
);
\Lxy0__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(15),
I1 => \Lxy_1_reg_n_0_[15]\,
I2 => Lxy_3(15),
I3 => \Lxy_0_reg_n_0_[15]\,
O => \Lxy0__1_carry__2_i_11_n_0\
);
\Lxy0__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(14),
I1 => \Lxy_1_reg_n_0_[14]\,
I2 => Lxy_2(14),
O => \Lxy0__1_carry__2_i_12_n_0\
);
\Lxy0__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[12]\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => Lxy_3(11),
I3 => Lxy_2(11),
I4 => \Lxy_1_reg_n_0_[11]\,
O => \Lxy0__1_carry__2_i_2_n_0\
);
\Lxy0__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[11]\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => Lxy_3(10),
I3 => Lxy_2(10),
I4 => \Lxy_1_reg_n_0_[10]\,
O => \Lxy0__1_carry__2_i_3_n_0\
);
\Lxy0__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E87781E87E11E87"
)
port map (
I0 => \Lxy0__1_carry__2_i_10_n_0\,
I1 => \Lxy_0_reg_n_0_[14]\,
I2 => \Lxy0__1_carry__2_i_11_n_0\,
I3 => \Lxy_1_reg_n_0_[14]\,
I4 => Lxy_2(14),
I5 => Lxy_3(14),
O => \Lxy0__1_carry__2_i_4_n_0\
);
\Lxy0__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_1_n_0\,
I1 => \Lxy0__1_carry__2_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[14]\,
I3 => \Lxy_1_reg_n_0_[13]\,
I4 => Lxy_2(13),
I5 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_5_n_0\
);
\Lxy0__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_2_n_0\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[13]\,
I3 => \Lxy_1_reg_n_0_[12]\,
I4 => Lxy_2(12),
I5 => Lxy_3(12),
O => \Lxy0__1_carry__2_i_6_n_0\
);
\Lxy0__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_3_n_0\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[12]\,
I3 => \Lxy_1_reg_n_0_[11]\,
I4 => Lxy_2(11),
I5 => Lxy_3(11),
O => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(13),
I1 => \Lxy_1_reg_n_0_[13]\,
I2 => Lxy_2(13),
O => \Lxy0__1_carry__2_i_8_n_0\
);
\Lxy0__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(12),
I1 => \Lxy_1_reg_n_0_[12]\,
I2 => Lxy_2(12),
O => \Lxy0__1_carry__2_i_9_n_0\
);
\Lxy0__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBEEBBE8228EBBE"
)
port map (
I0 => \Lxy_0_reg_n_0_[2]\,
I1 => Lxy_2(2),
I2 => \Lxy_1_reg_n_0_[2]\,
I3 => Lxy_3(2),
I4 => \Lxy_1_reg_n_0_[1]\,
I5 => Lxy_2(1),
O => \Lxy0__1_carry_i_1_n_0\
);
\Lxy0__1_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => Lxy_2(1),
I1 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_10_n_0\
);
\Lxy0__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4DD4"
)
port map (
I0 => Lxy_3(1),
I1 => \Lxy_0_reg_n_0_[1]\,
I2 => \Lxy_1_reg_n_0_[1]\,
I3 => Lxy_2(1),
O => \Lxy0__1_carry_i_2_n_0\
);
\Lxy0__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxy_1_reg_n_0_[1]\,
I1 => Lxy_2(1),
I2 => Lxy_3(1),
I3 => \Lxy_0_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_3_n_0\
);
\Lxy0__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry_i_1_n_0\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[3]\,
I3 => \Lxy_1_reg_n_0_[2]\,
I4 => Lxy_2(2),
I5 => Lxy_3(2),
O => \Lxy0__1_carry_i_4_n_0\
);
\Lxy0__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"69966969"
)
port map (
I0 => \Lxy0__1_carry_i_2_n_0\,
I1 => \Lxy0__1_carry_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[2]\,
I3 => Lxy_2(1),
I4 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_5_n_0\
);
\Lxy0__1_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy_0_reg_n_0_[1]\,
I1 => Lxy_3(1),
I2 => \Lxy0__1_carry_i_10_n_0\,
I3 => Lxy_3(0),
I4 => Lxy_2(0),
I5 => \Lxy_1_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_6_n_0\
);
\Lxy0__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(0),
I1 => \Lxy_1_reg_n_0_[0]\,
I2 => Lxy_3(0),
I3 => \Lxy_0_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(3),
I1 => \Lxy_1_reg_n_0_[3]\,
I2 => Lxy_2(3),
O => \Lxy0__1_carry_i_8_n_0\
);
\Lxy0__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(2),
I1 => \Lxy_1_reg_n_0_[2]\,
I2 => Lxy_2(2),
O => \Lxy0__1_carry_i_9_n_0\
);
\Lxy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => \Lxy_0[15]_i_1_n_0\
);
\Lxy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxy_0_reg_n_0_[0]\,
R => '0'
);
\Lxy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxy_0_reg_n_0_[10]\,
R => '0'
);
\Lxy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxy_0_reg_n_0_[11]\,
R => '0'
);
\Lxy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxy_0_reg_n_0_[12]\,
R => '0'
);
\Lxy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxy_0_reg_n_0_[13]\,
R => '0'
);
\Lxy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxy_0_reg_n_0_[14]\,
R => '0'
);
\Lxy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxy_0_reg_n_0_[15]\,
R => '0'
);
\Lxy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxy_0_reg_n_0_[1]\,
R => '0'
);
\Lxy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxy_0_reg_n_0_[2]\,
R => '0'
);
\Lxy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxy_0_reg_n_0_[3]\,
R => '0'
);
\Lxy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxy_0_reg_n_0_[4]\,
R => '0'
);
\Lxy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxy_0_reg_n_0_[5]\,
R => '0'
);
\Lxy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxy_0_reg_n_0_[6]\,
R => '0'
);
\Lxy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxy_0_reg_n_0_[7]\,
R => '0'
);
\Lxy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxy_0_reg_n_0_[8]\,
R => '0'
);
\Lxy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxy_0_reg_n_0_[9]\,
R => '0'
);
\Lxy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => Lxy_1
);
\Lxy_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(0),
Q => \Lxy_1_reg_n_0_[0]\,
R => '0'
);
\Lxy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(10),
Q => \Lxy_1_reg_n_0_[10]\,
R => '0'
);
\Lxy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(11),
Q => \Lxy_1_reg_n_0_[11]\,
R => '0'
);
\Lxy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(12),
Q => \Lxy_1_reg_n_0_[12]\,
R => '0'
);
\Lxy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(13),
Q => \Lxy_1_reg_n_0_[13]\,
R => '0'
);
\Lxy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(14),
Q => \Lxy_1_reg_n_0_[14]\,
R => '0'
);
\Lxy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(15),
Q => \Lxy_1_reg_n_0_[15]\,
R => '0'
);
\Lxy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(1),
Q => \Lxy_1_reg_n_0_[1]\,
R => '0'
);
\Lxy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(2),
Q => \Lxy_1_reg_n_0_[2]\,
R => '0'
);
\Lxy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(3),
Q => \Lxy_1_reg_n_0_[3]\,
R => '0'
);
\Lxy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(4),
Q => \Lxy_1_reg_n_0_[4]\,
R => '0'
);
\Lxy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(5),
Q => \Lxy_1_reg_n_0_[5]\,
R => '0'
);
\Lxy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(6),
Q => \Lxy_1_reg_n_0_[6]\,
R => '0'
);
\Lxy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(7),
Q => \Lxy_1_reg_n_0_[7]\,
R => '0'
);
\Lxy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(8),
Q => \Lxy_1_reg_n_0_[8]\,
R => '0'
);
\Lxy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(9),
Q => \Lxy_1_reg_n_0_[9]\,
R => '0'
);
\Lxy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(0),
Q => Lxy_2(0),
R => '0'
);
\Lxy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(10),
Q => Lxy_2(10),
R => '0'
);
\Lxy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(11),
Q => Lxy_2(11),
R => '0'
);
\Lxy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(12),
Q => Lxy_2(12),
R => '0'
);
\Lxy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(13),
Q => Lxy_2(13),
R => '0'
);
\Lxy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(14),
Q => Lxy_2(14),
R => '0'
);
\Lxy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(15),
Q => Lxy_2(15),
R => '0'
);
\Lxy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(1),
Q => Lxy_2(1),
R => '0'
);
\Lxy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(2),
Q => Lxy_2(2),
R => '0'
);
\Lxy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(3),
Q => Lxy_2(3),
R => '0'
);
\Lxy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(4),
Q => Lxy_2(4),
R => '0'
);
\Lxy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(5),
Q => Lxy_2(5),
R => '0'
);
\Lxy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(6),
Q => Lxy_2(6),
R => '0'
);
\Lxy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(7),
Q => Lxy_2(7),
R => '0'
);
\Lxy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(8),
Q => Lxy_2(8),
R => '0'
);
\Lxy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(9),
Q => Lxy_2(9),
R => '0'
);
\Lxy_3[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => cycle(3),
O => y6
);
\Lxy_3_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(0),
Q => Lxy_3(0),
R => '0'
);
\Lxy_3_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(10),
Q => Lxy_3(10),
R => '0'
);
\Lxy_3_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(11),
Q => Lxy_3(11),
R => '0'
);
\Lxy_3_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(12),
Q => Lxy_3(12),
R => '0'
);
\Lxy_3_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(13),
Q => Lxy_3(13),
R => '0'
);
\Lxy_3_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(14),
Q => Lxy_3(14),
R => '0'
);
\Lxy_3_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(15),
Q => Lxy_3(15),
R => '0'
);
\Lxy_3_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(1),
Q => Lxy_3(1),
R => '0'
);
\Lxy_3_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(2),
Q => Lxy_3(2),
R => '0'
);
\Lxy_3_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(3),
Q => Lxy_3(3),
R => '0'
);
\Lxy_3_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(4),
Q => Lxy_3(4),
R => '0'
);
\Lxy_3_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(5),
Q => Lxy_3(5),
R => '0'
);
\Lxy_3_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(6),
Q => Lxy_3(6),
R => '0'
);
\Lxy_3_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(7),
Q => Lxy_3(7),
R => '0'
);
\Lxy_3_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(8),
Q => Lxy_3(8),
R => '0'
);
\Lxy_3_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(9),
Q => Lxy_3(9),
R => '0'
);
Lyy0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lyy0_carry_n_0,
CO(2) => Lyy0_carry_n_1,
CO(1) => Lyy0_carry_n_2,
CO(0) => Lyy0_carry_n_3,
CYINIT => '0',
DI(3) => Lyy0_carry_i_1_n_0,
DI(2) => Lyy0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lyy_2_reg_n_0_[0]\,
O(3 downto 0) => B(3 downto 0),
S(3) => Lyy0_carry_i_3_n_0,
S(2) => Lyy0_carry_i_4_n_0,
S(1) => Lyy0_carry_i_5_n_0,
S(0) => Lyy0_carry_i_6_n_0
);
\Lyy0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lyy0_carry_n_0,
CO(3) => \Lyy0_carry__0_n_0\,
CO(2) => \Lyy0_carry__0_n_1\,
CO(1) => \Lyy0_carry__0_n_2\,
CO(0) => \Lyy0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__0_i_1_n_0\,
DI(2) => \Lyy0_carry__0_i_2_n_0\,
DI(1) => \Lyy0_carry__0_i_3_n_0\,
DI(0) => \Lyy0_carry__0_i_4_n_0\,
O(3 downto 0) => B(7 downto 4),
S(3) => \Lyy0_carry__0_i_5_n_0\,
S(2) => \Lyy0_carry__0_i_6_n_0\,
S(1) => \Lyy0_carry__0_i_7_n_0\,
S(0) => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
O => \Lyy0_carry__0_i_1_n_0\
);
\Lyy0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
O => \Lyy0_carry__0_i_2_n_0\
);
\Lyy0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
O => \Lyy0_carry__0_i_3_n_0\
);
\Lyy0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
O => \Lyy0_carry__0_i_4_n_0\
);
\Lyy0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
I3 => \Lyy0_carry__0_i_1_n_0\,
O => \Lyy0_carry__0_i_5_n_0\
);
\Lyy0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
I3 => \Lyy0_carry__0_i_2_n_0\,
O => \Lyy0_carry__0_i_6_n_0\
);
\Lyy0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
I3 => \Lyy0_carry__0_i_3_n_0\,
O => \Lyy0_carry__0_i_7_n_0\
);
\Lyy0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
I3 => \Lyy0_carry__0_i_4_n_0\,
O => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__0_n_0\,
CO(3) => \Lyy0_carry__1_n_0\,
CO(2) => \Lyy0_carry__1_n_1\,
CO(1) => \Lyy0_carry__1_n_2\,
CO(0) => \Lyy0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__1_i_1_n_0\,
DI(2) => \Lyy0_carry__1_i_2_n_0\,
DI(1) => \Lyy0_carry__1_i_3_n_0\,
DI(0) => \Lyy0_carry__1_i_4_n_0\,
O(3 downto 0) => B(11 downto 8),
S(3) => \Lyy0_carry__1_i_5_n_0\,
S(2) => \Lyy0_carry__1_i_6_n_0\,
S(1) => \Lyy0_carry__1_i_7_n_0\,
S(0) => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
O => \Lyy0_carry__1_i_1_n_0\
);
\Lyy0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
O => \Lyy0_carry__1_i_2_n_0\
);
\Lyy0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
O => \Lyy0_carry__1_i_3_n_0\
);
\Lyy0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
O => \Lyy0_carry__1_i_4_n_0\
);
\Lyy0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
I3 => \Lyy0_carry__1_i_1_n_0\,
O => \Lyy0_carry__1_i_5_n_0\
);
\Lyy0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
I3 => \Lyy0_carry__1_i_2_n_0\,
O => \Lyy0_carry__1_i_6_n_0\
);
\Lyy0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
I3 => \Lyy0_carry__1_i_3_n_0\,
O => \Lyy0_carry__1_i_7_n_0\
);
\Lyy0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
I3 => \Lyy0_carry__1_i_4_n_0\,
O => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__1_n_0\,
CO(3) => \NLW_Lyy0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy0_carry__2_n_1\,
CO(1) => \Lyy0_carry__2_n_2\,
CO(0) => \Lyy0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy0_carry__2_i_1_n_0\,
DI(1) => \Lyy0_carry__2_i_2_n_0\,
DI(0) => \Lyy0_carry__2_i_3_n_0\,
O(3 downto 0) => B(15 downto 12),
S(3) => \Lyy0_carry__2_i_4_n_0\,
S(2) => \Lyy0_carry__2_i_5_n_0\,
S(1) => \Lyy0_carry__2_i_6_n_0\,
S(0) => \Lyy0_carry__2_i_7_n_0\
);
\Lyy0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
O => \Lyy0_carry__2_i_1_n_0\
);
\Lyy0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
O => \Lyy0_carry__2_i_2_n_0\
);
\Lyy0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
O => \Lyy0_carry__2_i_3_n_0\
);
\Lyy0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \Lyy_0_reg_n_0_[14]\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_2_reg_n_0_[15]\,
I4 => Lyy_1(15),
I5 => \Lyy_0_reg_n_0_[15]\,
O => \Lyy0_carry__2_i_4_n_0\
);
\Lyy0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lyy0_carry__2_i_1_n_0\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_0_reg_n_0_[14]\,
O => \Lyy0_carry__2_i_5_n_0\
);
\Lyy0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
I3 => \Lyy0_carry__2_i_2_n_0\,
O => \Lyy0_carry__2_i_6_n_0\
);
\Lyy0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
I3 => \Lyy0_carry__2_i_3_n_0\,
O => \Lyy0_carry__2_i_7_n_0\
);
Lyy0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
O => Lyy0_carry_i_1_n_0
);
Lyy0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_2_n_0
);
Lyy0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
I3 => Lyy0_carry_i_1_n_0,
O => Lyy0_carry_i_3_n_0
);
Lyy0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
I3 => Lyy0_carry_i_2_n_0,
O => Lyy0_carry_i_4_n_0
);
Lyy0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_5_n_0
);
Lyy0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lyy_2_reg_n_0_[0]\,
I1 => \Lyy_0_reg_n_0_[0]\,
O => Lyy0_carry_i_6_n_0
);
\Lyy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[0]_rep_n_0\,
O => Lyy_0
);
\Lyy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(0),
Q => \Lyy_0_reg_n_0_[0]\,
R => '0'
);
\Lyy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(10),
Q => \Lyy_0_reg_n_0_[10]\,
R => '0'
);
\Lyy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(11),
Q => \Lyy_0_reg_n_0_[11]\,
R => '0'
);
\Lyy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(12),
Q => \Lyy_0_reg_n_0_[12]\,
R => '0'
);
\Lyy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(13),
Q => \Lyy_0_reg_n_0_[13]\,
R => '0'
);
\Lyy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(14),
Q => \Lyy_0_reg_n_0_[14]\,
R => '0'
);
\Lyy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(15),
Q => \Lyy_0_reg_n_0_[15]\,
R => '0'
);
\Lyy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(1),
Q => \Lyy_0_reg_n_0_[1]\,
R => '0'
);
\Lyy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(2),
Q => \Lyy_0_reg_n_0_[2]\,
R => '0'
);
\Lyy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(3),
Q => \Lyy_0_reg_n_0_[3]\,
R => '0'
);
\Lyy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(4),
Q => \Lyy_0_reg_n_0_[4]\,
R => '0'
);
\Lyy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(5),
Q => \Lyy_0_reg_n_0_[5]\,
R => '0'
);
\Lyy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(6),
Q => \Lyy_0_reg_n_0_[6]\,
R => '0'
);
\Lyy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(7),
Q => \Lyy_0_reg_n_0_[7]\,
R => '0'
);
\Lyy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(8),
Q => \Lyy_0_reg_n_0_[8]\,
R => '0'
);
\Lyy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(9),
Q => \Lyy_0_reg_n_0_[9]\,
R => '0'
);
\Lyy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => rst,
I3 => active,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y1
);
\Lyy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(9),
Q => Lyy_1(10),
R => '0'
);
\Lyy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(10),
Q => Lyy_1(11),
R => '0'
);
\Lyy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(11),
Q => Lyy_1(12),
R => '0'
);
\Lyy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(12),
Q => Lyy_1(13),
R => '0'
);
\Lyy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(13),
Q => Lyy_1(14),
R => '0'
);
\Lyy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(14),
Q => Lyy_1(15),
R => '0'
);
\Lyy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(0),
Q => Lyy_1(1),
R => '0'
);
\Lyy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(1),
Q => Lyy_1(2),
R => '0'
);
\Lyy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(2),
Q => Lyy_1(3),
R => '0'
);
\Lyy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(3),
Q => Lyy_1(4),
R => '0'
);
\Lyy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(4),
Q => Lyy_1(5),
R => '0'
);
\Lyy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(5),
Q => Lyy_1(6),
R => '0'
);
\Lyy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(6),
Q => Lyy_1(7),
R => '0'
);
\Lyy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(7),
Q => Lyy_1(8),
R => '0'
);
\Lyy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(8),
Q => Lyy_1(9),
R => '0'
);
\Lyy_20__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_20__1_carry_n_0\,
CO(2) => \Lyy_20__1_carry_n_1\,
CO(1) => \Lyy_20__1_carry_n_2\,
CO(0) => \Lyy_20__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry_i_1_n_0\,
DI(2) => \Lyy_20__1_carry_i_2_n_0\,
DI(1) => \Lyy_20__1_carry_i_3_n_0\,
DI(0) => Lyy_2_bottom_right(0),
O(3 downto 0) => Lyy_20(3 downto 0),
S(3) => \Lyy_20__1_carry_i_4_n_0\,
S(2) => \Lyy_20__1_carry_i_5_n_0\,
S(1) => \Lyy_20__1_carry_i_6_n_0\,
S(0) => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry_n_0\,
CO(3) => \Lyy_20__1_carry__0_n_0\,
CO(2) => \Lyy_20__1_carry__0_n_1\,
CO(1) => \Lyy_20__1_carry__0_n_2\,
CO(0) => \Lyy_20__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__0_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__0_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__0_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_20(7 downto 4),
S(3) => \Lyy_20__1_carry__0_i_5_n_0\,
S(2) => \Lyy_20__1_carry__0_i_6_n_0\,
S(1) => \Lyy_20__1_carry__0_i_7_n_0\,
S(0) => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(6),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_right(6),
I3 => \Lyy_20__1_carry__0_i_9_n_0\,
I4 => Lyy_2_bottom_right(6),
O => \Lyy_20__1_carry__0_i_1_n_0\
);
\Lyy_20__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(5),
I1 => Lyy_2_bottom_left(5),
I2 => Lyy_2_top_right(5),
O => \Lyy_20__1_carry__0_i_10_n_0\
);
\Lyy_20__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(3),
I1 => Lyy_2_top_left(3),
I2 => Lyy_2_bottom_left(3),
O => \Lyy_20__1_carry__0_i_11_n_0\
);
\Lyy_20__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(7),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_right(7),
O => \Lyy_20__1_carry__0_i_12_n_0\
);
\Lyy_20__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(5),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_left(4),
I3 => Lyy_2_top_right(4),
I4 => \Lyy_20__1_carry__0_i_10_n_0\,
O => \Lyy_20__1_carry__0_i_2_n_0\
);
\Lyy_20__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(4),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_right(4),
I3 => \Lyy_20__1_carry__0_i_11_n_0\,
I4 => Lyy_2_bottom_right(4),
O => \Lyy_20__1_carry__0_i_3_n_0\
);
\Lyy_20__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(3),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_left(2),
I3 => Lyy_2_top_right(2),
I4 => \Lyy_20__1_carry_i_8_n_0\,
O => \Lyy_20__1_carry__0_i_4_n_0\
);
\Lyy_20__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_1_n_0\,
I1 => \Lyy_20__1_carry__0_i_12_n_0\,
I2 => Lyy_2_bottom_right(7),
I3 => Lyy_2_top_right(6),
I4 => Lyy_2_top_left(6),
I5 => Lyy_2_bottom_left(6),
O => \Lyy_20__1_carry__0_i_5_n_0\
);
\Lyy_20__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_2_n_0\,
I1 => Lyy_2_top_right(6),
I2 => Lyy_2_bottom_left(6),
I3 => Lyy_2_top_left(6),
I4 => Lyy_2_bottom_right(6),
I5 => \Lyy_20__1_carry__0_i_9_n_0\,
O => \Lyy_20__1_carry__0_i_6_n_0\
);
\Lyy_20__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_3_n_0\,
I1 => \Lyy_20__1_carry__0_i_10_n_0\,
I2 => Lyy_2_bottom_right(5),
I3 => Lyy_2_top_right(4),
I4 => Lyy_2_top_left(4),
I5 => Lyy_2_bottom_left(4),
O => \Lyy_20__1_carry__0_i_7_n_0\
);
\Lyy_20__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_4_n_0\,
I1 => Lyy_2_top_right(4),
I2 => Lyy_2_bottom_left(4),
I3 => Lyy_2_top_left(4),
I4 => Lyy_2_bottom_right(4),
I5 => \Lyy_20__1_carry__0_i_11_n_0\,
O => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(5),
I1 => Lyy_2_top_left(5),
I2 => Lyy_2_bottom_left(5),
O => \Lyy_20__1_carry__0_i_9_n_0\
);
\Lyy_20__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__0_n_0\,
CO(3) => \Lyy_20__1_carry__1_n_0\,
CO(2) => \Lyy_20__1_carry__1_n_1\,
CO(1) => \Lyy_20__1_carry__1_n_2\,
CO(0) => \Lyy_20__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__1_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__1_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__1_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_20(11 downto 8),
S(3) => \Lyy_20__1_carry__1_i_5_n_0\,
S(2) => \Lyy_20__1_carry__1_i_6_n_0\,
S(1) => \Lyy_20__1_carry__1_i_7_n_0\,
S(0) => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(10),
I1 => Lyy_2_bottom_left(10),
I2 => Lyy_2_top_right(10),
I3 => \Lyy_20__1_carry__1_i_9_n_0\,
I4 => Lyy_2_bottom_right(10),
O => \Lyy_20__1_carry__1_i_1_n_0\
);
\Lyy_20__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(9),
I1 => Lyy_2_bottom_left(9),
I2 => Lyy_2_top_right(9),
O => \Lyy_20__1_carry__1_i_10_n_0\
);
\Lyy_20__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(8),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_right(8),
O => \Lyy_20__1_carry__1_i_11_n_0\
);
\Lyy_20__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(10),
I1 => Lyy_2_top_left(10),
I2 => Lyy_2_bottom_left(10),
O => \Lyy_20__1_carry__1_i_12_n_0\
);
\Lyy_20__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(9),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_left(8),
I3 => Lyy_2_top_right(8),
I4 => \Lyy_20__1_carry__1_i_10_n_0\,
O => \Lyy_20__1_carry__1_i_2_n_0\
);
\Lyy_20__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(8),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_left(7),
I3 => Lyy_2_top_right(7),
I4 => \Lyy_20__1_carry__1_i_11_n_0\,
O => \Lyy_20__1_carry__1_i_3_n_0\
);
\Lyy_20__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(7),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_left(6),
I3 => Lyy_2_top_right(6),
I4 => \Lyy_20__1_carry__0_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_4_n_0\
);
\Lyy_20__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_1_n_0\,
I1 => Lyy_2_top_right(11),
I2 => Lyy_2_bottom_left(11),
I3 => Lyy_2_top_left(11),
I4 => Lyy_2_bottom_right(11),
I5 => \Lyy_20__1_carry__1_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_5_n_0\
);
\Lyy_20__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_2_n_0\,
I1 => Lyy_2_top_right(10),
I2 => Lyy_2_bottom_left(10),
I3 => Lyy_2_top_left(10),
I4 => Lyy_2_bottom_right(10),
I5 => \Lyy_20__1_carry__1_i_9_n_0\,
O => \Lyy_20__1_carry__1_i_6_n_0\
);
\Lyy_20__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_3_n_0\,
I1 => \Lyy_20__1_carry__1_i_10_n_0\,
I2 => Lyy_2_bottom_right(9),
I3 => Lyy_2_top_right(8),
I4 => Lyy_2_top_left(8),
I5 => Lyy_2_bottom_left(8),
O => \Lyy_20__1_carry__1_i_7_n_0\
);
\Lyy_20__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_4_n_0\,
I1 => \Lyy_20__1_carry__1_i_11_n_0\,
I2 => Lyy_2_bottom_right(8),
I3 => Lyy_2_top_right(7),
I4 => Lyy_2_top_left(7),
I5 => Lyy_2_bottom_left(7),
O => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(9),
I1 => Lyy_2_top_left(9),
I2 => Lyy_2_bottom_left(9),
O => \Lyy_20__1_carry__1_i_9_n_0\
);
\Lyy_20__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__1_n_0\,
CO(3) => \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_20__1_carry__2_n_1\,
CO(1) => \Lyy_20__1_carry__2_n_2\,
CO(0) => \Lyy_20__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_20__1_carry__2_i_1_n_0\,
DI(1) => \Lyy_20__1_carry__2_i_2_n_0\,
DI(0) => \Lyy_20__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_20(15 downto 12),
S(3) => \Lyy_20__1_carry__2_i_4_n_0\,
S(2) => \Lyy_20__1_carry__2_i_5_n_0\,
S(1) => \Lyy_20__1_carry__2_i_6_n_0\,
S(0) => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(13),
I1 => Lyy_2_top_right(12),
I2 => Lyy_2_top_left(12),
I3 => Lyy_2_bottom_left(12),
I4 => \Lyy_20__1_carry__2_i_8_n_0\,
O => \Lyy_20__1_carry__2_i_1_n_0\
);
\Lyy_20__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_10_n_0\
);
\Lyy_20__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(15),
I1 => Lyy_2_bottom_left(15),
I2 => Lyy_2_top_left(15),
I3 => Lyy_2_bottom_right(15),
O => \Lyy_20__1_carry__2_i_11_n_0\
);
\Lyy_20__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(12),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_left(11),
I3 => Lyy_2_top_right(11),
I4 => \Lyy_20__1_carry__2_i_9_n_0\,
O => \Lyy_20__1_carry__2_i_2_n_0\
);
\Lyy_20__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(11),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_right(11),
I3 => \Lyy_20__1_carry__1_i_12_n_0\,
I4 => Lyy_2_bottom_right(11),
O => \Lyy_20__1_carry__2_i_3_n_0\
);
\Lyy_20__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E78871E871EE187"
)
port map (
I0 => Lyy_2_bottom_right(14),
I1 => \Lyy_20__1_carry__2_i_10_n_0\,
I2 => \Lyy_20__1_carry__2_i_11_n_0\,
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_left(14),
I5 => Lyy_2_top_right(14),
O => \Lyy_20__1_carry__2_i_4_n_0\
);
\Lyy_20__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__2_i_1_n_0\,
I1 => Lyy_2_top_right(14),
I2 => Lyy_2_bottom_left(14),
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_right(14),
I5 => \Lyy_20__1_carry__2_i_10_n_0\,
O => \Lyy_20__1_carry__2_i_5_n_0\
);
\Lyy_20__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_2_n_0\,
I1 => \Lyy_20__1_carry__2_i_8_n_0\,
I2 => Lyy_2_bottom_right(13),
I3 => Lyy_2_bottom_left(12),
I4 => Lyy_2_top_left(12),
I5 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_6_n_0\
);
\Lyy_20__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_3_n_0\,
I1 => \Lyy_20__1_carry__2_i_9_n_0\,
I2 => Lyy_2_bottom_right(12),
I3 => Lyy_2_top_right(11),
I4 => Lyy_2_top_left(11),
I5 => Lyy_2_bottom_left(11),
O => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_8_n_0\
);
\Lyy_20__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(12),
I1 => Lyy_2_bottom_left(12),
I2 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_9_n_0\
);
\Lyy_20__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FFFFFF00969696"
)
port map (
I0 => Lyy_2_top_left(2),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_right(2),
I3 => Lyy_2_top_right(1),
I4 => Lyy_2_bottom_left(1),
I5 => Lyy_2_bottom_right(2),
O => \Lyy_20__1_carry_i_1_n_0\
);
\Lyy_20__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => Lyy_2_top_right(1),
I1 => Lyy_2_bottom_left(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_2_n_0\
);
\Lyy_20__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_3_n_0\
);
\Lyy_20__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry_i_1_n_0\,
I1 => \Lyy_20__1_carry_i_8_n_0\,
I2 => Lyy_2_bottom_right(3),
I3 => Lyy_2_top_right(2),
I4 => Lyy_2_top_left(2),
I5 => Lyy_2_bottom_left(2),
O => \Lyy_20__1_carry_i_4_n_0\
);
\Lyy_20__1_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry_i_2_n_0\,
I1 => Lyy_2_top_right(2),
I2 => Lyy_2_bottom_left(2),
I3 => Lyy_2_top_left(2),
I4 => Lyy_2_bottom_right(2),
I5 => \Lyy_20__1_carry_i_9_n_0\,
O => \Lyy_20__1_carry_i_5_n_0\
);
\Lyy_20__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A59"
)
port map (
I0 => \Lyy_20__1_carry_i_3_n_0\,
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_top_right(0),
O => \Lyy_20__1_carry_i_6_n_0\
);
\Lyy_20__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(0),
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_bottom_right(0),
O => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(3),
I1 => Lyy_2_bottom_left(3),
I2 => Lyy_2_top_right(3),
O => \Lyy_20__1_carry_i_8_n_0\
);
\Lyy_20__1_carry_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
O => \Lyy_20__1_carry_i_9_n_0\
);
\Lyy_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \Lyy_2[15]_i_1_n_0\
);
\Lyy_2_bottom_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(0),
Q => Lyy_2_bottom_left(0),
R => '0'
);
\Lyy_2_bottom_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(10),
Q => Lyy_2_bottom_left(10),
R => '0'
);
\Lyy_2_bottom_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(11),
Q => Lyy_2_bottom_left(11),
R => '0'
);
\Lyy_2_bottom_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(12),
Q => Lyy_2_bottom_left(12),
R => '0'
);
\Lyy_2_bottom_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(13),
Q => Lyy_2_bottom_left(13),
R => '0'
);
\Lyy_2_bottom_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(14),
Q => Lyy_2_bottom_left(14),
R => '0'
);
\Lyy_2_bottom_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(15),
Q => Lyy_2_bottom_left(15),
R => '0'
);
\Lyy_2_bottom_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(1),
Q => Lyy_2_bottom_left(1),
R => '0'
);
\Lyy_2_bottom_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(2),
Q => Lyy_2_bottom_left(2),
R => '0'
);
\Lyy_2_bottom_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(3),
Q => Lyy_2_bottom_left(3),
R => '0'
);
\Lyy_2_bottom_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(4),
Q => Lyy_2_bottom_left(4),
R => '0'
);
\Lyy_2_bottom_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(5),
Q => Lyy_2_bottom_left(5),
R => '0'
);
\Lyy_2_bottom_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(6),
Q => Lyy_2_bottom_left(6),
R => '0'
);
\Lyy_2_bottom_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(7),
Q => Lyy_2_bottom_left(7),
R => '0'
);
\Lyy_2_bottom_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(8),
Q => Lyy_2_bottom_left(8),
R => '0'
);
\Lyy_2_bottom_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(9),
Q => Lyy_2_bottom_left(9),
R => '0'
);
\Lyy_2_bottom_right0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(3 downto 0),
S(3) => \Lyy_2_bottom_right0__0_carry_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__0_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__0_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(7 downto 4),
S(3) => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(6),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => \corner_reg_n_0_[5]\,
I3 => \top_reg_n_0_[5]\,
I4 => \left_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[5]\,
I1 => \left_reg_n_0_[5]\,
I2 => \top_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[4]\,
I1 => \left_reg_n_0_[4]\,
I2 => \top_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[7]\,
I1 => \left_reg_n_0_[7]\,
I2 => \top_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(5),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => \corner_reg_n_0_[4]\,
I3 => \top_reg_n_0_[4]\,
I4 => \left_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(4),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => \corner_reg_n_0_[3]\,
I3 => \top_reg_n_0_[3]\,
I4 => \left_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(3),
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => \corner_reg_n_0_[2]\,
I3 => \top_reg_n_0_[2]\,
I4 => \left_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => last_value(7),
I3 => \left_reg_n_0_[6]\,
I4 => \top_reg_n_0_[6]\,
I5 => \corner_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => last_value(6),
I3 => \left_reg_n_0_[5]\,
I4 => \top_reg_n_0_[5]\,
I5 => \corner_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => last_value(5),
I3 => \left_reg_n_0_[4]\,
I4 => \top_reg_n_0_[4]\,
I5 => \corner_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => last_value(4),
I3 => \left_reg_n_0_[3]\,
I4 => \top_reg_n_0_[3]\,
I5 => \corner_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[6]\,
I1 => \left_reg_n_0_[6]\,
I2 => \top_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__1_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__1_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(11 downto 8),
S(3) => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \corner_reg_n_0_[10]\,
I3 => \corner_reg_n_0_[9]\,
I4 => \top_reg_n_0_[9]\,
I5 => \left_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \top_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \top_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \top_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \corner_reg_n_0_[9]\,
I3 => \corner_reg_n_0_[8]\,
I4 => \top_reg_n_0_[8]\,
I5 => \left_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \corner_reg_n_0_[8]\,
I3 => \corner_reg_n_0_[7]\,
I4 => \top_reg_n_0_[7]\,
I5 => \left_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(7),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => \corner_reg_n_0_[6]\,
I3 => \top_reg_n_0_[6]\,
I4 => \left_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\,
I2 => \left_reg_n_0_[10]\,
I3 => \top_reg_n_0_[10]\,
I4 => \corner_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\,
I2 => \left_reg_n_0_[9]\,
I3 => \top_reg_n_0_[9]\,
I4 => \corner_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\,
I2 => \left_reg_n_0_[8]\,
I3 => \top_reg_n_0_[8]\,
I4 => \corner_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\,
I2 => \left_reg_n_0_[7]\,
I3 => \top_reg_n_0_[7]\,
I4 => \corner_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \top_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(3) => \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_2_bottom_right0__0_carry__2_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__2_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(15 downto 12),
S(3) => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
I3 => \corner_reg_n_0_[12]\,
I4 => \top_reg_n_0_[12]\,
I5 => \left_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \left_reg_n_0_[14]\,
I2 => \top_reg_n_0_[14]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \top_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \top_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \corner_reg_n_0_[12]\,
I3 => \corner_reg_n_0_[11]\,
I4 => \top_reg_n_0_[11]\,
I5 => \left_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \corner_reg_n_0_[11]\,
I3 => \corner_reg_n_0_[10]\,
I4 => \top_reg_n_0_[10]\,
I5 => \left_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D2882"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\,
I1 => \corner_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[14]\,
I4 => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\,
O => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\,
I2 => \left_reg_n_0_[13]\,
I3 => \top_reg_n_0_[13]\,
I4 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\,
I2 => \left_reg_n_0_[12]\,
I3 => \top_reg_n_0_[12]\,
I4 => \corner_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\,
I2 => \left_reg_n_0_[11]\,
I3 => \top_reg_n_0_[11]\,
I4 => \corner_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \left_reg_n_0_[13]\,
I1 => \top_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"D42B2BD42BD4D42B"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \top_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[15]\,
I4 => \left_reg_n_0_[15]\,
I5 => \corner_reg_n_0_[15]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(2),
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => \corner_reg_n_0_[1]\,
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[3]\,
I1 => \left_reg_n_0_[3]\,
I2 => \top_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \top_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"20BABA20BA2020BA"
)
port map (
I0 => last_value(1),
I1 => \corner_reg_n_0_[0]\,
I2 => last_value(0),
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669966969969669"
)
port map (
I0 => \top_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \corner_reg_n_0_[1]\,
I3 => last_value(1),
I4 => last_value(0),
I5 => \corner_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => last_value(3),
I3 => \left_reg_n_0_[2]\,
I4 => \top_reg_n_0_[2]\,
I5 => \corner_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => last_value(2),
I3 => \left_reg_n_0_[1]\,
I4 => \top_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB44B4BB4"
)
port map (
I0 => \corner_reg_n_0_[0]\,
I1 => last_value(0),
I2 => last_value(1),
I3 => \Lyy_2_bottom_right0__0_carry_i_11_n_0\,
I4 => \left_reg_n_0_[0]\,
I5 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
I2 => \corner_reg_n_0_[0]\,
I3 => last_value(0),
O => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[2]\,
I1 => \left_reg_n_0_[2]\,
I2 => \top_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_9_n_0\
);
\Lyy_2_bottom_right[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => y5
);
\Lyy_2_bottom_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(0),
Q => Lyy_2_bottom_right(0),
R => '0'
);
\Lyy_2_bottom_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(10),
Q => Lyy_2_bottom_right(10),
R => '0'
);
\Lyy_2_bottom_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(11),
Q => Lyy_2_bottom_right(11),
R => '0'
);
\Lyy_2_bottom_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(12),
Q => Lyy_2_bottom_right(12),
R => '0'
);
\Lyy_2_bottom_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(13),
Q => Lyy_2_bottom_right(13),
R => '0'
);
\Lyy_2_bottom_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(14),
Q => Lyy_2_bottom_right(14),
R => '0'
);
\Lyy_2_bottom_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(15),
Q => Lyy_2_bottom_right(15),
R => '0'
);
\Lyy_2_bottom_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(1),
Q => Lyy_2_bottom_right(1),
R => '0'
);
\Lyy_2_bottom_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(2),
Q => Lyy_2_bottom_right(2),
R => '0'
);
\Lyy_2_bottom_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(3),
Q => Lyy_2_bottom_right(3),
R => '0'
);
\Lyy_2_bottom_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(4),
Q => Lyy_2_bottom_right(4),
R => '0'
);
\Lyy_2_bottom_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(5),
Q => Lyy_2_bottom_right(5),
R => '0'
);
\Lyy_2_bottom_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(6),
Q => Lyy_2_bottom_right(6),
R => '0'
);
\Lyy_2_bottom_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(7),
Q => Lyy_2_bottom_right(7),
R => '0'
);
\Lyy_2_bottom_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(8),
Q => Lyy_2_bottom_right(8),
R => '0'
);
\Lyy_2_bottom_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(9),
Q => Lyy_2_bottom_right(9),
R => '0'
);
\Lyy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(0),
Q => \Lyy_2_reg_n_0_[0]\,
R => '0'
);
\Lyy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(10),
Q => \Lyy_2_reg_n_0_[10]\,
R => '0'
);
\Lyy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(11),
Q => \Lyy_2_reg_n_0_[11]\,
R => '0'
);
\Lyy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(12),
Q => \Lyy_2_reg_n_0_[12]\,
R => '0'
);
\Lyy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(13),
Q => \Lyy_2_reg_n_0_[13]\,
R => '0'
);
\Lyy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(14),
Q => \Lyy_2_reg_n_0_[14]\,
R => '0'
);
\Lyy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(15),
Q => \Lyy_2_reg_n_0_[15]\,
R => '0'
);
\Lyy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(1),
Q => \Lyy_2_reg_n_0_[1]\,
R => '0'
);
\Lyy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(2),
Q => \Lyy_2_reg_n_0_[2]\,
R => '0'
);
\Lyy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(3),
Q => \Lyy_2_reg_n_0_[3]\,
R => '0'
);
\Lyy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(4),
Q => \Lyy_2_reg_n_0_[4]\,
R => '0'
);
\Lyy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(5),
Q => \Lyy_2_reg_n_0_[5]\,
R => '0'
);
\Lyy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(6),
Q => \Lyy_2_reg_n_0_[6]\,
R => '0'
);
\Lyy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(7),
Q => \Lyy_2_reg_n_0_[7]\,
R => '0'
);
\Lyy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(8),
Q => \Lyy_2_reg_n_0_[8]\,
R => '0'
);
\Lyy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(9),
Q => \Lyy_2_reg_n_0_[9]\,
R => '0'
);
\Lyy_2_top_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(0),
Q => Lyy_2_top_left(0),
R => '0'
);
\Lyy_2_top_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(10),
Q => Lyy_2_top_left(10),
R => '0'
);
\Lyy_2_top_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(11),
Q => Lyy_2_top_left(11),
R => '0'
);
\Lyy_2_top_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(12),
Q => Lyy_2_top_left(12),
R => '0'
);
\Lyy_2_top_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(13),
Q => Lyy_2_top_left(13),
R => '0'
);
\Lyy_2_top_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(14),
Q => Lyy_2_top_left(14),
R => '0'
);
\Lyy_2_top_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(15),
Q => Lyy_2_top_left(15),
R => '0'
);
\Lyy_2_top_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(1),
Q => Lyy_2_top_left(1),
R => '0'
);
\Lyy_2_top_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(2),
Q => Lyy_2_top_left(2),
R => '0'
);
\Lyy_2_top_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(3),
Q => Lyy_2_top_left(3),
R => '0'
);
\Lyy_2_top_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(4),
Q => Lyy_2_top_left(4),
R => '0'
);
\Lyy_2_top_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(5),
Q => Lyy_2_top_left(5),
R => '0'
);
\Lyy_2_top_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(6),
Q => Lyy_2_top_left(6),
R => '0'
);
\Lyy_2_top_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(7),
Q => Lyy_2_top_left(7),
R => '0'
);
\Lyy_2_top_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(8),
Q => Lyy_2_top_left(8),
R => '0'
);
\Lyy_2_top_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(9),
Q => Lyy_2_top_left(9),
R => '0'
);
\Lyy_2_top_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[0]\,
Q => Lyy_2_top_right(0),
R => '0'
);
\Lyy_2_top_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[10]\,
Q => Lyy_2_top_right(10),
R => '0'
);
\Lyy_2_top_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[11]\,
Q => Lyy_2_top_right(11),
R => '0'
);
\Lyy_2_top_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[12]\,
Q => Lyy_2_top_right(12),
R => '0'
);
\Lyy_2_top_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[13]\,
Q => Lyy_2_top_right(13),
R => '0'
);
\Lyy_2_top_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[14]\,
Q => Lyy_2_top_right(14),
R => '0'
);
\Lyy_2_top_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[15]\,
Q => Lyy_2_top_right(15),
R => '0'
);
\Lyy_2_top_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[1]\,
Q => Lyy_2_top_right(1),
R => '0'
);
\Lyy_2_top_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[2]\,
Q => Lyy_2_top_right(2),
R => '0'
);
\Lyy_2_top_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[3]\,
Q => Lyy_2_top_right(3),
R => '0'
);
\Lyy_2_top_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[4]\,
Q => Lyy_2_top_right(4),
R => '0'
);
\Lyy_2_top_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[5]\,
Q => Lyy_2_top_right(5),
R => '0'
);
\Lyy_2_top_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[6]\,
Q => Lyy_2_top_right(6),
R => '0'
);
\Lyy_2_top_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[7]\,
Q => Lyy_2_top_right(7),
R => '0'
);
\Lyy_2_top_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[8]\,
Q => Lyy_2_top_right(8),
R => '0'
);
\Lyy_2_top_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[9]\,
Q => Lyy_2_top_right(9),
R => '0'
);
\addr_0[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[0]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[0]\,
O => \addr_0[0]_i_1_n_0\
);
\addr_0[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[10]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[10]\,
O => \addr_0[10]_i_1_n_0\
);
\addr_0[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[11]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[11]\,
O => \addr_0[11]_i_1_n_0\
);
\addr_0[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[12]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[12]\,
O => \addr_0[12]_i_1_n_0\
);
\addr_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => addr_0
);
\addr_0[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[13]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[13]\,
O => \addr_0[13]_i_2_n_0\
);
\addr_0[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[1]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[1]\,
O => \addr_0[1]_i_1_n_0\
);
\addr_0[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[2]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[2]\,
O => \addr_0[2]_i_1_n_0\
);
\addr_0[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[3]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[3]\,
O => \addr_0[3]_i_1_n_0\
);
\addr_0[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[4]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[4]\,
O => \addr_0[4]_i_1_n_0\
);
\addr_0[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[5]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[5]\,
O => \addr_0[5]_i_1_n_0\
);
\addr_0[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[6]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[6]\,
O => \addr_0[6]_i_1_n_0\
);
\addr_0[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[7]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[7]\,
O => \addr_0[7]_i_1_n_0\
);
\addr_0[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[8]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[8]\,
O => \addr_0[8]_i_1_n_0\
);
\addr_0[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[9]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[9]\,
O => \addr_0[9]_i_1_n_0\
);
\addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[0]_i_1_n_0\,
Q => \addr_0_reg_n_0_[0]\,
R => '0'
);
\addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[10]_i_1_n_0\,
Q => \addr_0_reg_n_0_[10]\,
R => '0'
);
\addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[11]_i_1_n_0\,
Q => \addr_0_reg_n_0_[11]\,
R => '0'
);
\addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[12]_i_1_n_0\,
Q => \addr_0_reg_n_0_[12]\,
R => '0'
);
\addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[13]_i_2_n_0\,
Q => \addr_0_reg_n_0_[13]\,
R => '0'
);
\addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[1]_i_1_n_0\,
Q => \addr_0_reg_n_0_[1]\,
R => '0'
);
\addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[2]_i_1_n_0\,
Q => \addr_0_reg_n_0_[2]\,
R => '0'
);
\addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[3]_i_1_n_0\,
Q => \addr_0_reg_n_0_[3]\,
R => '0'
);
\addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[4]_i_1_n_0\,
Q => \addr_0_reg_n_0_[4]\,
R => '0'
);
\addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[5]_i_1_n_0\,
Q => \addr_0_reg_n_0_[5]\,
R => '0'
);
\addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[6]_i_1_n_0\,
Q => \addr_0_reg_n_0_[6]\,
R => '0'
);
\addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[7]_i_1_n_0\,
Q => \addr_0_reg_n_0_[7]\,
R => '0'
);
\addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[8]_i_1_n_0\,
Q => \addr_0_reg_n_0_[8]\,
R => '0'
);
\addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[9]_i_1_n_0\,
Q => \addr_0_reg_n_0_[9]\,
R => '0'
);
\addr_1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(0),
O => \addr_1[0]_i_1_n_0\
);
\addr_1[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(10),
O => \addr_1[10]_i_1_n_0\
);
\addr_1[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(11),
O => \addr_1[11]_i_1_n_0\
);
\addr_1[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(12),
O => \addr_1[12]_i_1_n_0\
);
\addr_1[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(13),
O => \addr_1[13]_i_1_n_0\
);
\addr_1[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(1),
O => \addr_1[1]_i_1_n_0\
);
\addr_1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(2),
O => \addr_1[2]_i_1_n_0\
);
\addr_1[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(3),
O => \addr_1[3]_i_1_n_0\
);
\addr_1[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(4),
O => \addr_1[4]_i_1_n_0\
);
\addr_1[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(5),
O => \addr_1[5]_i_1_n_0\
);
\addr_1[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(6),
O => \addr_1[6]_i_1_n_0\
);
\addr_1[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(7),
O => \addr_1[7]_i_1_n_0\
);
\addr_1[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(8),
O => \addr_1[8]_i_1_n_0\
);
\addr_1[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(9),
O => \addr_1[9]_i_1_n_0\
);
\addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[0]_i_1_n_0\,
Q => addr_1(0),
R => '0'
);
\addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[10]_i_1_n_0\,
Q => addr_1(10),
R => '0'
);
\addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[11]_i_1_n_0\,
Q => addr_1(11),
R => '0'
);
\addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[12]_i_1_n_0\,
Q => addr_1(12),
R => '0'
);
\addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[13]_i_1_n_0\,
Q => addr_1(13),
R => '0'
);
\addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[1]_i_1_n_0\,
Q => addr_1(1),
R => '0'
);
\addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[2]_i_1_n_0\,
Q => addr_1(2),
R => '0'
);
\addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[3]_i_1_n_0\,
Q => addr_1(3),
R => '0'
);
\addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[4]_i_1_n_0\,
Q => addr_1(4),
R => '0'
);
\addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[5]_i_1_n_0\,
Q => addr_1(5),
R => '0'
);
\addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[6]_i_1_n_0\,
Q => addr_1(6),
R => '0'
);
\addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[7]_i_1_n_0\,
Q => addr_1(7),
R => '0'
);
\addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[8]_i_1_n_0\,
Q => addr_1(8),
R => '0'
);
\addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[9]_i_1_n_0\,
Q => addr_1(9),
R => '0'
);
\bottom_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8800880000000800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[1]_rep_n_0\,
O => bottom_left_0
);
\bottom_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(0),
Q => \bottom_left_0_reg_n_0_[0]\,
R => '0'
);
\bottom_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(10),
Q => \bottom_left_0_reg_n_0_[10]\,
R => '0'
);
\bottom_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(11),
Q => \bottom_left_0_reg_n_0_[11]\,
R => '0'
);
\bottom_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(12),
Q => \bottom_left_0_reg_n_0_[12]\,
R => '0'
);
\bottom_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(13),
Q => \bottom_left_0_reg_n_0_[13]\,
R => '0'
);
\bottom_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(14),
Q => \bottom_left_0_reg_n_0_[14]\,
R => '0'
);
\bottom_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(15),
Q => \bottom_left_0_reg_n_0_[15]\,
R => '0'
);
\bottom_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(1),
Q => \bottom_left_0_reg_n_0_[1]\,
R => '0'
);
\bottom_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(2),
Q => \bottom_left_0_reg_n_0_[2]\,
R => '0'
);
\bottom_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(3),
Q => \bottom_left_0_reg_n_0_[3]\,
R => '0'
);
\bottom_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(4),
Q => \bottom_left_0_reg_n_0_[4]\,
R => '0'
);
\bottom_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(5),
Q => \bottom_left_0_reg_n_0_[5]\,
R => '0'
);
\bottom_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(6),
Q => \bottom_left_0_reg_n_0_[6]\,
R => '0'
);
\bottom_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(7),
Q => \bottom_left_0_reg_n_0_[7]\,
R => '0'
);
\bottom_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(8),
Q => \bottom_left_0_reg_n_0_[8]\,
R => '0'
);
\bottom_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(9),
Q => \bottom_left_0_reg_n_0_[9]\,
R => '0'
);
\bottom_left_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000040"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
O => top_right_1
);
\bottom_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(0),
Q => bottom_left_1(0),
R => '0'
);
\bottom_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(10),
Q => bottom_left_1(10),
R => '0'
);
\bottom_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(11),
Q => bottom_left_1(11),
R => '0'
);
\bottom_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(12),
Q => bottom_left_1(12),
R => '0'
);
\bottom_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(13),
Q => bottom_left_1(13),
R => '0'
);
\bottom_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(14),
Q => bottom_left_1(14),
R => '0'
);
\bottom_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(15),
Q => bottom_left_1(15),
R => '0'
);
\bottom_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(1),
Q => bottom_left_1(1),
R => '0'
);
\bottom_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(2),
Q => bottom_left_1(2),
R => '0'
);
\bottom_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(3),
Q => bottom_left_1(3),
R => '0'
);
\bottom_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(4),
Q => bottom_left_1(4),
R => '0'
);
\bottom_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(5),
Q => bottom_left_1(5),
R => '0'
);
\bottom_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(6),
Q => bottom_left_1(6),
R => '0'
);
\bottom_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(7),
Q => bottom_left_1(7),
R => '0'
);
\bottom_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(8),
Q => bottom_left_1(8),
R => '0'
);
\bottom_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(9),
Q => bottom_left_1(9),
R => '0'
);
\bottom_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[0]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(0),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(0),
O => p_0_out(0)
);
\bottom_right_0[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(0),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[0]_i_2_n_0\
);
\bottom_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[10]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(10),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(10),
O => p_0_out(10)
);
\bottom_right_0[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(10),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(10),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[10]_i_2_n_0\
);
\bottom_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[11]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(11),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(11),
O => p_0_out(11)
);
\bottom_right_0[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(11),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(11),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[11]_i_2_n_0\
);
\bottom_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[12]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(12),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(12),
O => p_0_out(12)
);
\bottom_right_0[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(12),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(12),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[12]_i_2_n_0\
);
\bottom_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[13]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(13),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(13),
O => p_0_out(13)
);
\bottom_right_0[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(13),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(13),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[13]_i_2_n_0\
);
\bottom_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[14]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(14),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(14),
O => p_0_out(14)
);
\bottom_right_0[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(14),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(14),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[14]_i_2_n_0\
);
\bottom_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"444A000000000000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \bottom_right_0[15]_i_1_n_0\
);
\bottom_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[15]_i_4_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(15),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(15),
O => p_0_out(15)
);
\bottom_right_0[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(2),
O => \bottom_right_0[15]_i_3_n_0\
);
\bottom_right_0[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(15),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(15),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[15]_i_4_n_0\
);
\bottom_right_0[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(0),
O => \bottom_right_0[15]_i_5_n_0\
);
\bottom_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[1]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(1),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(1),
O => p_0_out(1)
);
\bottom_right_0[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(1),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[1]_i_2_n_0\
);
\bottom_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[2]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(2),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(2),
O => p_0_out(2)
);
\bottom_right_0[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(2),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[2]_i_2_n_0\
);
\bottom_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[3]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(3),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(3),
O => p_0_out(3)
);
\bottom_right_0[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(3),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[3]_i_2_n_0\
);
\bottom_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[4]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(4),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(4),
O => p_0_out(4)
);
\bottom_right_0[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(4),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[4]_i_2_n_0\
);
\bottom_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[5]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(5),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(5),
O => p_0_out(5)
);
\bottom_right_0[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(5),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[5]_i_2_n_0\
);
\bottom_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[6]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(6),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(6),
O => p_0_out(6)
);
\bottom_right_0[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(6),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[6]_i_2_n_0\
);
\bottom_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[7]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(7),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(7),
O => p_0_out(7)
);
\bottom_right_0[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(7),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[7]_i_2_n_0\
);
\bottom_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[8]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(8),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(8),
O => p_0_out(8)
);
\bottom_right_0[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(8),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[8]_i_2_n_0\
);
\bottom_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[9]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(9),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(9),
O => p_0_out(9)
);
\bottom_right_0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(9),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[9]_i_2_n_0\
);
\bottom_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(0),
Q => \bottom_right_0_reg_n_0_[0]\,
R => '0'
);
\bottom_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(10),
Q => \bottom_right_0_reg_n_0_[10]\,
R => '0'
);
\bottom_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(11),
Q => \bottom_right_0_reg_n_0_[11]\,
R => '0'
);
\bottom_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(12),
Q => \bottom_right_0_reg_n_0_[12]\,
R => '0'
);
\bottom_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(13),
Q => \bottom_right_0_reg_n_0_[13]\,
R => '0'
);
\bottom_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(14),
Q => \bottom_right_0_reg_n_0_[14]\,
R => '0'
);
\bottom_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(15),
Q => \bottom_right_0_reg_n_0_[15]\,
R => '0'
);
\bottom_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(1),
Q => \bottom_right_0_reg_n_0_[1]\,
R => '0'
);
\bottom_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(2),
Q => \bottom_right_0_reg_n_0_[2]\,
R => '0'
);
\bottom_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(3),
Q => \bottom_right_0_reg_n_0_[3]\,
R => '0'
);
\bottom_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(4),
Q => \bottom_right_0_reg_n_0_[4]\,
R => '0'
);
\bottom_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(5),
Q => \bottom_right_0_reg_n_0_[5]\,
R => '0'
);
\bottom_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(6),
Q => \bottom_right_0_reg_n_0_[6]\,
R => '0'
);
\bottom_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(7),
Q => \bottom_right_0_reg_n_0_[7]\,
R => '0'
);
\bottom_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(8),
Q => \bottom_right_0_reg_n_0_[8]\,
R => '0'
);
\bottom_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(9),
Q => \bottom_right_0_reg_n_0_[9]\,
R => '0'
);
\bottom_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[0]\,
O => \bottom_right_1[0]_i_1_n_0\
);
\bottom_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(10),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \bottom_right_1[10]_i_1_n_0\
);
\bottom_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(11),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \bottom_right_1[11]_i_1_n_0\
);
\bottom_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(12),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \bottom_right_1[12]_i_1_n_0\
);
\bottom_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(13),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[13]\,
O => \bottom_right_1[13]_i_1_n_0\
);
\bottom_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(14),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[14]\,
O => \bottom_right_1[14]_i_1_n_0\
);
\bottom_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(15),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[15]\,
O => \bottom_right_1[15]_i_1_n_0\
);
\bottom_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(1),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[1]\,
O => \bottom_right_1[1]_i_1_n_0\
);
\bottom_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(2),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \bottom_right_1[2]_i_1_n_0\
);
\bottom_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(3),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \bottom_right_1[3]_i_1_n_0\
);
\bottom_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(4),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \bottom_right_1[4]_i_1_n_0\
);
\bottom_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(5),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \bottom_right_1[5]_i_1_n_0\
);
\bottom_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(6),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \bottom_right_1[6]_i_1_n_0\
);
\bottom_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(7),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \bottom_right_1[7]_i_1_n_0\
);
\bottom_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \bottom_right_1[8]_i_1_n_0\
);
\bottom_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(9),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \bottom_right_1[9]_i_1_n_0\
);
\bottom_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[0]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[0]\,
R => '0'
);
\bottom_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[10]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[10]\,
R => '0'
);
\bottom_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[11]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[11]\,
R => '0'
);
\bottom_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[12]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[12]\,
R => '0'
);
\bottom_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[13]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[13]\,
R => '0'
);
\bottom_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[14]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[14]\,
R => '0'
);
\bottom_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[15]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[15]\,
R => '0'
);
\bottom_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[1]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[1]\,
R => '0'
);
\bottom_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[2]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[2]\,
R => '0'
);
\bottom_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[3]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[3]\,
R => '0'
);
\bottom_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[4]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[4]\,
R => '0'
);
\bottom_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[5]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[5]\,
R => '0'
);
\bottom_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[6]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[6]\,
R => '0'
);
\bottom_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[7]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[7]\,
R => '0'
);
\bottom_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[8]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[8]\,
R => '0'
);
\bottom_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[9]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[9]\,
R => '0'
);
bram_0: entity work.system_vga_hessian_0_0_blk_mem_gen_0
port map (
addra(13) => \addr_0_reg_n_0_[13]\,
addra(12) => \addr_0_reg_n_0_[12]\,
addra(11) => \addr_0_reg_n_0_[11]\,
addra(10) => \addr_0_reg_n_0_[10]\,
addra(9) => \addr_0_reg_n_0_[9]\,
addra(8) => \addr_0_reg_n_0_[8]\,
addra(7) => \addr_0_reg_n_0_[7]\,
addra(6) => \addr_0_reg_n_0_[6]\,
addra(5) => \addr_0_reg_n_0_[5]\,
addra(4) => \addr_0_reg_n_0_[4]\,
addra(3) => \addr_0_reg_n_0_[3]\,
addra(2) => \addr_0_reg_n_0_[2]\,
addra(1) => \addr_0_reg_n_0_[1]\,
addra(0) => \addr_0_reg_n_0_[0]\,
addrb(13 downto 0) => addr_1(13 downto 0),
clka => clk_x16,
clkb => clk_x16,
dina(15) => \din_reg_n_0_[15]\,
dina(14) => \din_reg_n_0_[14]\,
dina(13) => \din_reg_n_0_[13]\,
dina(12) => \din_reg_n_0_[12]\,
dina(11) => \din_reg_n_0_[11]\,
dina(10) => \din_reg_n_0_[10]\,
dina(9) => \din_reg_n_0_[9]\,
dina(8) => \din_reg_n_0_[8]\,
dina(7) => \din_reg_n_0_[7]\,
dina(6) => \din_reg_n_0_[6]\,
dina(5) => \din_reg_n_0_[5]\,
dina(4) => \din_reg_n_0_[4]\,
dina(3) => \din_reg_n_0_[3]\,
dina(2) => \din_reg_n_0_[2]\,
dina(1) => \din_reg_n_0_[1]\,
dina(0) => \din_reg_n_0_[0]\,
dinb(15 downto 0) => B"0000000000000000",
douta(15 downto 0) => dout_0(15 downto 0),
doutb(15 downto 0) => dout_1(15 downto 0),
ena => '1',
enb => '1',
wea(0) => wen_reg_n_0,
web(0) => '0'
);
\cache[9][15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => \cache[9][15]_i_1_n_0\
);
\cache[9][15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => active,
I1 => cycle(2),
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => \cycle_reg[0]_rep_n_0\,
O => \cache[10]_5\
);
\cache_reg[0][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(0),
Q => \cache_reg[0]_4\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(10),
Q => \cache_reg[0]_4\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(11),
Q => \cache_reg[0]_4\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(12),
Q => \cache_reg[0]_4\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(13),
Q => \cache_reg[0]_4\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(14),
Q => \cache_reg[0]_4\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(15),
Q => \cache_reg[0]_4\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(1),
Q => \cache_reg[0]_4\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(2),
Q => \cache_reg[0]_4\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(3),
Q => \cache_reg[0]_4\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(4),
Q => \cache_reg[0]_4\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(5),
Q => \cache_reg[0]_4\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(6),
Q => \cache_reg[0]_4\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(7),
Q => \cache_reg[0]_4\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(8),
Q => \cache_reg[0]_4\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(9),
Q => \cache_reg[0]_4\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(0),
Q => \cache_reg[10]_3\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(10),
Q => \cache_reg[10]_3\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(11),
Q => \cache_reg[10]_3\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(12),
Q => \cache_reg[10]_3\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(13),
Q => \cache_reg[10]_3\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(14),
Q => \cache_reg[10]_3\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(15),
Q => \cache_reg[10]_3\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(1),
Q => \cache_reg[10]_3\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(2),
Q => \cache_reg[10]_3\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(3),
Q => \cache_reg[10]_3\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(4),
Q => \cache_reg[10]_3\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(5),
Q => \cache_reg[10]_3\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(6),
Q => \cache_reg[10]_3\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(7),
Q => \cache_reg[10]_3\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(8),
Q => \cache_reg[10]_3\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(9),
Q => \cache_reg[10]_3\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[2][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(0),
Q => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(10),
Q => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(11),
Q => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(12),
Q => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(13),
Q => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(14),
Q => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(15),
Q => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(1),
Q => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(2),
Q => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(3),
Q => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(4),
Q => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(5),
Q => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(6),
Q => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(7),
Q => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(8),
Q => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(9),
Q => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[3][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[4][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__14_n_0\,
Q => \cache_reg[4]_0\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__4_n_0\,
Q => \cache_reg[4]_0\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__3_n_0\,
Q => \cache_reg[4]_0\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__2_n_0\,
Q => \cache_reg[4]_0\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__1_n_0\,
Q => \cache_reg[4]_0\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__0_n_0\,
Q => \cache_reg[4]_0\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_gate_n_0,
Q => \cache_reg[4]_0\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__13_n_0\,
Q => \cache_reg[4]_0\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__12_n_0\,
Q => \cache_reg[4]_0\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__11_n_0\,
Q => \cache_reg[4]_0\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__10_n_0\,
Q => \cache_reg[4]_0\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__9_n_0\,
Q => \cache_reg[4]_0\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__8_n_0\,
Q => \cache_reg[4]_0\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__7_n_0\,
Q => \cache_reg[4]_0\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__6_n_0\,
Q => \cache_reg[4]_0\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__5_n_0\,
Q => \cache_reg[4]_0\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[6][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(0),
Q => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(10),
Q => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(11),
Q => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(12),
Q => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(13),
Q => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(14),
Q => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(15),
Q => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(1),
Q => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(2),
Q => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(3),
Q => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(4),
Q => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(5),
Q => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(6),
Q => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(7),
Q => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(8),
Q => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(9),
Q => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[7][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__30_n_0\,
Q => \cache_reg[8]_1\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__20_n_0\,
Q => \cache_reg[8]_1\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__19_n_0\,
Q => \cache_reg[8]_1\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__18_n_0\,
Q => \cache_reg[8]_1\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__17_n_0\,
Q => \cache_reg[8]_1\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__16_n_0\,
Q => \cache_reg[8]_1\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__15_n_0\,
Q => \cache_reg[8]_1\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__29_n_0\,
Q => \cache_reg[8]_1\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__28_n_0\,
Q => \cache_reg[8]_1\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__27_n_0\,
Q => \cache_reg[8]_1\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__26_n_0\,
Q => \cache_reg[8]_1\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__25_n_0\,
Q => \cache_reg[8]_1\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__24_n_0\,
Q => \cache_reg[8]_1\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__23_n_0\,
Q => \cache_reg[8]_1\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__22_n_0\,
Q => \cache_reg[8]_1\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__21_n_0\,
Q => \cache_reg[8]_1\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(0),
Q => \cache_reg[9]_2\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(10),
Q => \cache_reg[9]_2\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(11),
Q => \cache_reg[9]_2\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(12),
Q => \cache_reg[9]_2\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(13),
Q => \cache_reg[9]_2\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(14),
Q => \cache_reg[9]_2\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(15),
Q => \cache_reg[9]_2\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(1),
Q => \cache_reg[9]_2\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(2),
Q => \cache_reg[9]_2\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(3),
Q => \cache_reg[9]_2\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(4),
Q => \cache_reg[9]_2\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(5),
Q => \cache_reg[9]_2\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(6),
Q => \cache_reg[9]_2\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(7),
Q => \cache_reg[9]_2\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(8),
Q => \cache_reg[9]_2\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(9),
Q => \cache_reg[9]_2\(9),
R => \cache[9][15]_i_1_n_0\
);
cache_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => cache_reg_gate_n_0
);
\cache_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__0_n_0\
);
\cache_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__1_n_0\
);
\cache_reg_gate__10\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__10_n_0\
);
\cache_reg_gate__11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__11_n_0\
);
\cache_reg_gate__12\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__12_n_0\
);
\cache_reg_gate__13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__13_n_0\
);
\cache_reg_gate__14\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__14_n_0\
);
\cache_reg_gate__15\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__15_n_0\
);
\cache_reg_gate__16\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__16_n_0\
);
\cache_reg_gate__17\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__17_n_0\
);
\cache_reg_gate__18\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__18_n_0\
);
\cache_reg_gate__19\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__19_n_0\
);
\cache_reg_gate__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__2_n_0\
);
\cache_reg_gate__20\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__20_n_0\
);
\cache_reg_gate__21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__21_n_0\
);
\cache_reg_gate__22\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__22_n_0\
);
\cache_reg_gate__23\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__23_n_0\
);
\cache_reg_gate__24\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__24_n_0\
);
\cache_reg_gate__25\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__25_n_0\
);
\cache_reg_gate__26\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__26_n_0\
);
\cache_reg_gate__27\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__27_n_0\
);
\cache_reg_gate__28\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__28_n_0\
);
\cache_reg_gate__29\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__29_n_0\
);
\cache_reg_gate__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__3_n_0\
);
\cache_reg_gate__30\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__30_n_0\
);
\cache_reg_gate__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__4_n_0\
);
\cache_reg_gate__5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__5_n_0\
);
\cache_reg_gate__6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__6_n_0\
);
\cache_reg_gate__7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__7_n_0\
);
\cache_reg_gate__8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__8_n_0\
);
\cache_reg_gate__9\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__9_n_0\
);
cache_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => '1',
Q => cache_reg_r_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_n_0,
Q => cache_reg_r_0_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_0_n_0,
Q => cache_reg_r_1_n_0,
R => \cache[9][15]_i_1_n_0\
);
\compute_addr_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(0),
O => \compute_addr_0[0]_i_1_n_0\
);
\compute_addr_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[10]_i_2_n_0\,
O => \compute_addr_0[10]_i_1_n_0\
);
\compute_addr_0[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[0]\,
I1 => data5(10),
I2 => cycle(3),
I3 => \y1_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[10]_i_2_n_0\
);
\compute_addr_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDCDC88888"
)
port map (
I0 => cycle(0),
I1 => data5(11),
I2 => cycle(3),
I3 => \y1_reg_n_0_[1]\,
I4 => \compute_addr_0[11]_i_2_n_0\,
I5 => \compute_addr_0[11]_i_3_n_0\,
O => \compute_addr_0[11]_i_1_n_0\
);
\compute_addr_0[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_2_n_0\
);
\compute_addr_0[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAAAAAACFC0"
)
port map (
I0 => \compute_addr_2[11]_i_2_n_0\,
I1 => \y1_reg_n_0_[1]\,
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_3_n_0\
);
\compute_addr_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[12]_i_2_n_0\,
O => \compute_addr_0[12]_i_1_n_0\
);
\compute_addr_0[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[2]\,
I1 => data5(12),
I2 => cycle(3),
I3 => \y1_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[12]_i_2_n_0\
);
\compute_addr_0[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(0),
O => compute_addr_0
);
\compute_addr_0[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[13]_i_3_n_0\,
O => \compute_addr_0[13]_i_2_n_0\
);
\compute_addr_0[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => \y1_reg_n_0_[3]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[13]_i_3_n_0\
);
\compute_addr_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(1),
O => \compute_addr_0[1]_i_1_n_0\
);
\compute_addr_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \compute_addr_0[2]_i_1_n_0\
);
\compute_addr_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(3),
O => \compute_addr_0[3]_i_1_n_0\
);
\compute_addr_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(4),
O => \compute_addr_0[4]_i_1_n_0\
);
\compute_addr_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(5),
O => \compute_addr_0[5]_i_1_n_0\
);
\compute_addr_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(6),
O => \compute_addr_0[6]_i_1_n_0\
);
\compute_addr_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \compute_addr_0[7]_i_1_n_0\
);
\compute_addr_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(8),
O => \compute_addr_0[8]_i_1_n_0\
);
\compute_addr_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data1(9),
O => \compute_addr_0[9]_i_1_n_0\
);
\compute_addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[0]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[0]\,
R => '0'
);
\compute_addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[10]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[10]\,
R => '0'
);
\compute_addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[11]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[11]\,
R => '0'
);
\compute_addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[12]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[12]\,
R => '0'
);
\compute_addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[13]_i_2_n_0\,
Q => \compute_addr_0_reg_n_0_[13]\,
R => '0'
);
\compute_addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[1]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[1]\,
R => '0'
);
\compute_addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[2]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[2]\,
R => '0'
);
\compute_addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[3]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[3]\,
R => '0'
);
\compute_addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[4]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[4]\,
R => '0'
);
\compute_addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[5]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[5]\,
R => '0'
);
\compute_addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[6]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[6]\,
R => '0'
);
\compute_addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[7]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[7]\,
R => '0'
);
\compute_addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[8]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[8]\,
R => '0'
);
\compute_addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[9]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[9]\,
R => '0'
);
\compute_addr_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(0),
O => \compute_addr_1[0]_i_1_n_0\
);
\compute_addr_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[10]_i_2_n_0\,
O => \compute_addr_1[10]_i_1_n_0\
);
\compute_addr_1[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(10),
I1 => data2(10),
I2 => cycle(3),
I3 => \y3_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[10]_i_2_n_0\
);
\compute_addr_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(11),
I1 => cycle(0),
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[11]_i_2_n_0\,
O => \compute_addr_1[11]_i_1_n_0\
);
\compute_addr_1[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(11),
I1 => data2(11),
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[11]_i_2_n_0\
);
\compute_addr_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[12]_i_2_n_0\,
O => \compute_addr_1[12]_i_1_n_0\
);
\compute_addr_1[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(12),
I1 => data2(12),
I2 => cycle(3),
I3 => \y3_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[12]_i_2_n_0\
);
\compute_addr_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[13]_i_2_n_0\,
O => \compute_addr_1[13]_i_1_n_0\
);
\compute_addr_1[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => data2(13),
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[13]_i_2_n_0\
);
\compute_addr_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(1),
O => \compute_addr_1[1]_i_1_n_0\
);
\compute_addr_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(2),
O => \compute_addr_1[2]_i_1_n_0\
);
\compute_addr_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(3),
O => \compute_addr_1[3]_i_1_n_0\
);
\compute_addr_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(4),
O => \compute_addr_1[4]_i_1_n_0\
);
\compute_addr_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(5),
O => \compute_addr_1[5]_i_1_n_0\
);
\compute_addr_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(6),
O => \compute_addr_1[6]_i_1_n_0\
);
\compute_addr_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(7),
O => \compute_addr_1[7]_i_1_n_0\
);
\compute_addr_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(8),
O => \compute_addr_1[8]_i_1_n_0\
);
\compute_addr_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(9),
O => \compute_addr_1[9]_i_1_n_0\
);
\compute_addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[0]_i_1_n_0\,
Q => compute_addr_1(0),
R => '0'
);
\compute_addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[10]_i_1_n_0\,
Q => compute_addr_1(10),
R => '0'
);
\compute_addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[11]_i_1_n_0\,
Q => compute_addr_1(11),
R => '0'
);
\compute_addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[12]_i_1_n_0\,
Q => compute_addr_1(12),
R => '0'
);
\compute_addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[13]_i_1_n_0\,
Q => compute_addr_1(13),
R => '0'
);
\compute_addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[1]_i_1_n_0\,
Q => compute_addr_1(1),
R => '0'
);
\compute_addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[2]_i_1_n_0\,
Q => compute_addr_1(2),
R => '0'
);
\compute_addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[3]_i_1_n_0\,
Q => compute_addr_1(3),
R => '0'
);
\compute_addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[4]_i_1_n_0\,
Q => compute_addr_1(4),
R => '0'
);
\compute_addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[5]_i_1_n_0\,
Q => compute_addr_1(5),
R => '0'
);
\compute_addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[6]_i_1_n_0\,
Q => compute_addr_1(6),
R => '0'
);
\compute_addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[7]_i_1_n_0\,
Q => compute_addr_1(7),
R => '0'
);
\compute_addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[8]_i_1_n_0\,
Q => compute_addr_1(8),
R => '0'
);
\compute_addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[9]_i_1_n_0\,
Q => compute_addr_1(9),
R => '0'
);
\compute_addr_2[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[0]\,
O => \compute_addr_2[10]_i_1_n_0\
);
\compute_addr_2[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[0]\,
I1 => cycle(3),
I2 => data1(10),
O => \compute_addr_2[10]_i_2_n_0\
);
\compute_addr_2[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[1]\,
O => \compute_addr_2[11]_i_1_n_0\
);
\compute_addr_2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[1]\,
I1 => cycle(3),
I2 => data1(11),
O => \compute_addr_2[11]_i_2_n_0\
);
\compute_addr_2[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[2]\,
O => \compute_addr_2[12]_i_1_n_0\
);
\compute_addr_2[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[2]\,
I1 => cycle(3),
I2 => data1(12),
O => \compute_addr_2[12]_i_2_n_0\
);
\compute_addr_2[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080808000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => compute_addr_2
);
\compute_addr_2[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[3]\,
O => \compute_addr_2[13]_i_2_n_0\
);
\compute_addr_2[13]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"81FF"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
O => \compute_addr_2[13]_i_3_n_0\
);
\compute_addr_2[13]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[3]\,
I1 => cycle(3),
I2 => data1(13),
O => \compute_addr_2[13]_i_4_n_0\
);
\compute_addr_2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(0),
Q => \compute_addr_2_reg_n_0_[0]\,
R => '0'
);
\compute_addr_2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[10]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[10]\,
R => '0'
);
\compute_addr_2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[11]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[11]\,
R => '0'
);
\compute_addr_2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[12]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[12]\,
R => '0'
);
\compute_addr_2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[13]_i_2_n_0\,
Q => \compute_addr_2_reg_n_0_[13]\,
R => '0'
);
\compute_addr_2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(1),
Q => \compute_addr_2_reg_n_0_[1]\,
R => '0'
);
\compute_addr_2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(2),
Q => \compute_addr_2_reg_n_0_[2]\,
R => '0'
);
\compute_addr_2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(3),
Q => \compute_addr_2_reg_n_0_[3]\,
R => '0'
);
\compute_addr_2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(4),
Q => \compute_addr_2_reg_n_0_[4]\,
R => '0'
);
\compute_addr_2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(5),
Q => \compute_addr_2_reg_n_0_[5]\,
R => '0'
);
\compute_addr_2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(6),
Q => \compute_addr_2_reg_n_0_[6]\,
R => '0'
);
\compute_addr_2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(7),
Q => \compute_addr_2_reg_n_0_[7]\,
R => '0'
);
\compute_addr_2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(8),
Q => \compute_addr_2_reg_n_0_[8]\,
R => '0'
);
\compute_addr_2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(9),
Q => \compute_addr_2_reg_n_0_[9]\,
R => '0'
);
\compute_addr_3[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(0),
O => \compute_addr_3[0]_i_1_n_0\
);
\compute_addr_3[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(10),
O => \compute_addr_3[10]_i_1_n_0\
);
\compute_addr_3[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(0),
I1 => cycle(3),
I2 => y8(0),
O => \compute_addr_3[10]_i_2_n_0\
);
\compute_addr_3[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(11),
O => \compute_addr_3[11]_i_1_n_0\
);
\compute_addr_3[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(1),
I1 => cycle(3),
I2 => y8(1),
O => \compute_addr_3[11]_i_2_n_0\
);
\compute_addr_3[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(12),
O => \compute_addr_3[12]_i_1_n_0\
);
\compute_addr_3[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(2),
I1 => cycle(3),
I2 => y8(2),
O => \compute_addr_3[12]_i_2_n_0\
);
\compute_addr_3[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(13),
O => \compute_addr_3[13]_i_1_n_0\
);
\compute_addr_3[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(3),
I1 => cycle(3),
I2 => y8(3),
O => \compute_addr_3[13]_i_2_n_0\
);
\compute_addr_3[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(1),
O => \compute_addr_3[1]_i_1_n_0\
);
\compute_addr_3[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(2),
O => \compute_addr_3[2]_i_1_n_0\
);
\compute_addr_3[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(3),
O => \compute_addr_3[3]_i_1_n_0\
);
\compute_addr_3[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(4),
O => \compute_addr_3[4]_i_1_n_0\
);
\compute_addr_3[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(5),
O => \compute_addr_3[5]_i_1_n_0\
);
\compute_addr_3[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(6),
O => \compute_addr_3[6]_i_1_n_0\
);
\compute_addr_3[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(7),
O => \compute_addr_3[7]_i_1_n_0\
);
\compute_addr_3[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(8),
O => \compute_addr_3[8]_i_1_n_0\
);
\compute_addr_3[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(9),
O => \compute_addr_3[9]_i_1_n_0\
);
\compute_addr_3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[0]_i_1_n_0\,
Q => compute_addr_3(0),
R => '0'
);
\compute_addr_3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[10]_i_1_n_0\,
Q => compute_addr_3(10),
R => '0'
);
\compute_addr_3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[11]_i_1_n_0\,
Q => compute_addr_3(11),
R => '0'
);
\compute_addr_3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[12]_i_1_n_0\,
Q => compute_addr_3(12),
R => '0'
);
\compute_addr_3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[13]_i_1_n_0\,
Q => compute_addr_3(13),
R => '0'
);
\compute_addr_3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[1]_i_1_n_0\,
Q => compute_addr_3(1),
R => '0'
);
\compute_addr_3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[2]_i_1_n_0\,
Q => compute_addr_3(2),
R => '0'
);
\compute_addr_3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[3]_i_1_n_0\,
Q => compute_addr_3(3),
R => '0'
);
\compute_addr_3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[4]_i_1_n_0\,
Q => compute_addr_3(4),
R => '0'
);
\compute_addr_3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[5]_i_1_n_0\,
Q => compute_addr_3(5),
R => '0'
);
\compute_addr_3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[6]_i_1_n_0\,
Q => compute_addr_3(6),
R => '0'
);
\compute_addr_3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[7]_i_1_n_0\,
Q => compute_addr_3(7),
R => '0'
);
\compute_addr_3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[8]_i_1_n_0\,
Q => compute_addr_3(8),
R => '0'
);
\compute_addr_3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[9]_i_1_n_0\,
Q => compute_addr_3(9),
R => '0'
);
\corner[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
I5 => top,
O => corner
);
\corner_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(0),
Q => \corner_reg_n_0_[0]\,
R => corner
);
\corner_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(10),
Q => \corner_reg_n_0_[10]\,
R => corner
);
\corner_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(11),
Q => \corner_reg_n_0_[11]\,
R => corner
);
\corner_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(12),
Q => \corner_reg_n_0_[12]\,
R => corner
);
\corner_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(13),
Q => \corner_reg_n_0_[13]\,
R => corner
);
\corner_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(14),
Q => \corner_reg_n_0_[14]\,
R => corner
);
\corner_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(15),
Q => \corner_reg_n_0_[15]\,
R => corner
);
\corner_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(1),
Q => \corner_reg_n_0_[1]\,
R => corner
);
\corner_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(2),
Q => \corner_reg_n_0_[2]\,
R => corner
);
\corner_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(3),
Q => \corner_reg_n_0_[3]\,
R => corner
);
\corner_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(4),
Q => \corner_reg_n_0_[4]\,
R => corner
);
\corner_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(5),
Q => \corner_reg_n_0_[5]\,
R => corner
);
\corner_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(6),
Q => \corner_reg_n_0_[6]\,
R => corner
);
\corner_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(7),
Q => \corner_reg_n_0_[7]\,
R => corner
);
\corner_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(8),
Q => \corner_reg_n_0_[8]\,
R => corner
);
\corner_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(9),
Q => \corner_reg_n_0_[9]\,
R => corner
);
\cycle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_i_1_n_0\
);
\cycle[0]_rep_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_rep_i_1_n_0\
);
\cycle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_i_1_n_0\
);
\cycle[1]_rep_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1_n_0\
);
\cycle[1]_rep_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1__0_n_0\
);
\cycle[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => cycle(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
O => \cycle[2]_i_1_n_0\
);
\cycle[2]_rep_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => cycle(0),
I2 => cycle(2),
O => \cycle[2]_rep_i_1_n_0\
);
\cycle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => active,
O => \cycle[3]_i_1_n_0\
);
\cycle[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => cycle(1),
I3 => \cycle_reg[0]_rep_n_0\,
O => \cycle[3]_i_2_n_0\
);
\cycle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_i_1_n_0\,
Q => cycle(0),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_rep_i_1_n_0\,
Q => \cycle_reg[0]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_i_1_n_0\,
Q => cycle(1),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1_n_0\,
Q => \cycle_reg[1]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1__0_n_0\,
Q => \cycle_reg[1]_rep__0_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_i_1_n_0\,
Q => cycle(2),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_rep_i_1_n_0\,
Q => \cycle_reg[2]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[3]_i_2_n_0\,
Q => cycle(3),
R => \cycle[3]_i_1_n_0\
);
det_0_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => A(15),
A(28) => A(15),
A(27) => A(15),
A(26) => A(15),
A(25) => A(15),
A(24) => A(15),
A(23) => A(15),
A(22) => A(15),
A(21) => A(15),
A(20) => A(15),
A(19) => A(15),
A(18) => A(15),
A(17) => A(15),
A(16) => A(15),
A(15 downto 0) => A(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_0_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => B(15),
B(16) => B(15),
B(15 downto 0) => B(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_0_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_0_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => Lxx,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => det_0_reg_i_2_n_0,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => det_0,
CEP => '0',
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_det_0_reg_OVERFLOW_UNCONNECTED,
P(47 downto 0) => NLW_det_0_reg_P_UNCONNECTED(47 downto 0),
PATTERNBDETECT => NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_0_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => det_0_reg_n_106,
PCOUT(46) => det_0_reg_n_107,
PCOUT(45) => det_0_reg_n_108,
PCOUT(44) => det_0_reg_n_109,
PCOUT(43) => det_0_reg_n_110,
PCOUT(42) => det_0_reg_n_111,
PCOUT(41) => det_0_reg_n_112,
PCOUT(40) => det_0_reg_n_113,
PCOUT(39) => det_0_reg_n_114,
PCOUT(38) => det_0_reg_n_115,
PCOUT(37) => det_0_reg_n_116,
PCOUT(36) => det_0_reg_n_117,
PCOUT(35) => det_0_reg_n_118,
PCOUT(34) => det_0_reg_n_119,
PCOUT(33) => det_0_reg_n_120,
PCOUT(32) => det_0_reg_n_121,
PCOUT(31) => det_0_reg_n_122,
PCOUT(30) => det_0_reg_n_123,
PCOUT(29) => det_0_reg_n_124,
PCOUT(28) => det_0_reg_n_125,
PCOUT(27) => det_0_reg_n_126,
PCOUT(26) => det_0_reg_n_127,
PCOUT(25) => det_0_reg_n_128,
PCOUT(24) => det_0_reg_n_129,
PCOUT(23) => det_0_reg_n_130,
PCOUT(22) => det_0_reg_n_131,
PCOUT(21) => det_0_reg_n_132,
PCOUT(20) => det_0_reg_n_133,
PCOUT(19) => det_0_reg_n_134,
PCOUT(18) => det_0_reg_n_135,
PCOUT(17) => det_0_reg_n_136,
PCOUT(16) => det_0_reg_n_137,
PCOUT(15) => det_0_reg_n_138,
PCOUT(14) => det_0_reg_n_139,
PCOUT(13) => det_0_reg_n_140,
PCOUT(12) => det_0_reg_n_141,
PCOUT(11) => det_0_reg_n_142,
PCOUT(10) => det_0_reg_n_143,
PCOUT(9) => det_0_reg_n_144,
PCOUT(8) => det_0_reg_n_145,
PCOUT(7) => det_0_reg_n_146,
PCOUT(6) => det_0_reg_n_147,
PCOUT(5) => det_0_reg_n_148,
PCOUT(4) => det_0_reg_n_149,
PCOUT(3) => det_0_reg_n_150,
PCOUT(2) => det_0_reg_n_151,
PCOUT(1) => det_0_reg_n_152,
PCOUT(0) => det_0_reg_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_0_reg_UNDERFLOW_UNCONNECTED
);
det_0_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => Lxx
);
det_0_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => rst,
I5 => active,
O => det_0_reg_i_2_n_0
);
det_0_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => cycle(1),
I3 => rst,
I4 => active,
I5 => \cycle_reg[0]_rep_n_0\,
O => det_0
);
\det_abs[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(10),
I1 => det_reg_n_95,
I2 => det_reg_n_74,
O => \det_abs[10]_i_1_n_0\
);
\det_abs[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(11),
I1 => det_reg_n_94,
I2 => det_reg_n_74,
O => \det_abs[11]_i_1_n_0\
);
\det_abs[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(12),
I1 => det_reg_n_93,
I2 => det_reg_n_74,
O => \det_abs[12]_i_1_n_0\
);
\det_abs[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_93,
O => \det_abs[12]_i_3_n_0\
);
\det_abs[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_94,
O => \det_abs[12]_i_4_n_0\
);
\det_abs[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_95,
O => \det_abs[12]_i_5_n_0\
);
\det_abs[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_96,
O => \det_abs[12]_i_6_n_0\
);
\det_abs[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(13),
I1 => det_reg_n_92,
I2 => det_reg_n_74,
O => \det_abs[13]_i_1_n_0\
);
\det_abs[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(14),
I1 => det_reg_n_91,
I2 => det_reg_n_74,
O => \det_abs[14]_i_1_n_0\
);
\det_abs[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(15),
I1 => det_reg_n_90,
I2 => det_reg_n_74,
O => \det_abs[15]_i_1_n_0\
);
\det_abs[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(16),
I1 => det_reg_n_89,
I2 => det_reg_n_74,
O => \det_abs[16]_i_1_n_0\
);
\det_abs[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_89,
O => \det_abs[16]_i_3_n_0\
);
\det_abs[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_90,
O => \det_abs[16]_i_4_n_0\
);
\det_abs[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_91,
O => \det_abs[16]_i_5_n_0\
);
\det_abs[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_92,
O => \det_abs[16]_i_6_n_0\
);
\det_abs[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(17),
I1 => det_reg_n_88,
I2 => det_reg_n_74,
O => \det_abs[17]_i_1_n_0\
);
\det_abs[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(18),
I1 => det_reg_n_87,
I2 => det_reg_n_74,
O => \det_abs[18]_i_1_n_0\
);
\det_abs[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(19),
I1 => det_reg_n_86,
I2 => det_reg_n_74,
O => \det_abs[19]_i_1_n_0\
);
\det_abs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(1),
I1 => det_reg_n_104,
I2 => det_reg_n_74,
O => \det_abs[1]_i_1_n_0\
);
\det_abs[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(20),
I1 => det_reg_n_85,
I2 => det_reg_n_74,
O => \det_abs[20]_i_1_n_0\
);
\det_abs[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_85,
O => \det_abs[20]_i_3_n_0\
);
\det_abs[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_86,
O => \det_abs[20]_i_4_n_0\
);
\det_abs[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_87,
O => \det_abs[20]_i_5_n_0\
);
\det_abs[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_88,
O => \det_abs[20]_i_6_n_0\
);
\det_abs[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(21),
I1 => det_reg_n_84,
I2 => det_reg_n_74,
O => \det_abs[21]_i_1_n_0\
);
\det_abs[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(22),
I1 => det_reg_n_83,
I2 => det_reg_n_74,
O => \det_abs[22]_i_1_n_0\
);
\det_abs[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(23),
I1 => det_reg_n_82,
I2 => det_reg_n_74,
O => \det_abs[23]_i_1_n_0\
);
\det_abs[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(24),
I1 => det_reg_n_81,
I2 => det_reg_n_74,
O => \det_abs[24]_i_1_n_0\
);
\det_abs[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_81,
O => \det_abs[24]_i_3_n_0\
);
\det_abs[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_82,
O => \det_abs[24]_i_4_n_0\
);
\det_abs[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_83,
O => \det_abs[24]_i_5_n_0\
);
\det_abs[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_84,
O => \det_abs[24]_i_6_n_0\
);
\det_abs[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(25),
I1 => det_reg_n_80,
I2 => det_reg_n_74,
O => \det_abs[25]_i_1_n_0\
);
\det_abs[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(26),
I1 => det_reg_n_79,
I2 => det_reg_n_74,
O => \det_abs[26]_i_1_n_0\
);
\det_abs[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(27),
I1 => det_reg_n_78,
I2 => det_reg_n_74,
O => \det_abs[27]_i_1_n_0\
);
\det_abs[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(28),
I1 => det_reg_n_77,
I2 => det_reg_n_74,
O => \det_abs[28]_i_1_n_0\
);
\det_abs[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_77,
O => \det_abs[28]_i_3_n_0\
);
\det_abs[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_78,
O => \det_abs[28]_i_4_n_0\
);
\det_abs[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_79,
O => \det_abs[28]_i_5_n_0\
);
\det_abs[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_80,
O => \det_abs[28]_i_6_n_0\
);
\det_abs[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(29),
I1 => det_reg_n_76,
I2 => det_reg_n_74,
O => \det_abs[29]_i_1_n_0\
);
\det_abs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(2),
I1 => det_reg_n_103,
I2 => det_reg_n_74,
O => \det_abs[2]_i_1_n_0\
);
\det_abs[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(30),
I1 => det_reg_n_75,
I2 => det_reg_n_74,
O => \det_abs[30]_i_1_n_0\
);
\det_abs[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => det_abs0(31),
I1 => det_reg_n_74,
O => \det_abs[31]_i_1_n_0\
);
\det_abs[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_74,
O => \det_abs[31]_i_3_n_0\
);
\det_abs[31]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_75,
O => \det_abs[31]_i_4_n_0\
);
\det_abs[31]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_76,
O => \det_abs[31]_i_5_n_0\
);
\det_abs[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(3),
I1 => det_reg_n_102,
I2 => det_reg_n_74,
O => \det_abs[3]_i_1_n_0\
);
\det_abs[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(4),
I1 => det_reg_n_101,
I2 => det_reg_n_74,
O => \det_abs[4]_i_1_n_0\
);
\det_abs[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_105,
O => \det_abs[4]_i_3_n_0\
);
\det_abs[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_101,
O => \det_abs[4]_i_4_n_0\
);
\det_abs[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_102,
O => \det_abs[4]_i_5_n_0\
);
\det_abs[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_103,
O => \det_abs[4]_i_6_n_0\
);
\det_abs[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_104,
O => \det_abs[4]_i_7_n_0\
);
\det_abs[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(5),
I1 => det_reg_n_100,
I2 => det_reg_n_74,
O => \det_abs[5]_i_1_n_0\
);
\det_abs[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(6),
I1 => det_reg_n_99,
I2 => det_reg_n_74,
O => \det_abs[6]_i_1_n_0\
);
\det_abs[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(7),
I1 => det_reg_n_98,
I2 => det_reg_n_74,
O => \det_abs[7]_i_1_n_0\
);
\det_abs[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(8),
I1 => det_reg_n_97,
I2 => det_reg_n_74,
O => \det_abs[8]_i_1_n_0\
);
\det_abs[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_97,
O => \det_abs[8]_i_3_n_0\
);
\det_abs[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_98,
O => \det_abs[8]_i_4_n_0\
);
\det_abs[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_99,
O => \det_abs[8]_i_5_n_0\
);
\det_abs[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_100,
O => \det_abs[8]_i_6_n_0\
);
\det_abs[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(9),
I1 => det_reg_n_96,
I2 => det_reg_n_74,
O => \det_abs[9]_i_1_n_0\
);
\det_abs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => det_reg_n_105,
Q => det_abs(0),
R => '0'
);
\det_abs_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[10]_i_1_n_0\,
Q => det_abs(10),
R => '0'
);
\det_abs_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[11]_i_1_n_0\,
Q => det_abs(11),
R => '0'
);
\det_abs_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[12]_i_1_n_0\,
Q => det_abs(12),
R => '0'
);
\det_abs_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[8]_i_2_n_0\,
CO(3) => \det_abs_reg[12]_i_2_n_0\,
CO(2) => \det_abs_reg[12]_i_2_n_1\,
CO(1) => \det_abs_reg[12]_i_2_n_2\,
CO(0) => \det_abs_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(12 downto 9),
S(3) => \det_abs[12]_i_3_n_0\,
S(2) => \det_abs[12]_i_4_n_0\,
S(1) => \det_abs[12]_i_5_n_0\,
S(0) => \det_abs[12]_i_6_n_0\
);
\det_abs_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[13]_i_1_n_0\,
Q => det_abs(13),
R => '0'
);
\det_abs_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[14]_i_1_n_0\,
Q => det_abs(14),
R => '0'
);
\det_abs_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[15]_i_1_n_0\,
Q => det_abs(15),
R => '0'
);
\det_abs_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[16]_i_1_n_0\,
Q => det_abs(16),
R => '0'
);
\det_abs_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[12]_i_2_n_0\,
CO(3) => \det_abs_reg[16]_i_2_n_0\,
CO(2) => \det_abs_reg[16]_i_2_n_1\,
CO(1) => \det_abs_reg[16]_i_2_n_2\,
CO(0) => \det_abs_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(16 downto 13),
S(3) => \det_abs[16]_i_3_n_0\,
S(2) => \det_abs[16]_i_4_n_0\,
S(1) => \det_abs[16]_i_5_n_0\,
S(0) => \det_abs[16]_i_6_n_0\
);
\det_abs_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[17]_i_1_n_0\,
Q => det_abs(17),
R => '0'
);
\det_abs_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[18]_i_1_n_0\,
Q => det_abs(18),
R => '0'
);
\det_abs_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[19]_i_1_n_0\,
Q => det_abs(19),
R => '0'
);
\det_abs_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[1]_i_1_n_0\,
Q => det_abs(1),
R => '0'
);
\det_abs_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[20]_i_1_n_0\,
Q => det_abs(20),
R => '0'
);
\det_abs_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[16]_i_2_n_0\,
CO(3) => \det_abs_reg[20]_i_2_n_0\,
CO(2) => \det_abs_reg[20]_i_2_n_1\,
CO(1) => \det_abs_reg[20]_i_2_n_2\,
CO(0) => \det_abs_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(20 downto 17),
S(3) => \det_abs[20]_i_3_n_0\,
S(2) => \det_abs[20]_i_4_n_0\,
S(1) => \det_abs[20]_i_5_n_0\,
S(0) => \det_abs[20]_i_6_n_0\
);
\det_abs_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[21]_i_1_n_0\,
Q => det_abs(21),
R => '0'
);
\det_abs_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[22]_i_1_n_0\,
Q => det_abs(22),
R => '0'
);
\det_abs_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[23]_i_1_n_0\,
Q => det_abs(23),
R => '0'
);
\det_abs_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[24]_i_1_n_0\,
Q => det_abs(24),
R => '0'
);
\det_abs_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[20]_i_2_n_0\,
CO(3) => \det_abs_reg[24]_i_2_n_0\,
CO(2) => \det_abs_reg[24]_i_2_n_1\,
CO(1) => \det_abs_reg[24]_i_2_n_2\,
CO(0) => \det_abs_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(24 downto 21),
S(3) => \det_abs[24]_i_3_n_0\,
S(2) => \det_abs[24]_i_4_n_0\,
S(1) => \det_abs[24]_i_5_n_0\,
S(0) => \det_abs[24]_i_6_n_0\
);
\det_abs_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[25]_i_1_n_0\,
Q => det_abs(25),
R => '0'
);
\det_abs_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[26]_i_1_n_0\,
Q => det_abs(26),
R => '0'
);
\det_abs_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[27]_i_1_n_0\,
Q => det_abs(27),
R => '0'
);
\det_abs_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[28]_i_1_n_0\,
Q => det_abs(28),
R => '0'
);
\det_abs_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[24]_i_2_n_0\,
CO(3) => \det_abs_reg[28]_i_2_n_0\,
CO(2) => \det_abs_reg[28]_i_2_n_1\,
CO(1) => \det_abs_reg[28]_i_2_n_2\,
CO(0) => \det_abs_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(28 downto 25),
S(3) => \det_abs[28]_i_3_n_0\,
S(2) => \det_abs[28]_i_4_n_0\,
S(1) => \det_abs[28]_i_5_n_0\,
S(0) => \det_abs[28]_i_6_n_0\
);
\det_abs_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[29]_i_1_n_0\,
Q => det_abs(29),
R => '0'
);
\det_abs_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[2]_i_1_n_0\,
Q => det_abs(2),
R => '0'
);
\det_abs_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[30]_i_1_n_0\,
Q => det_abs(30),
R => '0'
);
\det_abs_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[31]_i_1_n_0\,
Q => det_abs(31),
R => '0'
);
\det_abs_reg[31]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \det_abs_reg[31]_i_2_n_2\,
CO(0) => \det_abs_reg[31]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\(3),
O(2 downto 0) => det_abs0(31 downto 29),
S(3) => '0',
S(2) => \det_abs[31]_i_3_n_0\,
S(1) => \det_abs[31]_i_4_n_0\,
S(0) => \det_abs[31]_i_5_n_0\
);
\det_abs_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[3]_i_1_n_0\,
Q => det_abs(3),
R => '0'
);
\det_abs_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[4]_i_1_n_0\,
Q => det_abs(4),
R => '0'
);
\det_abs_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \det_abs_reg[4]_i_2_n_0\,
CO(2) => \det_abs_reg[4]_i_2_n_1\,
CO(1) => \det_abs_reg[4]_i_2_n_2\,
CO(0) => \det_abs_reg[4]_i_2_n_3\,
CYINIT => \det_abs[4]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(4 downto 1),
S(3) => \det_abs[4]_i_4_n_0\,
S(2) => \det_abs[4]_i_5_n_0\,
S(1) => \det_abs[4]_i_6_n_0\,
S(0) => \det_abs[4]_i_7_n_0\
);
\det_abs_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[5]_i_1_n_0\,
Q => det_abs(5),
R => '0'
);
\det_abs_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[6]_i_1_n_0\,
Q => det_abs(6),
R => '0'
);
\det_abs_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[7]_i_1_n_0\,
Q => det_abs(7),
R => '0'
);
\det_abs_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[8]_i_1_n_0\,
Q => det_abs(8),
R => '0'
);
\det_abs_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[4]_i_2_n_0\,
CO(3) => \det_abs_reg[8]_i_2_n_0\,
CO(2) => \det_abs_reg[8]_i_2_n_1\,
CO(1) => \det_abs_reg[8]_i_2_n_2\,
CO(0) => \det_abs_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(8 downto 5),
S(3) => \det_abs[8]_i_3_n_0\,
S(2) => \det_abs[8]_i_4_n_0\,
S(1) => \det_abs[8]_i_5_n_0\,
S(0) => \det_abs[8]_i_6_n_0\
);
\det_abs_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[9]_i_1_n_0\,
Q => det_abs(9),
R => '0'
);
det_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \Lxy0__1_carry__2_n_4\,
A(28) => \Lxy0__1_carry__2_n_4\,
A(27) => \Lxy0__1_carry__2_n_4\,
A(26) => \Lxy0__1_carry__2_n_4\,
A(25) => \Lxy0__1_carry__2_n_4\,
A(24) => \Lxy0__1_carry__2_n_4\,
A(23) => \Lxy0__1_carry__2_n_4\,
A(22) => \Lxy0__1_carry__2_n_4\,
A(21) => \Lxy0__1_carry__2_n_4\,
A(20) => \Lxy0__1_carry__2_n_4\,
A(19) => \Lxy0__1_carry__2_n_4\,
A(18) => \Lxy0__1_carry__2_n_4\,
A(17) => \Lxy0__1_carry__2_n_4\,
A(16) => \Lxy0__1_carry__2_n_4\,
A(15) => \Lxy0__1_carry__2_n_4\,
A(14) => \Lxy0__1_carry__2_n_5\,
A(13) => \Lxy0__1_carry__2_n_6\,
A(12) => \Lxy0__1_carry__2_n_7\,
A(11) => \Lxy0__1_carry__1_n_4\,
A(10) => \Lxy0__1_carry__1_n_5\,
A(9) => \Lxy0__1_carry__1_n_6\,
A(8) => \Lxy0__1_carry__1_n_7\,
A(7) => \Lxy0__1_carry__0_n_4\,
A(6) => \Lxy0__1_carry__0_n_5\,
A(5) => \Lxy0__1_carry__0_n_6\,
A(4) => \Lxy0__1_carry__0_n_7\,
A(3) => \Lxy0__1_carry_n_4\,
A(2) => \Lxy0__1_carry_n_5\,
A(1) => \Lxy0__1_carry_n_6\,
A(0) => \Lxy0__1_carry_n_7\,
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0011",
B(17) => \Lxy0__1_carry__2_n_4\,
B(16) => \Lxy0__1_carry__2_n_4\,
B(15) => \Lxy0__1_carry__2_n_4\,
B(14) => \Lxy0__1_carry__2_n_5\,
B(13) => \Lxy0__1_carry__2_n_6\,
B(12) => \Lxy0__1_carry__2_n_7\,
B(11) => \Lxy0__1_carry__1_n_4\,
B(10) => \Lxy0__1_carry__1_n_5\,
B(9) => \Lxy0__1_carry__1_n_6\,
B(8) => \Lxy0__1_carry__1_n_7\,
B(7) => \Lxy0__1_carry__0_n_4\,
B(6) => \Lxy0__1_carry__0_n_5\,
B(5) => \Lxy0__1_carry__0_n_6\,
B(4) => \Lxy0__1_carry__0_n_7\,
B(3) => \Lxy0__1_carry_n_4\,
B(2) => \Lxy0__1_carry_n_5\,
B(1) => \Lxy0__1_carry_n_6\,
B(0) => \Lxy0__1_carry_n_7\,
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => y3,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => y3,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => y2,
CEP => y9,
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0010101",
OVERFLOW => NLW_det_reg_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_det_reg_P_UNCONNECTED(47 downto 32),
P(31) => det_reg_n_74,
P(30) => det_reg_n_75,
P(29) => det_reg_n_76,
P(28) => det_reg_n_77,
P(27) => det_reg_n_78,
P(26) => det_reg_n_79,
P(25) => det_reg_n_80,
P(24) => det_reg_n_81,
P(23) => det_reg_n_82,
P(22) => det_reg_n_83,
P(21) => det_reg_n_84,
P(20) => det_reg_n_85,
P(19) => det_reg_n_86,
P(18) => det_reg_n_87,
P(17) => det_reg_n_88,
P(16) => det_reg_n_89,
P(15) => det_reg_n_90,
P(14) => det_reg_n_91,
P(13) => det_reg_n_92,
P(12) => det_reg_n_93,
P(11) => det_reg_n_94,
P(10) => det_reg_n_95,
P(9) => det_reg_n_96,
P(8) => det_reg_n_97,
P(7) => det_reg_n_98,
P(6) => det_reg_n_99,
P(5) => det_reg_n_100,
P(4) => det_reg_n_101,
P(3) => det_reg_n_102,
P(2) => det_reg_n_103,
P(1) => det_reg_n_104,
P(0) => det_reg_n_105,
PATTERNBDETECT => NLW_det_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47) => det_0_reg_n_106,
PCIN(46) => det_0_reg_n_107,
PCIN(45) => det_0_reg_n_108,
PCIN(44) => det_0_reg_n_109,
PCIN(43) => det_0_reg_n_110,
PCIN(42) => det_0_reg_n_111,
PCIN(41) => det_0_reg_n_112,
PCIN(40) => det_0_reg_n_113,
PCIN(39) => det_0_reg_n_114,
PCIN(38) => det_0_reg_n_115,
PCIN(37) => det_0_reg_n_116,
PCIN(36) => det_0_reg_n_117,
PCIN(35) => det_0_reg_n_118,
PCIN(34) => det_0_reg_n_119,
PCIN(33) => det_0_reg_n_120,
PCIN(32) => det_0_reg_n_121,
PCIN(31) => det_0_reg_n_122,
PCIN(30) => det_0_reg_n_123,
PCIN(29) => det_0_reg_n_124,
PCIN(28) => det_0_reg_n_125,
PCIN(27) => det_0_reg_n_126,
PCIN(26) => det_0_reg_n_127,
PCIN(25) => det_0_reg_n_128,
PCIN(24) => det_0_reg_n_129,
PCIN(23) => det_0_reg_n_130,
PCIN(22) => det_0_reg_n_131,
PCIN(21) => det_0_reg_n_132,
PCIN(20) => det_0_reg_n_133,
PCIN(19) => det_0_reg_n_134,
PCIN(18) => det_0_reg_n_135,
PCIN(17) => det_0_reg_n_136,
PCIN(16) => det_0_reg_n_137,
PCIN(15) => det_0_reg_n_138,
PCIN(14) => det_0_reg_n_139,
PCIN(13) => det_0_reg_n_140,
PCIN(12) => det_0_reg_n_141,
PCIN(11) => det_0_reg_n_142,
PCIN(10) => det_0_reg_n_143,
PCIN(9) => det_0_reg_n_144,
PCIN(8) => det_0_reg_n_145,
PCIN(7) => det_0_reg_n_146,
PCIN(6) => det_0_reg_n_147,
PCIN(5) => det_0_reg_n_148,
PCIN(4) => det_0_reg_n_149,
PCIN(3) => det_0_reg_n_150,
PCIN(2) => det_0_reg_n_151,
PCIN(1) => det_0_reg_n_152,
PCIN(0) => det_0_reg_n_153,
PCOUT(47 downto 0) => NLW_det_reg_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_reg_UNDERFLOW_UNCONNECTED
);
det_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y2
);
det_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y9
);
\din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(0),
Q => \din_reg_n_0_[0]\,
R => '0'
);
\din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(10),
Q => \din_reg_n_0_[10]\,
R => '0'
);
\din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(11),
Q => \din_reg_n_0_[11]\,
R => '0'
);
\din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(12),
Q => \din_reg_n_0_[12]\,
R => '0'
);
\din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(13),
Q => \din_reg_n_0_[13]\,
R => '0'
);
\din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(14),
Q => \din_reg_n_0_[14]\,
R => '0'
);
\din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(15),
Q => \din_reg_n_0_[15]\,
R => '0'
);
\din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(1),
Q => \din_reg_n_0_[1]\,
R => '0'
);
\din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(2),
Q => \din_reg_n_0_[2]\,
R => '0'
);
\din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(3),
Q => \din_reg_n_0_[3]\,
R => '0'
);
\din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(4),
Q => \din_reg_n_0_[4]\,
R => '0'
);
\din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(5),
Q => \din_reg_n_0_[5]\,
R => '0'
);
\din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(6),
Q => \din_reg_n_0_[6]\,
R => '0'
);
\din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(7),
Q => \din_reg_n_0_[7]\,
R => '0'
);
\din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(8),
Q => \din_reg_n_0_[8]\,
R => '0'
);
\din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(9),
Q => \din_reg_n_0_[9]\,
R => '0'
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y3
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(0),
Q => hessian_out(0),
R => '0'
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(10),
Q => hessian_out(10),
R => '0'
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(11),
Q => hessian_out(11),
R => '0'
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(12),
Q => hessian_out(12),
R => '0'
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(13),
Q => hessian_out(13),
R => '0'
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(14),
Q => hessian_out(14),
R => '0'
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(15),
Q => hessian_out(15),
R => '0'
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(16),
Q => hessian_out(16),
R => '0'
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(17),
Q => hessian_out(17),
R => '0'
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(18),
Q => hessian_out(18),
R => '0'
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(19),
Q => hessian_out(19),
R => '0'
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(1),
Q => hessian_out(1),
R => '0'
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(20),
Q => hessian_out(20),
R => '0'
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(21),
Q => hessian_out(21),
R => '0'
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(22),
Q => hessian_out(22),
R => '0'
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(23),
Q => hessian_out(23),
R => '0'
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(24),
Q => hessian_out(24),
R => '0'
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(25),
Q => hessian_out(25),
R => '0'
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(26),
Q => hessian_out(26),
R => '0'
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(27),
Q => hessian_out(27),
R => '0'
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(28),
Q => hessian_out(28),
R => '0'
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(29),
Q => hessian_out(29),
R => '0'
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(2),
Q => hessian_out(2),
R => '0'
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(30),
Q => hessian_out(30),
R => '0'
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(31),
Q => hessian_out(31),
R => '0'
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(3),
Q => hessian_out(3),
R => '0'
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(4),
Q => hessian_out(4),
R => '0'
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(5),
Q => hessian_out(5),
R => '0'
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(6),
Q => hessian_out(6),
R => '0'
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(7),
Q => hessian_out(7),
R => '0'
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(8),
Q => hessian_out(8),
R => '0'
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(9),
Q => hessian_out(9),
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[7]\,
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[6]\,
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[5]\,
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[4]\,
O => \i__carry__0_i_5_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[9]\,
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[8]\,
O => \i__carry__1_i_2_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[3]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55599555"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"5595"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_4_n_0\
);
\last_value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[0]\,
Q => last_value(0),
R => '0'
);
\last_value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[1]\,
Q => last_value(1),
R => '0'
);
\last_value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[2]\,
Q => last_value(2),
R => '0'
);
\last_value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[3]\,
Q => last_value(3),
R => '0'
);
\last_value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[4]\,
Q => last_value(4),
R => '0'
);
\last_value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[5]\,
Q => last_value(5),
R => '0'
);
\last_value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[6]\,
Q => last_value(6),
R => '0'
);
\last_value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[7]\,
Q => last_value(7),
R => '0'
);
\left[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
O => left
);
\left[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[6]\,
I3 => \left[15]_i_3_n_0\,
O => \left[15]_i_2_n_0\
);
\left[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \left[15]_i_3_n_0\
);
\left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(0),
Q => \left_reg_n_0_[0]\,
R => left
);
\left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(10),
Q => \left_reg_n_0_[10]\,
R => left
);
\left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(11),
Q => \left_reg_n_0_[11]\,
R => left
);
\left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(12),
Q => \left_reg_n_0_[12]\,
R => left
);
\left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(13),
Q => \left_reg_n_0_[13]\,
R => left
);
\left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(14),
Q => \left_reg_n_0_[14]\,
R => left
);
\left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(15),
Q => \left_reg_n_0_[15]\,
R => left
);
\left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(1),
Q => \left_reg_n_0_[1]\,
R => left
);
\left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(2),
Q => \left_reg_n_0_[2]\,
R => left
);
\left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(3),
Q => \left_reg_n_0_[3]\,
R => left
);
\left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(4),
Q => \left_reg_n_0_[4]\,
R => left
);
\left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(5),
Q => \left_reg_n_0_[5]\,
R => left
);
\left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(6),
Q => \left_reg_n_0_[6]\,
R => left
);
\left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(7),
Q => \left_reg_n_0_[7]\,
R => left
);
\left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(8),
Q => \left_reg_n_0_[8]\,
R => left
);
\left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(9),
Q => \left_reg_n_0_[9]\,
R => left
);
\plusOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \plusOp_inferred__0/i__carry_n_0\,
CO(2) => \plusOp_inferred__0/i__carry_n_1\,
CO(1) => \plusOp_inferred__0/i__carry_n_2\,
CO(0) => \plusOp_inferred__0/i__carry_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[3]\,
DI(2) => \x_reg_n_0_[2]\,
DI(1) => \x_reg_n_0_[1]\,
DI(0) => \x_reg_n_0_[0]\,
O(3) => \plusOp_inferred__0/i__carry_n_4\,
O(2) => \plusOp_inferred__0/i__carry_n_5\,
O(1) => \plusOp_inferred__0/i__carry_n_6\,
O(0) => \plusOp_inferred__0/i__carry_n_7\,
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\plusOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry_n_0\,
CO(3) => \plusOp_inferred__0/i__carry__0_n_0\,
CO(2) => \plusOp_inferred__0/i__carry__0_n_1\,
CO(1) => \plusOp_inferred__0/i__carry__0_n_2\,
CO(0) => \plusOp_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[6]\,
DI(2) => \x_reg_n_0_[5]\,
DI(1) => \x_reg_n_0_[4]\,
DI(0) => \i__carry__0_i_1_n_0\,
O(3) => \plusOp_inferred__0/i__carry__0_n_4\,
O(2) => \plusOp_inferred__0/i__carry__0_n_5\,
O(1) => \plusOp_inferred__0/i__carry__0_n_6\,
O(0) => \plusOp_inferred__0/i__carry__0_n_7\,
S(3) => \i__carry__0_i_2_n_0\,
S(2) => \i__carry__0_i_3_n_0\,
S(1) => \i__carry__0_i_4_n_0\,
S(0) => \i__carry__0_i_5_n_0\
);
\plusOp_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_reg_n_0_[7]\,
O(3 downto 2) => \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_inferred__0/i__carry__1_n_6\,
O(0) => \plusOp_inferred__0/i__carry__1_n_7\,
S(3 downto 2) => B"00",
S(1) => \i__carry__1_i_1_n_0\,
S(0) => \i__carry__1_i_2_n_0\
);
\top[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => x,
I1 => \top[15]_i_2_n_0\,
I2 => \y_actual_reg_n_0_[3]\,
I3 => \y_actual_reg_n_0_[0]\,
I4 => \y_actual_reg_n_0_[1]\,
I5 => \y_actual_reg_n_0_[2]\,
O => top
);
\top[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \y_actual_reg_n_0_[8]\,
I1 => \y_actual_reg_n_0_[9]\,
I2 => \y_actual_reg_n_0_[6]\,
I3 => \y_actual_reg_n_0_[7]\,
I4 => \y_actual_reg_n_0_[4]\,
I5 => \y_actual_reg_n_0_[5]\,
O => \top[15]_i_2_n_0\
);
\top_left_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(0),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_left_0[0]_i_1_n_0\
);
\top_left_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(10),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_left_0[10]_i_1_n_0\
);
\top_left_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(11),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_left_0[11]_i_1_n_0\
);
\top_left_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(12),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_left_0[12]_i_1_n_0\
);
\top_left_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(13),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_left_0[13]_i_1_n_0\
);
\top_left_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(14),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_left_0[14]_i_1_n_0\
);
\top_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000700010000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep_n_0\,
O => top_left_0
);
\top_left_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(15),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_left_0[15]_i_2_n_0\
);
\top_left_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(1),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_left_0[1]_i_1_n_0\
);
\top_left_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(2),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_left_0[2]_i_1_n_0\
);
\top_left_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_left_0[3]_i_1_n_0\
);
\top_left_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(4),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_left_0[4]_i_1_n_0\
);
\top_left_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(5),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_left_0[5]_i_1_n_0\
);
\top_left_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(6),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_left_0[6]_i_1_n_0\
);
\top_left_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(7),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_left_0[7]_i_1_n_0\
);
\top_left_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(8),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_left_0[8]_i_1_n_0\
);
\top_left_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(9),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_left_0[9]_i_1_n_0\
);
\top_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[0]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[0]\,
R => '0'
);
\top_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[10]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[10]\,
R => '0'
);
\top_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[11]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[11]\,
R => '0'
);
\top_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[12]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[12]\,
R => '0'
);
\top_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[13]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[13]\,
R => '0'
);
\top_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[14]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[14]\,
R => '0'
);
\top_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[15]_i_2_n_0\,
Q => \top_left_0_reg_n_0_[15]\,
R => '0'
);
\top_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[1]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[1]\,
R => '0'
);
\top_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[2]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[2]\,
R => '0'
);
\top_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[3]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[3]\,
R => '0'
);
\top_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[4]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[4]\,
R => '0'
);
\top_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[5]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[5]\,
R => '0'
);
\top_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[6]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[6]\,
R => '0'
);
\top_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[7]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[7]\,
R => '0'
);
\top_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[8]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[8]\,
R => '0'
);
\top_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[9]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[9]\,
R => '0'
);
\top_left_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[0]\,
O => \top_left_1[0]_i_1_n_0\
);
\top_left_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[10]\,
O => \top_left_1[10]_i_1_n_0\
);
\top_left_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[11]\,
O => \top_left_1[11]_i_1_n_0\
);
\top_left_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[12]\,
O => \top_left_1[12]_i_1_n_0\
);
\top_left_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[13]\,
O => \top_left_1[13]_i_1_n_0\
);
\top_left_1[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(14),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[14]\,
O => \top_left_1[14]_i_1_n_0\
);
\top_left_1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
O => bottom_right_1
);
\top_left_1[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(15),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[15]\,
O => \top_left_1[15]_i_2_n_0\
);
\top_left_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[1]\,
O => \top_left_1[1]_i_1_n_0\
);
\top_left_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[2]\,
O => \top_left_1[2]_i_1_n_0\
);
\top_left_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[3]\,
O => \top_left_1[3]_i_1_n_0\
);
\top_left_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[4]\,
O => \top_left_1[4]_i_1_n_0\
);
\top_left_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[5]\,
O => \top_left_1[5]_i_1_n_0\
);
\top_left_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[6]\,
O => \top_left_1[6]_i_1_n_0\
);
\top_left_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[7]\,
O => \top_left_1[7]_i_1_n_0\
);
\top_left_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[8]\,
O => \top_left_1[8]_i_1_n_0\
);
\top_left_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[9]\,
O => \top_left_1[9]_i_1_n_0\
);
\top_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[0]_i_1_n_0\,
Q => top_left_1(0),
R => '0'
);
\top_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[10]_i_1_n_0\,
Q => top_left_1(10),
R => '0'
);
\top_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[11]_i_1_n_0\,
Q => top_left_1(11),
R => '0'
);
\top_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[12]_i_1_n_0\,
Q => top_left_1(12),
R => '0'
);
\top_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[13]_i_1_n_0\,
Q => top_left_1(13),
R => '0'
);
\top_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[14]_i_1_n_0\,
Q => top_left_1(14),
R => '0'
);
\top_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[15]_i_2_n_0\,
Q => top_left_1(15),
R => '0'
);
\top_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[1]_i_1_n_0\,
Q => top_left_1(1),
R => '0'
);
\top_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[2]_i_1_n_0\,
Q => top_left_1(2),
R => '0'
);
\top_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[3]_i_1_n_0\,
Q => top_left_1(3),
R => '0'
);
\top_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[4]_i_1_n_0\,
Q => top_left_1(4),
R => '0'
);
\top_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[5]_i_1_n_0\,
Q => top_left_1(5),
R => '0'
);
\top_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[6]_i_1_n_0\,
Q => top_left_1(6),
R => '0'
);
\top_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[7]_i_1_n_0\,
Q => top_left_1(7),
R => '0'
);
\top_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[8]_i_1_n_0\,
Q => top_left_1(8),
R => '0'
);
\top_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[9]_i_1_n_0\,
Q => top_left_1(9),
R => '0'
);
\top_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(0),
Q => \top_reg_n_0_[0]\,
R => top
);
\top_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(10),
Q => \top_reg_n_0_[10]\,
R => top
);
\top_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(11),
Q => \top_reg_n_0_[11]\,
R => top
);
\top_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(12),
Q => \top_reg_n_0_[12]\,
R => top
);
\top_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(13),
Q => \top_reg_n_0_[13]\,
R => top
);
\top_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(14),
Q => \top_reg_n_0_[14]\,
R => top
);
\top_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(15),
Q => \top_reg_n_0_[15]\,
R => top
);
\top_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(1),
Q => \top_reg_n_0_[1]\,
R => top
);
\top_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(2),
Q => \top_reg_n_0_[2]\,
R => top
);
\top_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(3),
Q => \top_reg_n_0_[3]\,
R => top
);
\top_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(4),
Q => \top_reg_n_0_[4]\,
R => top
);
\top_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(5),
Q => \top_reg_n_0_[5]\,
R => top
);
\top_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(6),
Q => \top_reg_n_0_[6]\,
R => top
);
\top_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(7),
Q => \top_reg_n_0_[7]\,
R => top
);
\top_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(8),
Q => \top_reg_n_0_[8]\,
R => top
);
\top_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(9),
Q => \top_reg_n_0_[9]\,
R => top
);
\top_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_right_0[0]_i_1_n_0\
);
\top_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(10),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_right_0[10]_i_1_n_0\
);
\top_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(11),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_right_0[11]_i_1_n_0\
);
\top_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(12),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_right_0[12]_i_1_n_0\
);
\top_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(13),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_right_0[13]_i_1_n_0\
);
\top_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(14),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_right_0[14]_i_1_n_0\
);
\top_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0880000080080800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => top_right_0
);
\top_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(15),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_right_0[15]_i_2_n_0\
);
\top_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(1),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_right_0[1]_i_1_n_0\
);
\top_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(2),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_right_0[2]_i_1_n_0\
);
\top_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(3),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_right_0[3]_i_1_n_0\
);
\top_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(4),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_right_0[4]_i_1_n_0\
);
\top_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(5),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_right_0[5]_i_1_n_0\
);
\top_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(6),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_right_0[6]_i_1_n_0\
);
\top_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(7),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_right_0[7]_i_1_n_0\
);
\top_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(8),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_right_0[8]_i_1_n_0\
);
\top_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(9),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_right_0[9]_i_1_n_0\
);
\top_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[0]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[0]\,
R => '0'
);
\top_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[10]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[10]\,
R => '0'
);
\top_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[11]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[11]\,
R => '0'
);
\top_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[12]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[12]\,
R => '0'
);
\top_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[13]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[13]\,
R => '0'
);
\top_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[14]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[14]\,
R => '0'
);
\top_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[15]_i_2_n_0\,
Q => \top_right_0_reg_n_0_[15]\,
R => '0'
);
\top_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[1]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[1]\,
R => '0'
);
\top_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[2]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[2]\,
R => '0'
);
\top_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[3]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[3]\,
R => '0'
);
\top_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[4]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[4]\,
R => '0'
);
\top_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[5]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[5]\,
R => '0'
);
\top_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[6]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[6]\,
R => '0'
);
\top_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[7]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[7]\,
R => '0'
);
\top_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[8]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[8]\,
R => '0'
);
\top_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[9]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[9]\,
R => '0'
);
\top_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[0]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[0]\,
O => \top_right_1[0]_i_1_n_0\
);
\top_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[10]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[10]\,
O => \top_right_1[10]_i_1_n_0\
);
\top_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[11]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[11]\,
O => \top_right_1[11]_i_1_n_0\
);
\top_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[12]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[12]\,
O => \top_right_1[12]_i_1_n_0\
);
\top_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[13]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[13]\,
O => \top_right_1[13]_i_1_n_0\
);
\top_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[14]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[14]\,
O => \top_right_1[14]_i_1_n_0\
);
\top_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[15]\,
O => \top_right_1[15]_i_1_n_0\
);
\top_right_1[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => cycle(3),
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \top_right_1[15]_i_2_n_0\
);
\top_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[1]\,
O => \top_right_1[1]_i_1_n_0\
);
\top_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[2]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[2]\,
O => \top_right_1[2]_i_1_n_0\
);
\top_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[3]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[3]\,
O => \top_right_1[3]_i_1_n_0\
);
\top_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[4]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[4]\,
O => \top_right_1[4]_i_1_n_0\
);
\top_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[5]\,
O => \top_right_1[5]_i_1_n_0\
);
\top_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[6]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[6]\,
O => \top_right_1[6]_i_1_n_0\
);
\top_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[7]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[7]\,
O => \top_right_1[7]_i_1_n_0\
);
\top_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[8]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[8]\,
O => \top_right_1[8]_i_1_n_0\
);
\top_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[9]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[9]\,
O => \top_right_1[9]_i_1_n_0\
);
\top_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[0]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[0]\,
R => '0'
);
\top_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[10]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[10]\,
R => '0'
);
\top_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[11]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[11]\,
R => '0'
);
\top_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[12]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[12]\,
R => '0'
);
\top_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[13]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[13]\,
R => '0'
);
\top_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[14]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[14]\,
R => '0'
);
\top_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[15]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[15]\,
R => '0'
);
\top_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[1]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[1]\,
R => '0'
);
\top_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[2]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[2]\,
R => '0'
);
\top_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[3]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[3]\,
R => '0'
);
\top_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[4]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[4]\,
R => '0'
);
\top_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[5]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[5]\,
R => '0'
);
\top_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[6]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[6]\,
R => '0'
);
\top_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[7]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[7]\,
R => '0'
);
\top_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[8]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[8]\,
R => '0'
);
\top_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[9]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[9]\,
R => '0'
);
\value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(0),
Q => \value_reg_n_0_[0]\,
R => '0'
);
\value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(1),
Q => \value_reg_n_0_[1]\,
R => '0'
);
\value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(2),
Q => \value_reg_n_0_[2]\,
R => '0'
);
\value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(3),
Q => \value_reg_n_0_[3]\,
R => '0'
);
\value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(4),
Q => \value_reg_n_0_[4]\,
R => '0'
);
\value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(5),
Q => \value_reg_n_0_[5]\,
R => '0'
);
\value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(6),
Q => \value_reg_n_0_[6]\,
R => '0'
);
\value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(7),
Q => \value_reg_n_0_[7]\,
R => '0'
);
wen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAAA2AAAA"
)
port map (
I0 => wen_reg_n_0,
I1 => wen_i_2_n_0,
I2 => \cycle_reg[0]_rep_n_0\,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => wen_i_1_n_0
);
wen_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => active,
I1 => rst,
O => wen_i_2_n_0
);
wen_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => wen_i_1_n_0,
Q => wen_reg_n_0,
R => '0'
);
\x0[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3B01FFC53A00FEC4"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => data2(0),
I4 => \x_reg_n_0_[0]\,
I5 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_2_n_0\
);
\x0[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(0),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_3_n_0\
);
\x0[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCEECCEEEEEECCFC"
)
port map (
I0 => data2(1),
I1 => \x0[1]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_6\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_2_n_0\
);
\x0[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(1),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_6\,
O => \x0[1]_i_3_n_0\
);
\x0[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"60600060"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[0]\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_4_n_0\
);
\x0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBFBBBFFBBBBBB"
)
port map (
I0 => \x0[2]_i_2_n_0\,
I1 => \x0[2]_i_3_n_0\,
I2 => data2(2),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry_n_5\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[2]_i_1_n_0\
);
\x0[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88AA22A0880022A0"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x0[2]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(2),
O => \x0[2]_i_2_n_0\
);
\x0[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FF3F3F377777777"
)
port map (
I0 => data2(2),
I1 => \x0[2]_i_5_n_0\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
I5 => \x1[6]_i_8_n_0\,
O => \x0[2]_i_3_n_0\
);
\x0[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[2]_i_4_n_0\
);
\x0[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
O => \x0[2]_i_5_n_0\
);
\x0[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x0[3]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[3]_i_3_n_0\,
I3 => cycle(3),
I4 => \x0[3]_i_4_n_0\,
O => \x0[3]_i_1_n_0\
);
\x0[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"660FFF00660FFFFF"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_5_n_0\,
I2 => data2(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_2_n_0\
);
\x0[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F9F090000900"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(3),
O => \x0[3]_i_3_n_0\
);
\x0[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(3),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_4_n_0\
);
\x0[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_5_n_0\
);
\x0[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_6_n_0\
);
\x0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[4]_i_2_n_0\,
I1 => \x0[4]_i_3_n_0\,
I2 => data2(4),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[4]_i_1_n_0\
);
\x0[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x0[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[4]_i_2_n_0\
);
\x0[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"008A0080A08AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data2(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x0[4]_i_5_n_0\,
O => \x0[4]_i_3_n_0\
);
\x0[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
O => \x0[4]_i_4_n_0\
);
\x0[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"95555555"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
O => \x0[4]_i_5_n_0\
);
\x0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[5]_i_2_n_0\,
I1 => \x0[5]_i_3_n_0\,
I2 => data2(5),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_6\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[5]_i_1_n_0\
);
\x0[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(5),
I1 => \x_reg_n_0_[5]\,
I2 => \x0[8]_i_7_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[5]_i_2_n_0\
);
\x0[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A80008AAAAAAAA"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \plusOp_inferred__0/i__carry__0_n_6\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => data2(5),
I5 => \x0[5]_i_4_n_0\,
O => \x0[5]_i_3_n_0\
);
\x0[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x0[5]_i_5_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(0),
O => \x0[5]_i_4_n_0\
);
\x0[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x0[5]_i_5_n_0\
);
\x0[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0507"
)
port map (
I0 => \x0[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(3),
I3 => \x0[6]_i_3_n_0\,
I4 => \x0[6]_i_4_n_0\,
O => \x0[6]_i_1_n_0\
);
\x0[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0707077077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data2(6),
I2 => \x_reg_n_0_[6]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x0[8]_i_5_n_0\,
O => \x0[6]_i_2_n_0\
);
\x0[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6600FF0F66FFFF0F"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x0[6]_i_5_n_0\,
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(6),
O => \x0[6]_i_3_n_0\
);
\x0[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C0C0C0C0C0C088"
)
port map (
I0 => data2(6),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[6]_i_4_n_0\
);
\x0[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x0[6]_i_5_n_0\
);
\x0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF020000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x0[7]_i_2_n_0\,
I3 => \x0[7]_i_3_n_0\,
I4 => \x0[7]_i_4_n_0\,
I5 => \x0[7]_i_5_n_0\,
O => \x0[7]_i_1_n_0\
);
\x0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[8]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \x_reg_n_0_[6]\,
O => \x0[7]_i_2_n_0\
);
\x0[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99F000FF99F00000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[7]_i_6_n_0\,
I2 => data2(7),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_3_n_0\
);
\x0[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
O => \x0[7]_i_4_n_0\
);
\x0[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x0[7]_i_7_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data2(7),
I4 => cycle(3),
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_5_n_0\
);
\x0[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x0[6]_i_5_n_0\,
I1 => \x_reg_n_0_[6]\,
O => \x0[7]_i_6_n_0\
);
\x0[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x_reg_n_0_[6]\,
I3 => \x_reg_n_0_[5]\,
I4 => \x0[8]_i_7_n_0\,
I5 => \x_reg_n_0_[7]\,
O => \x0[7]_i_7_n_0\
);
\x0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0FFF1F1F1"
)
port map (
I0 => \x0[8]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[8]_i_3_n_0\,
I3 => \x0[8]_i_4_n_0\,
I4 => \x0[8]_i_5_n_0\,
I5 => cycle(3),
O => \x0[8]_i_1_n_0\
);
\x0[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"990FFF00990FFFFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x0[8]_i_6_n_0\,
I2 => data2(8),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__1_n_7\,
O => \x0[8]_i_2_n_0\
);
\x0[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888B888B888B8C0"
)
port map (
I0 => \plusOp_inferred__0/i__carry__1_n_7\,
I1 => cycle(3),
I2 => data2(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[8]_i_3_n_0\
);
\x0[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x0[8]_i_4_n_0\
);
\x0[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x0[8]_i_5_n_0\
);
\x0[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x0[6]_i_5_n_0\,
O => \x0[8]_i_6_n_0\
);
\x0[8]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[0]\,
I4 => \x_reg_n_0_[3]\,
O => \x0[8]_i_7_n_0\
);
\x0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"77FE000000000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => active,
I5 => rst,
O => \x0[9]_i_1_n_0\
);
\x0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0101"
)
port map (
I0 => \x0[9]_i_3_n_0\,
I1 => cycle(3),
I2 => cycle(2),
I3 => \x0[9]_i_4_n_0\,
I4 => \x0[9]_i_5_n_0\,
O => \x0[9]_i_2_n_0\
);
\x0[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF03AFF3A003A0F3"
)
port map (
I0 => \x0[9]_i_6_n_0\,
I1 => \plusOp_inferred__0/i__carry__1_n_6\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => data2(9),
I5 => \x0[9]_i_7_n_0\,
O => \x0[9]_i_3_n_0\
);
\x0[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C0C0C0C0C44"
)
port map (
I0 => data2(9),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__1_n_6\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \x0[9]_i_4_n_0\
);
\x0[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5CCC0000"
)
port map (
I0 => \x0[9]_i_7_n_0\,
I1 => data2(9),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => \x0[9]_i_5_n_0\
);
\x0[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"55559555"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x_reg_n_0_[6]\,
I4 => \x0[6]_i_5_n_0\,
O => \x0[9]_i_6_n_0\
);
\x0[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x_reg_n_0_[6]\,
O => \x0[9]_i_7_n_0\
);
\x0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[0]_i_1_n_0\,
Q => data1(0),
R => '0'
);
\x0_reg[0]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[0]_i_2_n_0\,
I1 => \x0[0]_i_3_n_0\,
O => \x0_reg[0]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[1]_i_1_n_0\,
Q => data1(1),
R => '0'
);
\x0_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[1]_i_2_n_0\,
I1 => \x0[1]_i_3_n_0\,
O => \x0_reg[1]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[2]_i_1_n_0\,
Q => data1(2),
R => '0'
);
\x0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[3]_i_1_n_0\,
Q => data1(3),
R => '0'
);
\x0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[4]_i_1_n_0\,
Q => data1(4),
R => '0'
);
\x0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[5]_i_1_n_0\,
Q => data1(5),
R => '0'
);
\x0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[6]_i_1_n_0\,
Q => data1(6),
R => '0'
);
\x0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[7]_i_1_n_0\,
Q => data1(7),
R => '0'
);
\x0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[8]_i_1_n_0\,
Q => data1(8),
R => '0'
);
\x0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[9]_i_2_n_0\,
Q => data1(9),
R => '0'
);
\x1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF01FF4EFE00B100"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \x_reg_n_0_[0]\,
I4 => cycle(3),
I5 => data1(0),
O => \x1[0]_i_1_n_0\
);
\x1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFEFAAA955565010"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => data1(1),
I5 => \x_reg_n_0_[1]\,
O => \x1[1]_i_1_n_0\
);
\x1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEAEAEAEFEAE"
)
port map (
I0 => \x1[2]_i_2_n_0\,
I1 => \x1[2]_i_3_n_0\,
I2 => cycle(3),
I3 => \x_reg_n_0_[2]\,
I4 => \x1[5]_i_3_n_0\,
I5 => data1(2),
O => \x1[2]_i_1_n_0\
);
\x1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A2A288880202888"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x_reg_n_0_[2]\,
I2 => cycle(0),
I3 => \x_reg_n_0_[1]\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \x1[2]_i_2_n_0\
);
\x1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3CAAAAAA00000000"
)
port map (
I0 => data1(2),
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[2]_i_3_n_0\
);
\x1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[3]_i_2_n_0\,
I1 => \x1[3]_i_3_n_0\,
I2 => data1(3),
I3 => cycle(3),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[3]_i_1_n_0\
);
\x1[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0770707077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data1(3),
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x0[8]_i_5_n_0\,
O => \x1[3]_i_2_n_0\
);
\x1[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[3]_i_4_n_0\,
O => \x1[3]_i_3_n_0\
);
\x1[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[2]\,
O => \x1[3]_i_4_n_0\
);
\x1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[4]_i_2_n_0\,
I1 => \x1[4]_i_3_n_0\,
I2 => data1(4),
I3 => cycle(3),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[4]_i_1_n_0\
);
\x1[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data1(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x1[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[4]_i_2_n_0\
);
\x1[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[4]_i_5_n_0\,
O => \x1[4]_i_3_n_0\
);
\x1[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_4_n_0\
);
\x1[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_5_n_0\
);
\x1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => \x1[5]_i_2_n_0\,
I1 => data1(5),
I2 => \x1[5]_i_3_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => cycle(3),
O => \x1[5]_i_1_n_0\
);
\x1[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDFDCDCDFDFDFDCD"
)
port map (
I0 => \x1[5]_i_4_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[6]_i_8_n_0\,
I4 => data1(5),
I5 => \x1[5]_i_5_n_0\,
O => \x1[5]_i_2_n_0\
);
\x1[5]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
O => \x1[5]_i_3_n_0\
);
\x1[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0530FA3FF5300A3F"
)
port map (
I0 => \x1[6]_i_7_n_0\,
I1 => data1(5),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[5]\,
I5 => \left[15]_i_3_n_0\,
O => \x1[5]_i_4_n_0\
);
\x1[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555666"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[4]\,
O => \x1[5]_i_5_n_0\
);
\x1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[6]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[6]_i_4_n_0\,
O => \x1[6]_i_1_n_0\
);
\x1[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05050CFC05F5F"
)
port map (
I0 => data1(6),
I1 => \x1[6]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[6]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[6]\,
O => \x1[6]_i_2_n_0\
);
\x1[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A900FF00A9000000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x1[6]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \x1[6]_i_8_n_0\,
I5 => data1(6),
O => \x1[6]_i_3_n_0\
);
\x1[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(6),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[6]\,
O => \x1[6]_i_4_n_0\
);
\x1[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_5_n_0\
);
\x1[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555666"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_6_n_0\
);
\x1[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x1[6]_i_7_n_0\
);
\x1[6]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
O => \x1[6]_i_8_n_0\
);
\x1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[7]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[7]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[7]_i_4_n_0\,
O => \x1[7]_i_1_n_0\
);
\x1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"303F5050CFC05F5F"
)
port map (
I0 => data1(7),
I1 => \x1[7]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[9]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[7]\,
O => \x1[7]_i_2_n_0\
);
\x1[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F0F090000000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x1[9]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \x1[7]_i_3_n_0\
);
\x1[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(7),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[7]_i_4_n_0\
);
\x1[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[4]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[7]_i_5_n_0\
);
\x1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => \x1[8]_i_2_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[8]_i_3_n_0\,
O => \x1[8]_i_1_n_0\
);
\x1[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA300A3F0A30FA3F"
)
port map (
I0 => \x1[8]_i_4_n_0\,
I1 => data1(8),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[8]\,
I5 => \left[15]_i_2_n_0\,
O => \x1[8]_i_2_n_0\
);
\x1[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[8]_i_5_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(8),
I4 => cycle(3),
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_3_n_0\
);
\x1[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555556"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x1[6]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[8]_i_4_n_0\
);
\x1[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000002"
)
port map (
I0 => \x1[8]_i_6_n_0\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[6]_i_7_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_5_n_0\
);
\x1[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x1[8]_i_6_n_0\
);
\x1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008880880880"
)
port map (
I0 => active,
I1 => rst,
I2 => cycle(0),
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => x1
);
\x1[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000047"
)
port map (
I0 => \x1[9]_i_3_n_0\,
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x1[9]_i_4_n_0\,
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \x1[9]_i_5_n_0\,
O => \x1[9]_i_2_n_0\
);
\x1[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C335555"
)
port map (
I0 => data1(9),
I1 => \x_reg_n_0_[9]\,
I2 => \x_reg_n_0_[8]\,
I3 => \left[15]_i_2_n_0\,
I4 => cycle(0),
O => \x1[9]_i_3_n_0\
);
\x1[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0100FEFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[9]_i_6_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[9]\,
O => \x1[9]_i_4_n_0\
);
\x1[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[9]_i_8_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(9),
I4 => cycle(3),
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_5_n_0\
);
\x1[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFE"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x_reg_n_0_[4]\,
O => \x1[9]_i_6_n_0\
);
\x1[9]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \x1[9]_i_7_n_0\
);
\x1[9]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x1[9]_i_6_n_0\,
I3 => \x_reg_n_0_[7]\,
I4 => \x_reg_n_0_[8]\,
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_8_n_0\
);
\x1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[0]_i_1_n_0\,
Q => data2(0),
R => '0'
);
\x1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[1]_i_1_n_0\,
Q => data2(1),
R => '0'
);
\x1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[2]_i_1_n_0\,
Q => data2(2),
R => '0'
);
\x1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[3]_i_1_n_0\,
Q => data2(3),
R => '0'
);
\x1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[4]_i_1_n_0\,
Q => data2(4),
R => '0'
);
\x1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[5]_i_1_n_0\,
Q => data2(5),
R => '0'
);
\x1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[6]_i_1_n_0\,
Q => data2(6),
R => '0'
);
\x1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[7]_i_1_n_0\,
Q => data2(7),
R => '0'
);
\x1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[8]_i_1_n_0\,
Q => data2(8),
R => '0'
);
\x1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[9]_i_2_n_0\,
Q => data2(9),
R => '0'
);
\x[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => x
);
\x_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(0),
Q => \x_reg_n_0_[0]\,
R => '0'
);
\x_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(1),
Q => \x_reg_n_0_[1]\,
R => '0'
);
\x_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(2),
Q => \x_reg_n_0_[2]\,
R => '0'
);
\x_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(3),
Q => \x_reg_n_0_[3]\,
R => '0'
);
\x_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(4),
Q => \x_reg_n_0_[4]\,
R => '0'
);
\x_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(5),
Q => \x_reg_n_0_[5]\,
R => '0'
);
\x_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(6),
Q => \x_reg_n_0_[6]\,
R => '0'
);
\x_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(7),
Q => \x_reg_n_0_[7]\,
R => '0'
);
\x_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(8),
Q => \x_reg_n_0_[8]\,
R => '0'
);
\x_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(9),
Q => \x_reg_n_0_[9]\,
R => '0'
);
\y1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y1[2]_i_1_n_0\
);
\y1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
I3 => \y_actual_reg_n_0_[3]\,
O => \y1[3]_i_1_n_0\
);
\y1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[0]_i_1_n_0\,
Q => \y1_reg_n_0_[0]\,
R => '0'
);
\y1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[1]_i_1_n_0\,
Q => \y1_reg_n_0_[1]\,
R => '0'
);
\y1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[2]_i_1_n_0\,
Q => \y1_reg_n_0_[2]\,
R => '0'
);
\y1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[3]_i_1_n_0\,
Q => \y1_reg_n_0_[3]\,
R => '0'
);
\y2[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
O => \y2[1]_i_1_n_0\
);
\y2[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y2[2]_i_1_n_0\
);
\y2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y2[3]_i_1_n_0\
);
\y2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y_actual_reg_n_0_[0]\,
Q => \y2_reg_n_0_[0]\,
R => '0'
);
\y2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[1]_i_1_n_0\,
Q => \y2_reg_n_0_[1]\,
R => '0'
);
\y2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[2]_i_1_n_0\,
Q => \y2_reg_n_0_[2]\,
R => '0'
);
\y2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[3]_i_1_n_0\,
Q => \y2_reg_n_0_[3]\,
R => '0'
);
\y3[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y3[1]_i_1_n_0\
);
\y3[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"87"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y3[2]_i_1_n_0\
);
\y3[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y3[3]_i_1_n_0\
);
\y3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y5[0]_i_1_n_0\,
Q => \y3_reg_n_0_[0]\,
R => '0'
);
\y3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[1]_i_1_n_0\,
Q => \y3_reg_n_0_[1]\,
R => '0'
);
\y3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[2]_i_1_n_0\,
Q => \y3_reg_n_0_[2]\,
R => '0'
);
\y3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[3]_i_1_n_0\,
Q => \y3_reg_n_0_[3]\,
R => '0'
);
\y4[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
O => \y4[2]_i_1_n_0\
);
\y4[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y4[3]_i_1_n_0\
);
\y4_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[0]\,
Q => data2(10),
R => '0'
);
\y4_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[1]\,
Q => data2(11),
R => '0'
);
\y4_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[2]_i_1_n_0\,
Q => data2(12),
R => '0'
);
\y4_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[3]_i_1_n_0\,
Q => data2(13),
R => '0'
);
\y5[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
O => \y5[0]_i_1_n_0\
);
\y5[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[0]\,
O => \y5[1]_i_1_n_0\
);
\y5[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y5[2]_i_1_n_0\
);
\y5[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A955"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y5[3]_i_1_n_0\
);
\y5_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[0]_i_1_n_0\,
Q => data1(10),
R => '0'
);
\y5_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[1]_i_1_n_0\,
Q => data1(11),
R => '0'
);
\y5_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[2]_i_1_n_0\,
Q => data1(12),
R => '0'
);
\y5_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[3]_i_1_n_0\,
Q => data1(13),
R => '0'
);
\y6[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y6[2]_i_1_n_0\
);
\y6[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y6[3]_i_1_n_0\
);
\y6_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y_actual_reg_n_0_[0]\,
Q => \y6_reg_n_0_[0]\,
R => '0'
);
\y6_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y2[1]_i_1_n_0\,
Q => \y6_reg_n_0_[1]\,
R => '0'
);
\y6_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[2]_i_1_n_0\,
Q => \y6_reg_n_0_[2]\,
R => '0'
);
\y6_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[3]_i_1_n_0\,
Q => \y6_reg_n_0_[3]\,
R => '0'
);
\y7[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y7[2]_i_1_n_0\
);
\y7[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y7[3]_i_1_n_0\
);
\y7_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y5[0]_i_1_n_0\,
Q => y7(0),
R => '0'
);
\y7_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y3[1]_i_1_n_0\,
Q => y7(1),
R => '0'
);
\y7_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[2]_i_1_n_0\,
Q => y7(2),
R => '0'
);
\y7_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[3]_i_1_n_0\,
Q => y7(3),
R => '0'
);
\y8[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
O => \y8[3]_i_1_n_0\
);
\y8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[0]\,
Q => y8(0),
R => '0'
);
\y8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[1]\,
Q => y8(1),
R => '0'
);
\y8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[2]\,
Q => y8(2),
R => '0'
);
\y8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y8[3]_i_1_n_0\,
Q => y8(3),
R => '0'
);
\y9[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y9[3]_i_1_n_0\
);
\y9_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[0]_i_1_n_0\,
Q => data5(10),
R => '0'
);
\y9_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[1]_i_1_n_0\,
Q => data5(11),
R => '0'
);
\y9_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y1[2]_i_1_n_0\,
Q => data5(12),
R => '0'
);
\y9_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y9[3]_i_1_n_0\,
Q => data5(13),
R => '0'
);
\y_actual_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(0),
Q => \y_actual_reg_n_0_[0]\,
R => '0'
);
\y_actual_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(1),
Q => \y_actual_reg_n_0_[1]\,
R => '0'
);
\y_actual_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(2),
Q => \y_actual_reg_n_0_[2]\,
R => '0'
);
\y_actual_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(3),
Q => \y_actual_reg_n_0_[3]\,
R => '0'
);
\y_actual_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(4),
Q => \y_actual_reg_n_0_[4]\,
R => '0'
);
\y_actual_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(5),
Q => \y_actual_reg_n_0_[5]\,
R => '0'
);
\y_actual_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(6),
Q => \y_actual_reg_n_0_[6]\,
R => '0'
);
\y_actual_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(7),
Q => \y_actual_reg_n_0_[7]\,
R => '0'
);
\y_actual_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(8),
Q => \y_actual_reg_n_0_[8]\,
R => '0'
);
\y_actual_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(9),
Q => \y_actual_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_hessian_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_0_0 : entity is "system_vga_hessian_0_0,vga_hessian,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_0_0 : entity is "vga_hessian,Vivado 2016.4";
end system_vga_hessian_0_0;
architecture STRUCTURE of system_vga_hessian_0_0 is
begin
U0: entity work.system_vga_hessian_0_0_vga_hessian
port map (
active => active,
clk_x16 => clk_x16,
g_in(7 downto 0) => g_in(7 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
rst => rst,
x_addr(9 downto 0) => x_addr(9 downto 0),
y_addr(9 downto 0) => y_addr(9 downto 0)
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity lutFile is
generic (
gLutCount : natural := 4;
gLutWidth : natural := 32;
gLutInitValue : std_logic_vector :=
x"1111_1111" & x"2222_2222" & x"3333_3333" & x"4444_4444"
);
port (
iAddrRead : in std_logic_vector(LogDualis(gLutCount)-1 downto 0);
oData : out std_logic_vector
);
end lutFile;
architecture Rtl of lutFile is
constant cLutFile : std_logic_vector(gLutCount*gLutWidth-1 downto 0) :=
gLutInitValue;
signal lutOutput : std_logic_vector(gLutWidth-1 downto 0);
begin
--Lut File is a bitstream that is blockwise (gLutWidth) read with
--respect to iAddrRead.
bitSelect : process(iAddrRead)
begin
--default
lutOutput <= (others => '0');
for i in gLutWidth-1 downto 0 loop
--assign selected bits in Lut File to output
lutOutput(i) <= cLutFile
( (gLutCount-1-to_integer(unsigned(iAddrRead)))*gLutWidth + i );
end loop;
end process;
--! downscale lut width to output
oData <= lutOutput(oData'range);
end Rtl;
|
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
architecture RTL of FIFO is
type state_machine is (IDLE, WRITE, READ, DONE);
-- Violations below
type state_machine is (IDLE, WRITE, READ, DONE);
begin
end architecture RTL;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY KUNGFUMASTER_BROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END KUNGFUMASTER_BROM;
ARCHITECTURE KUNGFUMASTER_BROM_arch OF KUNGFUMASTER_BROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF KUNGFUMASTER_BROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF KUNGFUMASTER_BROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF KUNGFUMASTER_BROM_arch : ARCHITECTURE IS "KUNGFUMASTER_BROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF KUNGFUMASTER_BROM_arch: ARCHITECTURE IS "KUNGFUMASTER_BROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=KUNGFUMASTER_BROM.mif,C_INIT_FILE=KUNGFUMASTER_BROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "KUNGFUMASTER_BROM.mif",
C_INIT_FILE => "KUNGFUMASTER_BROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END KUNGFUMASTER_BROM_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config_types
-- File: config_types.vhd
-- Description: GRLIB Global configuration types package.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package config_types is
-----------------------------------------------------------------------------
-- Configuration constants part of GRLIB configuration array
-----------------------------------------------------------------------------
-- debug level and debug mask controls debug output from tech map
constant grlib_debug_level : integer := 0;
constant grlib_debug_mask : integer := 1;
-- Defines if strict RAM techmap should be used. Otherwise small (shallow)
-- RAMs may be mapped to inferred technology.
constant grlib_techmap_strict_ram : integer := 2;
-- Expand testin vector to syncrams with additional bits
constant grlib_techmap_testin_extra : integer := 3;
-- Add synchronous resets to all registers (requires support in IP cores)
constant grlib_sync_reset_enable_all : integer := 4;
-- Use asynchronous reset, with this option enabled all registers will be
-- reset using asynchronous reset (within IP cores that support this).
constant grlib_async_reset_enable : integer := 5;
type grlib_config_array_type is array (0 to 6) of integer;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module scales video streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_Scaler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 15; -- Frame's Data Width
EW :INTEGER := 0; -- Frame's Empty Width
WIW :INTEGER := 9; -- Incoming frame's width's address width
HIW :INTEGER := 7; -- Incoming frame's height's address width
WIDTH_IN :INTEGER := 640;
WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0101";
HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000";
MH_WW :INTEGER := 8; -- Multiply height's incoming width's address width
MH_WIDTH_IN :INTEGER := 320; -- Multiply height's incoming width
MH_CW :INTEGER := 0; -- Multiply height's counter width
MW_CW :INTEGER := 0 -- Multiply width's counter width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_Scaler;
ARCHITECTURE Behaviour OF Video_System_Video_Scaler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL internal_startofpacket :STD_LOGIC;
SIGNAL internal_endofpacket :STD_LOGIC;
SIGNAL internal_valid :STD_LOGIC;
SIGNAL internal_ready :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_scaler_shrink
GENERIC (
DW :INTEGER;
WW :INTEGER;
HW :INTEGER;
WIDTH_IN :INTEGER;
WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0);
HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_out_empty <= (OTHERS => '0');
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Shrink_Frame : altera_up_video_scaler_shrink
GENERIC MAP (
DW => DW,
WW => WIW,
HW => HIW,
WIDTH_IN => WIDTH_IN,
WIDTH_DROP_MASK => WIDTH_DROP_MASK,
HEIGHT_DROP_MASK => HEIGHT_DROP_MASK
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => stream_in_data,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_valid => stream_in_valid,
stream_out_ready => stream_out_ready,
-- Bidirectional
-- Outputs
stream_in_ready => stream_in_ready,
stream_out_data => stream_out_data,
stream_out_startofpacket => stream_out_startofpacket,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_valid => stream_out_valid
);
END Behaviour;
|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package Constants is
subtype Byte is std_logic_vector (7 downto 0);
-- FIXME: Change "16" to "4095" when using GHDL simulator.
type MemoryArray is array(0 to 110) of Byte;
subtype Word is std_logic_vector (31 downto 0);
subtype Opcode is std_logic_vector (2 downto 0);
subtype Operator is std_logic_vector (2 downto 0);
subtype RegisterReference is std_logic_vector (4 downto 0);
subtype ImmediateValue is std_logic_vector (15 downto 0);
subtype ImmediateAddress is std_logic_vector (25 downto 0);
subtype ImmediateConditionalAddress is std_logic_vector(20 downto 0);
function GetOpcode (
W : Word)
return std_logic_vector; --Opcode
function GetOperator (
W : Word)
return std_logic_vector; --Operator
function GetRegisterReferenceA (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceB (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceC (
W : Word)
return std_logic_vector; --RegisterReference
function GetRegisterReferenceD (
W : Word)
return std_logic_vector; --RegisterReference
function GetImmediateValue (
W : Word)
return std_logic_vector; --ImmediateValue
function GetImmediateAddress (
W : Word)
return std_logic_vector; --ImmediateAddress
function GetImmediateConditionalAddress
( W : Word)
return std_logic_vector; --ImmediateConditionalAddress
function SignExtendImmediateValue (
VALUE : ImmediateValue)
return std_logic_vector; --Word
function SignExtendImmediateAddress (
ADDR : ImmediateAddress)
return std_logic_vector; --Word
function SignExtendImmediateConditionalAddress (
ADDR : ImmediateConditionalAddress)
return std_logic_vector; --Word
function GetIRQ (
IRQ : std_logic_vector(23 downto 0))
return integer;
constant OpcodeLogical : opcode := "000";
constant OpcodeArithmetic : opcode := "001";
constant OpcodeShift : opcode := "010";
constant OpcodeRelational : opcode := "011";
constant OpcodeMemory : opcode := "100";
constant OpcodePort : opcode := "101";
constant OpcodeBranch : opcode := "110";
constant RegisterMode : std_logic := '0';
constant ImmediateMode : std_logic := '1';
constant LoadByteUnsigned : Operator := "000";
constant LoadByteSigned : Operator := "001";
constant LoadHalfWordUnsigned : Operator := "010";
constant LoadHalfWordSigned : Operator := "011";
constant LoadWord : Operator := "100";
constant StoreByte : Operator := "101";
constant StoreHalfWord : Operator := "110";
constant StoreWord : Operator := "111";
constant NormalAOnly : std_logic_vector(1 downto 0) := "00";
constant DivideOverflow : std_logic_vector(1 downto 0) := "01";
constant NormalAAndD : std_logic_vector(1 downto 0) := "10";
constant GenericError : std_logic_vector(1 downto 0) := "11";
constant InterruptTableADDR : Word := "11111111111111111111111110000000";
constant JumpToReg29 : Word := "11000000000111010000000000000000";
end Constants;
package body Constants is
function GetOpcode (
W : Word)
return std_logic_vector is --Opcode
begin
return w (31 downto 29);
end;
function GetOperator (
W : Word)
return std_logic_vector is --Operator
begin
return w (28 downto 26);
end;
function GetRegisterReferenceA (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (25 downto 21);
end;
function GetRegisterReferenceB (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (20 downto 16);
end;
function GetRegisterReferenceC (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (15 downto 11);
end;
function GetRegisterReferenceD (
W : Word)
return std_logic_vector is --RegisterReference
begin
return w (10 downto 6);
end;
function GetImmediateValue (
W : Word)
return std_logic_vector is --ImmediateValue
begin
return w (15 downto 0);
end;
function GetImmediateAddress (
W : Word)
return std_logic_vector is --ImmediateAddress
begin
return w (25 downto 0);
end;
function GetImmediateConditionalAddress (
W : Word)
return std_logic_vector is --ImmediateConditionalAddress
begin
return w (20 downto 0);
end;
function SignExtendImmediateValue (
VALUE : ImmediateValue)
return std_logic_vector is --Word
begin -- SignExtendImmediate
return std_logic_vector(resize(signed(VALUE), 32));
end SignExtendImmediateValue;
function SignExtendImmediateAddress (
ADDR : ImmediateAddress)
return std_logic_vector is --Word
begin -- SignExtendImmediateAddress
return std_logic_vector(resize(signed(unsigned(ADDR) & "00"), 32));
end SignExtendImmediateAddress;
function SignExtendImmediateConditionalAddress (
ADDR : ImmediateConditionalAddress)
return std_logic_vector is --Word
begin -- SignExtendImmediateAddress
return std_logic_vector(resize(signed(unsigned(ADDR) & "00"), 32));
end SignExtendImmediateConditionalAddress;
function GetIRQ(
IRQ : std_logic_vector(23 downto 0))
return integer is
begin
for i in 0 to 23 loop
if IRQ (i) /= '0' then
return i;
end if;
end loop; -- i
return -1;
end GetIRQ;
end Constants;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sun Oct 4 22:06:59 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/cmbarker/Private/Atari7800/lab3sound/lab3sound.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl
-- Design : blk_mem_gen_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blk_mem_gen_0 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end blk_mem_gen_0;
architecture stub of blk_mem_gen_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[16:0],dina[15:0],clkb,enb,addrb[16:0],doutb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_2,Vivado 2015.2";
begin
end;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mux.vhd: Generic multiplexer
-- Copyright (C) 2006 CESNET
-- Author(s): Martin Kosek <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mux.vhd 14 2007-07-31 06:44:05Z kosek $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- library containing log2 function
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity GEN_MUX is
generic(
DATA_WIDTH : integer;
MUX_WIDTH : integer -- multiplexer width (number of inputs)
);
port(
DATA_IN : in std_logic_vector(DATA_WIDTH*MUX_WIDTH-1 downto 0);
SEL : in std_logic_vector(log2(MUX_WIDTH)-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity GEN_MUX;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture full of GEN_MUX is
begin
genmuxp:process(SEL, DATA_IN)
begin
DATA_OUT <= DATA_IN(DATA_WIDTH-1 downto 0);
for i in 0 to MUX_WIDTH-1 loop
if(conv_std_logic_vector(i, log2(MUX_WIDTH)) = SEL) then
DATA_OUT <= DATA_IN(((i+1)*DATA_WIDTH)-1 downto i*DATA_WIDTH);
end if;
end loop;
end process;
end architecture full;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
for_label : for i in 0 to 7 generate
end generate;
if_label : if a = '1' generate
end generate;
case_label : case data generate
end generate;
end;
|
entity repro is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of repro is
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
subtype ST_AXILite_32 is t_axilite_if (
write_address_channel (
awaddr(31 downto 0) ),
write_data_channel (
wdata(31 downto 0),
wstrb(3 downto 0) ),
read_address_channel (
araddr(31 downto 0) ),
read_data_channel (
rdata(31 downto 0) )
);
signal s : st_axilite_32;
begin
s.write_address_channel.awaddr <= x"0000_1000", x"1000_ffff" after 2 ns;
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer0 is
generic (
abits0 : integer := 5;
dbits0 : integer := 64
);
port (
i_clk0 : in std_logic;
i_raddr0 : in std_logic_vector(abits0-1 downto 0);
o_rdata0 : out std_logic_vector(dbits0-1 downto 0);
i_we0 : in std_logic;
i_waddr0 : in std_logic_vector(abits0-1 downto 0);
i_wdata0 : in std_logic_vector(dbits0-1 downto 0)
);
end;
architecture arch_StackTraceBuffer0 of StackTraceBuffer0 is
type ram_type0 is array ((2**abits0)-1 downto 0) of std_logic_vector (dbits0-1 downto 0);
signal stackbuf0 : ram_type0;
signal raddr0 : std_logic_vector(abits0-1 downto 0);
begin
-- registers:
process(i_clk0) begin
if rising_edge(i_clk0) then
if i_we0 = '1' then
stackbuf0(conv_integer(i_waddr0)) <= i_wdata0;
end if;
raddr0 <= i_raddr0;
end if;
end process;
o_rdata0 <= stackbuf0(conv_integer(raddr0));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer0 is
generic (
abits0 : integer := 5;
dbits0 : integer := 64
);
port (
i_clk0 : in std_logic;
i_raddr0 : in std_logic_vector(abits0-1 downto 0);
o_rdata0 : out std_logic_vector(dbits0-1 downto 0);
i_we0 : in std_logic;
i_waddr0 : in std_logic_vector(abits0-1 downto 0);
i_wdata0 : in std_logic_vector(dbits0-1 downto 0)
);
end;
architecture arch_StackTraceBuffer0 of StackTraceBuffer0 is
type ram_type0 is array ((2**abits0)-1 downto 0) of std_logic_vector (dbits0-1 downto 0);
signal stackbuf0 : ram_type0;
signal raddr0 : std_logic_vector(abits0-1 downto 0);
begin
-- registers:
process(i_clk0) begin
if rising_edge(i_clk0) then
if i_we0 = '1' then
stackbuf0(conv_integer(i_waddr0)) <= i_wdata0;
end if;
raddr0 <= i_raddr0;
end if;
end process;
o_rdata0 <= stackbuf0(conv_integer(raddr0));
end;
|
entity repro1 is
end entity;
architecture A of repro1 is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
-- partially constrained array -> constrained outer array (vector)
subtype P2 is A(15 downto 0)(open);
signal S2 : P2(open)(7 downto 0); -- fully constrained.
begin
end architecture;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Testbench
--
-- $Id: tb.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
entity tb is
end tb;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb is
component tb_elem
generic (
chip_type_g : string := "none";
has_sd_card_g : integer := 1
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
eos_o : out boolean
);
end component;
constant period_c : time := 100 ns;
constant reset_level_c : integer := 0;
signal clk_s : std_logic;
signal reset_s : std_logic;
signal eos_full_s,
eos_mmc_s,
eos_sd_s,
eos_minimal_s : boolean;
begin
-----------------------------------------------------------------------------
-- Testbench element including full featured chip
-----------------------------------------------------------------------------
tb_elem_full_b : tb_elem
generic map (
chip_type_g => "Full Chip",
has_sd_card_g => 1
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_full_s
);
-----------------------------------------------------------------------------
-- Testbench element including MMC chip
-----------------------------------------------------------------------------
tb_elem_mmc_b : tb_elem
generic map (
chip_type_g => "MMC Chip",
has_sd_card_g => 0
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_mmc_s
);
-----------------------------------------------------------------------------
-- Testbench element including SD chip
-----------------------------------------------------------------------------
tb_elem_sd_b : tb_elem
generic map (
chip_type_g => "SD Chip",
has_sd_card_g => 1
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_sd_s
);
-----------------------------------------------------------------------------
-- Testbench element including cip with minimal features
-----------------------------------------------------------------------------
tb_elem_minimal_b : tb_elem
generic map (
chip_type_g => "Minimal Chip",
has_sd_card_g => 0
)
port map (
clk_i => clk_s,
reset_i => reset_s,
eos_o => eos_minimal_s
);
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End Of Simulation Detection
-----------------------------------------------------------------------------
eos: process (eos_full_s,
eos_mmc_s,
eos_sd_s,
eos_minimal_s)
begin
if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
assert false
report "End of Simulation."
severity failure;
end if;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity ex_reg is
port(
clk : in vl_logic;
reset : in vl_logic;
alu_out : in vl_logic_vector(31 downto 0);
alu_of : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
int_detect : in vl_logic;
id_pc : in vl_logic_vector(29 downto 0);
id_en : in vl_logic;
id_br_flag : in vl_logic;
id_mem_op : in vl_logic_vector(1 downto 0);
id_mem_wr_data : in vl_logic_vector(31 downto 0);
id_ctrl_op : in vl_logic_vector(1 downto 0);
id_dst_addr : in vl_logic_vector(4 downto 0);
id_gpr_we_n : in vl_logic;
id_exp_code : in vl_logic_vector(2 downto 0);
ex_pc : out vl_logic_vector(29 downto 0);
ex_en : out vl_logic;
ex_br_flag : out vl_logic;
ex_mem_op : out vl_logic_vector(1 downto 0);
ex_mem_wr_data : out vl_logic_vector(31 downto 0);
ex_ctrl_op : out vl_logic_vector(1 downto 0);
ex_dst_addr : out vl_logic_vector(4 downto 0);
ex_gpr_we_n : out vl_logic;
ex_exp_code : out vl_logic_vector(2 downto 0);
ex_out : out vl_logic_vector(31 downto 0)
);
end ex_reg;
|
architecture RTL of FIFO is
begin
process
begin
a <= b;
end process;
-- Violations below
process
begin
a <= b;
end process;
end architecture RTL;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Fri Sep 26 21:45:04 2014
-- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_stub.vhdl
-- Design : cascaded_integrator_comb
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cascaded_integrator_comb is
Port (
aclk : in STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC
);
end cascaded_integrator_comb;
architecture stub of cascaded_integrator_comb is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tdata[7:0],s_axis_data_tvalid,s_axis_data_tready,m_axis_data_tdata[23:0],m_axis_data_tvalid";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "cic_compiler_v4_0,Vivado 2014.2";
begin
end;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end usb_system_mm_interconnect_0_router;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
architecture Behavioral of opcode_fetch is
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
begin
PC <= LPC;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LPC <= X"0000";
elsif (CE = '1' and T2 = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end process;
end Behavioral;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_40.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_40 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END clk_40;
ARCHITECTURE SYN OF clk_40 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "3000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=clk_40",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_40.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "3000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_40_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#00f3#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#00002B#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fffe#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_wm is
Port ( RDin : in STD_LOGIC_VECTOR (5 downto 0);
o15 : in STD_LOGIC_VECTOR (5 downto 0);
RFDest : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0)
);
end MUX_wm;
architecture Behavioral of MUX_wm is
begin
process(RDin, RFDest, o15) begin
if (RFDest = '1') then
nRD <= o15;
else
nRD <= RDin;
end if;
end process;
end Behavioral;
|
architecture arch of entity1 is
begin
block_label : block is
type type1;
begin
end block block_label;
end architecture arch;
|
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: testb_20_01.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity testb_20_01 is
end testb_20_01;
architecture behavioral of testb_20_01 is
constant SYSCLK_PERIOD : time := 50 ns;
signal SYSCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
component Top
-- ports
port(
-- Inputs
CLKA : in std_logic;
PAD : in std_logic;
NSYSRESET : in std_logic;
BUTTON_1 : in std_logic;
BUTTON_2 : in std_logic;
-- Outputs
h_sync : out std_logic;
v_sync : out std_logic;
red : out std_logic;
green : out std_logic;
blue : out std_logic
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- 10MHz Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
-- Instantiate Unit Under Test: Top
Top_0 : Top
-- port map
port map(
-- Inputs
CLKA => SYSCLK,
PAD => '0',
NSYSRESET => NSYSRESET,
BUTTON_1 => '1',
BUTTON_2 => '0',
-- Outputs
h_sync => open,
v_sync => open,
red => open,
green => open,
blue => open
-- Inouts
);
end behavioral;
|
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- lpddr2ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_ca : out std_logic_vector(9 downto 0); -- memory.mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- .readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rzqin : in std_logic := '0'; -- oct.rzqin
pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
pll_write_clk : out std_logic; -- .pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
pll_locked : out std_logic; -- .pll_locked
pll_avl_clk : out std_logic; -- .pll_avl_clk
pll_config_clk : out std_logic; -- .pll_config_clk
pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
afi_phy_clk : out std_logic; -- .afi_phy_clk
pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
);
end entity lpddr2ctrl1;
architecture rtl of lpddr2ctrl1 is
component lpddr2ctrl1_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1_0002;
begin
lpddr2ctrl1_inst : component lpddr2ctrl1_0002
port map (
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
global_reset_n => global_reset_n, -- global_reset.reset_n
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
afi_clk => afi_clk, -- afi_clk.clk
afi_half_clk => afi_half_clk, -- afi_half_clk.clk
afi_reset_n => afi_reset_n, -- afi_reset.reset_n
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
mem_ca => mem_ca, -- memory.mem_ca
mem_ck => mem_ck, -- .mem_ck
mem_ck_n => mem_ck_n, -- .mem_ck_n
mem_cke => mem_cke, -- .mem_cke
mem_cs_n => mem_cs_n, -- .mem_cs_n
mem_dm => mem_dm, -- .mem_dm
mem_dq => mem_dq, -- .mem_dq
mem_dqs => mem_dqs, -- .mem_dqs
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
avl_ready => avl_ready, -- avl.waitrequest_n
avl_burstbegin => avl_burstbegin, -- .beginbursttransfer
avl_addr => avl_addr, -- .address
avl_rdata_valid => avl_rdata_valid, -- .readdatavalid
avl_rdata => avl_rdata, -- .readdata
avl_wdata => avl_wdata, -- .writedata
avl_be => avl_be, -- .byteenable
avl_read_req => avl_read_req, -- .read
avl_write_req => avl_write_req, -- .write
avl_size => avl_size, -- .burstcount
local_init_done => local_init_done, -- status.local_init_done
local_cal_success => local_cal_success, -- .local_cal_success
local_cal_fail => local_cal_fail, -- .local_cal_fail
oct_rzqin => oct_rzqin, -- oct.rzqin
pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk
pll_write_clk => pll_write_clk, -- .pll_write_clk
pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk
pll_locked => pll_locked, -- .pll_locked
pll_avl_clk => pll_avl_clk, -- .pll_avl_clk
pll_config_clk => pll_config_clk, -- .pll_config_clk
pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk
afi_phy_clk => afi_phy_clk, -- .afi_phy_clk
pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk
);
end architecture rtl; -- of lpddr2ctrl1
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_mem_if_lpddr2_emif" version="13.0" >
-- Retrieval info: <generic name="MEM_VENDOR" value="Micron" />
-- Retrieval info: <generic name="MEM_FORMAT" value="DISCRETE" />
-- Retrieval info: <generic name="DISCRETE_FLY_BY" value="true" />
-- Retrieval info: <generic name="DEVICE_DEPTH" value="1" />
-- Retrieval info: <generic name="MEM_MIRROR_ADDRESSING" value="0" />
-- Retrieval info: <generic name="MEM_CLK_FREQ_MAX" value="400.0" />
-- Retrieval info: <generic name="MEM_ROW_ADDR_WIDTH" value="14" />
-- Retrieval info: <generic name="MEM_COL_ADDR_WIDTH" value="10" />
-- Retrieval info: <generic name="MEM_DQ_WIDTH" value="16" />
-- Retrieval info: <generic name="MEM_DQ_PER_DQS" value="8" />
-- Retrieval info: <generic name="MEM_BANKADDR_WIDTH" value="3" />
-- Retrieval info: <generic name="MEM_IF_DM_PINS_EN" value="true" />
-- Retrieval info: <generic name="MEM_IF_DQSN_EN" value="true" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_DIMMS" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-- Retrieval info: <generic name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-- Retrieval info: <generic name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-- Retrieval info: <generic name="MEM_CK_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CS_WIDTH" value="1" />
-- Retrieval info: <generic name="MEM_CLK_EN_WIDTH" value="1" />
-- Retrieval info: <generic name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-- Retrieval info: <generic name="NEXTGEN" value="true" />
-- Retrieval info: <generic name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-- Retrieval info: <generic name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-- Retrieval info: <generic name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-- Retrieval info: <generic name="MEM_VERBOSE" value="true" />
-- Retrieval info: <generic name="PINGPONGPHY_EN" value="false" />
-- Retrieval info: <generic name="REFRESH_BURST_VALIDATION" value="false" />
-- Retrieval info: <generic name="MEM_BL" value="8" />
-- Retrieval info: <generic name="MEM_BT" value="Sequential" />
-- Retrieval info: <generic name="MEM_DRV_STR" value="40" />
-- Retrieval info: <generic name="MEM_DLL_EN" value="true" />
-- Retrieval info: <generic name="MEM_ATCL" value="0" />
-- Retrieval info: <generic name="MEM_TCL" value="7" />
-- Retrieval info: <generic name="MEM_AUTO_LEVELING_MODE" value="true" />
-- Retrieval info: <generic name="MEM_USER_LEVELING_MODE" value="Leveling" />
-- Retrieval info: <generic name="MEM_INIT_EN" value="false" />
-- Retrieval info: <generic name="MEM_INIT_FILE" value="" />
-- Retrieval info: <generic name="DAT_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="TIMING_TIS" value="290" />
-- Retrieval info: <generic name="TIMING_TIH" value="290" />
-- Retrieval info: <generic name="TIMING_TDS" value="270" />
-- Retrieval info: <generic name="TIMING_TDH" value="270" />
-- Retrieval info: <generic name="TIMING_TDQSQ" value="240" />
-- Retrieval info: <generic name="TIMING_TQHS" value="280" />
-- Retrieval info: <generic name="TIMING_TDQSCK" value="5500" />
-- Retrieval info: <generic name="TIMING_TDQSCKDS" value="450" />
-- Retrieval info: <generic name="TIMING_TDQSCKDM" value="900" />
-- Retrieval info: <generic name="TIMING_TDQSCKDL" value="1200" />
-- Retrieval info: <generic name="TIMING_TDQSS" value="1.0" />
-- Retrieval info: <generic name="TIMING_TDQSH" value="0.4" />
-- Retrieval info: <generic name="TIMING_TDSH" value="0.2" />
-- Retrieval info: <generic name="TIMING_TDSS" value="0.2" />
-- Retrieval info: <generic name="MEM_TINIT_US" value="200" />
-- Retrieval info: <generic name="MEM_TMRD_CK" value="2" />
-- Retrieval info: <generic name="MEM_TRAS_NS" value="70.0" />
-- Retrieval info: <generic name="MEM_TRCD_NS" value="18.0" />
-- Retrieval info: <generic name="MEM_TRP_NS" value="18.0" />
-- Retrieval info: <generic name="MEM_TREFI_US" value="3.9" />
-- Retrieval info: <generic name="MEM_TRFC_NS" value="60.0" />
-- Retrieval info: <generic name="CFG_TCCD_NS" value="2.5" />
-- Retrieval info: <generic name="MEM_TWR_NS" value="15.0" />
-- Retrieval info: <generic name="MEM_TWTR" value="2" />
-- Retrieval info: <generic name="MEM_TFAW_NS" value="50.0" />
-- Retrieval info: <generic name="MEM_TRRD_NS" value="10.0" />
-- Retrieval info: <generic name="MEM_TRTP_NS" value="7.5" />
-- Retrieval info: <generic name="RATE" value="Half" />
-- Retrieval info: <generic name="MEM_CLK_FREQ" value="300.0" />
-- Retrieval info: <generic name="USE_MEM_CLK_FREQ" value="false" />
-- Retrieval info: <generic name="FORCE_DQS_TRACKING" value="AUTO" />
-- Retrieval info: <generic name="FORCE_SHADOW_REGS" value="AUTO" />
-- Retrieval info: <generic name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-- Retrieval info: <generic name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="DEVICE_FAMILY_PARAM" value="" />
-- Retrieval info: <generic name="SPEED_GRADE" value="7" />
-- Retrieval info: <generic name="IS_ES_DEVICE" value="false" />
-- Retrieval info: <generic name="DISABLE_CHILD_MESSAGING" value="false" />
-- Retrieval info: <generic name="HARD_EMIF" value="false" />
-- Retrieval info: <generic name="HHP_HPS" value="false" />
-- Retrieval info: <generic name="HHP_HPS_VERIFICATION" value="false" />
-- Retrieval info: <generic name="HHP_HPS_SIMULATION" value="false" />
-- Retrieval info: <generic name="HPS_PROTOCOL" value="DEFAULT" />
-- Retrieval info: <generic name="CUT_NEW_FAMILY_TIMING" value="true" />
-- Retrieval info: <generic name="POWER_OF_TWO_BUS" value="false" />
-- Retrieval info: <generic name="SOPC_COMPAT_RESET" value="false" />
-- Retrieval info: <generic name="AVL_MAX_SIZE" value="4" />
-- Retrieval info: <generic name="BYTE_ENABLE" value="true" />
-- Retrieval info: <generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-- Retrieval info: <generic name="CTL_DEEP_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="CTL_SELF_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="AUTO_POWERDN_EN" value="false" />
-- Retrieval info: <generic name="AUTO_PD_CYCLES" value="0" />
-- Retrieval info: <generic name="CTL_USR_REFRESH_EN" value="false" />
-- Retrieval info: <generic name="CTL_AUTOPCH_EN" value="false" />
-- Retrieval info: <generic name="CTL_ZQCAL_EN" value="false" />
-- Retrieval info: <generic name="ADDR_ORDER" value="0" />
-- Retrieval info: <generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-- Retrieval info: <generic name="CONTROLLER_LATENCY" value="5" />
-- Retrieval info: <generic name="CFG_REORDER_DATA" value="true" />
-- Retrieval info: <generic name="STARVE_LIMIT" value="10" />
-- Retrieval info: <generic name="CTL_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="CTL_ECC_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_HRB_ENABLED" value="false" />
-- Retrieval info: <generic name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-- Retrieval info: <generic name="MULTICAST_EN" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-- Retrieval info: <generic name="CTL_DYNAMIC_BANK_NUM" value="4" />
-- Retrieval info: <generic name="DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_BURST_MERGE" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
-- Retrieval info: <generic name="CTL_ENABLE_BURST_TERMINATE" value="false" />
-- Retrieval info: <generic name="LOCAL_ID_WIDTH" value="8" />
-- Retrieval info: <generic name="WRBUFFER_ADDR_WIDTH" value="6" />
-- Retrieval info: <generic name="MAX_PENDING_WR_CMD" value="8" />
-- Retrieval info: <generic name="MAX_PENDING_RD_CMD" value="16" />
-- Retrieval info: <generic name="USE_MM_ADAPTOR" value="true" />
-- Retrieval info: <generic name="USE_AXI_ADAPTOR" value="false" />
-- Retrieval info: <generic name="HCX_COMPAT_MODE" value="false" />
-- Retrieval info: <generic name="CTL_CMD_QUEUE_DEPTH" value="8" />
-- Retrieval info: <generic name="CTL_CSR_READ_ONLY" value="1" />
-- Retrieval info: <generic name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-- Retrieval info: <generic name="NUM_OF_PORTS" value="1" />
-- Retrieval info: <generic name="ENABLE_BONDING" value="false" />
-- Retrieval info: <generic name="ENABLE_USER_ECC" value="false" />
-- Retrieval info: <generic name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-- Retrieval info: <generic name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-- Retrieval info: <generic name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-- Retrieval info: <generic name="CPORT_TYPE_PORT" value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
-- Retrieval info: <generic name="ENABLE_EMIT_BFM_MASTER" value="false" />
-- Retrieval info: <generic name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-- Retrieval info: <generic name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ" value="125.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-- Retrieval info: <generic name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_DR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_DR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_HR_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_HR_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-- Retrieval info: <generic name="PLL_CLK_PARAM_VALID" value="false" />
-- Retrieval info: <generic name="ENABLE_EXTRA_REPORTING" value="false" />
-- Retrieval info: <generic name="NUM_EXTRA_REPORT_PATH" value="10" />
-- Retrieval info: <generic name="ENABLE_ISS_PROBES" value="false" />
-- Retrieval info: <generic name="CALIB_REG_WIDTH" value="8" />
-- Retrieval info: <generic name="USE_SEQUENCER_BFM" value="false" />
-- Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
-- Retrieval info: <generic name="PLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_PLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="EXPORT_AFI_HALF_CLK" value="false" />
-- Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-- Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-- Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
-- Retrieval info: <generic name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-- Retrieval info: <generic name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-- Retrieval info: <generic name="TRACKING_ERROR_TEST" value="false" />
-- Retrieval info: <generic name="TRACKING_WATCH_TEST" value="false" />
-- Retrieval info: <generic name="MARGIN_VARIATION_TEST" value="false" />
-- Retrieval info: <generic name="EXTRA_SETTINGS" value="" />
-- Retrieval info: <generic name="MEM_DEVICE" value="MISSING_MODEL" />
-- Retrieval info: <generic name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-- Retrieval info: <generic name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-- Retrieval info: <generic name="SEQUENCER_TYPE" value="NIOS" />
-- Retrieval info: <generic name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-- Retrieval info: <generic name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-- Retrieval info: <generic name="PHY_ONLY" value="false" />
-- Retrieval info: <generic name="SEQ_MODE" value="0" />
-- Retrieval info: <generic name="ADVANCED_CK_PHASES" value="false" />
-- Retrieval info: <generic name="COMMAND_PHASE" value="0.0" />
-- Retrieval info: <generic name="MEM_CK_PHASE" value="0.0" />
-- Retrieval info: <generic name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-- Retrieval info: <generic name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-- Retrieval info: <generic name="PLL_LOCATION" value="Top_Bottom" />
-- Retrieval info: <generic name="SKIP_MEM_INIT" value="false" />
-- Retrieval info: <generic name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-- Retrieval info: <generic name="DQ_INPUT_REG_USE_CLKN" value="false" />
-- Retrieval info: <generic name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-- Retrieval info: <generic name="AFI_DEBUG_INFO_WIDTH" value="32" />
-- Retrieval info: <generic name="CALIBRATION_MODE" value="Full" />
-- Retrieval info: <generic name="NIOS_ROM_DATA_WIDTH" value="32" />
-- Retrieval info: <generic name="READ_FIFO_SIZE" value="8" />
-- Retrieval info: <generic name="PHY_CSR_ENABLED" value="false" />
-- Retrieval info: <generic name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-- Retrieval info: <generic name="USER_DEBUG_LEVEL" value="0" />
-- Retrieval info: <generic name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TIH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDS" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_TDH" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-- Retrieval info: <generic name="PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="AC_PACKAGE_DESKEW" value="false" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_SKEW" value="0.02" />
-- Retrieval info: <generic name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-- Retrieval info: <generic name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-- Retrieval info: <generic name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-- Retrieval info: <generic name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-- Retrieval info: <generic name="ED_EXPORT_SEQ_DEBUG" value="false" />
-- Retrieval info: <generic name="ADD_EFFICIENCY_MONITOR" value="false" />
-- Retrieval info: <generic name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-- Retrieval info: <generic name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-- Retrieval info: <generic name="DLL_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_DLL_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="OCT_SHARING_MODE" value="None" />
-- Retrieval info: <generic name="NUM_OCT_SHARING_INTERFACES" value="1" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : lpddr2ctrl1.vho
-- RELATED_FILES: lpddr2ctrl1.vhd, lpddr2ctrl1_0002.v, lpddr2ctrl1_pll0.sv, lpddr2ctrl1_p0_clock_pair_generator.v, lpddr2ctrl1_p0_read_valid_selector.v, lpddr2ctrl1_p0_addr_cmd_datapath.v, lpddr2ctrl1_p0_reset.v, lpddr2ctrl1_p0_acv_ldc.v, lpddr2ctrl1_p0_memphy.sv, lpddr2ctrl1_p0_reset_sync.v, lpddr2ctrl1_p0_new_io_pads.v, lpddr2ctrl1_p0_fr_cycle_shifter.v, lpddr2ctrl1_p0_fr_cycle_extender.v, lpddr2ctrl1_p0_read_datapath.sv, lpddr2ctrl1_p0_write_datapath.v, lpddr2ctrl1_p0_simple_ddio_out.sv, lpddr2ctrl1_p0_phy_csr.sv, lpddr2ctrl1_p0_iss_probe.v, lpddr2ctrl1_p0_flop_mem.v, lpddr2ctrl1_p0_addr_cmd_pads.v, lpddr2ctrl1_p0.sv, lpddr2ctrl1_p0_altdqdqs.v, altdq_dqs2_acv_cyclonev_lpddr2.sv, afi_mux_lpddr2.v, lpddr2ctrl1_s0.v, rw_manager_bitcheck.v, rw_manager_datamux.v, lpddr2ctrl1_s0_id_router.sv, altera_merlin_traffic_limiter.sv, lpddr2ctrl1_s0_cmd_xbar_demux_001.sv, sequencer_trk_mgr.sv, lpddr2ctrl1_s0_addr_router_002.sv, sequencer_scc_sv_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_demux_003.sv, rw_manager_ac_ROM_reg.v, altera_merlin_burst_uncompressor.sv, rw_manager_read_datapath.v, rw_manager_lfsr12.v, rw_manager_lfsr36.v, rw_manager_data_broadcast.v, altera_avalon_mm_bridge.v, lpddr2ctrl1_s0_irq_mapper.sv, rw_manager_lfsr72.v, sequencer_reg_file.sv, rw_manager_di_buffer_wrap.v, rw_manager_jumplogic.v, altera_merlin_slave_agent.sv, altera_merlin_slave_translator.sv, altera_mem_if_sequencer_mem_no_ifdef_params.sv, lpddr2ctrl1_s0_cmd_xbar_mux.sv, sequencer_data_mgr.sv, sequencer_scc_reg_file.v, rw_manager_ram.v, rw_manager_lpddr2.v, rw_manager_ram_csr.v, rw_manager_generic.sv, altera_avalon_sc_fifo.v, altera_avalon_st_pipeline_base.v, lpddr2ctrl1_s0_id_router_003.sv, lpddr2ctrl1_s0_rsp_xbar_mux_003.sv, rw_manager_write_decoder.v, sequencer_scc_acv_wrapper.sv, rw_manager_ac_ROM_no_ifdef_params.v, lpddr2ctrl1_s0_id_router_001.sv, rw_manager_core.sv, sequencer_phy_mgr.sv, lpddr2ctrl1_s0_cmd_xbar_demux_003.sv, sequencer_scc_acv_phase_decode.v, lpddr2ctrl1_s0_addr_router.sv, sequencer_scc_siii_phase_decode.v, lpddr2ctrl1_s0_cmd_xbar_demux.sv, lpddr2ctrl1_s0_rsp_xbar_demux.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v, rw_manager_dm_decoder.v, lpddr2ctrl1_s0_addr_router_001.sv, rw_manager_inst_ROM_reg.v, rw_manager_data_decoder.v, sequencer_scc_mgr.sv, sequencer_scc_siii_wrapper.sv, lpddr2ctrl1_s0_rsp_xbar_mux.sv, altera_merlin_master_translator.sv, altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v, lpddr2ctrl1_s0_addr_router_003.sv, lpddr2ctrl1_s0_id_router_002.sv, rw_manager_di_buffer.v, rw_manager_pattern_fifo.v, altera_merlin_master_agent.sv, altera_merlin_arbitrator.sv, sequencer_scc_sv_phase_decode.v, rw_manager_inst_ROM_no_ifdef_params.v, altera_mem_if_sequencer_rst.sv, lpddr2ctrl1_c0.v, altera_mem_if_oct_cyclonev.sv, altera_mem_if_dll_cyclonev.sv, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_axi_st_converter.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_controller_st_top.v, alt_mem_if_nextgen_lpddr2_controller_core.sv, alt_mem_ddrx_mm_st_converter.v
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00650ent IS
END c03s04b01x00p01n01i00650ent;
ARCHITECTURE c03s04b01x00p01n01i00650arch OF c03s04b01x00p01n01i00650ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : resistance_file open read_mode is "iofile.63";
variable v : resistance;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C47) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00650"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00650 - File reading operation (resistance_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00650ent IS
END c03s04b01x00p01n01i00650ent;
ARCHITECTURE c03s04b01x00p01n01i00650arch OF c03s04b01x00p01n01i00650ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : resistance_file open read_mode is "iofile.63";
variable v : resistance;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C47) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00650"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00650 - File reading operation (resistance_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00650ent IS
END c03s04b01x00p01n01i00650ent;
ARCHITECTURE c03s04b01x00p01n01i00650arch OF c03s04b01x00p01n01i00650ent IS
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_file is file of resistance;
constant C47 : resistance := 1 Ohm;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : resistance_file open read_mode is "iofile.63";
variable v : resistance;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C47) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00650"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00650 - File reading operation (resistance_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00650arch;
|
entity seatbelt is
port (k, p, s, t: in BIT; w: out BIT);
end entity seatbelt;
architecture arch1 of seatbelt is
begin
w <= k and p and not s or t;
end architecture arch1
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
p_mix_case_go : out std_ulogic
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--
-- A simulation model of VIC20 hardware - VIA implementation
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
--
-- Revision list
--
-- version 005 Many fixes to all areas, VIA now passes all VICE tests
-- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation
-- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS)
-- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger
-- version 002 fix from Mark McDougall, untested
-- version 001 initial release
-- not very sure about the shift register, documentation is a bit light.
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity M6522 is
port (
I_RS : in std_logic_vector(3 downto 0);
I_DATA : in std_logic_vector(7 downto 0);
O_DATA : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
I_RW_L : in std_logic;
I_CS1 : in std_logic;
I_CS2_L : in std_logic;
O_IRQ_L : out std_logic; -- note, not open drain
-- port a
I_CA1 : in std_logic;
I_CA2 : in std_logic;
O_CA2 : out std_logic;
O_CA2_OE_L : out std_logic;
I_PA : in std_logic_vector(7 downto 0);
O_PA : out std_logic_vector(7 downto 0);
O_PA_OE_L : out std_logic_vector(7 downto 0);
-- port b
I_CB1 : in std_logic;
O_CB1 : out std_logic;
O_CB1_OE_L : out std_logic;
I_CB2 : in std_logic;
O_CB2 : out std_logic;
O_CB2_OE_L : out std_logic;
I_PB : in std_logic_vector(7 downto 0);
O_PB : out std_logic_vector(7 downto 0);
O_PB_OE_L : out std_logic_vector(7 downto 0);
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
RESET_L : in std_logic;
ENA_4 : in std_logic; -- clk enable
CLK : in std_logic
);
end;
architecture RTL of M6522 is
signal phase : std_logic_vector(1 downto 0):="00";
signal p2_h_t1 : std_logic;
signal cs : std_logic;
-- registers
signal r_ddra : std_logic_vector(7 downto 0);
signal r_ora : std_logic_vector(7 downto 0);
signal r_ira : std_logic_vector(7 downto 0);
signal r_ddrb : std_logic_vector(7 downto 0);
signal r_orb : std_logic_vector(7 downto 0);
signal r_irb : std_logic_vector(7 downto 0);
signal r_t1l_l : std_logic_vector(7 downto 0);
signal r_t1l_h : std_logic_vector(7 downto 0);
signal r_t2l_l : std_logic_vector(7 downto 0);
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
signal r_sr : std_logic_vector(7 downto 0);
signal r_acr : std_logic_vector(7 downto 0);
signal r_pcr : std_logic_vector(7 downto 0);
signal r_ifr : std_logic_vector(7 downto 0);
signal r_ier : std_logic_vector(6 downto 0);
signal sr_write_ena : boolean;
signal sr_read_ena : boolean;
signal ifr_write_ena : boolean;
signal ier_write_ena : boolean;
signal clear_irq : std_logic_vector(7 downto 0);
signal load_data : std_logic_vector(7 downto 0);
-- timer 1
signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t1c_active : boolean;
signal t1c_done : boolean;
signal t1_w_reset_int : boolean;
signal t1_r_reset_int : boolean;
signal t1_load_counter : boolean;
signal t1_reload_counter : boolean;
signal t1_int_enable : boolean := false;
signal t1_toggle : std_logic;
signal t1_irq : std_logic := '0';
signal t1_pb7 : std_logic := '1';
signal t1_pb7_en_c : std_logic;
signal t1_pb7_en_d : std_logic;
-- timer 2
signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here...
signal t2c_active : boolean;
signal t2c_done : boolean;
signal t2_pb6 : std_logic;
signal t2_pb6_t1 : std_logic;
signal t2_cnt_clk : std_logic := '1';
signal t2_w_reset_int : boolean;
signal t2_r_reset_int : boolean;
signal t2_load_counter : boolean;
signal t2_reload_counter : boolean;
signal t2_int_enable : boolean := false;
signal t2_irq : std_logic := '0';
signal t2_sr_ena : boolean;
-- shift reg
signal sr_cnt : std_logic_vector(3 downto 0);
signal sr_cb1_oe_l : std_logic;
signal sr_cb1_out : std_logic;
signal sr_drive_cb2 : std_logic;
signal sr_strobe : std_logic;
signal sr_do_shift : boolean := false;
signal sr_strobe_t1 : std_logic;
signal sr_strobe_falling : boolean;
signal sr_strobe_rising : boolean;
signal sr_irq : std_logic;
signal sr_out : std_logic;
signal sr_active : boolean;
-- io
signal w_orb_hs : std_logic;
signal w_ora_hs : std_logic;
signal r_irb_hs : std_logic;
signal r_ira_hs : std_logic;
signal ca_hs_sr : std_logic;
signal ca_hs_pulse : std_logic;
signal cb_hs_sr : std_logic;
signal cb_hs_pulse : std_logic;
signal cb1_in_mux : std_logic;
signal ca1_ip_reg_c : std_logic;
signal ca1_ip_reg_d : std_logic;
signal cb1_ip_reg_c : std_logic;
signal cb1_ip_reg_d : std_logic;
signal ca1_int : boolean;
signal cb1_int : boolean;
signal ca1_irq : std_logic;
signal cb1_irq : std_logic;
signal ca2_ip_reg_c : std_logic;
signal ca2_ip_reg_d : std_logic;
signal cb2_ip_reg_c : std_logic;
signal cb2_ip_reg_d : std_logic;
signal ca2_int : boolean;
signal cb2_int : boolean;
signal ca2_irq : std_logic;
signal cb2_irq : std_logic;
signal final_irq : std_logic;
begin
p_phase : process
begin
-- internal clock phase
wait until rising_edge(CLK);
if (ENA_4 = '1') then
p2_h_t1 <= I_P2_H;
if (p2_h_t1 = '0') and (I_P2_H = '1') then
phase <= "11";
else
phase <= std_logic_vector(unsigned(phase) + 1);
end if;
end if;
end process;
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
begin
cs <= '0';
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
cs <= '1';
end if;
end process;
-- peripheral control reg (pcr)
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
-- 3..1 ca2 operation
-- 000 input -ve edge
-- 001 independend interrupt input -ve edge
-- 010 input +ve edge
-- 011 independend interrupt input +ve edge
-- 100 handshake output
-- 101 pulse output
-- 110 low output
-- 111 high output
-- 7..4 as 3..0 for cb1,cb2
-- auxiliary control reg (acr)
-- 0 input latch PA (0 disable, 1 enable)
-- 1 input latch PB (0 disable, 1 enable)
-- 4..2 shift reg control
-- 000 disable
-- 001 shift in using t2
-- 010 shift in using o2
-- 011 shift in using ext clk
-- 100 shift out free running t2 rate
-- 101 shift out using t2
-- 101 shift out using o2
-- 101 shift out using ext clk
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
-- 7..6 t1 timer control
-- 00 timed interrupt each time t1 is loaded pb7 disable
-- 01 continuous interrupts pb7 disable
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
-- 01 continuous interrupts pb7 square wave output
--
p_write_reg_reset : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ora <= x"00"; r_orb <= x"00";
r_ddra <= x"00"; r_ddrb <= x"00";
r_acr <= x"00"; r_pcr <= x"00";
w_orb_hs <= '0';
w_ora_hs <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
w_orb_hs <= '0';
w_ora_hs <= '0';
if (cs = '1') and (I_RW_L = '0') then
case I_RS is
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
when x"2" => r_ddrb <= I_DATA;
when x"3" => r_ddra <= I_DATA;
when x"B" => r_acr <= I_DATA;
when x"C" => r_pcr <= I_DATA;
when x"F" => r_ora <= I_DATA;
when others => null;
end case;
end if;
-- Set timer PB7 state, only on rising edge of setting ACR(7)
if ((t1_pb7_en_d = '0') and (t1_pb7_en_c = '1')) then
t1_pb7 <= '1';
end if;
if t1_load_counter then
t1_pb7 <= '0'; -- Reset internal timer 1 PB7 state on every timer load
elsif t1_toggle = '1' then
t1_pb7 <= not t1_pb7;
end if;
end if;
end if;
end process;
p_write_reg : process (RESET_L, CLK) is
begin
if (RESET_L = '0') then
-- The spec says, this is not reset.
-- Fact is that the 1541 VIA1 timer won't work,
-- as the firmware ONLY sets the r_t1l_h latch!!!!
r_t1l_l <= (others => '1'); -- All latches default to FFFF
r_t1l_h <= (others => '1');
r_t2l_l <= (others => '1');
r_t2l_h <= (others => '1');
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
t1_w_reset_int <= false;
t1_load_counter <= false;
t2_w_reset_int <= false;
t2_load_counter <= false;
load_data <= x"00";
sr_write_ena <= false;
ifr_write_ena <= false;
ier_write_ena <= false;
if (cs = '1') and (I_RW_L = '0') then
load_data <= I_DATA;
case I_RS is
when x"4" => r_t1l_l <= I_DATA;
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
t1_load_counter <= true;
when x"6" => r_t1l_l <= I_DATA;
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
when x"8" => r_t2l_l <= I_DATA;
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
t2_load_counter <= true;
when x"A" => sr_write_ena <= true;
when x"D" => ifr_write_ena <= true;
when x"E" => ier_write_ena <= true;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_oe : process(cs, I_RW_L)
begin
O_DATA_OE_L <= '1';
if (cs = '1') and (I_RW_L = '1') then
O_DATA_OE_L <= '0';
end if;
end process;
p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l,
r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_ora, r_orb, t1_pb7_en_d, t1_pb7)
variable orb : std_logic_vector(7 downto 0);
begin
t1_r_reset_int <= false;
t2_r_reset_int <= false;
sr_read_ena <= false;
r_irb_hs <= '0';
r_ira_hs <= '0';
O_DATA <= x"00"; -- default
orb := (r_irb and not r_ddrb) or (r_orb and r_ddrb);
-- If PB7 under timer control, assign value from timer
if (t1_pb7_en_d = '1') then
orb(7) := t1_pb7;
end if;
if (cs = '1') and (I_RW_L = '1') then
case I_RS is
when x"0" => O_DATA <= orb; r_irb_hs <= '1';
when x"1" => O_DATA <= (r_ira and not r_ddra) or (r_ora and r_ddra); r_ira_hs <= '1';
when x"2" => O_DATA <= r_ddrb;
when x"3" => O_DATA <= r_ddra;
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
when x"5" => O_DATA <= t1c(15 downto 8);
when x"6" => O_DATA <= r_t1l_l;
when x"7" => O_DATA <= r_t1l_h;
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
when x"9" => O_DATA <= t2c(15 downto 8);
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
when x"B" => O_DATA <= r_acr;
when x"C" => O_DATA <= r_pcr;
when x"D" => O_DATA <= r_ifr;
when x"E" => O_DATA <= ('0' & r_ier);
when x"F" => O_DATA <= r_ira;
when others => null;
end case;
end if;
end process;
--
-- IO
--
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
begin
-- if the shift register is enabled, cb1 may be an output
-- in this case we should NOT listen to the input as
-- CB1 interrupts are not generated by the shift register
if (sr_cb1_oe_l = '1') then
cb1_in_mux <= I_CB1;
else
cb1_in_mux <= '1';
end if;
end process;
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg_c, ca1_ip_reg_d, cb1_ip_reg_c, cb1_ip_reg_d)
begin
if (r_pcr(0) = '0') then -- ca1 control
-- negative edge
ca1_int <= (ca1_ip_reg_d = '1') and (ca1_ip_reg_c = '0');
else
-- positive edge
ca1_int <= (ca1_ip_reg_d = '0') and (ca1_ip_reg_c = '1');
end if;
if (r_pcr(4) = '0') then -- cb1 control
-- negative edge
cb1_int <= (cb1_ip_reg_d = '1') and (cb1_ip_reg_c = '0');
else
-- positive edge
cb1_int <= (cb1_ip_reg_d = '0') and (cb1_ip_reg_c = '1');
end if;
end process;
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg_c, ca2_ip_reg_d, cb2_ip_reg_c, cb2_ip_reg_d)
begin
ca2_int <= false;
if (r_pcr(3) = '0') then -- ca2 input
if (r_pcr(2) = '0') then -- ca2 edge
-- negative edge
ca2_int <= (ca2_ip_reg_d = '1') and (ca2_ip_reg_c = '0');
else
-- positive edge
ca2_int <= (ca2_ip_reg_d = '0') and (ca2_ip_reg_c = '1');
end if;
end if;
cb2_int <= false;
if (r_pcr(7) = '0') then -- cb2 input
if (r_pcr(6) = '0') then -- cb2 edge
-- negative edge
cb2_int <= (cb2_ip_reg_d = '1') and (cb2_ip_reg_c = '0');
else
-- positive edge
cb2_int <= (cb2_ip_reg_d = '0') and (cb2_ip_reg_c = '1');
end if;
end if;
end process;
p_ca2_cb2 : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_CA2 <= '1'; -- Pullup is default
O_CA2_OE_L <= '1';
O_CB2 <= '1'; -- Pullup is default
O_CB2_OE_L <= '1';
ca_hs_sr <= '0';
ca_hs_pulse <= '0';
cb_hs_sr <= '0';
cb_hs_pulse <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- ca
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
ca_hs_sr <= '1';
elsif ca1_int then
ca_hs_sr <= '0';
end if;
if (phase = "00") then
ca_hs_pulse <= w_ora_hs or r_ira_hs;
end if;
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
case r_pcr(3 downto 1) is
when "000" => O_CA2 <= I_CA2; -- input, output follows input
when "001" => O_CA2 <= I_CA2; -- input, output follows input
when "010" => O_CA2 <= I_CA2; -- input, output follows input
when "011" => O_CA2 <= I_CA2; -- input, output follows input
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
when "110" => O_CA2 <= '0'; -- low
when "111" => O_CA2 <= '1'; -- high
when others => null;
end case;
-- cb
if (phase = "00") and (w_orb_hs = '1') then
cb_hs_sr <= '1';
elsif cb1_int then
cb_hs_sr <= '0';
end if;
if (phase = "00") then
cb_hs_pulse <= w_orb_hs;
end if;
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
if (sr_drive_cb2 = '1') then -- serial output
O_CB2 <= sr_out;
else
case r_pcr(7 downto 5) is
when "000" => O_CB2 <= I_CB2; -- input, output follows input
when "001" => O_CB2 <= I_CB2; -- input, output follows input
when "010" => O_CB2 <= I_CB2; -- input, output follows input
when "011" => O_CB2 <= I_CB2; -- input, output follows input
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
when "110" => O_CB2 <= '0'; -- low
when "111" => O_CB2 <= '1'; -- high
when others => null;
end case;
end if;
end if;
end if;
end process;
O_CB1 <= sr_cb1_out;
O_CB1_OE_L <= sr_cb1_oe_l;
p_ca_cb_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_irq <= '0';
ca2_irq <= '0';
cb1_irq <= '0';
cb2_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- not pretty
if ca1_int then
ca1_irq <= '1';
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
ca1_irq <= '0';
end if;
if ca2_int then
ca2_irq <= '1';
else
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
(clear_irq(0) = '1') then
ca2_irq <= '0';
end if;
end if;
if cb1_int then
cb1_irq <= '1';
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
cb1_irq <= '0';
end if;
if cb2_int then
cb2_irq <= '1';
else
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
(clear_irq(3) = '1') then
cb2_irq <= '0';
end if;
end if;
end if;
end if;
end process;
p_input_reg : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
ca1_ip_reg_c <= '0';
ca1_ip_reg_d <= '0';
cb1_ip_reg_c <= '0';
cb1_ip_reg_d <= '0';
ca2_ip_reg_c <= '0';
ca2_ip_reg_d <= '0';
cb2_ip_reg_c <= '0';
cb2_ip_reg_d <= '0';
r_ira <= x"00";
r_irb <= x"00";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- we have a fast clock, so we can have input registers
ca1_ip_reg_c <= I_CA1;
ca1_ip_reg_d <= ca1_ip_reg_c;
cb1_ip_reg_c <= cb1_in_mux;
cb1_ip_reg_d <= cb1_ip_reg_c;
ca2_ip_reg_c <= I_CA2;
ca2_ip_reg_d <= ca2_ip_reg_c;
cb2_ip_reg_c <= I_CB2;
cb2_ip_reg_d <= cb2_ip_reg_c;
if (r_acr(0) = '0') then
r_ira <= I_PA;
else -- enable latching
if ca1_int then
r_ira <= I_PA;
end if;
end if;
if (r_acr(1) = '0') then
r_irb <= I_PB;
else -- enable latching
if cb1_int then
r_irb <= I_PB;
end if;
end if;
end if;
end if;
end process;
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb, t1_pb7_en_d, t1_pb7)
begin
-- data direction reg (ddr) 0 = input, 1 = output
O_PA <= r_ora;
O_PA_OE_L <= not r_ddra;
-- If PB7 is timer driven output set PB7 to the timer state, otherwise use value in ORB register
if (t1_pb7_en_d = '1') then
O_PB <= t1_pb7 & r_orb(6 downto 0);
else
O_PB <= r_orb;
end if;
-- NOTE: r_ddrb(7) must be set to enable T1 output on PB7 - [various datasheets specify this]
O_PB_OE_L <= not r_ddrb;
end process;
--
-- Timer 1
--
-- Detect change in r_acr(7), timer 1 mode for PB7
p_pb7_enable : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
t1_pb7_en_c <= r_acr(7);
t1_pb7_en_d <= t1_pb7_en_c;
end if;
end process;
p_timer1_done : process
variable done : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t1c = x"0000");
t1c_done <= done and (phase = "11");
if (phase = "11") and not t1_load_counter then -- Don't set reload if T1L-H written
t1_reload_counter <= done;
elsif t1_load_counter then -- Cancel a reload when T1L-H written
t1_reload_counter <= false;
end if;
if t1_load_counter then -- done reset on load!
t1c_done <= false;
end if;
end if;
end process;
p_timer1 : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if t1_load_counter or (t1_reload_counter and phase = "11") then
t1c( 7 downto 0) <= r_t1l_l;
t1c(15 downto 8) <= r_t1l_h;
-- There is a need to write to Latch HI to enable interrupts for both continuous and one-shot modes
if t1_load_counter then
t1_int_enable <= true;
end if;
elsif (phase="11") then
t1c <= std_logic_vector(unsigned(t1c) - 1);
end if;
if t1_load_counter or t1_reload_counter then
t1c_active <= true;
elsif t1c_done then
t1c_active <= false;
end if;
t1_toggle <= '0';
if t1c_active and t1c_done then
if t1_int_enable then -- Set interrupt only if T1L-H has been written
t1_toggle <= '1';
t1_irq <= '1';
if (r_acr(6) = '0') then -- Disable further interrupts if in one shot mode
t1_int_enable <= false;
end if;
end if;
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
t1_irq <= '0';
end if;
if t1_load_counter then -- irq reset on load!
t1_irq <= '0';
end if;
end if;
end process;
--
-- Timer2
--
p_timer2_pb6_input : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (phase = "01") then -- leading edge p2_h
t2_pb6 <= I_PB(6);
t2_pb6_t1 <= t2_pb6;
end if;
end if;
end process;
-- Ensure we don't start counting until the P2 clock after r_acr is changed
p_timer2_ena : process
begin
wait until rising_edge(I_P2_H);
if r_acr(5) = '0' then
t2_cnt_clk <= '1';
else
t2_cnt_clk <= '0';
end if;
end process;
p_timer2_done : process
variable done : boolean;
variable done_sr : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
done := (t2c = x"0000"); -- Normal timer expires at 0000
done_sr := (t2c(7 downto 0) = x"00"); -- Shift register expires on low byte = 00
t2c_done <= done and (phase = "11");
if (phase = "11") then
t2_reload_counter <= done_sr; -- Timer 2 is only reloaded when used for the shift register
end if;
if t2_load_counter then -- done reset on load!
t2c_done <= false;
end if;
end if;
end process;
p_timer2 : process
variable ena : boolean;
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
if (t2_cnt_clk ='1') then
ena := true;
t2c_active <= true;
t2_int_enable <= true;
else
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
end if;
-- Shift register reload is only active when shift register mode using T2 is enabled
if t2_reload_counter and (phase="11") and ((r_acr(4 downto 2) = "001") or (r_acr(4 downto 2) = "100") or (r_acr(4 downto 2) = "101")) then
t2c(7 downto 0) <= r_t2l_l; -- For shift register only low latch is loaded!
elsif t2_load_counter then
t2_int_enable <= true;
t2c( 7 downto 0) <= r_t2l_l;
t2c(15 downto 8) <= r_t2l_h;
else
if (phase="11") and ena then -- or count mode
t2c <= std_logic_vector(unsigned(t2c) - 1);
end if;
end if;
-- Shift register strobe on T2 occurs one P2H clock after timer expires
-- so enable the strobe when we roll over to FF
t2_sr_ena <= (t2c(7 downto 0) = x"FF") and (phase = "11");
if t2_load_counter then
t2c_active <= true;
elsif t2c_done then
t2c_active <= false;
end if;
if t2c_active and t2c_done and t2_int_enable then
t2_int_enable <= false;
t2_irq <= '1';
elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
t2_irq <= '0';
end if;
if t2_load_counter then -- irq reset on load!
t2_irq <= '0';
end if;
end if;
end process;
--
-- Shift Register
--
p_sr : process(RESET_L, CLK)
variable dir_out : std_logic;
variable ena : std_logic;
variable cb1_op : std_logic;
variable cb1_ip : std_logic;
variable use_t2 : std_logic;
variable free_run : std_logic;
variable sr_count_ena : boolean;
begin
if (RESET_L = '0') then
r_sr <= x"00";
sr_drive_cb2 <= '0';
sr_cb1_oe_l <= '1';
sr_cb1_out <= '0';
sr_do_shift <= false;
sr_strobe <= '1';
sr_cnt <= "0000";
sr_irq <= '0';
sr_out <= '0';
sr_active <= false;
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
-- decode mode
dir_out := r_acr(4); -- output on cb2
cb1_op := '0';
cb1_ip := '0';
use_t2 := '0';
free_run := '0';
-- DMB: SR still runs even in disabled mode (on rising edge of CB1).
-- It just doesn't generate any interrupts.
-- Ref BBC micro advanced user guide p409
case r_acr(4 downto 2) is
-- DMB: in disabled mode, configure cb1 as an input
when "000" => ena := '0'; cb1_ip := '1'; -- 0x00 Mode 0 SR disabled
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; -- 0x04 Mode 1 Shift in under T2 control
when "010" => ena := '1'; cb1_op := '1'; -- 0x08 Mode 2 Shift in under P2 control
when "011" => ena := '1'; cb1_ip := '1'; -- 0x0C Mode 3 Shift in under control of ext clock
when "100" => ena := '1'; cb1_op := '1'; use_t2 := '1'; free_run := '1'; -- 0x10 Mode 4 Shift out free running under T2 control
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; -- 0x14 Mode 5 Shift out under T2 control
when "110" => ena := '1'; cb1_op := '1'; -- 0x18 Mode 6 Shift out under P2 control
when "111" => ena := '1'; cb1_ip := '1'; -- 0x1C Mode 7 Shift out under control of ext clock
when others => null;
end case;
-- clock select
-- DMB: in disabled mode, strobe from cb1
if (cb1_ip = '1') then
sr_strobe <= I_CB1;
else
if (sr_cnt(3) = '0') and (free_run = '0') then
sr_strobe <= '1';
else
if ((use_t2 = '1') and t2_sr_ena) or
((use_t2 = '0') and (phase = "00")) then
sr_strobe <= not sr_strobe;
end if;
end if;
end if;
-- latch on rising edge, shift on falling edge of P2
if sr_write_ena then
r_sr <= load_data;
sr_out <= r_sr(7);
else
-- DMB: allow shifting in all modes
if (dir_out = '0') then
-- input
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
if sr_strobe_rising then
sr_do_shift <= true;
r_sr(0) <= I_CB2;
elsif sr_do_shift then
sr_do_shift <= false;
r_sr(7 downto 1) <= r_sr(6 downto 0);
end if;
end if;
else
-- output
if (sr_cnt(3) = '1') or (cb1_ip = '1') or (free_run = '1') then
if sr_strobe_falling then
sr_out <= r_sr(7);
sr_do_shift <= true;
elsif sr_do_shift then
sr_do_shift <= false;
r_sr <= r_sr(6 downto 0) & r_sr(7);
end if;
end if;
end if;
end if;
-- Set shift enabled flag, note does not get set for free_run mode !
if (ena = '1') and (sr_cnt(3) = '1') then
sr_active <= true;
elsif (ena = '1') and (sr_cnt(3) = '0') and (phase="11") then
sr_active <= false;
end if;
sr_count_ena := sr_strobe_rising;
-- DMB: reseting sr_count when not enabled cause the sr to
-- start running immediately it was enabled, which is incorrect
-- and broke the latest SmartSPI ROM on the BBC Micro
if (ena = '1') and (sr_write_ena or sr_read_ena) and (not sr_active) then
-- some documentation says sr bit in IFR must be set as well ?
sr_cnt <= "1000";
elsif sr_count_ena and (sr_cnt(3) = '1') then
sr_cnt <= std_logic_vector(unsigned(sr_cnt) + 1);
end if;
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
sr_irq <= '1';
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
sr_irq <= '0';
end if;
-- assign ops
sr_drive_cb2 <= dir_out;
sr_cb1_oe_l <= not cb1_op;
sr_cb1_out <= sr_strobe;
end if;
end if;
end process;
p_sr_strobe_rise_fall : process
begin
wait until rising_edge(CLK);
if (ENA_4 = '1') then
sr_strobe_t1 <= sr_strobe;
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
end if;
end process;
--
-- Interrupts
--
p_ier : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
r_ier <= "0000000";
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ier_write_ena then
if (load_data(7) = '1') then
-- set
r_ier <= r_ier or load_data(6 downto 0);
else
-- clear
r_ier <= r_ier and not load_data(6 downto 0);
end if;
end if;
end if;
end if;
end process;
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
cb1_irq, cb2_irq)
begin
r_ifr(7) <= final_irq;
r_ifr(6) <= t1_irq;
r_ifr(5) <= t2_irq;
r_ifr(4) <= cb1_irq;
r_ifr(3) <= cb2_irq;
r_ifr(2) <= sr_irq;
r_ifr(1) <= ca1_irq;
r_ifr(0) <= ca2_irq;
O_IRQ_L <= not final_irq;
end process;
p_irq : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
final_irq <= '0';
elsif rising_edge(CLK) then
if (ENA_4 = '1') then
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
final_irq <= '0'; -- no interrupts
else
final_irq <= '1';
end if;
end if;
end if;
end process;
p_clear_irq : process(ifr_write_ena, load_data)
begin
clear_irq <= x"00";
if ifr_write_ena then
clear_irq <= load_data;
end if;
end process;
end architecture RTL; |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdpipe is
port (
reset : in std_logic;
clk : in std_logic;
-- data in port
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
-- data out port
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end dsp_cmdpipe;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdpipe of dsp_cmdpipe is
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_dsp_cmdpipe is array(0 to (c_dsp_pipe_length - 1)) of t_dsp_cmdregs;
signal s_loaded : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_unload : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_pipe : t_dsp_cmdpipe;
begin -- archs_dsp_cmdpipe
p_pipe : process (clk, reset)
begin -- process p_pipe
if reset = '0' then -- asynchronous reset
s_loaded <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
-- loading first tap
if write = '1' then
s_loaded(0) <= '1';
s_pipe(0) <= cmd_in;
elsif s_unload(0) = '1' then
s_loaded(0) <= '0';
end if;
-- pipe
for i in 1 to c_dsp_pipe_length - 1 loop
if s_loaded(i) = '0' or s_unload(i) = '1' then
s_pipe(i) <= s_pipe(i - 1);
s_loaded(i) <= s_loaded(i - 1);
s_unload(i - 1) <= '1';
else
s_unload(i - 1) <= '0';
end if;
end loop;
-- unloading last tap
s_unload(c_dsp_pipe_length - 1) <= read;
end if;
end process p_pipe;
full <= s_loaded(0);
empty <= not s_loaded(c_dsp_pipe_length - 1);
cmd_out <= s_pipe(c_dsp_pipe_length - 1);
end archi_dsp_cmdpipe;
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdpipe is
port (
reset : in std_logic;
clk : in std_logic;
-- data in port
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
-- data out port
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end dsp_cmdpipe;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdpipe of dsp_cmdpipe is
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_dsp_cmdpipe is array(0 to (c_dsp_pipe_length - 1)) of t_dsp_cmdregs;
signal s_loaded : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_unload : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_pipe : t_dsp_cmdpipe;
begin -- archs_dsp_cmdpipe
p_pipe : process (clk, reset)
begin -- process p_pipe
if reset = '0' then -- asynchronous reset
s_loaded <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
-- loading first tap
if write = '1' then
s_loaded(0) <= '1';
s_pipe(0) <= cmd_in;
elsif s_unload(0) = '1' then
s_loaded(0) <= '0';
end if;
-- pipe
for i in 1 to c_dsp_pipe_length - 1 loop
if s_loaded(i) = '0' or s_unload(i) = '1' then
s_pipe(i) <= s_pipe(i - 1);
s_loaded(i) <= s_loaded(i - 1);
s_unload(i - 1) <= '1';
else
s_unload(i - 1) <= '0';
end if;
end loop;
-- unloading last tap
s_unload(c_dsp_pipe_length - 1) <= read;
end if;
end process p_pipe;
full <= s_loaded(0);
empty <= not s_loaded(c_dsp_pipe_length - 1);
cmd_out <= s_pipe(c_dsp_pipe_length - 1);
end archi_dsp_cmdpipe;
-------------------------------------------------------------------------------
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
D_I : in std_logic_vector(7 downto 0);
D_O : out std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D_I, -- D -> D_I
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D_I); -- D -> D_I
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
D_I : in std_logic_vector(7 downto 0);
D_O : out std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D_I, -- D -> D_I
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D_I); -- D -> D_I
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
|
-- File: gray_counter_20.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_20 is
port (
gray_count: out unsigned(19 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_20;
architecture MyHDL of gray_counter_20 is
signal even: std_logic;
signal gray: unsigned(19 downto 0);
begin
GRAY_COUNTER_20_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(19 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((20 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 20-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_20_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi;
architecture behave of contact_discovery_db_mem_V_m_axi is
component contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_write;
component contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_read;
component contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_db_mem_V_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_db_mem_V_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_reg_slice;
architecture behave of contact_discovery_db_mem_V_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_fifo;
architecture behave of contact_discovery_db_mem_V_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_db_mem_V_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_decoder;
architecture behav of contact_discovery_db_mem_V_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_throttl;
architecture behav of contact_discovery_db_mem_V_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_read;
architecture behave of contact_discovery_db_mem_V_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_write;
architecture behave of contact_discovery_db_mem_V_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi;
architecture behave of contact_discovery_db_mem_V_m_axi is
component contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_write;
component contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_read;
component contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_db_mem_V_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_db_mem_V_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_reg_slice;
architecture behave of contact_discovery_db_mem_V_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_fifo;
architecture behave of contact_discovery_db_mem_V_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_db_mem_V_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_decoder;
architecture behav of contact_discovery_db_mem_V_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_throttl;
architecture behav of contact_discovery_db_mem_V_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_read;
architecture behave of contact_discovery_db_mem_V_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_write;
architecture behave of contact_discovery_db_mem_V_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi;
architecture behave of contact_discovery_db_mem_V_m_axi is
component contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_write;
component contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_db_mem_V_m_axi_read;
component contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_db_mem_V_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_db_mem_V_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_db_mem_V_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_reg_slice;
architecture behave of contact_discovery_db_mem_V_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_fifo;
architecture behave of contact_discovery_db_mem_V_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_db_mem_V_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_db_mem_V_m_axi_decoder;
architecture behav of contact_discovery_db_mem_V_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_db_mem_V_m_axi_throttl;
architecture behav of contact_discovery_db_mem_V_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_read;
architecture behave of contact_discovery_db_mem_V_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_db_mem_V_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_db_mem_V_m_axi_write;
architecture behave of contact_discovery_db_mem_V_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_db_mem_V_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_db_mem_V_m_axi_fifo;
component contact_discovery_db_mem_V_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_db_mem_V_m_axi_reg_slice;
component contact_discovery_db_mem_V_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_db_mem_V_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_db_mem_V_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_db_mem_V_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_db_mem_V_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_db_mem_V_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_db_mem_V_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SRAM_Controller IS
PORT
(
clk, reset : IN STD_LOGIC;
-- to/from main system
mem : IN STD_LOGIC;
rw : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
data_f2s : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_s2f_r : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ready : OUT STD_LOGIC;
-- to/from chip
ad : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
we_n, oe_n : OUT STD_LOGIC;
-- SRAM chip
dio : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
ce_n, ub_n, lb_n : OUT STD_LOGIC
);
END SRAM_Controller;
ARCHITECTURE arch OF SRAM_Controller IS
TYPE state_type IS (idle, rd1, rd2, wr1, wr2);
SIGNAL state_reg, state_next : state_type;
SIGNAL data_f2s_reg, data_f2s_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL data_s2f_reg, data_s2f_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL addr_reg, addr_next : STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL we_buf, oe_buf, tri_buf : STD_LOGIC;
SIGNAL we_reg, oe_reg, tri_reg : STD_LOGIC;
BEGIN
-- state & data registers
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN
state_reg <= idle;
addr_reg <= (OTHERS => '0');
data_f2s_reg <= (OTHERS => '0');
data_s2f_reg <= (OTHERS => '0');
tri_reg <= '1';
we_reg <= '1';
oe_reg <= '1';
ELSIF (clk'event AND clk = '1') THEN
state_reg <= state_next;
addr_reg <= addr_next;
data_f2s_reg <= data_f2s_next;
data_s2f_reg <= data_s2f_next;
tri_reg <= tri_buf;
we_reg <= we_buf;
oe_reg <= oe_buf;
END IF;
END PROCESS;
-- next-state logic
PROCESS (state_reg, mem, rw, dio, addr, data_f2s,
data_f2s_reg, data_s2f_reg, addr_reg)
BEGIN
addr_next <= addr_reg;
data_f2s_next <= data_f2s_reg;
data_s2f_next <= data_s2f_reg;
-- ready <= '0';
CASE state_reg IS
WHEN idle =>
IF mem = '0' THEN
state_next <= idle;
ELSE
addr_next <= addr;
IF rw = '0' THEN --write
state_next <= wr1;
data_f2s_next <= data_f2s;
ELSE -- read
state_next <= rd1;
END IF;
END IF;
-- ready <= '1';
WHEN wr1 =>
state_next <= wr2;
WHEN wr2 =>
state_next <= idle;
WHEN rd1 =>
state_next <= rd2;
WHEN rd2 =>
data_s2f_next <= dio;
state_next <= idle;
END CASE;
END PROCESS;
-- next-state logic
PROCESS (state_next)
BEGIN
tri_buf <= '1'; -- signals are active low
we_buf <= '1';
oe_buf <= '1';
CASE state_next IS
WHEN idle =>
WHEN wr1 =>
tri_buf <= '0';
we_buf <= '0';
WHEN wr2 =>
tri_buf <= '0';
WHEN rd1 =>
oe_buf <= '0';
WHEN rd2 =>
oe_buf <= '0';
END CASE;
END PROCESS;
-- to main system
data_s2f_r <= data_s2f_reg;
-- to sram
we_n <= we_reg;
oe_n <= oe_reg;
ad <= addr_reg;
--i/o for SRAM chip a
ce_n <= '0';
ub_n <= '0';
lb_n <= '0';
dio <= data_f2s_reg WHEN tri_reg = '0' ELSE
(OTHERS => 'Z');
END arch;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24048)
`protect data_block
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|
`protect begin_protected
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`protect begin_protected
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
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|
`protect begin_protected
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`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity test_activation is
end test_activation;
architecture behave of test_activation is
constant clk_period : time := 10 ns;
constant num_samplers : integer := 1;
constant num_rngs_per_sampler : integer := 4;
constant tau : integer := 20;
constant threshold : membrane_t := make_fixed(3.0,
membrane_width-1-membrane_fraction,
membrane_fraction);
constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
others => (others => make_fixed(0.0, 2, 1))
);
signal clk, reset : std_ulogic;
signal clock_tick : std_ulogic;
signal systime : systime_t;
signal state_clamp_mask,
state_clamp,
state : state_array_t(1 to num_samplers);
signal membranes : membrane_array_t(1 to num_samplers);
signal fires : std_ulogic_vector(1 to num_samplers);
signal seeds : lfsr_state_array_t(1 to num_samplers*num_rngs_per_sampler);
signal biases : weight_array_t(1 to num_samplers);
begin
clock_generation: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
------------------------------------------------------------
-- unit under test
------------------------------------------------------------
uut: entity work.sampling_network
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => clock_tick,
systime => systime,
state => state,
membranes => membranes,
fires => fires,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
-- stimulus generation
------------------------------------------------------------
stimulus: process
variable l : line;
variable seed1, seed2 : positive;
variable rand : real;
variable int_rand : integer;
variable test_input : real;
begin
biases <= (others => make_fixed(0.0, 2, 1));
for i in seeds'range loop
uniform(seed1, seed2, rand);
int_rand := integer(rand*(2.0**lfsr_width-1.0));
seeds(i) <= std_logic_vector(to_unsigned(int_rand, seeds(i)'length));
end loop;
write(l, string'("biases:"));
writeline(output, l);
for i in biases'range loop
hwrite(l, std_logic_vector(biases(i)));
writeline(output, l);
end loop;
write(l, string'("weights:"));
writeline(output, l);
for i in 1 to num_samplers loop
for j in 1 to num_samplers loop
hwrite(l, std_logic_vector(weights(i,j)));
write(l, string'(" "));
end loop;
writeline(output, l);
end loop;
write(l, string'("threshold: "));
hwrite(l, std_logic_vector(threshold));
writeline(output, l);
reset <= '1';
wait for 100 ns;
reset <= '0';
wait until rising_edge(clk);
test_input := -4.0;
while test_input <= 3.5 loop
write(l, string'("test_input: "));
write(l, test_input);
biases <= (others => make_fixed(test_input, 2, 1));
write(l, string'(" ("));
hwrite(l, std_logic_vector(make_fixed(test_input, 2, 1)));
write(l, string'(")"));
writeline(output, l);
wait for 100000*clk_period;
test_input := test_input + 0.5;
end loop;
assert(false)
report "no error; simulation end"
severity failure;
end process;
------------------------------------------------------------
recorder: process
file f : text open write_mode is "activation_trace";
variable ln : line;
begin
loop
wait until rising_edge(clock_tick);
for i in state'range loop
write(ln, state(i));
write(ln, string'(" "));
write(ln, fires(i));
write(ln, string'(" "));
hwrite(ln, std_logic_vector(membranes(i)));
write(ln, string'(" "));
--hwrite(ln, std_logic_vector(biases(i)));
--write(ln, string'(" "));
end loop;
writeline(f, ln);
end loop;
end process;
------------------------------------------------------------
end behave;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.1 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: overloading my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_t_rtl_conf / ent_t
--
configuration ent_t_rtl_conf of ent_t is
for rtl
-- Generated Configuration
for inst_a : ent_a
use configuration work.ent_a_rtl_conf;
end for;
for inst_b : ent_b
use configuration work.ent_b_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_c : ent_c
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_c_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_t_rtl_conf;
--
-- End of Generated Configuration ent_t_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity top_ml605_gnss is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end top_ml605_gnss;
architecture arch_top_ml605_gnss of top_ml605_gnss is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal ib_clk_adc : std_logic;
signal ib_gps_I : std_logic_vector(1 downto 0);
signal ib_gps_Q : std_logic_vector(1 downto 0);
signal ib_glo_I : std_logic_vector(1 downto 0);
signal ib_glo_Q : std_logic_vector(1 downto 0);
signal ob_pps : std_logic;
signal ib_gps_ld : std_logic;
signal ib_glo_ld : std_logic;
signal ob_max_sclk : std_logic;
signal ob_max_sdata : std_logic;
signal ob_max_ncs : std_logic_vector(1 downto 0);
signal ib_antext_stat : std_logic;
signal ib_antext_detect : std_logic;
signal ob_antext_ena : std_logic;
signal ob_antint_contr : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! GNSS sub-system
iclkadc0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
adcx : for i in 0 to 1 generate
igpsi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_I(i), i_gps_I(i));
igpsq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_Q(i), i_gps_Q(i));
igloi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_I(i), i_glo_I(i));
igloq0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_Q(i), i_glo_Q(i));
end generate;
opps0 : obuf_tech generic map(CFG_PADTECH) port map (o_pps, ob_pps);
igpsld0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_gps_ld, i_gps_ld);
iglold0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_glo_ld, i_glo_ld);
omaxclk0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sclk, ob_max_sclk);
omaxdat0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_sdata, ob_max_sdata);
omaxcs0 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(0), ob_max_ncs(0));
omaxcs1 : obuf_tech generic map(CFG_PADTECH) port map (o_max_ncs(1), ob_max_ncs(1));
iantstat0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_stat, i_antext_stat);
iantdet0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_antext_detect, i_antext_detect);
oanten0 : obuf_tech generic map(CFG_PADTECH) port map (o_antext_ena, ob_antext_ena);
oantctr0 : obuf_tech generic map(CFG_PADTECH) port map (o_antint_contr, ob_antint_contr);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => open,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => ib_clk_adc,
i_gps_I => ib_gps_I,
i_gps_Q => ib_gps_Q,
i_glo_I => ib_glo_I,
i_glo_Q => ib_glo_Q,
o_pps => ob_pps,
i_gps_ld => ib_gps_ld,
i_glo_ld => ib_glo_ld,
o_max_sclk => ob_max_sclk,
o_max_sdata => ob_max_sdata,
o_max_ncs => ob_max_ncs,
i_antext_stat => ib_antext_stat,
i_antext_detect => ib_antext_detect,
o_antext_ena => ob_antext_ena,
o_antint_contr => ob_antint_contr
);
end arch_top_ml605_gnss;
|
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_label:
for i in 0 to 11 generate
genx:
test_ent
port map (
input => i
);
end generate;
end architecture;
|
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_label:
for i in 0 to 11 generate
genx:
test_ent
port map (
input => i
);
end generate;
end architecture;
|
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_label:
for i in 0 to 11 generate
genx:
test_ent
port map (
input => i
);
end generate;
end architecture;
|
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity oneshot is
generic (SIZE : positive := 12);
port(
CLK : in std_logic;
RESET : in std_logic;
ONESHOT_IN : in std_logic;
ONESHOT_OUT : out std_logic );
end oneshot;
architecture rtl of oneshot is
signal COUNTER : unsigned(SIZE-1 downto 0);
signal ONES : unsigned(SIZE-1 downto 0);
signal LOCK : std_logic;
begin
ONES <= (others=>'1');
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
LOCK <= '0';
COUNTER <= (others=>'0');
else
if ONESHOT_IN = '1' then
LOCK <= '1';
end if;
if LOCK = '1' then
if COUNTER /= ONES then
COUNTER <= COUNTER + 1;
else
LOCK <= '0';
COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
ONESHOT_OUT <= LOCK;
end rtl;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_sbi;
use bitvis_vip_sbi.transaction_pkg.all;
use bitvis_vip_sbi.vvc_methods_pkg.all;
use bitvis_vip_sbi.td_vvc_framework_common_methods_pkg.all;
use bitvis_vip_sbi.sbi_bfm_pkg.t_sbi_if;
use bitvis_vip_sbi.sbi_bfm_pkg.t_sbi_bfm_config;
use bitvis_vip_sbi.sbi_bfm_pkg.C_SBI_BFM_CONFIG_DEFAULT;
end context; |
architecture RTL of FIFO is
procedure proc1 is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
alias a : subtype_indicator is name;
begin
end procedure proc1;
procedure proc1 is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
alias a : subtype_indicator is name;
begin
end procedure proc1;
function func1 return integer is
constant c : integer;
variable v : integer;
file f : something;
begin
end function func1;
begin
end architecture RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8304)
`protect data_block
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`protect end_protected
|
-- -------------------------------------------------------------
--
-- Generated Configuration for PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:52 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: portlist_i_e-c.vhd,v 1.1 2007/03/05 15:35:27 wig Exp $
-- $Date: 2007/03/05 15:35:27 $
-- $Log: portlist_i_e-c.vhd,v $
-- Revision 1.1 2007/03/05 15:35:27 wig
-- Changed case of filenames.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration PORTLIST_i_rtl_conf / PORTLIST_i_e
--
configuration PORTLIST_i_rtl_conf of PORTLIST_i_e is
for rtl
-- Generated Configuration
end for;
end PORTLIST_i_rtl_conf;
--
-- End of Generated Configuration PORTLIST_i_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
entity tb_dff04 is
end tb_dff04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff04 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff04
port map (
r => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= x"00";
pulse;
assert dout = x"01" severity failure;
din <= x"ab";
pulse;
assert dout = x"ac" severity failure;
pulse;
assert dout = x"ac" severity failure;
din <= x"12";
pulse;
assert dout = x"13" severity failure;
wait;
end process;
end behav;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_processing_system7_0_0 is
Port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end system_processing_system7_0_0;
architecture stub of system_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity Clk_div_2 is
port
(
clk_in,rst : in std_logic;
clk_out : out std_logic
);
end Clk_div_2;
architecture bhv of clk_div_2 is
signal clk : std_logic;
begin
process(clk_in,rst)
begin
if(rst = '1') then
clk <= '0';
elsif(rising_edge(clk_in)) then
clk <= not clk;
end if;
end process;
clk_out <= clk;
end bhv; |
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
|
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- Violations
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
end architecture ARCH;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_0_stub.vhdl
-- Design : bram_2048_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_rec_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_rec_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_command_rec_fifo_top;
architecture xilinx of pcie_command_rec_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_rec_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_command_rec_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_stub.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_rgb565_0_0 is
Port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_rgb888_to_rgb565_0_0;
architecture stub of system_rgb888_to_rgb565_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb_888[23:0],rgb_565[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_rgb565,Vivado 2016.4";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when OTHERS;
end Mixed;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.seven_seg_pkg.all;
entity seven_seg_controller is
generic (
-- The controller cycles through the seven segment displays
-- This variable controls how long (in clk cycles) every digit is turned on.
hold_count : natural range 1 to natural'high;
digit_count : natural range 1 to natural'high
);
port (
clk : in std_logic;
rst : in std_logic;
-- Bus connection
mst2slv : in bus_mst2slv_type;
slv2mst : out bus_slv2mst_type;
digit_anodes : out std_logic_vector(digit_count - 1 downto 0);
kathode : out seven_seg_kath_type
);
end seven_seg_controller;
architecture behaviourial of seven_seg_controller is
constant check_range : addr_range_type := (
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(digit_count - 1, bus_address_type'length))
);
signal digit_storage : bus_byte_array(digit_count - 1 downto 0) := (others => (others => '0'));
signal timer_done : std_logic;
begin
sequential : process(clk)
variable full_addr : natural range 0 to 2*digit_count;
variable addr : natural range 0 to digit_count - 1 := 0;
variable cur_digit : natural range 0 to digit_count - 1 := 0;
begin
if rising_edge(clk) then
-- Bus interaction
slv2mst.readData <= (others => '0');
if bus_addr_in_range(mst2slv.address, check_range) then
full_addr := to_integer(unsigned(mst2slv.address(mst2slv.address'range)));
for b in 0 to bus_bytes_per_word - 1 loop
if (full_addr + b < digit_count) then
addr := full_addr + b;
if mst2slv.writeEnable = '1' and mst2slv.writeMask(b) = '1' then
digit_storage(addr) <= mst2slv.writeData((b+1) * bus_byte_size - 1 downto b*bus_byte_size);
end if;
slv2mst.readData((b+1) * bus_byte_size - 1 downto b*bus_byte_size) <= digit_storage(addr);
end if;
end loop;
slv2mst.fault <= '0';
else
slv2mst.fault <= '1';
end if;
if rst = '1' then
slv2mst.ack <= '0';
else
slv2mst.ack <= bus_requesting(mst2slv);
end if;
-- Digit control
if timer_done = '1' then
if cur_digit = digit_count - 1 then
cur_digit := 0;
else
cur_digit := cur_digit + 1;
end if;
end if;
-- Set the output to the digits
kathode <= hex_to_seven_seg(digit_storage(cur_digit)(digit_info_type'range));
digit_anodes <= (others => '1');
digit_anodes(cur_digit) <= '0';
end if;
end process;
timer : entity work.simple_multishot_timer
generic map (
match_val => hold_count
)
port map (
clk => clk,
rst => '0',
done => timer_done
);
end behaviourial;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1334.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01334ent IS
END c08s04b01x00p04n03i01334ent;
ARCHITECTURE c08s04b01x00p04n03i01334arch OF c08s04b01x00p04n03i01334ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= '0' after -5 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01334 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01334arch;
|
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